1259698Sdim//===-- LiveInterval.cpp - Live Interval Representation -------------------===// 2259698Sdim// 3259698Sdim// The LLVM Compiler Infrastructure 4259698Sdim// 5259698Sdim// This file is distributed under the University of Illinois Open Source 6259698Sdim// License. See LICENSE.TXT for details. 7259698Sdim// 8259698Sdim//===----------------------------------------------------------------------===// 9259698Sdim// 10259698Sdim// This file implements the LiveRegUnits utility for tracking liveness of 11259698Sdim// physical register units across machine instructions in forward or backward 12259698Sdim// order. 13259698Sdim// 14259698Sdim//===----------------------------------------------------------------------===// 15259698Sdim 16259698Sdim#include "llvm/CodeGen/LiveRegUnits.h" 17259698Sdim#include "llvm/CodeGen/MachineInstrBundle.h" 18259698Sdimusing namespace llvm; 19259698Sdim 20259698Sdim/// Return true if the given MachineOperand clobbers the given register unit. 21259698Sdim/// A register unit is only clobbered if all its super-registers are clobbered. 22259698Sdimstatic bool operClobbersUnit(const MachineOperand *MO, unsigned Unit, 23259698Sdim const MCRegisterInfo *MCRI) { 24259698Sdim for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) { 25259698Sdim for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI) { 26259698Sdim if (!MO->clobbersPhysReg(*SI)) 27259698Sdim return false; 28259698Sdim } 29259698Sdim } 30259698Sdim return true; 31259698Sdim} 32259698Sdim 33259698Sdim/// We assume the high bits of a physical super register are not preserved 34259698Sdim/// unless the instruction has an implicit-use operand reading the 35259698Sdim/// super-register or a register unit for the upper bits is available. 36259698Sdimvoid LiveRegUnits::removeRegsInMask(const MachineOperand &Op, 37259698Sdim const MCRegisterInfo &MCRI) { 38259698Sdim SparseSet<unsigned>::iterator LUI = LiveUnits.begin(); 39259698Sdim while (LUI != LiveUnits.end()) { 40259698Sdim if (operClobbersUnit(&Op, *LUI, &MCRI)) 41259698Sdim LUI = LiveUnits.erase(LUI); 42259698Sdim else 43259698Sdim ++LUI; 44259698Sdim } 45259698Sdim} 46259698Sdim 47259698Sdimvoid LiveRegUnits::stepBackward(const MachineInstr &MI, 48259698Sdim const MCRegisterInfo &MCRI) { 49259698Sdim // Remove defined registers and regmask kills from the set. 50259698Sdim for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) { 51259698Sdim if (O->isReg()) { 52259698Sdim if (!O->isDef()) 53259698Sdim continue; 54259698Sdim unsigned Reg = O->getReg(); 55259698Sdim if (Reg == 0) 56259698Sdim continue; 57259698Sdim removeReg(Reg, MCRI); 58259698Sdim } else if (O->isRegMask()) { 59259698Sdim removeRegsInMask(*O, MCRI); 60259698Sdim } 61259698Sdim } 62259698Sdim // Add uses to the set. 63259698Sdim for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) { 64259698Sdim if (!O->isReg() || !O->readsReg() || O->isUndef()) 65259698Sdim continue; 66259698Sdim unsigned Reg = O->getReg(); 67259698Sdim if (Reg == 0) 68259698Sdim continue; 69259698Sdim addReg(Reg, MCRI); 70259698Sdim } 71259698Sdim} 72259698Sdim 73259698Sdim/// Uses with kill flag get removed from the set, defs added. If possible 74259698Sdim/// use StepBackward() instead of this function because some kill flags may 75259698Sdim/// be missing. 76259698Sdimvoid LiveRegUnits::stepForward(const MachineInstr &MI, 77259698Sdim const MCRegisterInfo &MCRI) { 78259698Sdim SmallVector<unsigned, 4> Defs; 79259698Sdim // Remove killed registers from the set. 80259698Sdim for (ConstMIBundleOperands O(&MI); O.isValid(); ++O) { 81259698Sdim if (O->isReg()) { 82259698Sdim unsigned Reg = O->getReg(); 83259698Sdim if (Reg == 0) 84259698Sdim continue; 85259698Sdim if (O->isDef()) { 86259698Sdim if (!O->isDead()) 87259698Sdim Defs.push_back(Reg); 88259698Sdim } else { 89259698Sdim if (!O->isKill()) 90259698Sdim continue; 91259698Sdim assert(O->isUse()); 92259698Sdim removeReg(Reg, MCRI); 93259698Sdim } 94259698Sdim } else if (O->isRegMask()) { 95259698Sdim removeRegsInMask(*O, MCRI); 96259698Sdim } 97259698Sdim } 98259698Sdim // Add defs to the set. 99259698Sdim for (unsigned i = 0, e = Defs.size(); i != e; ++i) { 100259698Sdim addReg(Defs[i], MCRI); 101259698Sdim } 102259698Sdim} 103259698Sdim 104259698Sdim/// Adds all registers in the live-in list of block @p BB. 105259698Sdimvoid LiveRegUnits::addLiveIns(const MachineBasicBlock *MBB, 106259698Sdim const MCRegisterInfo &MCRI) { 107259698Sdim for (MachineBasicBlock::livein_iterator L = MBB->livein_begin(), 108259698Sdim LE = MBB->livein_end(); L != LE; ++L) { 109259698Sdim addReg(*L, MCRI); 110259698Sdim } 111259698Sdim} 112