AggressiveAntiDepBreaker.h revision 199989
1//=- llvm/CodeGen/AggressiveAntiDepBreaker.h - Anti-Dep Support -*- C++ -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the AggressiveAntiDepBreaker class, which 11// implements register anti-dependence breaking during post-RA 12// scheduling. It attempts to break all anti-dependencies within a 13// block. 14// 15//===----------------------------------------------------------------------===// 16 17#ifndef LLVM_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H 18#define LLVM_CODEGEN_AGGRESSIVEANTIDEPBREAKER_H 19 20#include "AntiDepBreaker.h" 21#include "llvm/CodeGen/MachineBasicBlock.h" 22#include "llvm/CodeGen/MachineFrameInfo.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/CodeGen/ScheduleDAG.h" 26#include "llvm/Target/TargetSubtarget.h" 27#include "llvm/Target/TargetRegisterInfo.h" 28#include "llvm/ADT/BitVector.h" 29#include "llvm/ADT/SmallSet.h" 30#include <map> 31 32namespace llvm { 33 /// Class AggressiveAntiDepState 34 /// Contains all the state necessary for anti-dep breaking. 35 class AggressiveAntiDepState { 36 public: 37 /// RegisterReference - Information about a register reference 38 /// within a liverange 39 typedef struct { 40 /// Operand - The registers operand 41 MachineOperand *Operand; 42 /// RC - The register class 43 const TargetRegisterClass *RC; 44 } RegisterReference; 45 46 private: 47 /// GroupNodes - Implements a disjoint-union data structure to 48 /// form register groups. A node is represented by an index into 49 /// the vector. A node can "point to" itself to indicate that it 50 /// is the parent of a group, or point to another node to indicate 51 /// that it is a member of the same group as that node. 52 std::vector<unsigned> GroupNodes; 53 54 /// GroupNodeIndices - For each register, the index of the GroupNode 55 /// currently representing the group that the register belongs to. 56 /// Register 0 is always represented by the 0 group, a group 57 /// composed of registers that are not eligible for anti-aliasing. 58 unsigned GroupNodeIndices[TargetRegisterInfo::FirstVirtualRegister]; 59 60 /// RegRefs - Map registers to all their references within a live range. 61 std::multimap<unsigned, RegisterReference> RegRefs; 62 63 /// KillIndices - The index of the most recent kill (proceding bottom-up), 64 /// or ~0u if the register is not live. 65 unsigned KillIndices[TargetRegisterInfo::FirstVirtualRegister]; 66 67 /// DefIndices - The index of the most recent complete def (proceding bottom 68 /// up), or ~0u if the register is live. 69 unsigned DefIndices[TargetRegisterInfo::FirstVirtualRegister]; 70 71 public: 72 AggressiveAntiDepState(MachineBasicBlock *BB); 73 74 /// GetKillIndices - Return the kill indices. 75 unsigned *GetKillIndices() { return KillIndices; } 76 77 /// GetDefIndices - Return the define indices. 78 unsigned *GetDefIndices() { return DefIndices; } 79 80 /// GetRegRefs - Return the RegRefs map. 81 std::multimap<unsigned, RegisterReference>& GetRegRefs() { return RegRefs; } 82 83 // GetGroup - Get the group for a register. The returned value is 84 // the index of the GroupNode representing the group. 85 unsigned GetGroup(unsigned Reg); 86 87 // GetGroupRegs - Return a vector of the registers belonging to a 88 // group. If RegRefs is non-NULL then only included referenced registers. 89 void GetGroupRegs( 90 unsigned Group, 91 std::vector<unsigned> &Regs, 92 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs); 93 94 // UnionGroups - Union Reg1's and Reg2's groups to form a new 95 // group. Return the index of the GroupNode representing the 96 // group. 97 unsigned UnionGroups(unsigned Reg1, unsigned Reg2); 98 99 // LeaveGroup - Remove a register from its current group and place 100 // it alone in its own group. Return the index of the GroupNode 101 // representing the registers new group. 102 unsigned LeaveGroup(unsigned Reg); 103 104 /// IsLive - Return true if Reg is live 105 bool IsLive(unsigned Reg); 106 }; 107 108 109 /// Class AggressiveAntiDepBreaker 110 class AggressiveAntiDepBreaker : public AntiDepBreaker { 111 MachineFunction& MF; 112 MachineRegisterInfo &MRI; 113 const TargetRegisterInfo *TRI; 114 115 /// AllocatableSet - The set of allocatable registers. 116 /// We'll be ignoring anti-dependencies on non-allocatable registers, 117 /// because they may not be safe to break. 118 const BitVector AllocatableSet; 119 120 /// CriticalPathSet - The set of registers that should only be 121 /// renamed if they are on the critical path. 122 BitVector CriticalPathSet; 123 124 /// State - The state used to identify and rename anti-dependence 125 /// registers. 126 AggressiveAntiDepState *State; 127 128 public: 129 AggressiveAntiDepBreaker(MachineFunction& MFi, 130 TargetSubtarget::RegClassVector& CriticalPathRCs); 131 ~AggressiveAntiDepBreaker(); 132 133 /// Start - Initialize anti-dep breaking for a new basic block. 134 void StartBlock(MachineBasicBlock *BB); 135 136 /// BreakAntiDependencies - Identifiy anti-dependencies along the critical path 137 /// of the ScheduleDAG and break them by renaming registers. 138 /// 139 unsigned BreakAntiDependencies(std::vector<SUnit>& SUnits, 140 MachineBasicBlock::iterator& Begin, 141 MachineBasicBlock::iterator& End, 142 unsigned InsertPosIndex); 143 144 /// Observe - Update liveness information to account for the current 145 /// instruction, which will not be scheduled. 146 /// 147 void Observe(MachineInstr *MI, unsigned Count, unsigned InsertPosIndex); 148 149 /// Finish - Finish anti-dep breaking for a basic block. 150 void FinishBlock(); 151 152 private: 153 typedef std::map<const TargetRegisterClass *, 154 TargetRegisterClass::const_iterator> RenameOrderType; 155 156 /// IsImplicitDefUse - Return true if MO represents a register 157 /// that is both implicitly used and defined in MI 158 bool IsImplicitDefUse(MachineInstr *MI, MachineOperand& MO); 159 160 /// GetPassthruRegs - If MI implicitly def/uses a register, then 161 /// return that register and all subregisters. 162 void GetPassthruRegs(MachineInstr *MI, std::set<unsigned>& PassthruRegs); 163 164 void HandleLastUse(unsigned Reg, unsigned KillIdx, const char *tag, 165 const char *header =NULL, const char *footer =NULL); 166 167 void PrescanInstruction(MachineInstr *MI, unsigned Count, 168 std::set<unsigned>& PassthruRegs); 169 void ScanInstruction(MachineInstr *MI, unsigned Count); 170 BitVector GetRenameRegisters(unsigned Reg); 171 bool FindSuitableFreeRegisters(unsigned AntiDepGroupIndex, 172 RenameOrderType& RenameOrder, 173 std::map<unsigned, unsigned> &RenameMap); 174 }; 175} 176 177#endif 178