1224133Sdim//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==// 2224133Sdim// 3224133Sdim// The LLVM Compiler Infrastructure 4224133Sdim// 5224133Sdim// This file is distributed under the University of Illinois Open Source 6224133Sdim// License. See LICENSE.TXT for details. 7224133Sdim// 8224133Sdim//===----------------------------------------------------------------------===// 9224133Sdim// 10224133Sdim// This file describes the subtarget options of a Target machine. 11224133Sdim// 12224133Sdim//===----------------------------------------------------------------------===// 13224133Sdim 14224133Sdim#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H 15224133Sdim#define LLVM_TARGET_TARGETSUBTARGETINFO_H 16224133Sdim 17224133Sdim#include "llvm/MC/MCSubtargetInfo.h" 18234353Sdim#include "llvm/Support/CodeGen.h" 19224133Sdim 20224133Sdimnamespace llvm { 21224133Sdim 22249423Sdimclass MachineFunction; 23243830Sdimclass MachineInstr; 24224133Sdimclass SDep; 25224133Sdimclass SUnit; 26224133Sdimclass TargetRegisterClass; 27243830Sdimclass TargetSchedModel; 28263508Sdimstruct MachineSchedPolicy; 29224133Sdimtemplate <typename T> class SmallVectorImpl; 30224133Sdim 31224133Sdim//===----------------------------------------------------------------------===// 32224133Sdim/// 33224133Sdim/// TargetSubtargetInfo - Generic base class for all target subtargets. All 34224133Sdim/// Target-specific options that control code generation and printing should 35224133Sdim/// be exposed through a TargetSubtargetInfo-derived class. 36224133Sdim/// 37224133Sdimclass TargetSubtargetInfo : public MCSubtargetInfo { 38243830Sdim TargetSubtargetInfo(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 39243830Sdim void operator=(const TargetSubtargetInfo&) LLVM_DELETED_FUNCTION; 40224133Sdimprotected: // Can only create subclasses... 41224133Sdim TargetSubtargetInfo(); 42224133Sdimpublic: 43224133Sdim // AntiDepBreakMode - Type of anti-dependence breaking that should 44224133Sdim // be performed before post-RA scheduling. 45224133Sdim typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode; 46234353Sdim typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector; 47224133Sdim 48224133Sdim virtual ~TargetSubtargetInfo(); 49224133Sdim 50243830Sdim /// Resolve a SchedClass at runtime, where SchedClass identifies an 51243830Sdim /// MCSchedClassDesc with the isVariant property. This may return the ID of 52243830Sdim /// another variant SchedClass, but repeated invocation must quickly terminate 53243830Sdim /// in a nonvariant SchedClass. 54243830Sdim virtual unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, 55243830Sdim const TargetSchedModel* SchedModel) const { 56243830Sdim return 0; 57243830Sdim } 58224133Sdim 59263508Sdim /// \brief Temporary API to test migration to MI scheduler. 60263508Sdim bool useMachineScheduler() const; 61263508Sdim 62249423Sdim /// \brief True if the subtarget should run MachineScheduler after aggressive 63249423Sdim /// coalescing. 64249423Sdim /// 65249423Sdim /// This currently replaces the SelectionDAG scheduler with the "source" order 66249423Sdim /// scheduler. It does not yet disable the postRA scheduler. 67249423Sdim virtual bool enableMachineScheduler() const; 68249423Sdim 69263508Sdim /// \brief Override generic scheduling policy within a region. 70263508Sdim /// 71263508Sdim /// This is a convenient way for targets that don't provide any custom 72263508Sdim /// scheduling heuristics (no custom MachineSchedStrategy) to make 73263508Sdim /// changes to the generic scheduling policy. 74263508Sdim virtual void overrideSchedPolicy(MachineSchedPolicy &Policy, 75263508Sdim MachineInstr *begin, 76263508Sdim MachineInstr *end, 77263508Sdim unsigned NumRegionInstrs) const {} 78263508Sdim 79224133Sdim // enablePostRAScheduler - If the target can benefit from post-regalloc 80224133Sdim // scheduling and the specified optimization level meets the requirement 81224133Sdim // return true to enable post-register-allocation scheduling. In 82224133Sdim // CriticalPathRCs return any register classes that should only be broken 83243830Sdim // if on the critical path. 84224133Sdim virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 85224133Sdim AntiDepBreakMode& Mode, 86224133Sdim RegClassVector& CriticalPathRCs) const; 87224133Sdim // adjustSchedDependency - Perform target specific adjustments to 88224133Sdim // the latency of a schedule dependency. 89243830Sdim virtual void adjustSchedDependency(SUnit *def, SUnit *use, 90224133Sdim SDep& dep) const { } 91249423Sdim 92263508Sdim /// \brief Enable use of alias analysis during code generation (during MI 93263508Sdim /// scheduling, DAGCombine, etc.). 94263508Sdim virtual bool useAA() const; 95263508Sdim 96249423Sdim /// \brief Reset the features for the subtarget. 97249423Sdim virtual void resetSubtargetFeatures(const MachineFunction *MF) { } 98224133Sdim}; 99224133Sdim 100224133Sdim} // End llvm namespace 101224133Sdim 102224133Sdim#endif 103