1249259Sdim//===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// This file defines all of the ARM-specific intrinsics. 11249259Sdim// 12249259Sdim//===----------------------------------------------------------------------===// 13249259Sdim 14249259Sdim 15249259Sdim//===----------------------------------------------------------------------===// 16249259Sdim// TLS 17249259Sdim 18249259Sdimlet TargetPrefix = "arm" in { // All intrinsics start with "llvm.arm.". 19249259Sdim 20249259Sdimdef int_arm_thread_pointer : GCCBuiltin<"__builtin_thread_pointer">, 21249259Sdim Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>; 22249259Sdim 23249259Sdim//===----------------------------------------------------------------------===// 24249259Sdim// Saturating Arithmentic 25249259Sdim 26249259Sdimdef int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">, 27249259Sdim Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 28249259Sdim [IntrNoMem, Commutative]>; 29249259Sdimdef int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">, 30249259Sdim Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 31249259Sdimdef int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">, 32249259Sdim Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 33249259Sdimdef int_arm_usat : GCCBuiltin<"__builtin_arm_usat">, 34249259Sdim Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; 35249259Sdim 36249259Sdim//===----------------------------------------------------------------------===// 37263508Sdim// Load, Store and Clear exclusive 38249259Sdim 39263508Sdimdef int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>; 40263508Sdimdef int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>; 41263508Sdimdef int_arm_clrex : Intrinsic<[]>; 42263508Sdim 43249259Sdimdef int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, 44263508Sdim llvm_ptr_ty]>; 45263508Sdimdef int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>; 46249259Sdim 47249259Sdim//===----------------------------------------------------------------------===// 48263508Sdim// Data barrier instructions 49263508Sdimdef int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, Intrinsic<[], [llvm_i32_ty]>; 50263508Sdimdef int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, Intrinsic<[], [llvm_i32_ty]>; 51263508Sdim 52263508Sdim//===----------------------------------------------------------------------===// 53249259Sdim// VFP 54249259Sdim 55249259Sdimdef int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">, 56249259Sdim Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>; 57249259Sdimdef int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">, 58249259Sdim Intrinsic<[], [llvm_i32_ty], []>; 59249259Sdimdef int_arm_vcvtr : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], 60249259Sdim [IntrNoMem]>; 61249259Sdimdef int_arm_vcvtru : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty], 62249259Sdim [IntrNoMem]>; 63249259Sdim 64249259Sdim//===----------------------------------------------------------------------===// 65249259Sdim// Coprocessor 66249259Sdim 67249259Sdim// Move to coprocessor 68249259Sdimdef int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">, 69249259Sdim Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 70249259Sdim llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; 71249259Sdimdef int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">, 72249259Sdim Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 73249259Sdim llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; 74249259Sdim 75249259Sdim// Move from coprocessor 76249259Sdimdef int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">, 77249259Sdim Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 78249259Sdim llvm_i32_ty, llvm_i32_ty], []>; 79249259Sdimdef int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">, 80249259Sdim Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 81249259Sdim llvm_i32_ty, llvm_i32_ty], []>; 82249259Sdim 83249259Sdim// Coprocessor data processing 84249259Sdimdef int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">, 85249259Sdim Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 86249259Sdim llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; 87249259Sdimdef int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">, 88249259Sdim Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 89249259Sdim llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; 90249259Sdim 91249259Sdim// Move from two registers to coprocessor 92249259Sdimdef int_arm_mcrr : GCCBuiltin<"__builtin_arm_mcrr">, 93249259Sdim Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 94249259Sdim llvm_i32_ty, llvm_i32_ty], []>; 95249259Sdimdef int_arm_mcrr2 : GCCBuiltin<"__builtin_arm_mcrr2">, 96249259Sdim Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, 97249259Sdim llvm_i32_ty, llvm_i32_ty], []>; 98249259Sdim 99249259Sdim//===----------------------------------------------------------------------===// 100263508Sdim// CRC32 101263508Sdim 102263508Sdimdef int_arm_crc32b : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 103263508Sdim [IntrNoMem]>; 104263508Sdimdef int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 105263508Sdim [IntrNoMem]>; 106263508Sdimdef int_arm_crc32h : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 107263508Sdim [IntrNoMem]>; 108263508Sdimdef int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 109263508Sdim [IntrNoMem]>; 110263508Sdimdef int_arm_crc32w : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 111263508Sdim [IntrNoMem]>; 112263508Sdimdef int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], 113263508Sdim [IntrNoMem]>; 114263508Sdim 115263508Sdim//===----------------------------------------------------------------------===// 116263508Sdim// HINT 117263508Sdimdef int_arm_sevl : Intrinsic<[], []>; 118263508Sdim 119263508Sdim//===----------------------------------------------------------------------===// 120249259Sdim// Advanced SIMD (NEON) 121249259Sdim 122249259Sdim// The following classes do not correspond directly to GCC builtins. 123249259Sdimclass Neon_1Arg_Intrinsic 124249259Sdim : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>; 125249259Sdimclass Neon_1Arg_Narrow_Intrinsic 126249259Sdim : Intrinsic<[llvm_anyvector_ty], 127249259Sdim [LLVMExtendedElementVectorType<0>], [IntrNoMem]>; 128249259Sdimclass Neon_2Arg_Intrinsic 129249259Sdim : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>], 130249259Sdim [IntrNoMem]>; 131249259Sdimclass Neon_2Arg_Narrow_Intrinsic 132249259Sdim : Intrinsic<[llvm_anyvector_ty], 133249259Sdim [LLVMExtendedElementVectorType<0>, 134249259Sdim LLVMExtendedElementVectorType<0>], 135249259Sdim [IntrNoMem]>; 136249259Sdimclass Neon_2Arg_Long_Intrinsic 137249259Sdim : Intrinsic<[llvm_anyvector_ty], 138249259Sdim [LLVMTruncatedElementVectorType<0>, 139249259Sdim LLVMTruncatedElementVectorType<0>], 140249259Sdim [IntrNoMem]>; 141249259Sdimclass Neon_3Arg_Intrinsic 142249259Sdim : Intrinsic<[llvm_anyvector_ty], 143249259Sdim [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 144249259Sdim [IntrNoMem]>; 145249259Sdimclass Neon_3Arg_Long_Intrinsic 146249259Sdim : Intrinsic<[llvm_anyvector_ty], 147249259Sdim [LLVMMatchType<0>, 148249259Sdim LLVMTruncatedElementVectorType<0>, 149249259Sdim LLVMTruncatedElementVectorType<0>], 150249259Sdim [IntrNoMem]>; 151249259Sdimclass Neon_CvtFxToFP_Intrinsic 152249259Sdim : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>; 153249259Sdimclass Neon_CvtFPToFx_Intrinsic 154249259Sdim : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>; 155263508Sdimclass Neon_CvtFPtoInt_1Arg_Intrinsic 156263508Sdim : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>; 157249259Sdim 158249259Sdim// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors. 159249259Sdim// Besides the table, VTBL has one other v8i8 argument and VTBX has two. 160249259Sdim// Overall, the classes range from 2 to 6 v8i8 arguments. 161249259Sdimclass Neon_Tbl2Arg_Intrinsic 162249259Sdim : Intrinsic<[llvm_v8i8_ty], 163249259Sdim [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; 164249259Sdimclass Neon_Tbl3Arg_Intrinsic 165249259Sdim : Intrinsic<[llvm_v8i8_ty], 166249259Sdim [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; 167249259Sdimclass Neon_Tbl4Arg_Intrinsic 168249259Sdim : Intrinsic<[llvm_v8i8_ty], 169249259Sdim [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], 170249259Sdim [IntrNoMem]>; 171249259Sdimclass Neon_Tbl5Arg_Intrinsic 172249259Sdim : Intrinsic<[llvm_v8i8_ty], 173249259Sdim [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, 174249259Sdim llvm_v8i8_ty], [IntrNoMem]>; 175249259Sdimclass Neon_Tbl6Arg_Intrinsic 176249259Sdim : Intrinsic<[llvm_v8i8_ty], 177249259Sdim [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, 178249259Sdim llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>; 179249259Sdim 180249259Sdim// Arithmetic ops 181249259Sdim 182249259Sdimlet Properties = [IntrNoMem, Commutative] in { 183249259Sdim 184249259Sdim // Vector Add. 185249259Sdim def int_arm_neon_vhadds : Neon_2Arg_Intrinsic; 186249259Sdim def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic; 187249259Sdim def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic; 188249259Sdim def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic; 189249259Sdim def int_arm_neon_vqadds : Neon_2Arg_Intrinsic; 190249259Sdim def int_arm_neon_vqaddu : Neon_2Arg_Intrinsic; 191249259Sdim def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic; 192249259Sdim 193249259Sdim // Vector Multiply. 194249259Sdim def int_arm_neon_vmulp : Neon_2Arg_Intrinsic; 195249259Sdim def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic; 196249259Sdim def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic; 197249259Sdim def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic; 198249259Sdim def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic; 199249259Sdim def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic; 200249259Sdim def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic; 201249259Sdim 202249259Sdim // Vector Maximum. 203249259Sdim def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic; 204249259Sdim def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic; 205263508Sdim def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic; 206249259Sdim 207249259Sdim // Vector Minimum. 208249259Sdim def int_arm_neon_vmins : Neon_2Arg_Intrinsic; 209249259Sdim def int_arm_neon_vminu : Neon_2Arg_Intrinsic; 210263508Sdim def int_arm_neon_vminnm : Neon_2Arg_Intrinsic; 211249259Sdim 212249259Sdim // Vector Reciprocal Step. 213249259Sdim def int_arm_neon_vrecps : Neon_2Arg_Intrinsic; 214249259Sdim 215249259Sdim // Vector Reciprocal Square Root Step. 216249259Sdim def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic; 217249259Sdim} 218249259Sdim 219249259Sdim// Vector Subtract. 220249259Sdimdef int_arm_neon_vhsubs : Neon_2Arg_Intrinsic; 221249259Sdimdef int_arm_neon_vhsubu : Neon_2Arg_Intrinsic; 222249259Sdimdef int_arm_neon_vqsubs : Neon_2Arg_Intrinsic; 223249259Sdimdef int_arm_neon_vqsubu : Neon_2Arg_Intrinsic; 224249259Sdimdef int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic; 225249259Sdim 226249259Sdim// Vector Absolute Compare. 227249259Sdimdef int_arm_neon_vacged : Intrinsic<[llvm_v2i32_ty], 228249259Sdim [llvm_v2f32_ty, llvm_v2f32_ty], 229249259Sdim [IntrNoMem]>; 230249259Sdimdef int_arm_neon_vacgeq : Intrinsic<[llvm_v4i32_ty], 231249259Sdim [llvm_v4f32_ty, llvm_v4f32_ty], 232249259Sdim [IntrNoMem]>; 233249259Sdimdef int_arm_neon_vacgtd : Intrinsic<[llvm_v2i32_ty], 234249259Sdim [llvm_v2f32_ty, llvm_v2f32_ty], 235249259Sdim [IntrNoMem]>; 236249259Sdimdef int_arm_neon_vacgtq : Intrinsic<[llvm_v4i32_ty], 237249259Sdim [llvm_v4f32_ty, llvm_v4f32_ty], 238249259Sdim [IntrNoMem]>; 239249259Sdim 240249259Sdim// Vector Absolute Differences. 241249259Sdimdef int_arm_neon_vabds : Neon_2Arg_Intrinsic; 242249259Sdimdef int_arm_neon_vabdu : Neon_2Arg_Intrinsic; 243249259Sdim 244249259Sdim// Vector Pairwise Add. 245249259Sdimdef int_arm_neon_vpadd : Neon_2Arg_Intrinsic; 246249259Sdim 247249259Sdim// Vector Pairwise Add Long. 248249259Sdim// Note: This is different than the other "long" NEON intrinsics because 249249259Sdim// the result vector has half as many elements as the source vector. 250249259Sdim// The source and destination vector types must be specified separately. 251249259Sdimdef int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], 252249259Sdim [IntrNoMem]>; 253249259Sdimdef int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], 254249259Sdim [IntrNoMem]>; 255249259Sdim 256249259Sdim// Vector Pairwise Add and Accumulate Long. 257249259Sdim// Note: This is similar to vpaddl but the destination vector also appears 258249259Sdim// as the first argument. 259249259Sdimdef int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty], 260249259Sdim [LLVMMatchType<0>, llvm_anyvector_ty], 261249259Sdim [IntrNoMem]>; 262249259Sdimdef int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty], 263249259Sdim [LLVMMatchType<0>, llvm_anyvector_ty], 264249259Sdim [IntrNoMem]>; 265249259Sdim 266249259Sdim// Vector Pairwise Maximum and Minimum. 267249259Sdimdef int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic; 268249259Sdimdef int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic; 269249259Sdimdef int_arm_neon_vpmins : Neon_2Arg_Intrinsic; 270249259Sdimdef int_arm_neon_vpminu : Neon_2Arg_Intrinsic; 271249259Sdim 272249259Sdim// Vector Shifts: 273249259Sdim// 274249259Sdim// The various saturating and rounding vector shift operations need to be 275249259Sdim// represented by intrinsics in LLVM, and even the basic VSHL variable shift 276249259Sdim// operation cannot be safely translated to LLVM's shift operators. VSHL can 277249259Sdim// be used for both left and right shifts, or even combinations of the two, 278249259Sdim// depending on the signs of the shift amounts. It also has well-defined 279249259Sdim// behavior for shift amounts that LLVM leaves undefined. Only basic shifts 280249259Sdim// by constants can be represented with LLVM's shift operators. 281249259Sdim// 282249259Sdim// The shift counts for these intrinsics are always vectors, even for constant 283249259Sdim// shifts, where the constant is replicated. For consistency with VSHL (and 284249259Sdim// other variable shift instructions), left shifts have positive shift counts 285249259Sdim// and right shifts have negative shift counts. This convention is also used 286249259Sdim// for constant right shift intrinsics, and to help preserve sanity, the 287249259Sdim// intrinsic names use "shift" instead of either "shl" or "shr". Where 288249259Sdim// applicable, signed and unsigned versions of the intrinsics are 289249259Sdim// distinguished with "s" and "u" suffixes. A few NEON shift instructions, 290249259Sdim// such as VQSHLU, take signed operands but produce unsigned results; these 291249259Sdim// use a "su" suffix. 292249259Sdim 293249259Sdim// Vector Shift. 294249259Sdimdef int_arm_neon_vshifts : Neon_2Arg_Intrinsic; 295249259Sdimdef int_arm_neon_vshiftu : Neon_2Arg_Intrinsic; 296249259Sdimdef int_arm_neon_vshiftls : Neon_2Arg_Long_Intrinsic; 297249259Sdimdef int_arm_neon_vshiftlu : Neon_2Arg_Long_Intrinsic; 298249259Sdimdef int_arm_neon_vshiftn : Neon_2Arg_Narrow_Intrinsic; 299249259Sdim 300249259Sdim// Vector Rounding Shift. 301249259Sdimdef int_arm_neon_vrshifts : Neon_2Arg_Intrinsic; 302249259Sdimdef int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic; 303249259Sdimdef int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic; 304249259Sdim 305249259Sdim// Vector Saturating Shift. 306249259Sdimdef int_arm_neon_vqshifts : Neon_2Arg_Intrinsic; 307249259Sdimdef int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic; 308249259Sdimdef int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic; 309249259Sdimdef int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic; 310249259Sdimdef int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic; 311249259Sdimdef int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic; 312249259Sdim 313249259Sdim// Vector Saturating Rounding Shift. 314249259Sdimdef int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic; 315249259Sdimdef int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic; 316249259Sdimdef int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic; 317249259Sdimdef int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic; 318249259Sdimdef int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic; 319249259Sdim 320249259Sdim// Vector Shift and Insert. 321249259Sdimdef int_arm_neon_vshiftins : Neon_3Arg_Intrinsic; 322249259Sdim 323249259Sdim// Vector Absolute Value and Saturating Absolute Value. 324249259Sdimdef int_arm_neon_vabs : Neon_1Arg_Intrinsic; 325249259Sdimdef int_arm_neon_vqabs : Neon_1Arg_Intrinsic; 326249259Sdim 327249259Sdim// Vector Saturating Negate. 328249259Sdimdef int_arm_neon_vqneg : Neon_1Arg_Intrinsic; 329249259Sdim 330249259Sdim// Vector Count Leading Sign/Zero Bits. 331249259Sdimdef int_arm_neon_vcls : Neon_1Arg_Intrinsic; 332249259Sdimdef int_arm_neon_vclz : Neon_1Arg_Intrinsic; 333249259Sdim 334249259Sdim// Vector Count One Bits. 335249259Sdimdef int_arm_neon_vcnt : Neon_1Arg_Intrinsic; 336249259Sdim 337249259Sdim// Vector Reciprocal Estimate. 338249259Sdimdef int_arm_neon_vrecpe : Neon_1Arg_Intrinsic; 339249259Sdim 340249259Sdim// Vector Reciprocal Square Root Estimate. 341249259Sdimdef int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic; 342249259Sdim 343263508Sdim// Vector Conversions Between Floating-point and Integer 344263508Sdimdef int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic; 345263508Sdimdef int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic; 346263508Sdimdef int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic; 347263508Sdimdef int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic; 348263508Sdimdef int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic; 349263508Sdimdef int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic; 350263508Sdimdef int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic; 351263508Sdimdef int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic; 352263508Sdim 353249259Sdim// Vector Conversions Between Floating-point and Fixed-point. 354249259Sdimdef int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic; 355249259Sdimdef int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic; 356249259Sdimdef int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic; 357249259Sdimdef int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic; 358249259Sdim 359249259Sdim// Vector Conversions Between Half-Precision and Single-Precision. 360249259Sdimdef int_arm_neon_vcvtfp2hf 361249259Sdim : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>; 362249259Sdimdef int_arm_neon_vcvthf2fp 363249259Sdim : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>; 364249259Sdim 365249259Sdim// Narrowing Saturating Vector Moves. 366249259Sdimdef int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic; 367249259Sdimdef int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic; 368249259Sdimdef int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic; 369249259Sdim 370249259Sdim// Vector Table Lookup. 371249259Sdim// The first 1-4 arguments are the table. 372249259Sdimdef int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic; 373249259Sdimdef int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic; 374249259Sdimdef int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic; 375249259Sdimdef int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic; 376249259Sdim 377249259Sdim// Vector Table Extension. 378249259Sdim// Some elements of the destination vector may not be updated, so the original 379249259Sdim// value of that vector is passed as the first argument. The next 1-4 380249259Sdim// arguments after that are the table. 381249259Sdimdef int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic; 382249259Sdimdef int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic; 383249259Sdimdef int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic; 384249259Sdimdef int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic; 385249259Sdim 386263508Sdim// Vector Rounding 387263508Sdimdef int_arm_neon_vrintn : Neon_1Arg_Intrinsic; 388263508Sdimdef int_arm_neon_vrintx : Neon_1Arg_Intrinsic; 389263508Sdimdef int_arm_neon_vrinta : Neon_1Arg_Intrinsic; 390263508Sdimdef int_arm_neon_vrintz : Neon_1Arg_Intrinsic; 391263508Sdimdef int_arm_neon_vrintm : Neon_1Arg_Intrinsic; 392263508Sdimdef int_arm_neon_vrintp : Neon_1Arg_Intrinsic; 393263508Sdim 394249259Sdim// De-interleaving vector loads from N-element structures. 395249259Sdim// Source operands are the address and alignment. 396249259Sdimdef int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty], 397249259Sdim [llvm_ptr_ty, llvm_i32_ty], 398249259Sdim [IntrReadArgMem]>; 399249259Sdimdef int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 400249259Sdim [llvm_ptr_ty, llvm_i32_ty], 401249259Sdim [IntrReadArgMem]>; 402249259Sdimdef int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 403249259Sdim LLVMMatchType<0>], 404249259Sdim [llvm_ptr_ty, llvm_i32_ty], 405249259Sdim [IntrReadArgMem]>; 406249259Sdimdef int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 407249259Sdim LLVMMatchType<0>, LLVMMatchType<0>], 408249259Sdim [llvm_ptr_ty, llvm_i32_ty], 409249259Sdim [IntrReadArgMem]>; 410249259Sdim 411249259Sdim// Vector load N-element structure to one lane. 412249259Sdim// Source operands are: the address, the N input vectors (since only one 413249259Sdim// lane is assigned), the lane number, and the alignment. 414249259Sdimdef int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], 415249259Sdim [llvm_ptr_ty, LLVMMatchType<0>, 416249259Sdim LLVMMatchType<0>, llvm_i32_ty, 417249259Sdim llvm_i32_ty], [IntrReadArgMem]>; 418249259Sdimdef int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 419249259Sdim LLVMMatchType<0>], 420249259Sdim [llvm_ptr_ty, LLVMMatchType<0>, 421249259Sdim LLVMMatchType<0>, LLVMMatchType<0>, 422249259Sdim llvm_i32_ty, llvm_i32_ty], 423249259Sdim [IntrReadArgMem]>; 424249259Sdimdef int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, 425249259Sdim LLVMMatchType<0>, LLVMMatchType<0>], 426249259Sdim [llvm_ptr_ty, LLVMMatchType<0>, 427249259Sdim LLVMMatchType<0>, LLVMMatchType<0>, 428249259Sdim LLVMMatchType<0>, llvm_i32_ty, 429249259Sdim llvm_i32_ty], [IntrReadArgMem]>; 430249259Sdim 431249259Sdim// Interleaving vector stores from N-element structures. 432249259Sdim// Source operands are: the address, the N vectors, and the alignment. 433249259Sdimdef int_arm_neon_vst1 : Intrinsic<[], 434249259Sdim [llvm_ptr_ty, llvm_anyvector_ty, 435249259Sdim llvm_i32_ty], [IntrReadWriteArgMem]>; 436249259Sdimdef int_arm_neon_vst2 : Intrinsic<[], 437249259Sdim [llvm_ptr_ty, llvm_anyvector_ty, 438249259Sdim LLVMMatchType<0>, llvm_i32_ty], 439249259Sdim [IntrReadWriteArgMem]>; 440249259Sdimdef int_arm_neon_vst3 : Intrinsic<[], 441249259Sdim [llvm_ptr_ty, llvm_anyvector_ty, 442249259Sdim LLVMMatchType<0>, LLVMMatchType<0>, 443249259Sdim llvm_i32_ty], [IntrReadWriteArgMem]>; 444249259Sdimdef int_arm_neon_vst4 : Intrinsic<[], 445249259Sdim [llvm_ptr_ty, llvm_anyvector_ty, 446249259Sdim LLVMMatchType<0>, LLVMMatchType<0>, 447249259Sdim LLVMMatchType<0>, llvm_i32_ty], 448249259Sdim [IntrReadWriteArgMem]>; 449249259Sdim 450249259Sdim// Vector store N-element structure from one lane. 451249259Sdim// Source operands are: the address, the N vectors, the lane number, and 452249259Sdim// the alignment. 453249259Sdimdef int_arm_neon_vst2lane : Intrinsic<[], 454249259Sdim [llvm_ptr_ty, llvm_anyvector_ty, 455249259Sdim LLVMMatchType<0>, llvm_i32_ty, 456249259Sdim llvm_i32_ty], [IntrReadWriteArgMem]>; 457249259Sdimdef int_arm_neon_vst3lane : Intrinsic<[], 458249259Sdim [llvm_ptr_ty, llvm_anyvector_ty, 459249259Sdim LLVMMatchType<0>, LLVMMatchType<0>, 460249259Sdim llvm_i32_ty, llvm_i32_ty], 461249259Sdim [IntrReadWriteArgMem]>; 462249259Sdimdef int_arm_neon_vst4lane : Intrinsic<[], 463249259Sdim [llvm_ptr_ty, llvm_anyvector_ty, 464249259Sdim LLVMMatchType<0>, LLVMMatchType<0>, 465249259Sdim LLVMMatchType<0>, llvm_i32_ty, 466249259Sdim llvm_i32_ty], [IntrReadWriteArgMem]>; 467249259Sdim 468249259Sdim// Vector bitwise select. 469249259Sdimdef int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty], 470249259Sdim [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], 471249259Sdim [IntrNoMem]>; 472249259Sdim 473263508Sdim 474263508Sdim// Crypto instructions 475263508Sdimdef int_arm_neon_aesd : Neon_2Arg_Intrinsic; 476263508Sdimdef int_arm_neon_aese : Neon_2Arg_Intrinsic; 477263508Sdimdef int_arm_neon_aesimc : Neon_1Arg_Intrinsic; 478263508Sdimdef int_arm_neon_aesmc : Neon_1Arg_Intrinsic; 479263508Sdimdef int_arm_neon_sha1h : Neon_1Arg_Intrinsic; 480263508Sdimdef int_arm_neon_sha1su1 : Neon_2Arg_Intrinsic; 481263508Sdimdef int_arm_neon_sha256su0 : Neon_2Arg_Intrinsic; 482263508Sdimdef int_arm_neon_sha1c : Neon_3Arg_Intrinsic; 483263508Sdimdef int_arm_neon_sha1m : Neon_3Arg_Intrinsic; 484263508Sdimdef int_arm_neon_sha1p : Neon_3Arg_Intrinsic; 485263508Sdimdef int_arm_neon_sha1su0: Neon_3Arg_Intrinsic; 486263508Sdimdef int_arm_neon_sha256h: Neon_3Arg_Intrinsic; 487263508Sdimdef int_arm_neon_sha256h2: Neon_3Arg_Intrinsic; 488263508Sdimdef int_arm_neon_sha256su1: Neon_3Arg_Intrinsic; 489263508Sdim 490249259Sdim} // end TargetPrefix 491