1193323Sed//===-- llvm/CodeGen/MachineOperand.h - MachineOperand class ----*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the declaration of the MachineOperand class. 11193323Sed// 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sed#ifndef LLVM_CODEGEN_MACHINEOPERAND_H 15193323Sed#define LLVM_CODEGEN_MACHINEOPERAND_H 16193323Sed 17218893Sdim#include "llvm/Support/DataTypes.h" 18193323Sed#include <cassert> 19193323Sed 20193323Sednamespace llvm { 21218893Sdim 22204642Srdivackyclass BlockAddress; 23193323Sedclass ConstantFP; 24224145Sdimclass ConstantInt; 25204642Srdivackyclass GlobalValue; 26193323Sedclass MachineBasicBlock; 27193323Sedclass MachineInstr; 28193323Sedclass MachineRegisterInfo; 29202375Srdivackyclass MDNode; 30204642Srdivackyclass TargetMachine; 31210299Sedclass TargetRegisterInfo; 32243830Sdimclass hash_code; 33193323Sedclass raw_ostream; 34205218Srdivackyclass MCSymbol; 35218893Sdim 36193323Sed/// MachineOperand class - Representation of each machine instruction operand. 37193323Sed/// 38249423Sdim/// This class isn't a POD type because it has a private constructor, but its 39249423Sdim/// destructor must be trivial. Functions like MachineInstr::addOperand(), 40249423Sdim/// MachineRegisterInfo::moveOperands(), and MF::DeleteMachineInstr() depend on 41249423Sdim/// not having to call the MachineOperand destructor. 42249423Sdim/// 43193323Sedclass MachineOperand { 44193323Sedpublic: 45193323Sed enum MachineOperandType { 46194612Sed MO_Register, ///< Register operand. 47194612Sed MO_Immediate, ///< Immediate operand 48224145Sdim MO_CImmediate, ///< Immediate >64bit operand 49194612Sed MO_FPImmediate, ///< Floating-point immediate operand 50194612Sed MO_MachineBasicBlock, ///< MachineBasicBlock reference 51194612Sed MO_FrameIndex, ///< Abstract Stack Frame Index 52194612Sed MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool 53239462Sdim MO_TargetIndex, ///< Target-dependent index+offset operand. 54194612Sed MO_JumpTableIndex, ///< Address of indexed Jump Table for switch 55194612Sed MO_ExternalSymbol, ///< Name of external global symbol 56195340Sed MO_GlobalAddress, ///< Address of a global value 57202375Srdivacky MO_BlockAddress, ///< Address of a basic block 58234353Sdim MO_RegisterMask, ///< Mask of preserved registers. 59205218Srdivacky MO_Metadata, ///< Metadata reference (for debug info) 60205218Srdivacky MO_MCSymbol ///< MCSymbol reference (for debug/eh info) 61193323Sed }; 62193323Sed 63193323Sedprivate: 64193323Sed /// OpKind - Specify what kind of operand this is. This discriminates the 65193323Sed /// union. 66195098Sed unsigned char OpKind; // MachineOperandType 67218893Sdim 68249423Sdim /// Subregister number for MO_Register. A value of 0 indicates the 69249423Sdim /// MO_Register has no subReg. 70249423Sdim /// 71249423Sdim /// For all other kinds of operands, this field holds target-specific flags. 72249423Sdim unsigned SubReg_TargetFlags : 12; 73218893Sdim 74243830Sdim /// TiedTo - Non-zero when this register operand is tied to another register 75243830Sdim /// operand. The encoding of this field is described in the block comment 76243830Sdim /// before MachineInstr::tieOperands(). 77243830Sdim unsigned char TiedTo : 4; 78243830Sdim 79193323Sed /// IsDef/IsImp/IsKill/IsDead flags - These are only valid for MO_Register 80193323Sed /// operands. 81218893Sdim 82193323Sed /// IsDef - True if this is a def, false if this is a use of the register. 83193323Sed /// 84193323Sed bool IsDef : 1; 85218893Sdim 86193323Sed /// IsImp - True if this is an implicit def or use, false if it is explicit. 87193323Sed /// 88193323Sed bool IsImp : 1; 89193323Sed 90193323Sed /// IsKill - True if this instruction is the last use of the register on this 91193323Sed /// path through the function. This is only valid on uses of registers. 92193323Sed bool IsKill : 1; 93193323Sed 94193323Sed /// IsDead - True if this register is never used by a subsequent instruction. 95193323Sed /// This is only valid on definitions of registers. 96193323Sed bool IsDead : 1; 97193323Sed 98226633Sdim /// IsUndef - True if this register operand reads an "undef" value, i.e. the 99226633Sdim /// read value doesn't matter. This flag can be set on both use and def 100226633Sdim /// operands. On a sub-register def operand, it refers to the part of the 101226633Sdim /// register that isn't written. On a full-register def operand, it is a 102226633Sdim /// noop. See readsReg(). 103226633Sdim /// 104226633Sdim /// This is only valid on registers. 105226633Sdim /// 106226633Sdim /// Note that an instruction may have multiple <undef> operands referring to 107226633Sdim /// the same register. In that case, the instruction may depend on those 108226633Sdim /// operands reading the same dont-care value. For example: 109226633Sdim /// 110226633Sdim /// %vreg1<def> = XOR %vreg2<undef>, %vreg2<undef> 111226633Sdim /// 112226633Sdim /// Any register can be used for %vreg2, and its value doesn't matter, but 113226633Sdim /// the two operands must be the same register. 114226633Sdim /// 115195340Sed bool IsUndef : 1; 116195340Sed 117234353Sdim /// IsInternalRead - True if this operand reads a value that was defined 118234353Sdim /// inside the same instruction or bundle. This flag can be set on both use 119234353Sdim /// and def operands. On a sub-register def operand, it refers to the part 120234353Sdim /// of the register that isn't written. On a full-register def operand, it 121234353Sdim /// is a noop. 122234353Sdim /// 123234353Sdim /// When this flag is set, the instruction bundle must contain at least one 124234353Sdim /// other def of the register. If multiple instructions in the bundle define 125234353Sdim /// the register, the meaning is target-defined. 126234353Sdim bool IsInternalRead : 1; 127234353Sdim 128193323Sed /// IsEarlyClobber - True if this MO_Register 'def' operand is written to 129193323Sed /// by the MachineInstr before all input registers are read. This is used to 130193323Sed /// model the GCC inline asm '&' constraint modifier. 131193323Sed bool IsEarlyClobber : 1; 132193323Sed 133203954Srdivacky /// IsDebug - True if this MO_Register 'use' operand is in a debug pseudo, 134203954Srdivacky /// not a real instruction. Such uses should be ignored during codegen. 135203954Srdivacky bool IsDebug : 1; 136203954Srdivacky 137223017Sdim /// SmallContents - This really should be part of the Contents union, but 138223017Sdim /// lives out here so we can get a better packed struct. 139218893Sdim /// MO_Register: Register number. 140218893Sdim /// OffsetedInfo: Low bits of offset. 141218893Sdim union { 142218893Sdim unsigned RegNo; // For MO_Register. 143218893Sdim unsigned OffsetLo; // Matches Contents.OffsetedInfo.OffsetHi. 144218893Sdim } SmallContents; 145218893Sdim 146218893Sdim /// ParentMI - This is the instruction that this operand is embedded into. 147193323Sed /// This is valid for all operand types, when the operand is in an instr. 148193323Sed MachineInstr *ParentMI; 149193323Sed 150193323Sed /// Contents union - This contains the payload for the various operand types. 151193323Sed union { 152193323Sed MachineBasicBlock *MBB; // For MO_MachineBasicBlock. 153193323Sed const ConstantFP *CFP; // For MO_FPImmediate. 154224145Sdim const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit. 155193323Sed int64_t ImmVal; // For MO_Immediate. 156234353Sdim const uint32_t *RegMask; // For MO_RegisterMask. 157204642Srdivacky const MDNode *MD; // For MO_Metadata. 158205218Srdivacky MCSymbol *Sym; // For MO_MCSymbol 159193323Sed 160193323Sed struct { // For MO_Register. 161218893Sdim // Register number is in SmallContents.RegNo. 162239462Sdim MachineOperand *Prev; // Access list for register. See MRI. 163193323Sed MachineOperand *Next; 164193323Sed } Reg; 165218893Sdim 166193323Sed /// OffsetedInfo - This struct contains the offset and an object identifier. 167193323Sed /// this represent the object as with an optional offset from it. 168193323Sed struct { 169193323Sed union { 170193323Sed int Index; // For MO_*Index - The index itself. 171193323Sed const char *SymbolName; // For MO_ExternalSymbol. 172207618Srdivacky const GlobalValue *GV; // For MO_GlobalAddress. 173207618Srdivacky const BlockAddress *BA; // For MO_BlockAddress. 174193323Sed } Val; 175218893Sdim // Low bits of offset are in SmallContents.OffsetLo. 176218893Sdim int OffsetHi; // An offset from the object, high 32 bits. 177193323Sed } OffsetedInfo; 178193323Sed } Contents; 179218893Sdim 180249423Sdim explicit MachineOperand(MachineOperandType K) 181249423Sdim : OpKind(K), SubReg_TargetFlags(0), ParentMI(0) {} 182193323Sedpublic: 183193323Sed /// getType - Returns the MachineOperandType for this operand. 184193323Sed /// 185195098Sed MachineOperandType getType() const { return (MachineOperandType)OpKind; } 186218893Sdim 187249423Sdim unsigned getTargetFlags() const { 188249423Sdim return isReg() ? 0 : SubReg_TargetFlags; 189243830Sdim } 190249423Sdim void setTargetFlags(unsigned F) { 191243830Sdim assert(!isReg() && "Register operands can't have target flags"); 192249423Sdim SubReg_TargetFlags = F; 193249423Sdim assert(SubReg_TargetFlags == F && "Target flags out of range"); 194243830Sdim } 195249423Sdim void addTargetFlag(unsigned F) { 196243830Sdim assert(!isReg() && "Register operands can't have target flags"); 197249423Sdim SubReg_TargetFlags |= F; 198249423Sdim assert((SubReg_TargetFlags & F) && "Target flags out of range"); 199243830Sdim } 200193323Sed 201218893Sdim 202193323Sed /// getParent - Return the instruction that this operand belongs to. 203193323Sed /// 204193323Sed MachineInstr *getParent() { return ParentMI; } 205193323Sed const MachineInstr *getParent() const { return ParentMI; } 206218893Sdim 207218893Sdim /// clearParent - Reset the parent pointer. 208218893Sdim /// 209218893Sdim /// The MachineOperand copy constructor also copies ParentMI, expecting the 210218893Sdim /// original to be deleted. If a MachineOperand is ever stored outside a 211218893Sdim /// MachineInstr, the parent pointer must be cleared. 212218893Sdim /// 213218893Sdim /// Never call clearParent() on an operand in a MachineInstr. 214218893Sdim /// 215218893Sdim void clearParent() { ParentMI = 0; } 216218893Sdim 217193323Sed void print(raw_ostream &os, const TargetMachine *TM = 0) const; 218193323Sed 219193323Sed //===--------------------------------------------------------------------===// 220193323Sed // Accessors that tell you what kind of MachineOperand you're looking at. 221193323Sed //===--------------------------------------------------------------------===// 222193323Sed 223193323Sed /// isReg - Tests if this is a MO_Register operand. 224193323Sed bool isReg() const { return OpKind == MO_Register; } 225193323Sed /// isImm - Tests if this is a MO_Immediate operand. 226193323Sed bool isImm() const { return OpKind == MO_Immediate; } 227224145Sdim /// isCImm - Test if t his is a MO_CImmediate operand. 228224145Sdim bool isCImm() const { return OpKind == MO_CImmediate; } 229193323Sed /// isFPImm - Tests if this is a MO_FPImmediate operand. 230193323Sed bool isFPImm() const { return OpKind == MO_FPImmediate; } 231193323Sed /// isMBB - Tests if this is a MO_MachineBasicBlock operand. 232193323Sed bool isMBB() const { return OpKind == MO_MachineBasicBlock; } 233193323Sed /// isFI - Tests if this is a MO_FrameIndex operand. 234193323Sed bool isFI() const { return OpKind == MO_FrameIndex; } 235193323Sed /// isCPI - Tests if this is a MO_ConstantPoolIndex operand. 236193323Sed bool isCPI() const { return OpKind == MO_ConstantPoolIndex; } 237239462Sdim /// isTargetIndex - Tests if this is a MO_TargetIndex operand. 238239462Sdim bool isTargetIndex() const { return OpKind == MO_TargetIndex; } 239193323Sed /// isJTI - Tests if this is a MO_JumpTableIndex operand. 240193323Sed bool isJTI() const { return OpKind == MO_JumpTableIndex; } 241193323Sed /// isGlobal - Tests if this is a MO_GlobalAddress operand. 242193323Sed bool isGlobal() const { return OpKind == MO_GlobalAddress; } 243193323Sed /// isSymbol - Tests if this is a MO_ExternalSymbol operand. 244193323Sed bool isSymbol() const { return OpKind == MO_ExternalSymbol; } 245198892Srdivacky /// isBlockAddress - Tests if this is a MO_BlockAddress operand. 246198892Srdivacky bool isBlockAddress() const { return OpKind == MO_BlockAddress; } 247234353Sdim /// isRegMask - Tests if this is a MO_RegisterMask operand. 248234353Sdim bool isRegMask() const { return OpKind == MO_RegisterMask; } 249202375Srdivacky /// isMetadata - Tests if this is a MO_Metadata operand. 250202375Srdivacky bool isMetadata() const { return OpKind == MO_Metadata; } 251205218Srdivacky bool isMCSymbol() const { return OpKind == MO_MCSymbol; } 252193323Sed 253234353Sdim 254193323Sed //===--------------------------------------------------------------------===// 255193323Sed // Accessors for Register Operands 256193323Sed //===--------------------------------------------------------------------===// 257193323Sed 258193323Sed /// getReg - Returns the register number. 259193323Sed unsigned getReg() const { 260193323Sed assert(isReg() && "This is not a register operand!"); 261218893Sdim return SmallContents.RegNo; 262193323Sed } 263218893Sdim 264193323Sed unsigned getSubReg() const { 265193323Sed assert(isReg() && "Wrong MachineOperand accessor"); 266249423Sdim return SubReg_TargetFlags; 267193323Sed } 268218893Sdim 269218893Sdim bool isUse() const { 270193323Sed assert(isReg() && "Wrong MachineOperand accessor"); 271193323Sed return !IsDef; 272193323Sed } 273218893Sdim 274193323Sed bool isDef() const { 275193323Sed assert(isReg() && "Wrong MachineOperand accessor"); 276193323Sed return IsDef; 277193323Sed } 278218893Sdim 279218893Sdim bool isImplicit() const { 280193323Sed assert(isReg() && "Wrong MachineOperand accessor"); 281193323Sed return IsImp; 282193323Sed } 283218893Sdim 284193323Sed bool isDead() const { 285193323Sed assert(isReg() && "Wrong MachineOperand accessor"); 286193323Sed return IsDead; 287193323Sed } 288218893Sdim 289193323Sed bool isKill() const { 290193323Sed assert(isReg() && "Wrong MachineOperand accessor"); 291193323Sed return IsKill; 292193323Sed } 293218893Sdim 294195340Sed bool isUndef() const { 295195340Sed assert(isReg() && "Wrong MachineOperand accessor"); 296195340Sed return IsUndef; 297195340Sed } 298218893Sdim 299234353Sdim bool isInternalRead() const { 300234353Sdim assert(isReg() && "Wrong MachineOperand accessor"); 301234353Sdim return IsInternalRead; 302234353Sdim } 303234353Sdim 304193323Sed bool isEarlyClobber() const { 305193323Sed assert(isReg() && "Wrong MachineOperand accessor"); 306193323Sed return IsEarlyClobber; 307193323Sed } 308193323Sed 309243830Sdim bool isTied() const { 310243830Sdim assert(isReg() && "Wrong MachineOperand accessor"); 311243830Sdim return TiedTo; 312243830Sdim } 313243830Sdim 314203954Srdivacky bool isDebug() const { 315203954Srdivacky assert(isReg() && "Wrong MachineOperand accessor"); 316203954Srdivacky return IsDebug; 317203954Srdivacky } 318203954Srdivacky 319226633Sdim /// readsReg - Returns true if this operand reads the previous value of its 320226633Sdim /// register. A use operand with the <undef> flag set doesn't read its 321226633Sdim /// register. A sub-register def implicitly reads the other parts of the 322226633Sdim /// register being redefined unless the <undef> flag is set. 323234353Sdim /// 324234353Sdim /// This refers to reading the register value from before the current 325234353Sdim /// instruction or bundle. Internal bundle reads are not included. 326226633Sdim bool readsReg() const { 327226633Sdim assert(isReg() && "Wrong MachineOperand accessor"); 328234353Sdim return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); 329226633Sdim } 330226633Sdim 331193323Sed //===--------------------------------------------------------------------===// 332193323Sed // Mutators for Register Operands 333193323Sed //===--------------------------------------------------------------------===// 334218893Sdim 335193323Sed /// Change the register this operand corresponds to. 336193323Sed /// 337193323Sed void setReg(unsigned Reg); 338218893Sdim 339193323Sed void setSubReg(unsigned subReg) { 340193323Sed assert(isReg() && "Wrong MachineOperand accessor"); 341249423Sdim SubReg_TargetFlags = subReg; 342249423Sdim assert(SubReg_TargetFlags == subReg && "SubReg out of range"); 343193323Sed } 344210299Sed 345210299Sed /// substVirtReg - Substitute the current register with the virtual 346210299Sed /// subregister Reg:SubReg. Take any existing SubReg index into account, 347210299Sed /// using TargetRegisterInfo to compose the subreg indices if necessary. 348210299Sed /// Reg must be a virtual register, SubIdx can be 0. 349210299Sed /// 350210299Sed void substVirtReg(unsigned Reg, unsigned SubIdx, const TargetRegisterInfo&); 351210299Sed 352210299Sed /// substPhysReg - Substitute the current register with the physical register 353210299Sed /// Reg, taking any existing SubReg into account. For instance, 354210299Sed /// substPhysReg(%EAX) will change %reg1024:sub_8bit to %AL. 355210299Sed /// 356210299Sed void substPhysReg(unsigned Reg, const TargetRegisterInfo&); 357210299Sed 358239462Sdim void setIsUse(bool Val = true) { setIsDef(!Val); } 359218893Sdim 360239462Sdim void setIsDef(bool Val = true); 361193323Sed 362218893Sdim void setImplicit(bool Val = true) { 363193323Sed assert(isReg() && "Wrong MachineOperand accessor"); 364193323Sed IsImp = Val; 365193323Sed } 366193323Sed 367193323Sed void setIsKill(bool Val = true) { 368193323Sed assert(isReg() && !IsDef && "Wrong MachineOperand accessor"); 369203954Srdivacky assert((!Val || !isDebug()) && "Marking a debug operation as kill"); 370193323Sed IsKill = Val; 371193323Sed } 372218893Sdim 373193323Sed void setIsDead(bool Val = true) { 374193323Sed assert(isReg() && IsDef && "Wrong MachineOperand accessor"); 375193323Sed IsDead = Val; 376193323Sed } 377193323Sed 378195340Sed void setIsUndef(bool Val = true) { 379195340Sed assert(isReg() && "Wrong MachineOperand accessor"); 380195340Sed IsUndef = Val; 381195340Sed } 382218893Sdim 383234353Sdim void setIsInternalRead(bool Val = true) { 384234353Sdim assert(isReg() && "Wrong MachineOperand accessor"); 385234353Sdim IsInternalRead = Val; 386234353Sdim } 387234353Sdim 388193323Sed void setIsEarlyClobber(bool Val = true) { 389193323Sed assert(isReg() && IsDef && "Wrong MachineOperand accessor"); 390193323Sed IsEarlyClobber = Val; 391193323Sed } 392193323Sed 393206083Srdivacky void setIsDebug(bool Val = true) { 394263508Sdim assert(isReg() && !IsDef && "Wrong MachineOperand accessor"); 395206083Srdivacky IsDebug = Val; 396206083Srdivacky } 397206083Srdivacky 398193323Sed //===--------------------------------------------------------------------===// 399193323Sed // Accessors for various operand types. 400193323Sed //===--------------------------------------------------------------------===// 401218893Sdim 402193323Sed int64_t getImm() const { 403193323Sed assert(isImm() && "Wrong MachineOperand accessor"); 404193323Sed return Contents.ImmVal; 405193323Sed } 406218893Sdim 407224145Sdim const ConstantInt *getCImm() const { 408224145Sdim assert(isCImm() && "Wrong MachineOperand accessor"); 409224145Sdim return Contents.CI; 410224145Sdim } 411224145Sdim 412193323Sed const ConstantFP *getFPImm() const { 413193323Sed assert(isFPImm() && "Wrong MachineOperand accessor"); 414193323Sed return Contents.CFP; 415193323Sed } 416218893Sdim 417193323Sed MachineBasicBlock *getMBB() const { 418193323Sed assert(isMBB() && "Wrong MachineOperand accessor"); 419193323Sed return Contents.MBB; 420193323Sed } 421193323Sed 422193323Sed int getIndex() const { 423239462Sdim assert((isFI() || isCPI() || isTargetIndex() || isJTI()) && 424193323Sed "Wrong MachineOperand accessor"); 425193323Sed return Contents.OffsetedInfo.Val.Index; 426193323Sed } 427218893Sdim 428207618Srdivacky const GlobalValue *getGlobal() const { 429193323Sed assert(isGlobal() && "Wrong MachineOperand accessor"); 430193323Sed return Contents.OffsetedInfo.Val.GV; 431193323Sed } 432198892Srdivacky 433207618Srdivacky const BlockAddress *getBlockAddress() const { 434198892Srdivacky assert(isBlockAddress() && "Wrong MachineOperand accessor"); 435198892Srdivacky return Contents.OffsetedInfo.Val.BA; 436195340Sed } 437205218Srdivacky 438205218Srdivacky MCSymbol *getMCSymbol() const { 439205218Srdivacky assert(isMCSymbol() && "Wrong MachineOperand accessor"); 440205218Srdivacky return Contents.Sym; 441205218Srdivacky } 442218893Sdim 443198090Srdivacky /// getOffset - Return the offset from the symbol in this operand. This always 444198090Srdivacky /// returns 0 for ExternalSymbol operands. 445193323Sed int64_t getOffset() const { 446239462Sdim assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() || 447239462Sdim isBlockAddress()) && "Wrong MachineOperand accessor"); 448243830Sdim return int64_t(uint64_t(Contents.OffsetedInfo.OffsetHi) << 32) | 449218893Sdim SmallContents.OffsetLo; 450193323Sed } 451218893Sdim 452193323Sed const char *getSymbolName() const { 453193323Sed assert(isSymbol() && "Wrong MachineOperand accessor"); 454193323Sed return Contents.OffsetedInfo.Val.SymbolName; 455193323Sed } 456202375Srdivacky 457234353Sdim /// clobbersPhysReg - Returns true if this RegMask clobbers PhysReg. 458234353Sdim /// It is sometimes necessary to detach the register mask pointer from its 459234353Sdim /// machine operand. This static method can be used for such detached bit 460234353Sdim /// mask pointers. 461234353Sdim static bool clobbersPhysReg(const uint32_t *RegMask, unsigned PhysReg) { 462234353Sdim // See TargetRegisterInfo.h. 463234353Sdim assert(PhysReg < (1u << 30) && "Not a physical register"); 464234353Sdim return !(RegMask[PhysReg / 32] & (1u << PhysReg % 32)); 465234353Sdim } 466234353Sdim 467234353Sdim /// clobbersPhysReg - Returns true if this RegMask operand clobbers PhysReg. 468234353Sdim bool clobbersPhysReg(unsigned PhysReg) const { 469234353Sdim return clobbersPhysReg(getRegMask(), PhysReg); 470234353Sdim } 471234353Sdim 472234353Sdim /// getRegMask - Returns a bit mask of registers preserved by this RegMask 473234353Sdim /// operand. 474234353Sdim const uint32_t *getRegMask() const { 475234353Sdim assert(isRegMask() && "Wrong MachineOperand accessor"); 476234353Sdim return Contents.RegMask; 477234353Sdim } 478234353Sdim 479202375Srdivacky const MDNode *getMetadata() const { 480202375Srdivacky assert(isMetadata() && "Wrong MachineOperand accessor"); 481202375Srdivacky return Contents.MD; 482202375Srdivacky } 483218893Sdim 484193323Sed //===--------------------------------------------------------------------===// 485193323Sed // Mutators for various operand types. 486193323Sed //===--------------------------------------------------------------------===// 487218893Sdim 488193323Sed void setImm(int64_t immVal) { 489193323Sed assert(isImm() && "Wrong MachineOperand mutator"); 490193323Sed Contents.ImmVal = immVal; 491193323Sed } 492193323Sed 493193323Sed void setOffset(int64_t Offset) { 494239462Sdim assert((isGlobal() || isSymbol() || isCPI() || isTargetIndex() || 495239462Sdim isBlockAddress()) && "Wrong MachineOperand accessor"); 496218893Sdim SmallContents.OffsetLo = unsigned(Offset); 497218893Sdim Contents.OffsetedInfo.OffsetHi = int(Offset >> 32); 498193323Sed } 499218893Sdim 500193323Sed void setIndex(int Idx) { 501239462Sdim assert((isFI() || isCPI() || isTargetIndex() || isJTI()) && 502193323Sed "Wrong MachineOperand accessor"); 503193323Sed Contents.OffsetedInfo.Val.Index = Idx; 504193323Sed } 505218893Sdim 506193323Sed void setMBB(MachineBasicBlock *MBB) { 507193323Sed assert(isMBB() && "Wrong MachineOperand accessor"); 508193323Sed Contents.MBB = MBB; 509193323Sed } 510218893Sdim 511193323Sed //===--------------------------------------------------------------------===// 512193323Sed // Other methods. 513193323Sed //===--------------------------------------------------------------------===// 514218893Sdim 515193323Sed /// isIdenticalTo - Return true if this operand is identical to the specified 516193323Sed /// operand. Note: This method ignores isKill and isDead properties. 517193323Sed bool isIdenticalTo(const MachineOperand &Other) const; 518218893Sdim 519239462Sdim /// \brief MachineOperand hash_value overload. 520239462Sdim /// 521239462Sdim /// Note that this includes the same information in the hash that 522239462Sdim /// isIdenticalTo uses for comparison. It is thus suited for use in hash 523239462Sdim /// tables which use that function for equality comparisons only. 524239462Sdim friend hash_code hash_value(const MachineOperand &MO); 525239462Sdim 526193323Sed /// ChangeToImmediate - Replace this operand with a new immediate operand of 527193323Sed /// the specified value. If an operand is known to be an immediate already, 528193323Sed /// the setImm method should be used. 529193323Sed void ChangeToImmediate(int64_t ImmVal); 530218893Sdim 531193323Sed /// ChangeToRegister - Replace this operand with a new register operand of 532193323Sed /// the specified value. If an operand is known to be an register already, 533193323Sed /// the setReg method should be used. 534193323Sed void ChangeToRegister(unsigned Reg, bool isDef, bool isImp = false, 535195340Sed bool isKill = false, bool isDead = false, 536203954Srdivacky bool isUndef = false, bool isDebug = false); 537218893Sdim 538193323Sed //===--------------------------------------------------------------------===// 539193323Sed // Construction methods. 540193323Sed //===--------------------------------------------------------------------===// 541218893Sdim 542193323Sed static MachineOperand CreateImm(int64_t Val) { 543193323Sed MachineOperand Op(MachineOperand::MO_Immediate); 544193323Sed Op.setImm(Val); 545193323Sed return Op; 546193323Sed } 547218893Sdim 548224145Sdim static MachineOperand CreateCImm(const ConstantInt *CI) { 549224145Sdim MachineOperand Op(MachineOperand::MO_CImmediate); 550224145Sdim Op.Contents.CI = CI; 551224145Sdim return Op; 552224145Sdim } 553224145Sdim 554193323Sed static MachineOperand CreateFPImm(const ConstantFP *CFP) { 555193323Sed MachineOperand Op(MachineOperand::MO_FPImmediate); 556193323Sed Op.Contents.CFP = CFP; 557193323Sed return Op; 558193323Sed } 559218893Sdim 560193323Sed static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false, 561193323Sed bool isKill = false, bool isDead = false, 562195340Sed bool isUndef = false, 563195340Sed bool isEarlyClobber = false, 564203954Srdivacky unsigned SubReg = 0, 565239462Sdim bool isDebug = false, 566239462Sdim bool isInternalRead = false) { 567263508Sdim assert(!(isDead && !isDef) && "Dead flag on non-def"); 568263508Sdim assert(!(isKill && isDef) && "Kill flag on def"); 569193323Sed MachineOperand Op(MachineOperand::MO_Register); 570193323Sed Op.IsDef = isDef; 571193323Sed Op.IsImp = isImp; 572193323Sed Op.IsKill = isKill; 573193323Sed Op.IsDead = isDead; 574195340Sed Op.IsUndef = isUndef; 575239462Sdim Op.IsInternalRead = isInternalRead; 576193323Sed Op.IsEarlyClobber = isEarlyClobber; 577243830Sdim Op.TiedTo = 0; 578203954Srdivacky Op.IsDebug = isDebug; 579218893Sdim Op.SmallContents.RegNo = Reg; 580193323Sed Op.Contents.Reg.Prev = 0; 581193323Sed Op.Contents.Reg.Next = 0; 582249423Sdim Op.setSubReg(SubReg); 583193323Sed return Op; 584193323Sed } 585195098Sed static MachineOperand CreateMBB(MachineBasicBlock *MBB, 586195098Sed unsigned char TargetFlags = 0) { 587193323Sed MachineOperand Op(MachineOperand::MO_MachineBasicBlock); 588193323Sed Op.setMBB(MBB); 589195098Sed Op.setTargetFlags(TargetFlags); 590193323Sed return Op; 591193323Sed } 592223017Sdim static MachineOperand CreateFI(int Idx) { 593193323Sed MachineOperand Op(MachineOperand::MO_FrameIndex); 594193323Sed Op.setIndex(Idx); 595193323Sed return Op; 596193323Sed } 597195098Sed static MachineOperand CreateCPI(unsigned Idx, int Offset, 598195098Sed unsigned char TargetFlags = 0) { 599193323Sed MachineOperand Op(MachineOperand::MO_ConstantPoolIndex); 600193323Sed Op.setIndex(Idx); 601193323Sed Op.setOffset(Offset); 602195098Sed Op.setTargetFlags(TargetFlags); 603193323Sed return Op; 604193323Sed } 605239462Sdim static MachineOperand CreateTargetIndex(unsigned Idx, int64_t Offset, 606239462Sdim unsigned char TargetFlags = 0) { 607239462Sdim MachineOperand Op(MachineOperand::MO_TargetIndex); 608239462Sdim Op.setIndex(Idx); 609239462Sdim Op.setOffset(Offset); 610239462Sdim Op.setTargetFlags(TargetFlags); 611239462Sdim return Op; 612239462Sdim } 613195098Sed static MachineOperand CreateJTI(unsigned Idx, 614195098Sed unsigned char TargetFlags = 0) { 615193323Sed MachineOperand Op(MachineOperand::MO_JumpTableIndex); 616193323Sed Op.setIndex(Idx); 617195098Sed Op.setTargetFlags(TargetFlags); 618193323Sed return Op; 619193323Sed } 620207618Srdivacky static MachineOperand CreateGA(const GlobalValue *GV, int64_t Offset, 621195098Sed unsigned char TargetFlags = 0) { 622193323Sed MachineOperand Op(MachineOperand::MO_GlobalAddress); 623193323Sed Op.Contents.OffsetedInfo.Val.GV = GV; 624193323Sed Op.setOffset(Offset); 625195098Sed Op.setTargetFlags(TargetFlags); 626193323Sed return Op; 627193323Sed } 628198090Srdivacky static MachineOperand CreateES(const char *SymName, 629195098Sed unsigned char TargetFlags = 0) { 630193323Sed MachineOperand Op(MachineOperand::MO_ExternalSymbol); 631193323Sed Op.Contents.OffsetedInfo.Val.SymbolName = SymName; 632198090Srdivacky Op.setOffset(0); // Offset is always 0. 633195098Sed Op.setTargetFlags(TargetFlags); 634193323Sed return Op; 635193323Sed } 636243830Sdim static MachineOperand CreateBA(const BlockAddress *BA, int64_t Offset, 637199989Srdivacky unsigned char TargetFlags = 0) { 638198892Srdivacky MachineOperand Op(MachineOperand::MO_BlockAddress); 639198892Srdivacky Op.Contents.OffsetedInfo.Val.BA = BA; 640243830Sdim Op.setOffset(Offset); 641199989Srdivacky Op.setTargetFlags(TargetFlags); 642198892Srdivacky return Op; 643198892Srdivacky } 644234353Sdim /// CreateRegMask - Creates a register mask operand referencing Mask. The 645234353Sdim /// operand does not take ownership of the memory referenced by Mask, it must 646234353Sdim /// remain valid for the lifetime of the operand. 647234353Sdim /// 648234353Sdim /// A RegMask operand represents a set of non-clobbered physical registers on 649234353Sdim /// an instruction that clobbers many registers, typically a call. The bit 650234353Sdim /// mask has a bit set for each physreg that is preserved by this 651234353Sdim /// instruction, as described in the documentation for 652234353Sdim /// TargetRegisterInfo::getCallPreservedMask(). 653234353Sdim /// 654234353Sdim /// Any physreg with a 0 bit in the mask is clobbered by the instruction. 655234353Sdim /// 656234353Sdim static MachineOperand CreateRegMask(const uint32_t *Mask) { 657234353Sdim assert(Mask && "Missing register mask"); 658234353Sdim MachineOperand Op(MachineOperand::MO_RegisterMask); 659234353Sdim Op.Contents.RegMask = Mask; 660234353Sdim return Op; 661234353Sdim } 662204642Srdivacky static MachineOperand CreateMetadata(const MDNode *Meta) { 663202375Srdivacky MachineOperand Op(MachineOperand::MO_Metadata); 664202375Srdivacky Op.Contents.MD = Meta; 665202375Srdivacky return Op; 666202375Srdivacky } 667193323Sed 668205218Srdivacky static MachineOperand CreateMCSymbol(MCSymbol *Sym) { 669205218Srdivacky MachineOperand Op(MachineOperand::MO_MCSymbol); 670205218Srdivacky Op.Contents.Sym = Sym; 671205218Srdivacky return Op; 672205218Srdivacky } 673218893Sdim 674193323Sed friend class MachineInstr; 675193323Sed friend class MachineRegisterInfo; 676193323Sedprivate: 677193323Sed //===--------------------------------------------------------------------===// 678193323Sed // Methods for handling register use/def lists. 679193323Sed //===--------------------------------------------------------------------===// 680193323Sed 681193323Sed /// isOnRegUseList - Return true if this operand is on a register use/def list 682193323Sed /// or false if not. This can only be called for register operands that are 683193323Sed /// part of a machine instruction. 684193323Sed bool isOnRegUseList() const { 685193323Sed assert(isReg() && "Can only add reg operand to use lists"); 686193323Sed return Contents.Reg.Prev != 0; 687193323Sed } 688193323Sed}; 689193323Sed 690193323Sedinline raw_ostream &operator<<(raw_ostream &OS, const MachineOperand& MO) { 691193323Sed MO.print(OS, 0); 692193323Sed return OS; 693193323Sed} 694193323Sed 695243830Sdim // See friend declaration above. This additional declaration is required in 696243830Sdim // order to compile LLVM with IBM xlC compiler. 697243830Sdim hash_code hash_value(const MachineOperand &MO); 698193323Sed} // End llvm namespace 699193323Sed 700193323Sed#endif 701