reload1.c revision 52284
1/* Reload pseudo regs into hard regs for insns that require hard regs. 2 Copyright (C) 1987, 88, 89, 92-98, 1999 Free Software Foundation, Inc. 3 4This file is part of GNU CC. 5 6GNU CC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2, or (at your option) 9any later version. 10 11GNU CC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with GNU CC; see the file COPYING. If not, write to 18the Free Software Foundation, 59 Temple Place - Suite 330, 19Boston, MA 02111-1307, USA. */ 20 21 22#include "config.h" 23#include "system.h" 24 25#include "machmode.h" 26#include "hard-reg-set.h" 27#include "rtl.h" 28#include "obstack.h" 29#include "insn-config.h" 30#include "insn-flags.h" 31#include "insn-codes.h" 32#include "flags.h" 33#include "expr.h" 34#include "regs.h" 35#include "basic-block.h" 36#include "reload.h" 37#include "recog.h" 38#include "output.h" 39#include "real.h" 40#include "toplev.h" 41 42#if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY 43#define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY 44#endif 45 46/* This file contains the reload pass of the compiler, which is 47 run after register allocation has been done. It checks that 48 each insn is valid (operands required to be in registers really 49 are in registers of the proper class) and fixes up invalid ones 50 by copying values temporarily into registers for the insns 51 that need them. 52 53 The results of register allocation are described by the vector 54 reg_renumber; the insns still contain pseudo regs, but reg_renumber 55 can be used to find which hard reg, if any, a pseudo reg is in. 56 57 The technique we always use is to free up a few hard regs that are 58 called ``reload regs'', and for each place where a pseudo reg 59 must be in a hard reg, copy it temporarily into one of the reload regs. 60 61 Reload regs are allocated locally for every instruction that needs 62 reloads. When there are pseudos which are allocated to a register that 63 has been chosen as a reload reg, such pseudos must be ``spilled''. 64 This means that they go to other hard regs, or to stack slots if no other 65 available hard regs can be found. Spilling can invalidate more 66 insns, requiring additional need for reloads, so we must keep checking 67 until the process stabilizes. 68 69 For machines with different classes of registers, we must keep track 70 of the register class needed for each reload, and make sure that 71 we allocate enough reload registers of each class. 72 73 The file reload.c contains the code that checks one insn for 74 validity and reports the reloads that it needs. This file 75 is in charge of scanning the entire rtl code, accumulating the 76 reload needs, spilling, assigning reload registers to use for 77 fixing up each insn, and generating the new insns to copy values 78 into the reload registers. */ 79 80 81#ifndef REGISTER_MOVE_COST 82#define REGISTER_MOVE_COST(x, y) 2 83#endif 84 85/* During reload_as_needed, element N contains a REG rtx for the hard reg 86 into which reg N has been reloaded (perhaps for a previous insn). */ 87static rtx *reg_last_reload_reg; 88 89/* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn 90 for an output reload that stores into reg N. */ 91static char *reg_has_output_reload; 92 93/* Indicates which hard regs are reload-registers for an output reload 94 in the current insn. */ 95static HARD_REG_SET reg_is_output_reload; 96 97/* Element N is the constant value to which pseudo reg N is equivalent, 98 or zero if pseudo reg N is not equivalent to a constant. 99 find_reloads looks at this in order to replace pseudo reg N 100 with the constant it stands for. */ 101rtx *reg_equiv_constant; 102 103/* Element N is a memory location to which pseudo reg N is equivalent, 104 prior to any register elimination (such as frame pointer to stack 105 pointer). Depending on whether or not it is a valid address, this value 106 is transferred to either reg_equiv_address or reg_equiv_mem. */ 107rtx *reg_equiv_memory_loc; 108 109/* Element N is the address of stack slot to which pseudo reg N is equivalent. 110 This is used when the address is not valid as a memory address 111 (because its displacement is too big for the machine.) */ 112rtx *reg_equiv_address; 113 114/* Element N is the memory slot to which pseudo reg N is equivalent, 115 or zero if pseudo reg N is not equivalent to a memory slot. */ 116rtx *reg_equiv_mem; 117 118/* Widest width in which each pseudo reg is referred to (via subreg). */ 119static int *reg_max_ref_width; 120 121/* Element N is the list of insns that initialized reg N from its equivalent 122 constant or memory slot. */ 123static rtx *reg_equiv_init; 124 125/* Vector to remember old contents of reg_renumber before spilling. */ 126static short *reg_old_renumber; 127 128/* During reload_as_needed, element N contains the last pseudo regno reloaded 129 into hard register N. If that pseudo reg occupied more than one register, 130 reg_reloaded_contents points to that pseudo for each spill register in 131 use; all of these must remain set for an inheritance to occur. */ 132static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; 133 134/* During reload_as_needed, element N contains the insn for which 135 hard register N was last used. Its contents are significant only 136 when reg_reloaded_valid is set for this register. */ 137static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; 138 139/* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */ 140static HARD_REG_SET reg_reloaded_valid; 141/* Indicate if the register was dead at the end of the reload. 142 This is only valid if reg_reloaded_contents is set and valid. */ 143static HARD_REG_SET reg_reloaded_dead; 144 145/* Number of spill-regs so far; number of valid elements of spill_regs. */ 146static int n_spills; 147 148/* In parallel with spill_regs, contains REG rtx's for those regs. 149 Holds the last rtx used for any given reg, or 0 if it has never 150 been used for spilling yet. This rtx is reused, provided it has 151 the proper mode. */ 152static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; 153 154/* In parallel with spill_regs, contains nonzero for a spill reg 155 that was stored after the last time it was used. 156 The precise value is the insn generated to do the store. */ 157static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; 158 159/* This is the register that was stored with spill_reg_store. This is a 160 copy of reload_out / reload_out_reg when the value was stored; if 161 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ 162static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; 163 164/* This table is the inverse mapping of spill_regs: 165 indexed by hard reg number, 166 it contains the position of that reg in spill_regs, 167 or -1 for something that is not in spill_regs. 168 169 ?!? This is no longer accurate. */ 170static short spill_reg_order[FIRST_PSEUDO_REGISTER]; 171 172/* This reg set indicates registers that can't be used as spill registers for 173 the currently processed insn. These are the hard registers which are live 174 during the insn, but not allocated to pseudos, as well as fixed 175 registers. */ 176static HARD_REG_SET bad_spill_regs; 177 178/* These are the hard registers that can't be used as spill register for any 179 insn. This includes registers used for user variables and registers that 180 we can't eliminate. A register that appears in this set also can't be used 181 to retry register allocation. */ 182static HARD_REG_SET bad_spill_regs_global; 183 184/* Describes order of use of registers for reloading 185 of spilled pseudo-registers. `n_spills' is the number of 186 elements that are actually valid; new ones are added at the end. 187 188 Both spill_regs and spill_reg_order are used on two occasions: 189 once during find_reload_regs, where they keep track of the spill registers 190 for a single insn, but also during reload_as_needed where they show all 191 the registers ever used by reload. For the latter case, the information 192 is calculated during finish_spills. */ 193static short spill_regs[FIRST_PSEUDO_REGISTER]; 194 195/* This vector of reg sets indicates, for each pseudo, which hard registers 196 may not be used for retrying global allocation because the register was 197 formerly spilled from one of them. If we allowed reallocating a pseudo to 198 a register that it was already allocated to, reload might not 199 terminate. */ 200static HARD_REG_SET *pseudo_previous_regs; 201 202/* This vector of reg sets indicates, for each pseudo, which hard 203 registers may not be used for retrying global allocation because they 204 are used as spill registers during one of the insns in which the 205 pseudo is live. */ 206static HARD_REG_SET *pseudo_forbidden_regs; 207 208/* All hard regs that have been used as spill registers for any insn are 209 marked in this set. */ 210static HARD_REG_SET used_spill_regs; 211 212/* Index of last register assigned as a spill register. We allocate in 213 a round-robin fashion. */ 214static int last_spill_reg; 215 216/* Describes order of preference for putting regs into spill_regs. 217 Contains the numbers of all the hard regs, in order most preferred first. 218 This order is different for each function. 219 It is set up by order_regs_for_reload. 220 Empty elements at the end contain -1. */ 221static short potential_reload_regs[FIRST_PSEUDO_REGISTER]; 222 223/* Nonzero if indirect addressing is supported on the machine; this means 224 that spilling (REG n) does not require reloading it into a register in 225 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The 226 value indicates the level of indirect addressing supported, e.g., two 227 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get 228 a hard register. */ 229static char spill_indirect_levels; 230 231/* Nonzero if indirect addressing is supported when the innermost MEM is 232 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to 233 which these are valid is the same as spill_indirect_levels, above. */ 234char indirect_symref_ok; 235 236/* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ 237char double_reg_address_ok; 238 239/* Record the stack slot for each spilled hard register. */ 240static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; 241 242/* Width allocated so far for that stack slot. */ 243static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; 244 245/* Record which pseudos needed to be spilled. */ 246static regset spilled_pseudos; 247 248/* First uid used by insns created by reload in this function. 249 Used in find_equiv_reg. */ 250int reload_first_uid; 251 252/* Flag set by local-alloc or global-alloc if anything is live in 253 a call-clobbered reg across calls. */ 254int caller_save_needed; 255 256/* Set to 1 while reload_as_needed is operating. 257 Required by some machines to handle any generated moves differently. */ 258int reload_in_progress = 0; 259 260/* These arrays record the insn_code of insns that may be needed to 261 perform input and output reloads of special objects. They provide a 262 place to pass a scratch register. */ 263enum insn_code reload_in_optab[NUM_MACHINE_MODES]; 264enum insn_code reload_out_optab[NUM_MACHINE_MODES]; 265 266/* This obstack is used for allocation of rtl during register elimination. 267 The allocated storage can be freed once find_reloads has processed the 268 insn. */ 269struct obstack reload_obstack; 270 271/* Points to the beginning of the reload_obstack. All insn_chain structures 272 are allocated first. */ 273char *reload_startobj; 274 275/* The point after all insn_chain structures. Used to quickly deallocate 276 memory used while processing one insn. */ 277char *reload_firstobj; 278 279#define obstack_chunk_alloc xmalloc 280#define obstack_chunk_free free 281 282/* List of labels that must never be deleted. */ 283extern rtx forced_labels; 284 285/* List of insn_chain instructions, one for every insn that reload needs to 286 examine. */ 287struct insn_chain *reload_insn_chain; 288 289#ifdef TREE_CODE 290extern tree current_function_decl; 291#else 292extern union tree_node *current_function_decl; 293#endif 294 295/* List of all insns needing reloads. */ 296static struct insn_chain *insns_need_reload; 297 298/* This structure is used to record information about register eliminations. 299 Each array entry describes one possible way of eliminating a register 300 in favor of another. If there is more than one way of eliminating a 301 particular register, the most preferred should be specified first. */ 302 303struct elim_table 304{ 305 int from; /* Register number to be eliminated. */ 306 int to; /* Register number used as replacement. */ 307 int initial_offset; /* Initial difference between values. */ 308 int can_eliminate; /* Non-zero if this elimination can be done. */ 309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over 310 insns made by reload. */ 311 int offset; /* Current offset between the two regs. */ 312 int previous_offset; /* Offset at end of previous insn. */ 313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */ 314 rtx from_rtx; /* REG rtx for the register to be eliminated. 315 We cannot simply compare the number since 316 we might then spuriously replace a hard 317 register corresponding to a pseudo 318 assigned to the reg to be eliminated. */ 319 rtx to_rtx; /* REG rtx for the replacement. */ 320}; 321 322static struct elim_table * reg_eliminate = 0; 323 324/* This is an intermediate structure to initialize the table. It has 325 exactly the members provided by ELIMINABLE_REGS. */ 326static struct elim_table_1 327{ 328 int from; 329 int to; 330} reg_eliminate_1[] = 331 332/* If a set of eliminable registers was specified, define the table from it. 333 Otherwise, default to the normal case of the frame pointer being 334 replaced by the stack pointer. */ 335 336#ifdef ELIMINABLE_REGS 337 ELIMINABLE_REGS; 338#else 339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; 340#endif 341 342#define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0]) 343 344/* Record the number of pending eliminations that have an offset not equal 345 to their initial offset. If non-zero, we use a new copy of each 346 replacement result in any insns encountered. */ 347int num_not_at_initial_offset; 348 349/* Count the number of registers that we may be able to eliminate. */ 350static int num_eliminable; 351/* And the number of registers that are equivalent to a constant that 352 can be eliminated to frame_pointer / arg_pointer + constant. */ 353static int num_eliminable_invariants; 354 355/* For each label, we record the offset of each elimination. If we reach 356 a label by more than one path and an offset differs, we cannot do the 357 elimination. This information is indexed by the number of the label. 358 The first table is an array of flags that records whether we have yet 359 encountered a label and the second table is an array of arrays, one 360 entry in the latter array for each elimination. */ 361 362static char *offsets_known_at; 363static int (*offsets_at)[NUM_ELIMINABLE_REGS]; 364 365/* Number of labels in the current function. */ 366 367static int num_labels; 368 369struct hard_reg_n_uses 370{ 371 int regno; 372 unsigned int uses; 373}; 374 375static void maybe_fix_stack_asms PROTO((void)); 376static void calculate_needs_all_insns PROTO((int)); 377static void calculate_needs PROTO((struct insn_chain *)); 378static void find_reload_regs PROTO((struct insn_chain *chain, 379 FILE *)); 380static void find_tworeg_group PROTO((struct insn_chain *, int, 381 FILE *)); 382static void find_group PROTO((struct insn_chain *, int, 383 FILE *)); 384static int possible_group_p PROTO((struct insn_chain *, int)); 385static void count_possible_groups PROTO((struct insn_chain *, int)); 386static int modes_equiv_for_class_p PROTO((enum machine_mode, 387 enum machine_mode, 388 enum reg_class)); 389static void delete_caller_save_insns PROTO((void)); 390 391static void spill_failure PROTO((rtx)); 392static void new_spill_reg PROTO((struct insn_chain *, int, int, 393 int, FILE *)); 394static void maybe_mark_pseudo_spilled PROTO((int)); 395static void delete_dead_insn PROTO((rtx)); 396static void alter_reg PROTO((int, int)); 397static void set_label_offsets PROTO((rtx, rtx, int)); 398static int eliminate_regs_in_insn PROTO((rtx, int)); 399static void update_eliminable_offsets PROTO((void)); 400static void mark_not_eliminable PROTO((rtx, rtx)); 401static void set_initial_elim_offsets PROTO((void)); 402static void verify_initial_elim_offsets PROTO((void)); 403static void set_initial_label_offsets PROTO((void)); 404static void set_offsets_for_label PROTO((rtx)); 405static void init_elim_table PROTO((void)); 406static void update_eliminables PROTO((HARD_REG_SET *)); 407static void spill_hard_reg PROTO((int, FILE *, int)); 408static int finish_spills PROTO((int, FILE *)); 409static void ior_hard_reg_set PROTO((HARD_REG_SET *, HARD_REG_SET *)); 410static void scan_paradoxical_subregs PROTO((rtx)); 411static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR)); 412static void count_pseudo PROTO((struct hard_reg_n_uses *, int)); 413static void order_regs_for_reload PROTO((struct insn_chain *)); 414static void reload_as_needed PROTO((int)); 415static void forget_old_reloads_1 PROTO((rtx, rtx)); 416static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR)); 417static void mark_reload_reg_in_use PROTO((int, int, enum reload_type, 418 enum machine_mode)); 419static void clear_reload_reg_in_use PROTO((int, int, enum reload_type, 420 enum machine_mode)); 421static int reload_reg_free_p PROTO((int, int, enum reload_type)); 422static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int, int)); 423static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type)); 424static int allocate_reload_reg PROTO((struct insn_chain *, int, int, 425 int)); 426static void choose_reload_regs PROTO((struct insn_chain *)); 427static void merge_assigned_reloads PROTO((rtx)); 428static void emit_reload_insns PROTO((struct insn_chain *)); 429static void delete_output_reload PROTO((rtx, int, int)); 430static void delete_address_reloads PROTO((rtx, rtx)); 431static void delete_address_reloads_1 PROTO((rtx, rtx, rtx)); 432static rtx inc_for_reload PROTO((rtx, rtx, rtx, int)); 433static int constraint_accepts_reg_p PROTO((const char *, rtx)); 434static void reload_cse_regs_1 PROTO((rtx)); 435static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int)); 436static int reload_cse_mem_conflict_p PROTO((rtx, rtx)); 437static void reload_cse_invalidate_mem PROTO((rtx)); 438static void reload_cse_invalidate_rtx PROTO((rtx, rtx)); 439static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode)); 440static int reload_cse_noop_set_p PROTO((rtx, rtx)); 441static int reload_cse_simplify_set PROTO((rtx, rtx)); 442static int reload_cse_simplify_operands PROTO((rtx)); 443static void reload_cse_check_clobber PROTO((rtx, rtx)); 444static void reload_cse_record_set PROTO((rtx, rtx)); 445static void reload_combine PROTO((void)); 446static void reload_combine_note_use PROTO((rtx *, rtx)); 447static void reload_combine_note_store PROTO((rtx, rtx)); 448static void reload_cse_move2add PROTO((rtx)); 449static void move2add_note_store PROTO((rtx, rtx)); 450#ifdef AUTO_INC_DEC 451static void add_auto_inc_notes PROTO((rtx, rtx)); 452#endif 453 454/* Initialize the reload pass once per compilation. */ 455 456void 457init_reload () 458{ 459 register int i; 460 461 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. 462 Set spill_indirect_levels to the number of levels such addressing is 463 permitted, zero if it is not permitted at all. */ 464 465 register rtx tem 466 = gen_rtx_MEM (Pmode, 467 gen_rtx_PLUS (Pmode, 468 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1), 469 GEN_INT (4))); 470 spill_indirect_levels = 0; 471 472 while (memory_address_p (QImode, tem)) 473 { 474 spill_indirect_levels++; 475 tem = gen_rtx_MEM (Pmode, tem); 476 } 477 478 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ 479 480 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); 481 indirect_symref_ok = memory_address_p (QImode, tem); 482 483 /* See if reg+reg is a valid (and offsettable) address. */ 484 485 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 486 { 487 tem = gen_rtx_PLUS (Pmode, 488 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), 489 gen_rtx_REG (Pmode, i)); 490 /* This way, we make sure that reg+reg is an offsettable address. */ 491 tem = plus_constant (tem, 4); 492 493 if (memory_address_p (QImode, tem)) 494 { 495 double_reg_address_ok = 1; 496 break; 497 } 498 } 499 500 /* Initialize obstack for our rtl allocation. */ 501 gcc_obstack_init (&reload_obstack); 502 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0); 503} 504 505/* List of insn chains that are currently unused. */ 506static struct insn_chain *unused_insn_chains = 0; 507 508/* Allocate an empty insn_chain structure. */ 509struct insn_chain * 510new_insn_chain () 511{ 512 struct insn_chain *c; 513 514 if (unused_insn_chains == 0) 515 { 516 c = (struct insn_chain *) 517 obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); 518 c->live_before = OBSTACK_ALLOC_REG_SET (&reload_obstack); 519 c->live_after = OBSTACK_ALLOC_REG_SET (&reload_obstack); 520 } 521 else 522 { 523 c = unused_insn_chains; 524 unused_insn_chains = c->next; 525 } 526 c->is_caller_save_insn = 0; 527 c->need_operand_change = 0; 528 c->need_reload = 0; 529 c->need_elim = 0; 530 return c; 531} 532 533/* Small utility function to set all regs in hard reg set TO which are 534 allocated to pseudos in regset FROM. */ 535void 536compute_use_by_pseudos (to, from) 537 HARD_REG_SET *to; 538 regset from; 539{ 540 int regno; 541 EXECUTE_IF_SET_IN_REG_SET 542 (from, FIRST_PSEUDO_REGISTER, regno, 543 { 544 int r = reg_renumber[regno]; 545 int nregs; 546 if (r < 0) 547 { 548 /* reload_combine uses the information from 549 BASIC_BLOCK->global_live_at_start, which might still 550 contain registers that have not actually been allocated 551 since they have an equivalence. */ 552 if (! reload_completed) 553 abort (); 554 } 555 else 556 { 557 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno)); 558 while (nregs-- > 0) 559 SET_HARD_REG_BIT (*to, r + nregs); 560 } 561 }); 562} 563 564/* Global variables used by reload and its subroutines. */ 565 566/* Set during calculate_needs if an insn needs register elimination. */ 567static int something_needs_elimination; 568/* Set during calculate_needs if an insn needs an operand changed. */ 569int something_needs_operands_changed; 570 571/* Nonzero means we couldn't get enough spill regs. */ 572static int failure; 573 574/* Main entry point for the reload pass. 575 576 FIRST is the first insn of the function being compiled. 577 578 GLOBAL nonzero means we were called from global_alloc 579 and should attempt to reallocate any pseudoregs that we 580 displace from hard regs we will use for reloads. 581 If GLOBAL is zero, we do not have enough information to do that, 582 so any pseudo reg that is spilled must go to the stack. 583 584 DUMPFILE is the global-reg debugging dump file stream, or 0. 585 If it is nonzero, messages are written to it to describe 586 which registers are seized as reload regs, which pseudo regs 587 are spilled from them, and where the pseudo regs are reallocated to. 588 589 Return value is nonzero if reload failed 590 and we must not do any more for this function. */ 591 592int 593reload (first, global, dumpfile) 594 rtx first; 595 int global; 596 FILE *dumpfile; 597{ 598 register int i; 599 register rtx insn; 600 register struct elim_table *ep; 601 602 /* The two pointers used to track the true location of the memory used 603 for label offsets. */ 604 char *real_known_ptr = NULL_PTR; 605 int (*real_at_ptr)[NUM_ELIMINABLE_REGS]; 606 607 /* Make sure even insns with volatile mem refs are recognizable. */ 608 init_recog (); 609 610 failure = 0; 611 612 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); 613 614 /* Make sure that the last insn in the chain 615 is not something that needs reloading. */ 616 emit_note (NULL_PTR, NOTE_INSN_DELETED); 617 618 /* Enable find_equiv_reg to distinguish insns made by reload. */ 619 reload_first_uid = get_max_uid (); 620 621#ifdef SECONDARY_MEMORY_NEEDED 622 /* Initialize the secondary memory table. */ 623 clear_secondary_mem (); 624#endif 625 626 /* We don't have a stack slot for any spill reg yet. */ 627 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot); 628 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width); 629 630 /* Initialize the save area information for caller-save, in case some 631 are needed. */ 632 init_save_areas (); 633 634 /* Compute which hard registers are now in use 635 as homes for pseudo registers. 636 This is done here rather than (eg) in global_alloc 637 because this point is reached even if not optimizing. */ 638 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 639 mark_home_live (i); 640 641 /* A function that receives a nonlocal goto must save all call-saved 642 registers. */ 643 if (current_function_has_nonlocal_label) 644 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 645 { 646 if (! call_used_regs[i] && ! fixed_regs[i]) 647 regs_ever_live[i] = 1; 648 } 649 650 /* Find all the pseudo registers that didn't get hard regs 651 but do have known equivalent constants or memory slots. 652 These include parameters (known equivalent to parameter slots) 653 and cse'd or loop-moved constant memory addresses. 654 655 Record constant equivalents in reg_equiv_constant 656 so they will be substituted by find_reloads. 657 Record memory equivalents in reg_mem_equiv so they can 658 be substituted eventually by altering the REG-rtx's. */ 659 660 reg_equiv_constant = (rtx *) xmalloc (max_regno * sizeof (rtx)); 661 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx)); 662 reg_equiv_memory_loc = (rtx *) xmalloc (max_regno * sizeof (rtx)); 663 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx)); 664 reg_equiv_mem = (rtx *) xmalloc (max_regno * sizeof (rtx)); 665 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx)); 666 reg_equiv_init = (rtx *) xmalloc (max_regno * sizeof (rtx)); 667 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx)); 668 reg_equiv_address = (rtx *) xmalloc (max_regno * sizeof (rtx)); 669 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx)); 670 reg_max_ref_width = (int *) xmalloc (max_regno * sizeof (int)); 671 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int)); 672 reg_old_renumber = (short *) xmalloc (max_regno * sizeof (short)); 673 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short)); 674 pseudo_forbidden_regs 675 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET)); 676 pseudo_previous_regs 677 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET)); 678 679 CLEAR_HARD_REG_SET (bad_spill_regs_global); 680 bzero ((char *) pseudo_previous_regs, max_regno * sizeof (HARD_REG_SET)); 681 682 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. 683 Also find all paradoxical subregs and find largest such for each pseudo. 684 On machines with small register classes, record hard registers that 685 are used for user variables. These can never be used for spills. 686 Also look for a "constant" NOTE_INSN_SETJMP. This means that all 687 caller-saved registers must be marked live. */ 688 689 num_eliminable_invariants = 0; 690 for (insn = first; insn; insn = NEXT_INSN (insn)) 691 { 692 rtx set = single_set (insn); 693 694 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn) 695 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP) 696 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 697 if (! call_used_regs[i]) 698 regs_ever_live[i] = 1; 699 700 if (set != 0 && GET_CODE (SET_DEST (set)) == REG) 701 { 702 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); 703 if (note 704#ifdef LEGITIMATE_PIC_OPERAND_P 705 && (! function_invariant_p (XEXP (note, 0)) 706 || ! flag_pic 707 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))) 708#endif 709 ) 710 { 711 rtx x = XEXP (note, 0); 712 i = REGNO (SET_DEST (set)); 713 if (i > LAST_VIRTUAL_REGISTER) 714 { 715 if (GET_CODE (x) == MEM) 716 { 717 /* If the operand is a PLUS, the MEM may be shared, 718 so make sure we have an unshared copy here. */ 719 if (GET_CODE (XEXP (x, 0)) == PLUS) 720 x = copy_rtx (x); 721 722 reg_equiv_memory_loc[i] = x; 723 } 724 else if (function_invariant_p (x)) 725 { 726 if (GET_CODE (x) == PLUS) 727 { 728 /* This is PLUS of frame pointer and a constant, 729 and might be shared. Unshare it. */ 730 reg_equiv_constant[i] = copy_rtx (x); 731 num_eliminable_invariants++; 732 } 733 else if (x == frame_pointer_rtx 734 || x == arg_pointer_rtx) 735 { 736 reg_equiv_constant[i] = x; 737 num_eliminable_invariants++; 738 } 739 else if (LEGITIMATE_CONSTANT_P (x)) 740 reg_equiv_constant[i] = x; 741 else 742 reg_equiv_memory_loc[i] 743 = force_const_mem (GET_MODE (SET_DEST (set)), x); 744 } 745 else 746 continue; 747 748 /* If this register is being made equivalent to a MEM 749 and the MEM is not SET_SRC, the equivalencing insn 750 is one with the MEM as a SET_DEST and it occurs later. 751 So don't mark this insn now. */ 752 if (GET_CODE (x) != MEM 753 || rtx_equal_p (SET_SRC (set), x)) 754 reg_equiv_init[i] 755 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]); 756 } 757 } 758 } 759 760 /* If this insn is setting a MEM from a register equivalent to it, 761 this is the equivalencing insn. */ 762 else if (set && GET_CODE (SET_DEST (set)) == MEM 763 && GET_CODE (SET_SRC (set)) == REG 764 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] 765 && rtx_equal_p (SET_DEST (set), 766 reg_equiv_memory_loc[REGNO (SET_SRC (set))])) 767 reg_equiv_init[REGNO (SET_SRC (set))] 768 = gen_rtx_INSN_LIST (VOIDmode, insn, 769 reg_equiv_init[REGNO (SET_SRC (set))]); 770 771 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 772 scan_paradoxical_subregs (PATTERN (insn)); 773 } 774 775 init_elim_table (); 776 777 num_labels = max_label_num () - get_first_label_num (); 778 779 /* Allocate the tables used to store offset information at labels. */ 780 /* We used to use alloca here, but the size of what it would try to 781 allocate would occasionally cause it to exceed the stack limit and 782 cause a core dump. */ 783 real_known_ptr = xmalloc (num_labels); 784 real_at_ptr 785 = (int (*)[NUM_ELIMINABLE_REGS]) 786 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); 787 788 offsets_known_at = real_known_ptr - get_first_label_num (); 789 offsets_at 790 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ()); 791 792 /* Alter each pseudo-reg rtx to contain its hard reg number. 793 Assign stack slots to the pseudos that lack hard regs or equivalents. 794 Do not touch virtual registers. */ 795 796 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) 797 alter_reg (i, -1); 798 799 /* If we have some registers we think can be eliminated, scan all insns to 800 see if there is an insn that sets one of these registers to something 801 other than itself plus a constant. If so, the register cannot be 802 eliminated. Doing this scan here eliminates an extra pass through the 803 main reload loop in the most common case where register elimination 804 cannot be done. */ 805 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) 806 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN 807 || GET_CODE (insn) == CALL_INSN) 808 note_stores (PATTERN (insn), mark_not_eliminable); 809 810#ifndef REGISTER_CONSTRAINTS 811 /* If all the pseudo regs have hard regs, 812 except for those that are never referenced, 813 we know that no reloads are needed. */ 814 /* But that is not true if there are register constraints, since 815 in that case some pseudos might be in the wrong kind of hard reg. */ 816 817 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 818 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0) 819 break; 820 821 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed) 822 { 823 free (real_known_ptr); 824 free (real_at_ptr); 825 free (reg_equiv_constant); 826 free (reg_equiv_memory_loc); 827 free (reg_equiv_mem); 828 free (reg_equiv_init); 829 free (reg_equiv_address); 830 free (reg_max_ref_width); 831 free (reg_old_renumber); 832 free (pseudo_previous_regs); 833 free (pseudo_forbidden_regs); 834 return 0; 835 } 836#endif 837 838 maybe_fix_stack_asms (); 839 840 insns_need_reload = 0; 841 something_needs_elimination = 0; 842 843 /* Initialize to -1, which means take the first spill register. */ 844 last_spill_reg = -1; 845 846 spilled_pseudos = ALLOCA_REG_SET (); 847 848 /* Spill any hard regs that we know we can't eliminate. */ 849 CLEAR_HARD_REG_SET (used_spill_regs); 850 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 851 if (! ep->can_eliminate) 852 spill_hard_reg (ep->from, dumpfile, 1); 853 854#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 855 if (frame_pointer_needed) 856 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1); 857#endif 858 finish_spills (global, dumpfile); 859 860 /* From now on, we may need to generate moves differently. We may also 861 allow modifications of insns which cause them to not be recognized. 862 Any such modifications will be cleaned up during reload itself. */ 863 reload_in_progress = 1; 864 865 /* This loop scans the entire function each go-round 866 and repeats until one repetition spills no additional hard regs. */ 867 for (;;) 868 { 869 int something_changed; 870 int did_spill; 871 struct insn_chain *chain; 872 873 HOST_WIDE_INT starting_frame_size; 874 875 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done 876 here because the stack size may be a part of the offset computation 877 for register elimination, and there might have been new stack slots 878 created in the last iteration of this loop. */ 879 assign_stack_local (BLKmode, 0, 0); 880 881 starting_frame_size = get_frame_size (); 882 883 set_initial_elim_offsets (); 884 set_initial_label_offsets (); 885 886 /* For each pseudo register that has an equivalent location defined, 887 try to eliminate any eliminable registers (such as the frame pointer) 888 assuming initial offsets for the replacement register, which 889 is the normal case. 890 891 If the resulting location is directly addressable, substitute 892 the MEM we just got directly for the old REG. 893 894 If it is not addressable but is a constant or the sum of a hard reg 895 and constant, it is probably not addressable because the constant is 896 out of range, in that case record the address; we will generate 897 hairy code to compute the address in a register each time it is 898 needed. Similarly if it is a hard register, but one that is not 899 valid as an address register. 900 901 If the location is not addressable, but does not have one of the 902 above forms, assign a stack slot. We have to do this to avoid the 903 potential of producing lots of reloads if, e.g., a location involves 904 a pseudo that didn't get a hard register and has an equivalent memory 905 location that also involves a pseudo that didn't get a hard register. 906 907 Perhaps at some point we will improve reload_when_needed handling 908 so this problem goes away. But that's very hairy. */ 909 910 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 911 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) 912 { 913 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); 914 915 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), 916 XEXP (x, 0))) 917 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; 918 else if (CONSTANT_P (XEXP (x, 0)) 919 || (GET_CODE (XEXP (x, 0)) == REG 920 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) 921 || (GET_CODE (XEXP (x, 0)) == PLUS 922 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG 923 && (REGNO (XEXP (XEXP (x, 0), 0)) 924 < FIRST_PSEUDO_REGISTER) 925 && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) 926 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; 927 else 928 { 929 /* Make a new stack slot. Then indicate that something 930 changed so we go back and recompute offsets for 931 eliminable registers because the allocation of memory 932 below might change some offset. reg_equiv_{mem,address} 933 will be set up for this pseudo on the next pass around 934 the loop. */ 935 reg_equiv_memory_loc[i] = 0; 936 reg_equiv_init[i] = 0; 937 alter_reg (i, -1); 938 } 939 } 940 941 if (caller_save_needed) 942 setup_save_areas (); 943 944 /* If we allocated another stack slot, redo elimination bookkeeping. */ 945 if (starting_frame_size != get_frame_size ()) 946 continue; 947 948 if (caller_save_needed) 949 { 950 save_call_clobbered_regs (); 951 /* That might have allocated new insn_chain structures. */ 952 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); 953 } 954 955 calculate_needs_all_insns (global); 956 957 CLEAR_REG_SET (spilled_pseudos); 958 did_spill = 0; 959 960 something_changed = 0; 961 962 /* If we allocated any new memory locations, make another pass 963 since it might have changed elimination offsets. */ 964 if (starting_frame_size != get_frame_size ()) 965 something_changed = 1; 966 967 { 968 HARD_REG_SET to_spill; 969 CLEAR_HARD_REG_SET (to_spill); 970 update_eliminables (&to_spill); 971 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 972 if (TEST_HARD_REG_BIT (to_spill, i)) 973 { 974 spill_hard_reg (i, dumpfile, 1); 975 did_spill = 1; 976 977 /* Regardless of the state of spills, if we previously had 978 a register that we thought we could eliminate, but no can 979 not eliminate, we must run another pass. 980 981 Consider pseudos which have an entry in reg_equiv_* which 982 reference an eliminable register. We must make another pass 983 to update reg_equiv_* so that we do not substitute in the 984 old value from when we thought the elimination could be 985 performed. */ 986 something_changed = 1; 987 } 988 } 989 990 CLEAR_HARD_REG_SET (used_spill_regs); 991 /* Try to satisfy the needs for each insn. */ 992 for (chain = insns_need_reload; chain != 0; 993 chain = chain->next_need_reload) 994 find_reload_regs (chain, dumpfile); 995 996 if (failure) 997 goto failed; 998 999 if (insns_need_reload != 0 || did_spill) 1000 something_changed |= finish_spills (global, dumpfile); 1001 1002 if (! something_changed) 1003 break; 1004 1005 if (caller_save_needed) 1006 delete_caller_save_insns (); 1007 } 1008 1009 /* If global-alloc was run, notify it of any register eliminations we have 1010 done. */ 1011 if (global) 1012 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 1013 if (ep->can_eliminate) 1014 mark_elimination (ep->from, ep->to); 1015 1016 /* If a pseudo has no hard reg, delete the insns that made the equivalence. 1017 If that insn didn't set the register (i.e., it copied the register to 1018 memory), just delete that insn instead of the equivalencing insn plus 1019 anything now dead. If we call delete_dead_insn on that insn, we may 1020 delete the insn that actually sets the register if the register dies 1021 there and that is incorrect. */ 1022 1023 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 1024 { 1025 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) 1026 { 1027 rtx list; 1028 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) 1029 { 1030 rtx equiv_insn = XEXP (list, 0); 1031 if (GET_CODE (equiv_insn) == NOTE) 1032 continue; 1033 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) 1034 delete_dead_insn (equiv_insn); 1035 else 1036 { 1037 PUT_CODE (equiv_insn, NOTE); 1038 NOTE_SOURCE_FILE (equiv_insn) = 0; 1039 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; 1040 } 1041 } 1042 } 1043 } 1044 1045 /* Use the reload registers where necessary 1046 by generating move instructions to move the must-be-register 1047 values into or out of the reload registers. */ 1048 1049 if (insns_need_reload != 0 || something_needs_elimination 1050 || something_needs_operands_changed) 1051 { 1052 int old_frame_size = get_frame_size (); 1053 1054 reload_as_needed (global); 1055 1056 if (old_frame_size != get_frame_size ()) 1057 abort (); 1058 1059 if (num_eliminable) 1060 verify_initial_elim_offsets (); 1061 } 1062 1063 /* If we were able to eliminate the frame pointer, show that it is no 1064 longer live at the start of any basic block. If it ls live by 1065 virtue of being in a pseudo, that pseudo will be marked live 1066 and hence the frame pointer will be known to be live via that 1067 pseudo. */ 1068 1069 if (! frame_pointer_needed) 1070 for (i = 0; i < n_basic_blocks; i++) 1071 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start, 1072 HARD_FRAME_POINTER_REGNUM); 1073 1074 /* Come here (with failure set nonzero) if we can't get enough spill regs 1075 and we decide not to abort about it. */ 1076 failed: 1077 1078 reload_in_progress = 0; 1079 1080 /* Now eliminate all pseudo regs by modifying them into 1081 their equivalent memory references. 1082 The REG-rtx's for the pseudos are modified in place, 1083 so all insns that used to refer to them now refer to memory. 1084 1085 For a reg that has a reg_equiv_address, all those insns 1086 were changed by reloading so that no insns refer to it any longer; 1087 but the DECL_RTL of a variable decl may refer to it, 1088 and if so this causes the debugging info to mention the variable. */ 1089 1090 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 1091 { 1092 rtx addr = 0; 1093 int in_struct = 0; 1094 int is_scalar; 1095 int is_readonly = 0; 1096 1097 if (reg_equiv_memory_loc[i]) 1098 { 1099 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]); 1100 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]); 1101 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]); 1102 } 1103 1104 if (reg_equiv_mem[i]) 1105 addr = XEXP (reg_equiv_mem[i], 0); 1106 1107 if (reg_equiv_address[i]) 1108 addr = reg_equiv_address[i]; 1109 1110 if (addr) 1111 { 1112 if (reg_renumber[i] < 0) 1113 { 1114 rtx reg = regno_reg_rtx[i]; 1115 XEXP (reg, 0) = addr; 1116 REG_USERVAR_P (reg) = 0; 1117 RTX_UNCHANGING_P (reg) = is_readonly; 1118 MEM_IN_STRUCT_P (reg) = in_struct; 1119 MEM_SCALAR_P (reg) = is_scalar; 1120 /* We have no alias information about this newly created 1121 MEM. */ 1122 MEM_ALIAS_SET (reg) = 0; 1123 PUT_CODE (reg, MEM); 1124 } 1125 else if (reg_equiv_mem[i]) 1126 XEXP (reg_equiv_mem[i], 0) = addr; 1127 } 1128 } 1129 1130 /* We must set reload_completed now since the cleanup_subreg_operands call 1131 below will re-recognize each insn and reload may have generated insns 1132 which are only valid during and after reload. */ 1133 reload_completed = 1; 1134 1135 /* Make a pass over all the insns and delete all USEs which we 1136 inserted only to tag a REG_EQUAL note on them. Remove all 1137 REG_DEAD and REG_UNUSED notes. Delete all CLOBBER insns and 1138 simplify (subreg (reg)) operands. Also remove all REG_RETVAL and 1139 REG_LIBCALL notes since they are no longer useful or accurate. 1140 Strip and regenerate REG_INC notes that may have been moved 1141 around. */ 1142 1143 for (insn = first; insn; insn = NEXT_INSN (insn)) 1144 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 1145 { 1146 rtx *pnote; 1147 1148 if ((GET_CODE (PATTERN (insn)) == USE 1149 && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 1150 || GET_CODE (PATTERN (insn)) == CLOBBER) 1151 { 1152 PUT_CODE (insn, NOTE); 1153 NOTE_SOURCE_FILE (insn) = 0; 1154 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 1155 continue; 1156 } 1157 1158 pnote = ®_NOTES (insn); 1159 while (*pnote != 0) 1160 { 1161 if (REG_NOTE_KIND (*pnote) == REG_DEAD 1162 || REG_NOTE_KIND (*pnote) == REG_UNUSED 1163 || REG_NOTE_KIND (*pnote) == REG_INC 1164 || REG_NOTE_KIND (*pnote) == REG_RETVAL 1165 || REG_NOTE_KIND (*pnote) == REG_LIBCALL) 1166 *pnote = XEXP (*pnote, 1); 1167 else 1168 pnote = &XEXP (*pnote, 1); 1169 } 1170 1171#ifdef AUTO_INC_DEC 1172 add_auto_inc_notes (insn, PATTERN (insn)); 1173#endif 1174 1175 /* And simplify (subreg (reg)) if it appears as an operand. */ 1176 cleanup_subreg_operands (insn); 1177 } 1178 1179 /* If we are doing stack checking, give a warning if this function's 1180 frame size is larger than we expect. */ 1181 if (flag_stack_check && ! STACK_CHECK_BUILTIN) 1182 { 1183 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; 1184 static int verbose_warned = 0; 1185 1186 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1187 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) 1188 size += UNITS_PER_WORD; 1189 1190 if (size > STACK_CHECK_MAX_FRAME_SIZE) 1191 { 1192 warning ("frame size too large for reliable stack checking"); 1193 if (! verbose_warned) 1194 { 1195 warning ("try reducing the number of local variables"); 1196 verbose_warned = 1; 1197 } 1198 } 1199 } 1200 1201 /* Indicate that we no longer have known memory locations or constants. */ 1202 if (reg_equiv_constant) 1203 free (reg_equiv_constant); 1204 reg_equiv_constant = 0; 1205 if (reg_equiv_memory_loc) 1206 free (reg_equiv_memory_loc); 1207 reg_equiv_memory_loc = 0; 1208 1209 if (real_known_ptr) 1210 free (real_known_ptr); 1211 if (real_at_ptr) 1212 free (real_at_ptr); 1213 1214 free (reg_equiv_mem); 1215 free (reg_equiv_init); 1216 free (reg_equiv_address); 1217 free (reg_max_ref_width); 1218 free (reg_old_renumber); 1219 free (pseudo_previous_regs); 1220 free (pseudo_forbidden_regs); 1221 1222 FREE_REG_SET (spilled_pseudos); 1223 1224 CLEAR_HARD_REG_SET (used_spill_regs); 1225 for (i = 0; i < n_spills; i++) 1226 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); 1227 1228 /* Free all the insn_chain structures at once. */ 1229 obstack_free (&reload_obstack, reload_startobj); 1230 unused_insn_chains = 0; 1231 1232 return failure; 1233} 1234 1235/* Yet another special case. Unfortunately, reg-stack forces people to 1236 write incorrect clobbers in asm statements. These clobbers must not 1237 cause the register to appear in bad_spill_regs, otherwise we'll call 1238 fatal_insn later. We clear the corresponding regnos in the live 1239 register sets to avoid this. 1240 The whole thing is rather sick, I'm afraid. */ 1241static void 1242maybe_fix_stack_asms () 1243{ 1244#ifdef STACK_REGS 1245 char *constraints[MAX_RECOG_OPERANDS]; 1246 enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; 1247 struct insn_chain *chain; 1248 1249 for (chain = reload_insn_chain; chain != 0; chain = chain->next) 1250 { 1251 int i, noperands; 1252 HARD_REG_SET clobbered, allowed; 1253 rtx pat; 1254 1255 if (GET_RTX_CLASS (GET_CODE (chain->insn)) != 'i' 1256 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) 1257 continue; 1258 pat = PATTERN (chain->insn); 1259 if (GET_CODE (pat) != PARALLEL) 1260 continue; 1261 1262 CLEAR_HARD_REG_SET (clobbered); 1263 CLEAR_HARD_REG_SET (allowed); 1264 1265 /* First, make a mask of all stack regs that are clobbered. */ 1266 for (i = 0; i < XVECLEN (pat, 0); i++) 1267 { 1268 rtx t = XVECEXP (pat, 0, i); 1269 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) 1270 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); 1271 } 1272 1273 /* Get the operand values and constraints out of the insn. */ 1274 decode_asm_operands (pat, recog_operand, recog_operand_loc, 1275 constraints, operand_mode); 1276 1277 /* For every operand, see what registers are allowed. */ 1278 for (i = 0; i < noperands; i++) 1279 { 1280 char *p = constraints[i]; 1281 /* For every alternative, we compute the class of registers allowed 1282 for reloading in CLS, and merge its contents into the reg set 1283 ALLOWED. */ 1284 int cls = (int) NO_REGS; 1285 1286 for (;;) 1287 { 1288 char c = *p++; 1289 1290 if (c == '\0' || c == ',' || c == '#') 1291 { 1292 /* End of one alternative - mark the regs in the current 1293 class, and reset the class. */ 1294 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); 1295 cls = NO_REGS; 1296 if (c == '#') 1297 do { 1298 c = *p++; 1299 } while (c != '\0' && c != ','); 1300 if (c == '\0') 1301 break; 1302 continue; 1303 } 1304 1305 switch (c) 1306 { 1307 case '=': case '+': case '*': case '%': case '?': case '!': 1308 case '0': case '1': case '2': case '3': case '4': case 'm': 1309 case '<': case '>': case 'V': case 'o': case '&': case 'E': 1310 case 'F': case 's': case 'i': case 'n': case 'X': case 'I': 1311 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': 1312 case 'P': 1313#ifdef EXTRA_CONSTRAINT 1314 case 'Q': case 'R': case 'S': case 'T': case 'U': 1315#endif 1316 break; 1317 1318 case 'p': 1319 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS]; 1320 break; 1321 1322 case 'g': 1323 case 'r': 1324 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; 1325 break; 1326 1327 default: 1328 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)]; 1329 1330 } 1331 } 1332 } 1333 /* Those of the registers which are clobbered, but allowed by the 1334 constraints, must be usable as reload registers. So clear them 1335 out of the life information. */ 1336 AND_HARD_REG_SET (allowed, clobbered); 1337 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1338 if (TEST_HARD_REG_BIT (allowed, i)) 1339 { 1340 CLEAR_REGNO_REG_SET (chain->live_before, i); 1341 CLEAR_REGNO_REG_SET (chain->live_after, i); 1342 } 1343 } 1344 1345#endif 1346} 1347 1348 1349/* Walk the chain of insns, and determine for each whether it needs reloads 1350 and/or eliminations. Build the corresponding insns_need_reload list, and 1351 set something_needs_elimination as appropriate. */ 1352static void 1353calculate_needs_all_insns (global) 1354 int global; 1355{ 1356 struct insn_chain **pprev_reload = &insns_need_reload; 1357 struct insn_chain **pchain; 1358 1359 something_needs_elimination = 0; 1360 1361 for (pchain = &reload_insn_chain; *pchain != 0; pchain = &(*pchain)->next) 1362 { 1363 rtx insn; 1364 struct insn_chain *chain; 1365 1366 chain = *pchain; 1367 insn = chain->insn; 1368 1369 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might 1370 include REG_LABEL), we need to see what effects this has on the 1371 known offsets at labels. */ 1372 1373 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN 1374 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i' 1375 && REG_NOTES (insn) != 0)) 1376 set_label_offsets (insn, insn, 0); 1377 1378 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 1379 { 1380 rtx old_body = PATTERN (insn); 1381 int old_code = INSN_CODE (insn); 1382 rtx old_notes = REG_NOTES (insn); 1383 int did_elimination = 0; 1384 int operands_changed = 0; 1385 rtx set = single_set (insn); 1386 1387 /* Skip insns that only set an equivalence. */ 1388 if (set && GET_CODE (SET_DEST (set)) == REG 1389 && reg_renumber[REGNO (SET_DEST (set))] < 0 1390 && reg_equiv_constant[REGNO (SET_DEST (set))]) 1391 { 1392 /* Must clear out the shortcuts, in case they were set last 1393 time through. */ 1394 chain->need_elim = 0; 1395 chain->need_reload = 0; 1396 chain->need_operand_change = 0; 1397 continue; 1398 } 1399 1400 /* If needed, eliminate any eliminable registers. */ 1401 if (num_eliminable || num_eliminable_invariants) 1402 did_elimination = eliminate_regs_in_insn (insn, 0); 1403 1404 /* Analyze the instruction. */ 1405 operands_changed = find_reloads (insn, 0, spill_indirect_levels, 1406 global, spill_reg_order); 1407 1408 /* If a no-op set needs more than one reload, this is likely 1409 to be something that needs input address reloads. We 1410 can't get rid of this cleanly later, and it is of no use 1411 anyway, so discard it now. 1412 We only do this when expensive_optimizations is enabled, 1413 since this complements reload inheritance / output 1414 reload deletion, and it can make debugging harder. */ 1415 if (flag_expensive_optimizations && n_reloads > 1) 1416 { 1417 rtx set = single_set (insn); 1418 if (set 1419 && SET_SRC (set) == SET_DEST (set) 1420 && GET_CODE (SET_SRC (set)) == REG 1421 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) 1422 { 1423 PUT_CODE (insn, NOTE); 1424 NOTE_SOURCE_FILE (insn) = 0; 1425 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 1426 continue; 1427 } 1428 } 1429 if (num_eliminable) 1430 update_eliminable_offsets (); 1431 1432 /* Remember for later shortcuts which insns had any reloads or 1433 register eliminations. */ 1434 chain->need_elim = did_elimination; 1435 chain->need_reload = n_reloads > 0; 1436 chain->need_operand_change = operands_changed; 1437 1438 /* Discard any register replacements done. */ 1439 if (did_elimination) 1440 { 1441 obstack_free (&reload_obstack, reload_firstobj); 1442 PATTERN (insn) = old_body; 1443 INSN_CODE (insn) = old_code; 1444 REG_NOTES (insn) = old_notes; 1445 something_needs_elimination = 1; 1446 } 1447 1448 something_needs_operands_changed |= operands_changed; 1449 1450 if (n_reloads != 0) 1451 { 1452 *pprev_reload = chain; 1453 pprev_reload = &chain->next_need_reload; 1454 1455 calculate_needs (chain); 1456 } 1457 } 1458 } 1459 *pprev_reload = 0; 1460} 1461 1462/* Compute the most additional registers needed by one instruction, 1463 given by CHAIN. Collect information separately for each class of regs. 1464 1465 To compute the number of reload registers of each class needed for an 1466 insn, we must simulate what choose_reload_regs can do. We do this by 1467 splitting an insn into an "input" and an "output" part. RELOAD_OTHER 1468 reloads are used in both. The input part uses those reloads, 1469 RELOAD_FOR_INPUT reloads, which must be live over the entire input section 1470 of reloads, and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and 1471 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the inputs. 1472 1473 The registers needed for output are RELOAD_OTHER and RELOAD_FOR_OUTPUT, 1474 which are live for the entire output portion, and the maximum of all the 1475 RELOAD_FOR_OUTPUT_ADDRESS reloads for each operand. 1476 1477 The total number of registers needed is the maximum of the 1478 inputs and outputs. */ 1479 1480static void 1481calculate_needs (chain) 1482 struct insn_chain *chain; 1483{ 1484 int i; 1485 1486 /* Each `struct needs' corresponds to one RELOAD_... type. */ 1487 struct { 1488 struct needs other; 1489 struct needs input; 1490 struct needs output; 1491 struct needs insn; 1492 struct needs other_addr; 1493 struct needs op_addr; 1494 struct needs op_addr_reload; 1495 struct needs in_addr[MAX_RECOG_OPERANDS]; 1496 struct needs in_addr_addr[MAX_RECOG_OPERANDS]; 1497 struct needs out_addr[MAX_RECOG_OPERANDS]; 1498 struct needs out_addr_addr[MAX_RECOG_OPERANDS]; 1499 } insn_needs; 1500 1501 bzero ((char *) chain->group_size, sizeof chain->group_size); 1502 for (i = 0; i < N_REG_CLASSES; i++) 1503 chain->group_mode[i] = VOIDmode; 1504 bzero ((char *) &insn_needs, sizeof insn_needs); 1505 1506 /* Count each reload once in every class 1507 containing the reload's own class. */ 1508 1509 for (i = 0; i < n_reloads; i++) 1510 { 1511 register enum reg_class *p; 1512 enum reg_class class = reload_reg_class[i]; 1513 int size; 1514 enum machine_mode mode; 1515 struct needs *this_needs; 1516 1517 /* Don't count the dummy reloads, for which one of the 1518 regs mentioned in the insn can be used for reloading. 1519 Don't count optional reloads. 1520 Don't count reloads that got combined with others. */ 1521 if (reload_reg_rtx[i] != 0 1522 || reload_optional[i] != 0 1523 || (reload_out[i] == 0 && reload_in[i] == 0 1524 && ! reload_secondary_p[i])) 1525 continue; 1526 1527 mode = reload_inmode[i]; 1528 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode)) 1529 mode = reload_outmode[i]; 1530 size = CLASS_MAX_NREGS (class, mode); 1531 1532 /* Decide which time-of-use to count this reload for. */ 1533 switch (reload_when_needed[i]) 1534 { 1535 case RELOAD_OTHER: 1536 this_needs = &insn_needs.other; 1537 break; 1538 case RELOAD_FOR_INPUT: 1539 this_needs = &insn_needs.input; 1540 break; 1541 case RELOAD_FOR_OUTPUT: 1542 this_needs = &insn_needs.output; 1543 break; 1544 case RELOAD_FOR_INSN: 1545 this_needs = &insn_needs.insn; 1546 break; 1547 case RELOAD_FOR_OTHER_ADDRESS: 1548 this_needs = &insn_needs.other_addr; 1549 break; 1550 case RELOAD_FOR_INPUT_ADDRESS: 1551 this_needs = &insn_needs.in_addr[reload_opnum[i]]; 1552 break; 1553 case RELOAD_FOR_INPADDR_ADDRESS: 1554 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]]; 1555 break; 1556 case RELOAD_FOR_OUTPUT_ADDRESS: 1557 this_needs = &insn_needs.out_addr[reload_opnum[i]]; 1558 break; 1559 case RELOAD_FOR_OUTADDR_ADDRESS: 1560 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]]; 1561 break; 1562 case RELOAD_FOR_OPERAND_ADDRESS: 1563 this_needs = &insn_needs.op_addr; 1564 break; 1565 case RELOAD_FOR_OPADDR_ADDR: 1566 this_needs = &insn_needs.op_addr_reload; 1567 break; 1568 default: 1569 abort(); 1570 } 1571 1572 if (size > 1) 1573 { 1574 enum machine_mode other_mode, allocate_mode; 1575 1576 /* Count number of groups needed separately from 1577 number of individual regs needed. */ 1578 this_needs->groups[(int) class]++; 1579 p = reg_class_superclasses[(int) class]; 1580 while (*p != LIM_REG_CLASSES) 1581 this_needs->groups[(int) *p++]++; 1582 1583 /* Record size and mode of a group of this class. */ 1584 /* If more than one size group is needed, 1585 make all groups the largest needed size. */ 1586 if (chain->group_size[(int) class] < size) 1587 { 1588 other_mode = chain->group_mode[(int) class]; 1589 allocate_mode = mode; 1590 1591 chain->group_size[(int) class] = size; 1592 chain->group_mode[(int) class] = mode; 1593 } 1594 else 1595 { 1596 other_mode = mode; 1597 allocate_mode = chain->group_mode[(int) class]; 1598 } 1599 1600 /* Crash if two dissimilar machine modes both need 1601 groups of consecutive regs of the same class. */ 1602 1603 if (other_mode != VOIDmode && other_mode != allocate_mode 1604 && ! modes_equiv_for_class_p (allocate_mode, 1605 other_mode, class)) 1606 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class", 1607 chain->insn); 1608 } 1609 else if (size == 1) 1610 { 1611 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) class] += 1; 1612 p = reg_class_superclasses[(int) class]; 1613 while (*p != LIM_REG_CLASSES) 1614 this_needs->regs[(unsigned char)reload_nongroup[i]][(int) *p++] += 1; 1615 } 1616 else 1617 abort (); 1618 } 1619 1620 /* All reloads have been counted for this insn; 1621 now merge the various times of use. 1622 This sets insn_needs, etc., to the maximum total number 1623 of registers needed at any point in this insn. */ 1624 1625 for (i = 0; i < N_REG_CLASSES; i++) 1626 { 1627 int j, in_max, out_max; 1628 1629 /* Compute normal and nongroup needs. */ 1630 for (j = 0; j <= 1; j++) 1631 { 1632 int k; 1633 for (in_max = 0, out_max = 0, k = 0; k < reload_n_operands; k++) 1634 { 1635 in_max = MAX (in_max, 1636 (insn_needs.in_addr[k].regs[j][i] 1637 + insn_needs.in_addr_addr[k].regs[j][i])); 1638 out_max = MAX (out_max, insn_needs.out_addr[k].regs[j][i]); 1639 out_max = MAX (out_max, 1640 insn_needs.out_addr_addr[k].regs[j][i]); 1641 } 1642 1643 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs, 1644 and operand addresses but not things used to reload 1645 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads 1646 don't conflict with things needed to reload inputs or 1647 outputs. */ 1648 1649 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i], 1650 insn_needs.op_addr_reload.regs[j][i]), 1651 in_max); 1652 1653 out_max = MAX (out_max, insn_needs.insn.regs[j][i]); 1654 1655 insn_needs.input.regs[j][i] 1656 = MAX (insn_needs.input.regs[j][i] 1657 + insn_needs.op_addr.regs[j][i] 1658 + insn_needs.insn.regs[j][i], 1659 in_max + insn_needs.input.regs[j][i]); 1660 1661 insn_needs.output.regs[j][i] += out_max; 1662 insn_needs.other.regs[j][i] 1663 += MAX (MAX (insn_needs.input.regs[j][i], 1664 insn_needs.output.regs[j][i]), 1665 insn_needs.other_addr.regs[j][i]); 1666 1667 } 1668 1669 /* Now compute group needs. */ 1670 for (in_max = 0, out_max = 0, j = 0; j < reload_n_operands; j++) 1671 { 1672 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]); 1673 in_max = MAX (in_max, insn_needs.in_addr_addr[j].groups[i]); 1674 out_max = MAX (out_max, insn_needs.out_addr[j].groups[i]); 1675 out_max = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]); 1676 } 1677 1678 in_max = MAX (MAX (insn_needs.op_addr.groups[i], 1679 insn_needs.op_addr_reload.groups[i]), 1680 in_max); 1681 out_max = MAX (out_max, insn_needs.insn.groups[i]); 1682 1683 insn_needs.input.groups[i] 1684 = MAX (insn_needs.input.groups[i] 1685 + insn_needs.op_addr.groups[i] 1686 + insn_needs.insn.groups[i], 1687 in_max + insn_needs.input.groups[i]); 1688 1689 insn_needs.output.groups[i] += out_max; 1690 insn_needs.other.groups[i] 1691 += MAX (MAX (insn_needs.input.groups[i], 1692 insn_needs.output.groups[i]), 1693 insn_needs.other_addr.groups[i]); 1694 } 1695 1696 /* Record the needs for later. */ 1697 chain->need = insn_needs.other; 1698} 1699 1700/* Find a group of exactly 2 registers. 1701 1702 First try to fill out the group by spilling a single register which 1703 would allow completion of the group. 1704 1705 Then try to create a new group from a pair of registers, neither of 1706 which are explicitly used. 1707 1708 Then try to create a group from any pair of registers. */ 1709 1710static void 1711find_tworeg_group (chain, class, dumpfile) 1712 struct insn_chain *chain; 1713 int class; 1714 FILE *dumpfile; 1715{ 1716 int i; 1717 /* First, look for a register that will complete a group. */ 1718 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1719 { 1720 int j, other; 1721 1722 j = potential_reload_regs[i]; 1723 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j) 1724 && ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0) 1725 && TEST_HARD_REG_BIT (reg_class_contents[class], j) 1726 && TEST_HARD_REG_BIT (reg_class_contents[class], other) 1727 && HARD_REGNO_MODE_OK (other, chain->group_mode[class]) 1728 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other) 1729 /* We don't want one part of another group. 1730 We could get "two groups" that overlap! */ 1731 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other)) 1732 || (j < FIRST_PSEUDO_REGISTER - 1 1733 && (other = j + 1, spill_reg_order[other] >= 0) 1734 && TEST_HARD_REG_BIT (reg_class_contents[class], j) 1735 && TEST_HARD_REG_BIT (reg_class_contents[class], other) 1736 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]) 1737 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, other) 1738 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, other)))) 1739 { 1740 register enum reg_class *p; 1741 1742 /* We have found one that will complete a group, 1743 so count off one group as provided. */ 1744 chain->need.groups[class]--; 1745 p = reg_class_superclasses[class]; 1746 while (*p != LIM_REG_CLASSES) 1747 { 1748 if (chain->group_size [(int) *p] <= chain->group_size [class]) 1749 chain->need.groups[(int) *p]--; 1750 p++; 1751 } 1752 1753 /* Indicate both these regs are part of a group. */ 1754 SET_HARD_REG_BIT (chain->counted_for_groups, j); 1755 SET_HARD_REG_BIT (chain->counted_for_groups, other); 1756 break; 1757 } 1758 } 1759 /* We can't complete a group, so start one. */ 1760 if (i == FIRST_PSEUDO_REGISTER) 1761 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1762 { 1763 int j, k; 1764 j = potential_reload_regs[i]; 1765 /* Verify that J+1 is a potential reload reg. */ 1766 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++) 1767 if (potential_reload_regs[k] == j + 1) 1768 break; 1769 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER 1770 && k < FIRST_PSEUDO_REGISTER 1771 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0 1772 && TEST_HARD_REG_BIT (reg_class_contents[class], j) 1773 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1) 1774 && HARD_REGNO_MODE_OK (j, chain->group_mode[class]) 1775 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, j + 1) 1776 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)) 1777 break; 1778 } 1779 1780 /* I should be the index in potential_reload_regs 1781 of the new reload reg we have found. */ 1782 1783 new_spill_reg (chain, i, class, 0, dumpfile); 1784} 1785 1786/* Find a group of more than 2 registers. 1787 Look for a sufficient sequence of unspilled registers, and spill them all 1788 at once. */ 1789 1790static void 1791find_group (chain, class, dumpfile) 1792 struct insn_chain *chain; 1793 int class; 1794 FILE *dumpfile; 1795{ 1796 int i; 1797 1798 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1799 { 1800 int j = potential_reload_regs[i]; 1801 1802 if (j >= 0 1803 && j + chain->group_size[class] <= FIRST_PSEUDO_REGISTER 1804 && HARD_REGNO_MODE_OK (j, chain->group_mode[class])) 1805 { 1806 int k; 1807 /* Check each reg in the sequence. */ 1808 for (k = 0; k < chain->group_size[class]; k++) 1809 if (! (spill_reg_order[j + k] < 0 1810 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k) 1811 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k))) 1812 break; 1813 /* We got a full sequence, so spill them all. */ 1814 if (k == chain->group_size[class]) 1815 { 1816 register enum reg_class *p; 1817 for (k = 0; k < chain->group_size[class]; k++) 1818 { 1819 int idx; 1820 SET_HARD_REG_BIT (chain->counted_for_groups, j + k); 1821 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) 1822 if (potential_reload_regs[idx] == j + k) 1823 break; 1824 new_spill_reg (chain, idx, class, 0, dumpfile); 1825 } 1826 1827 /* We have found one that will complete a group, 1828 so count off one group as provided. */ 1829 chain->need.groups[class]--; 1830 p = reg_class_superclasses[class]; 1831 while (*p != LIM_REG_CLASSES) 1832 { 1833 if (chain->group_size [(int) *p] 1834 <= chain->group_size [class]) 1835 chain->need.groups[(int) *p]--; 1836 p++; 1837 } 1838 return; 1839 } 1840 } 1841 } 1842 /* There are no groups left. */ 1843 spill_failure (chain->insn); 1844 failure = 1; 1845} 1846 1847/* If pseudo REG conflicts with one of our reload registers, mark it as 1848 spilled. */ 1849static void 1850maybe_mark_pseudo_spilled (reg) 1851 int reg; 1852{ 1853 int i; 1854 int r = reg_renumber[reg]; 1855 int nregs; 1856 1857 if (r < 0) 1858 abort (); 1859 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); 1860 for (i = 0; i < n_spills; i++) 1861 if (r <= spill_regs[i] && r + nregs > spill_regs[i]) 1862 { 1863 SET_REGNO_REG_SET (spilled_pseudos, reg); 1864 return; 1865 } 1866} 1867 1868/* Find more reload regs to satisfy the remaining need of an insn, which 1869 is given by CHAIN. 1870 Do it by ascending class number, since otherwise a reg 1871 might be spilled for a big class and might fail to count 1872 for a smaller class even though it belongs to that class. 1873 1874 Count spilled regs in `spills', and add entries to 1875 `spill_regs' and `spill_reg_order'. 1876 1877 ??? Note there is a problem here. 1878 When there is a need for a group in a high-numbered class, 1879 and also need for non-group regs that come from a lower class, 1880 the non-group regs are chosen first. If there aren't many regs, 1881 they might leave no room for a group. 1882 1883 This was happening on the 386. To fix it, we added the code 1884 that calls possible_group_p, so that the lower class won't 1885 break up the last possible group. 1886 1887 Really fixing the problem would require changes above 1888 in counting the regs already spilled, and in choose_reload_regs. 1889 It might be hard to avoid introducing bugs there. */ 1890 1891static void 1892find_reload_regs (chain, dumpfile) 1893 struct insn_chain *chain; 1894 FILE *dumpfile; 1895{ 1896 int i, class; 1897 short *group_needs = chain->need.groups; 1898 short *simple_needs = chain->need.regs[0]; 1899 short *nongroup_needs = chain->need.regs[1]; 1900 1901 if (dumpfile) 1902 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn)); 1903 1904 /* Compute the order of preference for hard registers to spill. 1905 Store them by decreasing preference in potential_reload_regs. */ 1906 1907 order_regs_for_reload (chain); 1908 1909 /* So far, no hard regs have been spilled. */ 1910 n_spills = 0; 1911 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1912 spill_reg_order[i] = -1; 1913 1914 CLEAR_HARD_REG_SET (chain->used_spill_regs); 1915 CLEAR_HARD_REG_SET (chain->counted_for_groups); 1916 CLEAR_HARD_REG_SET (chain->counted_for_nongroups); 1917 1918 for (class = 0; class < N_REG_CLASSES; class++) 1919 { 1920 /* First get the groups of registers. 1921 If we got single registers first, we might fragment 1922 possible groups. */ 1923 while (group_needs[class] > 0) 1924 { 1925 /* If any single spilled regs happen to form groups, 1926 count them now. Maybe we don't really need 1927 to spill another group. */ 1928 count_possible_groups (chain, class); 1929 1930 if (group_needs[class] <= 0) 1931 break; 1932 1933 /* Groups of size 2, the only groups used on most machines, 1934 are treated specially. */ 1935 if (chain->group_size[class] == 2) 1936 find_tworeg_group (chain, class, dumpfile); 1937 else 1938 find_group (chain, class, dumpfile); 1939 if (failure) 1940 return; 1941 } 1942 1943 /* Now similarly satisfy all need for single registers. */ 1944 1945 while (simple_needs[class] > 0 || nongroup_needs[class] > 0) 1946 { 1947 /* If we spilled enough regs, but they weren't counted 1948 against the non-group need, see if we can count them now. 1949 If so, we can avoid some actual spilling. */ 1950 if (simple_needs[class] <= 0 && nongroup_needs[class] > 0) 1951 for (i = 0; i < n_spills; i++) 1952 { 1953 int regno = spill_regs[i]; 1954 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) 1955 && !TEST_HARD_REG_BIT (chain->counted_for_groups, regno) 1956 && !TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno) 1957 && nongroup_needs[class] > 0) 1958 { 1959 register enum reg_class *p; 1960 1961 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno); 1962 nongroup_needs[class]--; 1963 p = reg_class_superclasses[class]; 1964 while (*p != LIM_REG_CLASSES) 1965 nongroup_needs[(int) *p++]--; 1966 } 1967 } 1968 1969 if (simple_needs[class] <= 0 && nongroup_needs[class] <= 0) 1970 break; 1971 1972 /* Consider the potential reload regs that aren't 1973 yet in use as reload regs, in order of preference. 1974 Find the most preferred one that's in this class. */ 1975 1976 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1977 { 1978 int regno = potential_reload_regs[i]; 1979 if (regno >= 0 1980 && TEST_HARD_REG_BIT (reg_class_contents[class], regno) 1981 /* If this reg will not be available for groups, 1982 pick one that does not foreclose possible groups. 1983 This is a kludge, and not very general, 1984 but it should be sufficient to make the 386 work, 1985 and the problem should not occur on machines with 1986 more registers. */ 1987 && (nongroup_needs[class] == 0 1988 || possible_group_p (chain, regno))) 1989 break; 1990 } 1991 1992 /* If we couldn't get a register, try to get one even if we 1993 might foreclose possible groups. This may cause problems 1994 later, but that's better than aborting now, since it is 1995 possible that we will, in fact, be able to form the needed 1996 group even with this allocation. */ 1997 1998 if (i >= FIRST_PSEUDO_REGISTER 1999 && asm_noperands (chain->insn) < 0) 2000 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2001 if (potential_reload_regs[i] >= 0 2002 && TEST_HARD_REG_BIT (reg_class_contents[class], 2003 potential_reload_regs[i])) 2004 break; 2005 2006 /* I should be the index in potential_reload_regs 2007 of the new reload reg we have found. */ 2008 2009 new_spill_reg (chain, i, class, 1, dumpfile); 2010 if (failure) 2011 return; 2012 } 2013 } 2014 2015 /* We know which hard regs to use, now mark the pseudos that live in them 2016 as needing to be kicked out. */ 2017 EXECUTE_IF_SET_IN_REG_SET 2018 (chain->live_before, FIRST_PSEUDO_REGISTER, i, 2019 { 2020 maybe_mark_pseudo_spilled (i); 2021 }); 2022 EXECUTE_IF_SET_IN_REG_SET 2023 (chain->live_after, FIRST_PSEUDO_REGISTER, i, 2024 { 2025 maybe_mark_pseudo_spilled (i); 2026 }); 2027 2028 IOR_HARD_REG_SET (used_spill_regs, chain->used_spill_regs); 2029} 2030 2031void 2032dump_needs (chain, dumpfile) 2033 struct insn_chain *chain; 2034 FILE *dumpfile; 2035{ 2036 static char *reg_class_names[] = REG_CLASS_NAMES; 2037 int i; 2038 struct needs *n = &chain->need; 2039 2040 for (i = 0; i < N_REG_CLASSES; i++) 2041 { 2042 if (n->regs[i][0] > 0) 2043 fprintf (dumpfile, 2044 ";; Need %d reg%s of class %s.\n", 2045 n->regs[i][0], n->regs[i][0] == 1 ? "" : "s", 2046 reg_class_names[i]); 2047 if (n->regs[i][1] > 0) 2048 fprintf (dumpfile, 2049 ";; Need %d nongroup reg%s of class %s.\n", 2050 n->regs[i][1], n->regs[i][1] == 1 ? "" : "s", 2051 reg_class_names[i]); 2052 if (n->groups[i] > 0) 2053 fprintf (dumpfile, 2054 ";; Need %d group%s (%smode) of class %s.\n", 2055 n->groups[i], n->groups[i] == 1 ? "" : "s", 2056 mode_name[(int) chain->group_mode[i]], 2057 reg_class_names[i]); 2058 } 2059} 2060 2061/* Delete all insns that were inserted by emit_caller_save_insns during 2062 this iteration. */ 2063static void 2064delete_caller_save_insns () 2065{ 2066 struct insn_chain *c = reload_insn_chain; 2067 2068 while (c != 0) 2069 { 2070 while (c != 0 && c->is_caller_save_insn) 2071 { 2072 struct insn_chain *next = c->next; 2073 rtx insn = c->insn; 2074 2075 if (insn == BLOCK_HEAD (c->block)) 2076 BLOCK_HEAD (c->block) = NEXT_INSN (insn); 2077 if (insn == BLOCK_END (c->block)) 2078 BLOCK_END (c->block) = PREV_INSN (insn); 2079 if (c == reload_insn_chain) 2080 reload_insn_chain = next; 2081 2082 if (NEXT_INSN (insn) != 0) 2083 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn); 2084 if (PREV_INSN (insn) != 0) 2085 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn); 2086 2087 if (next) 2088 next->prev = c->prev; 2089 if (c->prev) 2090 c->prev->next = next; 2091 c->next = unused_insn_chains; 2092 unused_insn_chains = c; 2093 c = next; 2094 } 2095 if (c != 0) 2096 c = c->next; 2097 } 2098} 2099 2100/* Nonzero if, after spilling reg REGNO for non-groups, 2101 it will still be possible to find a group if we still need one. */ 2102 2103static int 2104possible_group_p (chain, regno) 2105 struct insn_chain *chain; 2106 int regno; 2107{ 2108 int i; 2109 int class = (int) NO_REGS; 2110 2111 for (i = 0; i < (int) N_REG_CLASSES; i++) 2112 if (chain->need.groups[i] > 0) 2113 { 2114 class = i; 2115 break; 2116 } 2117 2118 if (class == (int) NO_REGS) 2119 return 1; 2120 2121 /* Consider each pair of consecutive registers. */ 2122 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++) 2123 { 2124 /* Ignore pairs that include reg REGNO. */ 2125 if (i == regno || i + 1 == regno) 2126 continue; 2127 2128 /* Ignore pairs that are outside the class that needs the group. 2129 ??? Here we fail to handle the case where two different classes 2130 independently need groups. But this never happens with our 2131 current machine descriptions. */ 2132 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i) 2133 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1))) 2134 continue; 2135 2136 /* A pair of consecutive regs we can still spill does the trick. */ 2137 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0 2138 && ! TEST_HARD_REG_BIT (bad_spill_regs, i) 2139 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)) 2140 return 1; 2141 2142 /* A pair of one already spilled and one we can spill does it 2143 provided the one already spilled is not otherwise reserved. */ 2144 if (spill_reg_order[i] < 0 2145 && ! TEST_HARD_REG_BIT (bad_spill_regs, i) 2146 && spill_reg_order[i + 1] >= 0 2147 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i + 1) 2148 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i + 1)) 2149 return 1; 2150 if (spill_reg_order[i + 1] < 0 2151 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1) 2152 && spill_reg_order[i] >= 0 2153 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, i) 2154 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, i)) 2155 return 1; 2156 } 2157 2158 return 0; 2159} 2160 2161/* Count any groups of CLASS that can be formed from the registers recently 2162 spilled. */ 2163 2164static void 2165count_possible_groups (chain, class) 2166 struct insn_chain *chain; 2167 int class; 2168{ 2169 HARD_REG_SET new; 2170 int i, j; 2171 2172 /* Now find all consecutive groups of spilled registers 2173 and mark each group off against the need for such groups. 2174 But don't count them against ordinary need, yet. */ 2175 2176 if (chain->group_size[class] == 0) 2177 return; 2178 2179 CLEAR_HARD_REG_SET (new); 2180 2181 /* Make a mask of all the regs that are spill regs in class I. */ 2182 for (i = 0; i < n_spills; i++) 2183 { 2184 int regno = spill_regs[i]; 2185 2186 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno) 2187 && ! TEST_HARD_REG_BIT (chain->counted_for_groups, regno) 2188 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regno)) 2189 SET_HARD_REG_BIT (new, regno); 2190 } 2191 2192 /* Find each consecutive group of them. */ 2193 for (i = 0; i < FIRST_PSEUDO_REGISTER && chain->need.groups[class] > 0; i++) 2194 if (TEST_HARD_REG_BIT (new, i) 2195 && i + chain->group_size[class] <= FIRST_PSEUDO_REGISTER 2196 && HARD_REGNO_MODE_OK (i, chain->group_mode[class])) 2197 { 2198 for (j = 1; j < chain->group_size[class]; j++) 2199 if (! TEST_HARD_REG_BIT (new, i + j)) 2200 break; 2201 2202 if (j == chain->group_size[class]) 2203 { 2204 /* We found a group. Mark it off against this class's need for 2205 groups, and against each superclass too. */ 2206 register enum reg_class *p; 2207 2208 chain->need.groups[class]--; 2209 p = reg_class_superclasses[class]; 2210 while (*p != LIM_REG_CLASSES) 2211 { 2212 if (chain->group_size [(int) *p] <= chain->group_size [class]) 2213 chain->need.groups[(int) *p]--; 2214 p++; 2215 } 2216 2217 /* Don't count these registers again. */ 2218 for (j = 0; j < chain->group_size[class]; j++) 2219 SET_HARD_REG_BIT (chain->counted_for_groups, i + j); 2220 } 2221 2222 /* Skip to the last reg in this group. When i is incremented above, 2223 it will then point to the first reg of the next possible group. */ 2224 i += j - 1; 2225 } 2226} 2227 2228/* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is 2229 another mode that needs to be reloaded for the same register class CLASS. 2230 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail. 2231 ALLOCATE_MODE will never be smaller than OTHER_MODE. 2232 2233 This code used to also fail if any reg in CLASS allows OTHER_MODE but not 2234 ALLOCATE_MODE. This test is unnecessary, because we will never try to put 2235 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this 2236 causes unnecessary failures on machines requiring alignment of register 2237 groups when the two modes are different sizes, because the larger mode has 2238 more strict alignment rules than the smaller mode. */ 2239 2240static int 2241modes_equiv_for_class_p (allocate_mode, other_mode, class) 2242 enum machine_mode allocate_mode, other_mode; 2243 enum reg_class class; 2244{ 2245 register int regno; 2246 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 2247 { 2248 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) 2249 && HARD_REGNO_MODE_OK (regno, allocate_mode) 2250 && ! HARD_REGNO_MODE_OK (regno, other_mode)) 2251 return 0; 2252 } 2253 return 1; 2254} 2255 2256/* Handle the failure to find a register to spill. 2257 INSN should be one of the insns which needed this particular spill reg. */ 2258 2259static void 2260spill_failure (insn) 2261 rtx insn; 2262{ 2263 if (asm_noperands (PATTERN (insn)) >= 0) 2264 error_for_asm (insn, "`asm' needs too many reloads"); 2265 else 2266 fatal_insn ("Unable to find a register to spill.", insn); 2267} 2268 2269/* Add a new register to the tables of available spill-registers. 2270 CHAIN is the insn for which the register will be used; we decrease the 2271 needs of that insn. 2272 I is the index of this register in potential_reload_regs. 2273 CLASS is the regclass whose need is being satisfied. 2274 NONGROUP is 0 if this register is part of a group. 2275 DUMPFILE is the same as the one that `reload' got. */ 2276 2277static void 2278new_spill_reg (chain, i, class, nongroup, dumpfile) 2279 struct insn_chain *chain; 2280 int i; 2281 int class; 2282 int nongroup; 2283 FILE *dumpfile; 2284{ 2285 register enum reg_class *p; 2286 int regno = potential_reload_regs[i]; 2287 2288 if (i >= FIRST_PSEUDO_REGISTER) 2289 { 2290 spill_failure (chain->insn); 2291 failure = 1; 2292 return; 2293 } 2294 2295 if (TEST_HARD_REG_BIT (bad_spill_regs, regno)) 2296 { 2297 static char *reg_class_names[] = REG_CLASS_NAMES; 2298 2299 if (asm_noperands (PATTERN (chain->insn)) < 0) 2300 { 2301 /* The error message is still correct - we know only that it wasn't 2302 an asm statement that caused the problem, but one of the global 2303 registers declared by the users might have screwed us. */ 2304 error ("fixed or forbidden register %d (%s) was spilled for class %s.", 2305 regno, reg_names[regno], reg_class_names[class]); 2306 error ("This may be due to a compiler bug or to impossible asm"); 2307 error ("statements or clauses."); 2308 fatal_insn ("This is the instruction:", chain->insn); 2309 } 2310 error_for_asm (chain->insn, "Invalid `asm' statement:"); 2311 error_for_asm (chain->insn, 2312 "fixed or forbidden register %d (%s) was spilled for class %s.", 2313 regno, reg_names[regno], reg_class_names[class]); 2314 failure = 1; 2315 return; 2316 } 2317 2318 /* Make reg REGNO an additional reload reg. */ 2319 2320 potential_reload_regs[i] = -1; 2321 spill_regs[n_spills] = regno; 2322 spill_reg_order[regno] = n_spills; 2323 if (dumpfile) 2324 fprintf (dumpfile, "Spilling reg %d.\n", regno); 2325 SET_HARD_REG_BIT (chain->used_spill_regs, regno); 2326 2327 /* Clear off the needs we just satisfied. */ 2328 2329 chain->need.regs[0][class]--; 2330 p = reg_class_superclasses[class]; 2331 while (*p != LIM_REG_CLASSES) 2332 chain->need.regs[0][(int) *p++]--; 2333 2334 if (nongroup && chain->need.regs[1][class] > 0) 2335 { 2336 SET_HARD_REG_BIT (chain->counted_for_nongroups, regno); 2337 chain->need.regs[1][class]--; 2338 p = reg_class_superclasses[class]; 2339 while (*p != LIM_REG_CLASSES) 2340 chain->need.regs[1][(int) *p++]--; 2341 } 2342 2343 n_spills++; 2344} 2345 2346/* Delete an unneeded INSN and any previous insns who sole purpose is loading 2347 data that is dead in INSN. */ 2348 2349static void 2350delete_dead_insn (insn) 2351 rtx insn; 2352{ 2353 rtx prev = prev_real_insn (insn); 2354 rtx prev_dest; 2355 2356 /* If the previous insn sets a register that dies in our insn, delete it 2357 too. */ 2358 if (prev && GET_CODE (PATTERN (prev)) == SET 2359 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) 2360 && reg_mentioned_p (prev_dest, PATTERN (insn)) 2361 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) 2362 && ! side_effects_p (SET_SRC (PATTERN (prev)))) 2363 delete_dead_insn (prev); 2364 2365 PUT_CODE (insn, NOTE); 2366 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 2367 NOTE_SOURCE_FILE (insn) = 0; 2368} 2369 2370/* Modify the home of pseudo-reg I. 2371 The new home is present in reg_renumber[I]. 2372 2373 FROM_REG may be the hard reg that the pseudo-reg is being spilled from; 2374 or it may be -1, meaning there is none or it is not relevant. 2375 This is used so that all pseudos spilled from a given hard reg 2376 can share one stack slot. */ 2377 2378static void 2379alter_reg (i, from_reg) 2380 register int i; 2381 int from_reg; 2382{ 2383 /* When outputting an inline function, this can happen 2384 for a reg that isn't actually used. */ 2385 if (regno_reg_rtx[i] == 0) 2386 return; 2387 2388 /* If the reg got changed to a MEM at rtl-generation time, 2389 ignore it. */ 2390 if (GET_CODE (regno_reg_rtx[i]) != REG) 2391 return; 2392 2393 /* Modify the reg-rtx to contain the new hard reg 2394 number or else to contain its pseudo reg number. */ 2395 REGNO (regno_reg_rtx[i]) 2396 = reg_renumber[i] >= 0 ? reg_renumber[i] : i; 2397 2398 /* If we have a pseudo that is needed but has no hard reg or equivalent, 2399 allocate a stack slot for it. */ 2400 2401 if (reg_renumber[i] < 0 2402 && REG_N_REFS (i) > 0 2403 && reg_equiv_constant[i] == 0 2404 && reg_equiv_memory_loc[i] == 0) 2405 { 2406 register rtx x; 2407 int inherent_size = PSEUDO_REGNO_BYTES (i); 2408 int total_size = MAX (inherent_size, reg_max_ref_width[i]); 2409 int adjust = 0; 2410 2411 /* Each pseudo reg has an inherent size which comes from its own mode, 2412 and a total size which provides room for paradoxical subregs 2413 which refer to the pseudo reg in wider modes. 2414 2415 We can use a slot already allocated if it provides both 2416 enough inherent space and enough total space. 2417 Otherwise, we allocate a new slot, making sure that it has no less 2418 inherent space, and no less total space, then the previous slot. */ 2419 if (from_reg == -1) 2420 { 2421 /* No known place to spill from => no slot to reuse. */ 2422 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, 2423 inherent_size == total_size ? 0 : -1); 2424 if (BYTES_BIG_ENDIAN) 2425 /* Cancel the big-endian correction done in assign_stack_local. 2426 Get the address of the beginning of the slot. 2427 This is so we can do a big-endian correction unconditionally 2428 below. */ 2429 adjust = inherent_size - total_size; 2430 2431 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); 2432 } 2433 /* Reuse a stack slot if possible. */ 2434 else if (spill_stack_slot[from_reg] != 0 2435 && spill_stack_slot_width[from_reg] >= total_size 2436 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) 2437 >= inherent_size)) 2438 x = spill_stack_slot[from_reg]; 2439 /* Allocate a bigger slot. */ 2440 else 2441 { 2442 /* Compute maximum size needed, both for inherent size 2443 and for total size. */ 2444 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); 2445 rtx stack_slot; 2446 if (spill_stack_slot[from_reg]) 2447 { 2448 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) 2449 > inherent_size) 2450 mode = GET_MODE (spill_stack_slot[from_reg]); 2451 if (spill_stack_slot_width[from_reg] > total_size) 2452 total_size = spill_stack_slot_width[from_reg]; 2453 } 2454 /* Make a slot with that size. */ 2455 x = assign_stack_local (mode, total_size, 2456 inherent_size == total_size ? 0 : -1); 2457 stack_slot = x; 2458 if (BYTES_BIG_ENDIAN) 2459 { 2460 /* Cancel the big-endian correction done in assign_stack_local. 2461 Get the address of the beginning of the slot. 2462 This is so we can do a big-endian correction unconditionally 2463 below. */ 2464 adjust = GET_MODE_SIZE (mode) - total_size; 2465 if (adjust) 2466 stack_slot = gen_rtx_MEM (mode_for_size (total_size 2467 * BITS_PER_UNIT, 2468 MODE_INT, 1), 2469 plus_constant (XEXP (x, 0), adjust)); 2470 } 2471 spill_stack_slot[from_reg] = stack_slot; 2472 spill_stack_slot_width[from_reg] = total_size; 2473 } 2474 2475 /* On a big endian machine, the "address" of the slot 2476 is the address of the low part that fits its inherent mode. */ 2477 if (BYTES_BIG_ENDIAN && inherent_size < total_size) 2478 adjust += (total_size - inherent_size); 2479 2480 /* If we have any adjustment to make, or if the stack slot is the 2481 wrong mode, make a new stack slot. */ 2482 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i])) 2483 { 2484 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]), 2485 plus_constant (XEXP (x, 0), adjust)); 2486 2487 /* If this was shared among registers, must ensure we never 2488 set it readonly since that can cause scheduling 2489 problems. Note we would only have in this adjustment 2490 case in any event, since the code above doesn't set it. */ 2491 2492 if (from_reg == -1) 2493 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); 2494 } 2495 2496 /* Save the stack slot for later. */ 2497 reg_equiv_memory_loc[i] = x; 2498 } 2499} 2500 2501/* Mark the slots in regs_ever_live for the hard regs 2502 used by pseudo-reg number REGNO. */ 2503 2504void 2505mark_home_live (regno) 2506 int regno; 2507{ 2508 register int i, lim; 2509 i = reg_renumber[regno]; 2510 if (i < 0) 2511 return; 2512 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); 2513 while (i < lim) 2514 regs_ever_live[i++] = 1; 2515} 2516 2517/* This function handles the tracking of elimination offsets around branches. 2518 2519 X is a piece of RTL being scanned. 2520 2521 INSN is the insn that it came from, if any. 2522 2523 INITIAL_P is non-zero if we are to set the offset to be the initial 2524 offset and zero if we are setting the offset of the label to be the 2525 current offset. */ 2526 2527static void 2528set_label_offsets (x, insn, initial_p) 2529 rtx x; 2530 rtx insn; 2531 int initial_p; 2532{ 2533 enum rtx_code code = GET_CODE (x); 2534 rtx tem; 2535 unsigned int i; 2536 struct elim_table *p; 2537 2538 switch (code) 2539 { 2540 case LABEL_REF: 2541 if (LABEL_REF_NONLOCAL_P (x)) 2542 return; 2543 2544 x = XEXP (x, 0); 2545 2546 /* ... fall through ... */ 2547 2548 case CODE_LABEL: 2549 /* If we know nothing about this label, set the desired offsets. Note 2550 that this sets the offset at a label to be the offset before a label 2551 if we don't know anything about the label. This is not correct for 2552 the label after a BARRIER, but is the best guess we can make. If 2553 we guessed wrong, we will suppress an elimination that might have 2554 been possible had we been able to guess correctly. */ 2555 2556 if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) 2557 { 2558 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2559 offsets_at[CODE_LABEL_NUMBER (x)][i] 2560 = (initial_p ? reg_eliminate[i].initial_offset 2561 : reg_eliminate[i].offset); 2562 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; 2563 } 2564 2565 /* Otherwise, if this is the definition of a label and it is 2566 preceded by a BARRIER, set our offsets to the known offset of 2567 that label. */ 2568 2569 else if (x == insn 2570 && (tem = prev_nonnote_insn (insn)) != 0 2571 && GET_CODE (tem) == BARRIER) 2572 set_offsets_for_label (insn); 2573 else 2574 /* If neither of the above cases is true, compare each offset 2575 with those previously recorded and suppress any eliminations 2576 where the offsets disagree. */ 2577 2578 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2579 if (offsets_at[CODE_LABEL_NUMBER (x)][i] 2580 != (initial_p ? reg_eliminate[i].initial_offset 2581 : reg_eliminate[i].offset)) 2582 reg_eliminate[i].can_eliminate = 0; 2583 2584 return; 2585 2586 case JUMP_INSN: 2587 set_label_offsets (PATTERN (insn), insn, initial_p); 2588 2589 /* ... fall through ... */ 2590 2591 case INSN: 2592 case CALL_INSN: 2593 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly 2594 and hence must have all eliminations at their initial offsets. */ 2595 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) 2596 if (REG_NOTE_KIND (tem) == REG_LABEL) 2597 set_label_offsets (XEXP (tem, 0), insn, 1); 2598 return; 2599 2600 case ADDR_VEC: 2601 case ADDR_DIFF_VEC: 2602 /* Each of the labels in the address vector must be at their initial 2603 offsets. We want the first field for ADDR_VEC and the second 2604 field for ADDR_DIFF_VEC. */ 2605 2606 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) 2607 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), 2608 insn, initial_p); 2609 return; 2610 2611 case SET: 2612 /* We only care about setting PC. If the source is not RETURN, 2613 IF_THEN_ELSE, or a label, disable any eliminations not at 2614 their initial offsets. Similarly if any arm of the IF_THEN_ELSE 2615 isn't one of those possibilities. For branches to a label, 2616 call ourselves recursively. 2617 2618 Note that this can disable elimination unnecessarily when we have 2619 a non-local goto since it will look like a non-constant jump to 2620 someplace in the current function. This isn't a significant 2621 problem since such jumps will normally be when all elimination 2622 pairs are back to their initial offsets. */ 2623 2624 if (SET_DEST (x) != pc_rtx) 2625 return; 2626 2627 switch (GET_CODE (SET_SRC (x))) 2628 { 2629 case PC: 2630 case RETURN: 2631 return; 2632 2633 case LABEL_REF: 2634 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); 2635 return; 2636 2637 case IF_THEN_ELSE: 2638 tem = XEXP (SET_SRC (x), 1); 2639 if (GET_CODE (tem) == LABEL_REF) 2640 set_label_offsets (XEXP (tem, 0), insn, initial_p); 2641 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) 2642 break; 2643 2644 tem = XEXP (SET_SRC (x), 2); 2645 if (GET_CODE (tem) == LABEL_REF) 2646 set_label_offsets (XEXP (tem, 0), insn, initial_p); 2647 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) 2648 break; 2649 return; 2650 2651 default: 2652 break; 2653 } 2654 2655 /* If we reach here, all eliminations must be at their initial 2656 offset because we are doing a jump to a variable address. */ 2657 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) 2658 if (p->offset != p->initial_offset) 2659 p->can_eliminate = 0; 2660 break; 2661 2662 default: 2663 break; 2664 } 2665} 2666 2667/* Used for communication between the next two function to properly share 2668 the vector for an ASM_OPERANDS. */ 2669 2670static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec; 2671 2672/* Scan X and replace any eliminable registers (such as fp) with a 2673 replacement (such as sp), plus an offset. 2674 2675 MEM_MODE is the mode of an enclosing MEM. We need this to know how 2676 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a 2677 MEM, we are allowed to replace a sum of a register and the constant zero 2678 with the register, which we cannot do outside a MEM. In addition, we need 2679 to record the fact that a register is referenced outside a MEM. 2680 2681 If INSN is an insn, it is the insn containing X. If we replace a REG 2682 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a 2683 CLOBBER of the pseudo after INSN so find_equiv_regs will know that 2684 the REG is being modified. 2685 2686 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). 2687 That's used when we eliminate in expressions stored in notes. 2688 This means, do not set ref_outside_mem even if the reference 2689 is outside of MEMs. 2690 2691 If we see a modification to a register we know about, take the 2692 appropriate action (see case SET, below). 2693 2694 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had 2695 replacements done assuming all offsets are at their initial values. If 2696 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we 2697 encounter, return the actual location so that find_reloads will do 2698 the proper thing. */ 2699 2700rtx 2701eliminate_regs (x, mem_mode, insn) 2702 rtx x; 2703 enum machine_mode mem_mode; 2704 rtx insn; 2705{ 2706 enum rtx_code code = GET_CODE (x); 2707 struct elim_table *ep; 2708 int regno; 2709 rtx new; 2710 int i, j; 2711 char *fmt; 2712 int copied = 0; 2713 2714 if (! current_function_decl) 2715 return x; 2716 2717 switch (code) 2718 { 2719 case CONST_INT: 2720 case CONST_DOUBLE: 2721 case CONST: 2722 case SYMBOL_REF: 2723 case CODE_LABEL: 2724 case PC: 2725 case CC0: 2726 case ASM_INPUT: 2727 case ADDR_VEC: 2728 case ADDR_DIFF_VEC: 2729 case RETURN: 2730 return x; 2731 2732 case ADDRESSOF: 2733 /* This is only for the benefit of the debugging backends, which call 2734 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are 2735 removed after CSE. */ 2736 new = eliminate_regs (XEXP (x, 0), 0, insn); 2737 if (GET_CODE (new) == MEM) 2738 return XEXP (new, 0); 2739 return x; 2740 2741 case REG: 2742 regno = REGNO (x); 2743 2744 /* First handle the case where we encounter a bare register that 2745 is eliminable. Replace it with a PLUS. */ 2746 if (regno < FIRST_PSEUDO_REGISTER) 2747 { 2748 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2749 ep++) 2750 if (ep->from_rtx == x && ep->can_eliminate) 2751 { 2752 if (! mem_mode 2753 /* Refs inside notes don't count for this purpose. */ 2754 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST 2755 || GET_CODE (insn) == INSN_LIST))) 2756 ep->ref_outside_mem = 1; 2757 return plus_constant (ep->to_rtx, ep->previous_offset); 2758 } 2759 2760 } 2761 else if (reg_renumber[regno] < 0 && reg_equiv_constant 2762 && reg_equiv_constant[regno] 2763 && ! CONSTANT_P (reg_equiv_constant[regno])) 2764 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]), 2765 mem_mode, insn); 2766 return x; 2767 2768 case PLUS: 2769 /* If this is the sum of an eliminable register and a constant, rework 2770 the sum. */ 2771 if (GET_CODE (XEXP (x, 0)) == REG 2772 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 2773 && CONSTANT_P (XEXP (x, 1))) 2774 { 2775 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2776 ep++) 2777 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) 2778 { 2779 if (! mem_mode 2780 /* Refs inside notes don't count for this purpose. */ 2781 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST 2782 || GET_CODE (insn) == INSN_LIST))) 2783 ep->ref_outside_mem = 1; 2784 2785 /* The only time we want to replace a PLUS with a REG (this 2786 occurs when the constant operand of the PLUS is the negative 2787 of the offset) is when we are inside a MEM. We won't want 2788 to do so at other times because that would change the 2789 structure of the insn in a way that reload can't handle. 2790 We special-case the commonest situation in 2791 eliminate_regs_in_insn, so just replace a PLUS with a 2792 PLUS here, unless inside a MEM. */ 2793 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT 2794 && INTVAL (XEXP (x, 1)) == - ep->previous_offset) 2795 return ep->to_rtx; 2796 else 2797 return gen_rtx_PLUS (Pmode, ep->to_rtx, 2798 plus_constant (XEXP (x, 1), 2799 ep->previous_offset)); 2800 } 2801 2802 /* If the register is not eliminable, we are done since the other 2803 operand is a constant. */ 2804 return x; 2805 } 2806 2807 /* If this is part of an address, we want to bring any constant to the 2808 outermost PLUS. We will do this by doing register replacement in 2809 our operands and seeing if a constant shows up in one of them. 2810 2811 We assume here this is part of an address (or a "load address" insn) 2812 since an eliminable register is not likely to appear in any other 2813 context. 2814 2815 If we have (plus (eliminable) (reg)), we want to produce 2816 (plus (plus (replacement) (reg) (const))). If this was part of a 2817 normal add insn, (plus (replacement) (reg)) will be pushed as a 2818 reload. This is the desired action. */ 2819 2820 { 2821 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2822 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); 2823 2824 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) 2825 { 2826 /* If one side is a PLUS and the other side is a pseudo that 2827 didn't get a hard register but has a reg_equiv_constant, 2828 we must replace the constant here since it may no longer 2829 be in the position of any operand. */ 2830 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG 2831 && REGNO (new1) >= FIRST_PSEUDO_REGISTER 2832 && reg_renumber[REGNO (new1)] < 0 2833 && reg_equiv_constant != 0 2834 && reg_equiv_constant[REGNO (new1)] != 0) 2835 new1 = reg_equiv_constant[REGNO (new1)]; 2836 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG 2837 && REGNO (new0) >= FIRST_PSEUDO_REGISTER 2838 && reg_renumber[REGNO (new0)] < 0 2839 && reg_equiv_constant[REGNO (new0)] != 0) 2840 new0 = reg_equiv_constant[REGNO (new0)]; 2841 2842 new = form_sum (new0, new1); 2843 2844 /* As above, if we are not inside a MEM we do not want to 2845 turn a PLUS into something else. We might try to do so here 2846 for an addition of 0 if we aren't optimizing. */ 2847 if (! mem_mode && GET_CODE (new) != PLUS) 2848 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); 2849 else 2850 return new; 2851 } 2852 } 2853 return x; 2854 2855 case MULT: 2856 /* If this is the product of an eliminable register and a 2857 constant, apply the distribute law and move the constant out 2858 so that we have (plus (mult ..) ..). This is needed in order 2859 to keep load-address insns valid. This case is pathological. 2860 We ignore the possibility of overflow here. */ 2861 if (GET_CODE (XEXP (x, 0)) == REG 2862 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 2863 && GET_CODE (XEXP (x, 1)) == CONST_INT) 2864 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2865 ep++) 2866 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) 2867 { 2868 if (! mem_mode 2869 /* Refs inside notes don't count for this purpose. */ 2870 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST 2871 || GET_CODE (insn) == INSN_LIST))) 2872 ep->ref_outside_mem = 1; 2873 2874 return 2875 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), 2876 ep->previous_offset * INTVAL (XEXP (x, 1))); 2877 } 2878 2879 /* ... fall through ... */ 2880 2881 case CALL: 2882 case COMPARE: 2883 case MINUS: 2884 case DIV: case UDIV: 2885 case MOD: case UMOD: 2886 case AND: case IOR: case XOR: 2887 case ROTATERT: case ROTATE: 2888 case ASHIFTRT: case LSHIFTRT: case ASHIFT: 2889 case NE: case EQ: 2890 case GE: case GT: case GEU: case GTU: 2891 case LE: case LT: case LEU: case LTU: 2892 { 2893 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2894 rtx new1 2895 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; 2896 2897 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) 2898 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); 2899 } 2900 return x; 2901 2902 case EXPR_LIST: 2903 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ 2904 if (XEXP (x, 0)) 2905 { 2906 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2907 if (new != XEXP (x, 0)) 2908 { 2909 /* If this is a REG_DEAD note, it is not valid anymore. 2910 Using the eliminated version could result in creating a 2911 REG_DEAD note for the stack or frame pointer. */ 2912 if (GET_MODE (x) == REG_DEAD) 2913 return (XEXP (x, 1) 2914 ? eliminate_regs (XEXP (x, 1), mem_mode, insn) 2915 : NULL_RTX); 2916 2917 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); 2918 } 2919 } 2920 2921 /* ... fall through ... */ 2922 2923 case INSN_LIST: 2924 /* Now do eliminations in the rest of the chain. If this was 2925 an EXPR_LIST, this might result in allocating more memory than is 2926 strictly needed, but it simplifies the code. */ 2927 if (XEXP (x, 1)) 2928 { 2929 new = eliminate_regs (XEXP (x, 1), mem_mode, insn); 2930 if (new != XEXP (x, 1)) 2931 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); 2932 } 2933 return x; 2934 2935 case PRE_INC: 2936 case POST_INC: 2937 case PRE_DEC: 2938 case POST_DEC: 2939 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2940 if (ep->to_rtx == XEXP (x, 0)) 2941 { 2942 int size = GET_MODE_SIZE (mem_mode); 2943 2944 /* If more bytes than MEM_MODE are pushed, account for them. */ 2945#ifdef PUSH_ROUNDING 2946 if (ep->to_rtx == stack_pointer_rtx) 2947 size = PUSH_ROUNDING (size); 2948#endif 2949 if (code == PRE_DEC || code == POST_DEC) 2950 ep->offset += size; 2951 else 2952 ep->offset -= size; 2953 } 2954 2955 /* Fall through to generic unary operation case. */ 2956 case STRICT_LOW_PART: 2957 case NEG: case NOT: 2958 case SIGN_EXTEND: case ZERO_EXTEND: 2959 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: 2960 case FLOAT: case FIX: 2961 case UNSIGNED_FIX: case UNSIGNED_FLOAT: 2962 case ABS: 2963 case SQRT: 2964 case FFS: 2965 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2966 if (new != XEXP (x, 0)) 2967 return gen_rtx_fmt_e (code, GET_MODE (x), new); 2968 return x; 2969 2970 case SUBREG: 2971 /* Similar to above processing, but preserve SUBREG_WORD. 2972 Convert (subreg (mem)) to (mem) if not paradoxical. 2973 Also, if we have a non-paradoxical (subreg (pseudo)) and the 2974 pseudo didn't get a hard reg, we must replace this with the 2975 eliminated version of the memory location because push_reloads 2976 may do the replacement in certain circumstances. */ 2977 if (GET_CODE (SUBREG_REG (x)) == REG 2978 && (GET_MODE_SIZE (GET_MODE (x)) 2979 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 2980 && reg_equiv_memory_loc != 0 2981 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) 2982 { 2983#if 0 2984 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))], 2985 mem_mode, insn); 2986 2987 /* If we didn't change anything, we must retain the pseudo. */ 2988 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))]) 2989 new = SUBREG_REG (x); 2990 else 2991 { 2992 /* In this case, we must show that the pseudo is used in this 2993 insn so that delete_output_reload will do the right thing. */ 2994 if (insn != 0 && GET_CODE (insn) != EXPR_LIST 2995 && GET_CODE (insn) != INSN_LIST) 2996 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, 2997 SUBREG_REG (x)), 2998 insn)) 2999 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX); 3000 3001 /* Ensure NEW isn't shared in case we have to reload it. */ 3002 new = copy_rtx (new); 3003 } 3004#else 3005 new = SUBREG_REG (x); 3006#endif 3007 } 3008 else 3009 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); 3010 3011 if (new != XEXP (x, 0)) 3012 { 3013 int x_size = GET_MODE_SIZE (GET_MODE (x)); 3014 int new_size = GET_MODE_SIZE (GET_MODE (new)); 3015 3016 if (GET_CODE (new) == MEM 3017 && ((x_size < new_size 3018#ifdef WORD_REGISTER_OPERATIONS 3019 /* On these machines, combine can create rtl of the form 3020 (set (subreg:m1 (reg:m2 R) 0) ...) 3021 where m1 < m2, and expects something interesting to 3022 happen to the entire word. Moreover, it will use the 3023 (reg:m2 R) later, expecting all bits to be preserved. 3024 So if the number of words is the same, preserve the 3025 subreg so that push_reloads can see it. */ 3026 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD) 3027#endif 3028 ) 3029 || (x_size == new_size)) 3030 ) 3031 { 3032 int offset = SUBREG_WORD (x) * UNITS_PER_WORD; 3033 enum machine_mode mode = GET_MODE (x); 3034 3035 if (BYTES_BIG_ENDIAN) 3036 offset += (MIN (UNITS_PER_WORD, 3037 GET_MODE_SIZE (GET_MODE (new))) 3038 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); 3039 3040 PUT_MODE (new, mode); 3041 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset); 3042 return new; 3043 } 3044 else 3045 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x)); 3046 } 3047 3048 return x; 3049 3050 case USE: 3051 /* If using a register that is the source of an eliminate we still 3052 think can be performed, note it cannot be performed since we don't 3053 know how this register is used. */ 3054 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3055 if (ep->from_rtx == XEXP (x, 0)) 3056 ep->can_eliminate = 0; 3057 3058 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 3059 if (new != XEXP (x, 0)) 3060 return gen_rtx_fmt_e (code, GET_MODE (x), new); 3061 return x; 3062 3063 case CLOBBER: 3064 /* If clobbering a register that is the replacement register for an 3065 elimination we still think can be performed, note that it cannot 3066 be performed. Otherwise, we need not be concerned about it. */ 3067 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3068 if (ep->to_rtx == XEXP (x, 0)) 3069 ep->can_eliminate = 0; 3070 3071 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 3072 if (new != XEXP (x, 0)) 3073 return gen_rtx_fmt_e (code, GET_MODE (x), new); 3074 return x; 3075 3076 case ASM_OPERANDS: 3077 { 3078 rtx *temp_vec; 3079 /* Properly handle sharing input and constraint vectors. */ 3080 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec) 3081 { 3082 /* When we come to a new vector not seen before, 3083 scan all its elements; keep the old vector if none 3084 of them changes; otherwise, make a copy. */ 3085 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x); 3086 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx)); 3087 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) 3088 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i), 3089 mem_mode, insn); 3090 3091 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) 3092 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i)) 3093 break; 3094 3095 if (i == ASM_OPERANDS_INPUT_LENGTH (x)) 3096 new_asm_operands_vec = old_asm_operands_vec; 3097 else 3098 new_asm_operands_vec 3099 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec); 3100 } 3101 3102 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */ 3103 if (new_asm_operands_vec == old_asm_operands_vec) 3104 return x; 3105 3106 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x), 3107 ASM_OPERANDS_OUTPUT_CONSTRAINT (x), 3108 ASM_OPERANDS_OUTPUT_IDX (x), 3109 new_asm_operands_vec, 3110 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x), 3111 ASM_OPERANDS_SOURCE_FILE (x), 3112 ASM_OPERANDS_SOURCE_LINE (x)); 3113 new->volatil = x->volatil; 3114 return new; 3115 } 3116 3117 case SET: 3118 /* Check for setting a register that we know about. */ 3119 if (GET_CODE (SET_DEST (x)) == REG) 3120 { 3121 /* See if this is setting the replacement register for an 3122 elimination. 3123 3124 If DEST is the hard frame pointer, we do nothing because we 3125 assume that all assignments to the frame pointer are for 3126 non-local gotos and are being done at a time when they are valid 3127 and do not disturb anything else. Some machines want to 3128 eliminate a fake argument pointer (or even a fake frame pointer) 3129 with either the real frame or the stack pointer. Assignments to 3130 the hard frame pointer must not prevent this elimination. */ 3131 3132 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3133 ep++) 3134 if (ep->to_rtx == SET_DEST (x) 3135 && SET_DEST (x) != hard_frame_pointer_rtx) 3136 { 3137 /* If it is being incremented, adjust the offset. Otherwise, 3138 this elimination can't be done. */ 3139 rtx src = SET_SRC (x); 3140 3141 if (GET_CODE (src) == PLUS 3142 && XEXP (src, 0) == SET_DEST (x) 3143 && GET_CODE (XEXP (src, 1)) == CONST_INT) 3144 ep->offset -= INTVAL (XEXP (src, 1)); 3145 else 3146 ep->can_eliminate = 0; 3147 } 3148 3149 /* Now check to see we are assigning to a register that can be 3150 eliminated. If so, it must be as part of a PARALLEL, since we 3151 will not have been called if this is a single SET. So indicate 3152 that we can no longer eliminate this reg. */ 3153 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3154 ep++) 3155 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate) 3156 ep->can_eliminate = 0; 3157 } 3158 3159 /* Now avoid the loop below in this common case. */ 3160 { 3161 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn); 3162 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn); 3163 3164 /* If SET_DEST changed from a REG to a MEM and INSN is an insn, 3165 write a CLOBBER insn. */ 3166 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM 3167 && insn != 0 && GET_CODE (insn) != EXPR_LIST 3168 && GET_CODE (insn) != INSN_LIST) 3169 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn); 3170 3171 if (new0 != SET_DEST (x) || new1 != SET_SRC (x)) 3172 return gen_rtx_SET (VOIDmode, new0, new1); 3173 } 3174 3175 return x; 3176 3177 case MEM: 3178 /* This is only for the benefit of the debugging backends, which call 3179 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are 3180 removed after CSE. */ 3181 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) 3182 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); 3183 3184 /* Our only special processing is to pass the mode of the MEM to our 3185 recursive call and copy the flags. While we are here, handle this 3186 case more efficiently. */ 3187 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn); 3188 if (new != XEXP (x, 0)) 3189 { 3190 new = gen_rtx_MEM (GET_MODE (x), new); 3191 new->volatil = x->volatil; 3192 new->unchanging = x->unchanging; 3193 new->in_struct = x->in_struct; 3194 return new; 3195 } 3196 else 3197 return x; 3198 3199 default: 3200 break; 3201 } 3202 3203 /* Process each of our operands recursively. If any have changed, make a 3204 copy of the rtx. */ 3205 fmt = GET_RTX_FORMAT (code); 3206 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 3207 { 3208 if (*fmt == 'e') 3209 { 3210 new = eliminate_regs (XEXP (x, i), mem_mode, insn); 3211 if (new != XEXP (x, i) && ! copied) 3212 { 3213 rtx new_x = rtx_alloc (code); 3214 bcopy ((char *) x, (char *) new_x, 3215 (sizeof (*new_x) - sizeof (new_x->fld) 3216 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code))); 3217 x = new_x; 3218 copied = 1; 3219 } 3220 XEXP (x, i) = new; 3221 } 3222 else if (*fmt == 'E') 3223 { 3224 int copied_vec = 0; 3225 for (j = 0; j < XVECLEN (x, i); j++) 3226 { 3227 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); 3228 if (new != XVECEXP (x, i, j) && ! copied_vec) 3229 { 3230 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i), 3231 XVEC (x, i)->elem); 3232 if (! copied) 3233 { 3234 rtx new_x = rtx_alloc (code); 3235 bcopy ((char *) x, (char *) new_x, 3236 (sizeof (*new_x) - sizeof (new_x->fld) 3237 + (sizeof (new_x->fld[0]) 3238 * GET_RTX_LENGTH (code)))); 3239 x = new_x; 3240 copied = 1; 3241 } 3242 XVEC (x, i) = new_v; 3243 copied_vec = 1; 3244 } 3245 XVECEXP (x, i, j) = new; 3246 } 3247 } 3248 } 3249 3250 return x; 3251} 3252 3253/* Scan INSN and eliminate all eliminable registers in it. 3254 3255 If REPLACE is nonzero, do the replacement destructively. Also 3256 delete the insn as dead it if it is setting an eliminable register. 3257 3258 If REPLACE is zero, do all our allocations in reload_obstack. 3259 3260 If no eliminations were done and this insn doesn't require any elimination 3261 processing (these are not identical conditions: it might be updating sp, 3262 but not referencing fp; this needs to be seen during reload_as_needed so 3263 that the offset between fp and sp can be taken into consideration), zero 3264 is returned. Otherwise, 1 is returned. */ 3265 3266static int 3267eliminate_regs_in_insn (insn, replace) 3268 rtx insn; 3269 int replace; 3270{ 3271 rtx old_body = PATTERN (insn); 3272 rtx old_set = single_set (insn); 3273 rtx new_body; 3274 int val = 0; 3275 struct elim_table *ep; 3276 3277 if (! replace) 3278 push_obstacks (&reload_obstack, &reload_obstack); 3279 3280 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG 3281 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) 3282 { 3283 /* Check for setting an eliminable register. */ 3284 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3285 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) 3286 { 3287#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 3288 /* If this is setting the frame pointer register to the 3289 hardware frame pointer register and this is an elimination 3290 that will be done (tested above), this insn is really 3291 adjusting the frame pointer downward to compensate for 3292 the adjustment done before a nonlocal goto. */ 3293 if (ep->from == FRAME_POINTER_REGNUM 3294 && ep->to == HARD_FRAME_POINTER_REGNUM) 3295 { 3296 rtx src = SET_SRC (old_set); 3297 int offset = 0, ok = 0; 3298 rtx prev_insn, prev_set; 3299 3300 if (src == ep->to_rtx) 3301 offset = 0, ok = 1; 3302 else if (GET_CODE (src) == PLUS 3303 && GET_CODE (XEXP (src, 0)) == CONST_INT 3304 && XEXP (src, 1) == ep->to_rtx) 3305 offset = INTVAL (XEXP (src, 0)), ok = 1; 3306 else if (GET_CODE (src) == PLUS 3307 && GET_CODE (XEXP (src, 1)) == CONST_INT 3308 && XEXP (src, 0) == ep->to_rtx) 3309 offset = INTVAL (XEXP (src, 1)), ok = 1; 3310 else if ((prev_insn = prev_nonnote_insn (insn)) != 0 3311 && (prev_set = single_set (prev_insn)) != 0 3312 && rtx_equal_p (SET_DEST (prev_set), src)) 3313 { 3314 src = SET_SRC (prev_set); 3315 if (src == ep->to_rtx) 3316 offset = 0, ok = 1; 3317 else if (GET_CODE (src) == PLUS 3318 && GET_CODE (XEXP (src, 0)) == CONST_INT 3319 && XEXP (src, 1) == ep->to_rtx) 3320 offset = INTVAL (XEXP (src, 0)), ok = 1; 3321 else if (GET_CODE (src) == PLUS 3322 && GET_CODE (XEXP (src, 1)) == CONST_INT 3323 && XEXP (src, 0) == ep->to_rtx) 3324 offset = INTVAL (XEXP (src, 1)), ok = 1; 3325 } 3326 3327 if (ok) 3328 { 3329 if (replace) 3330 { 3331 rtx src 3332 = plus_constant (ep->to_rtx, offset - ep->offset); 3333 3334 /* First see if this insn remains valid when we 3335 make the change. If not, keep the INSN_CODE 3336 the same and let reload fit it up. */ 3337 validate_change (insn, &SET_SRC (old_set), src, 1); 3338 validate_change (insn, &SET_DEST (old_set), 3339 ep->to_rtx, 1); 3340 if (! apply_change_group ()) 3341 { 3342 SET_SRC (old_set) = src; 3343 SET_DEST (old_set) = ep->to_rtx; 3344 } 3345 } 3346 3347 val = 1; 3348 goto done; 3349 } 3350 } 3351#endif 3352 3353 /* In this case this insn isn't serving a useful purpose. We 3354 will delete it in reload_as_needed once we know that this 3355 elimination is, in fact, being done. 3356 3357 If REPLACE isn't set, we can't delete this insn, but needn't 3358 process it since it won't be used unless something changes. */ 3359 if (replace) 3360 delete_dead_insn (insn); 3361 val = 1; 3362 goto done; 3363 } 3364 3365 /* Check for (set (reg) (plus (reg from) (offset))) where the offset 3366 in the insn is the negative of the offset in FROM. Substitute 3367 (set (reg) (reg to)) for the insn and change its code. 3368 3369 We have to do this here, rather than in eliminate_regs, so that we can 3370 change the insn code. */ 3371 3372 if (GET_CODE (SET_SRC (old_set)) == PLUS 3373 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG 3374 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT) 3375 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3376 ep++) 3377 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0) 3378 && ep->can_eliminate) 3379 { 3380 /* We must stop at the first elimination that will be used. 3381 If this one would replace the PLUS with a REG, do it 3382 now. Otherwise, quit the loop and let eliminate_regs 3383 do its normal replacement. */ 3384 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1))) 3385 { 3386 /* We assume here that we don't need a PARALLEL of 3387 any CLOBBERs for this assignment. There's not 3388 much we can do if we do need it. */ 3389 PATTERN (insn) = gen_rtx_SET (VOIDmode, 3390 SET_DEST (old_set), 3391 ep->to_rtx); 3392 INSN_CODE (insn) = -1; 3393 val = 1; 3394 goto done; 3395 } 3396 3397 break; 3398 } 3399 } 3400 3401 old_asm_operands_vec = 0; 3402 3403 /* Replace the body of this insn with a substituted form. If we changed 3404 something, return non-zero. 3405 3406 If we are replacing a body that was a (set X (plus Y Z)), try to 3407 re-recognize the insn. We do this in case we had a simple addition 3408 but now can do this as a load-address. This saves an insn in this 3409 common case. */ 3410 3411 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX); 3412 if (new_body != old_body) 3413 { 3414 /* If we aren't replacing things permanently and we changed something, 3415 make another copy to ensure that all the RTL is new. Otherwise 3416 things can go wrong if find_reload swaps commutative operands 3417 and one is inside RTL that has been copied while the other is not. */ 3418 3419 /* Don't copy an asm_operands because (1) there's no need and (2) 3420 copy_rtx can't do it properly when there are multiple outputs. */ 3421 if (! replace && asm_noperands (old_body) < 0) 3422 new_body = copy_rtx (new_body); 3423 3424 /* If we had a move insn but now we don't, rerecognize it. This will 3425 cause spurious re-recognition if the old move had a PARALLEL since 3426 the new one still will, but we can't call single_set without 3427 having put NEW_BODY into the insn and the re-recognition won't 3428 hurt in this rare case. */ 3429 if (old_set != 0 3430 && ((GET_CODE (SET_SRC (old_set)) == REG 3431 && (GET_CODE (new_body) != SET 3432 || GET_CODE (SET_SRC (new_body)) != REG)) 3433 /* If this was a load from or store to memory, compare 3434 the MEM in recog_operand to the one in the insn. If they 3435 are not equal, then rerecognize the insn. */ 3436 || (old_set != 0 3437 && ((GET_CODE (SET_SRC (old_set)) == MEM 3438 && SET_SRC (old_set) != recog_operand[1]) 3439 || (GET_CODE (SET_DEST (old_set)) == MEM 3440 && SET_DEST (old_set) != recog_operand[0]))) 3441 /* If this was an add insn before, rerecognize. */ 3442 || GET_CODE (SET_SRC (old_set)) == PLUS)) 3443 { 3444 if (! validate_change (insn, &PATTERN (insn), new_body, 0)) 3445 /* If recognition fails, store the new body anyway. 3446 It's normal to have recognition failures here 3447 due to bizarre memory addresses; reloading will fix them. */ 3448 PATTERN (insn) = new_body; 3449 } 3450 else 3451 PATTERN (insn) = new_body; 3452 3453 val = 1; 3454 } 3455 3456 /* Loop through all elimination pairs. See if any have changed. 3457 3458 We also detect a cases where register elimination cannot be done, 3459 namely, if a register would be both changed and referenced outside a MEM 3460 in the resulting insn since such an insn is often undefined and, even if 3461 not, we cannot know what meaning will be given to it. Note that it is 3462 valid to have a register used in an address in an insn that changes it 3463 (presumably with a pre- or post-increment or decrement). 3464 3465 If anything changes, return nonzero. */ 3466 3467 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3468 { 3469 if (ep->previous_offset != ep->offset && ep->ref_outside_mem) 3470 ep->can_eliminate = 0; 3471 3472 ep->ref_outside_mem = 0; 3473 3474 if (ep->previous_offset != ep->offset) 3475 val = 1; 3476 } 3477 3478 done: 3479 /* If we changed something, perform elimination in REG_NOTES. This is 3480 needed even when REPLACE is zero because a REG_DEAD note might refer 3481 to a register that we eliminate and could cause a different number 3482 of spill registers to be needed in the final reload pass than in 3483 the pre-passes. */ 3484 if (val && REG_NOTES (insn) != 0) 3485 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); 3486 3487 if (! replace) 3488 pop_obstacks (); 3489 3490 return val; 3491} 3492 3493/* Loop through all elimination pairs. 3494 Recalculate the number not at initial offset. 3495 3496 Compute the maximum offset (minimum offset if the stack does not 3497 grow downward) for each elimination pair. */ 3498 3499static void 3500update_eliminable_offsets () 3501{ 3502 struct elim_table *ep; 3503 3504 num_not_at_initial_offset = 0; 3505 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3506 { 3507 ep->previous_offset = ep->offset; 3508 if (ep->can_eliminate && ep->offset != ep->initial_offset) 3509 num_not_at_initial_offset++; 3510 } 3511} 3512 3513/* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register 3514 replacement we currently believe is valid, mark it as not eliminable if X 3515 modifies DEST in any way other than by adding a constant integer to it. 3516 3517 If DEST is the frame pointer, we do nothing because we assume that 3518 all assignments to the hard frame pointer are nonlocal gotos and are being 3519 done at a time when they are valid and do not disturb anything else. 3520 Some machines want to eliminate a fake argument pointer with either the 3521 frame or stack pointer. Assignments to the hard frame pointer must not 3522 prevent this elimination. 3523 3524 Called via note_stores from reload before starting its passes to scan 3525 the insns of the function. */ 3526 3527static void 3528mark_not_eliminable (dest, x) 3529 rtx dest; 3530 rtx x; 3531{ 3532 register unsigned int i; 3533 3534 /* A SUBREG of a hard register here is just changing its mode. We should 3535 not see a SUBREG of an eliminable hard register, but check just in 3536 case. */ 3537 if (GET_CODE (dest) == SUBREG) 3538 dest = SUBREG_REG (dest); 3539 3540 if (dest == hard_frame_pointer_rtx) 3541 return; 3542 3543 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 3544 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx 3545 && (GET_CODE (x) != SET 3546 || GET_CODE (SET_SRC (x)) != PLUS 3547 || XEXP (SET_SRC (x), 0) != dest 3548 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) 3549 { 3550 reg_eliminate[i].can_eliminate_previous 3551 = reg_eliminate[i].can_eliminate = 0; 3552 num_eliminable--; 3553 } 3554} 3555 3556/* Verify that the initial elimination offsets did not change since the 3557 last call to set_initial_elim_offsets. This is used to catch cases 3558 where something illegal happened during reload_as_needed that could 3559 cause incorrect code to be generated if we did not check for it. */ 3560static void 3561verify_initial_elim_offsets () 3562{ 3563 int t; 3564 3565#ifdef ELIMINABLE_REGS 3566 struct elim_table *ep; 3567 3568 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3569 { 3570 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); 3571 if (t != ep->initial_offset) 3572 abort (); 3573 } 3574#else 3575 INITIAL_FRAME_POINTER_OFFSET (t); 3576 if (t != reg_eliminate[0].initial_offset) 3577 abort (); 3578#endif 3579} 3580 3581/* Reset all offsets on eliminable registers to their initial values. */ 3582static void 3583set_initial_elim_offsets () 3584{ 3585 struct elim_table *ep = reg_eliminate; 3586 3587#ifdef ELIMINABLE_REGS 3588 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3589 { 3590 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); 3591 ep->previous_offset = ep->offset = ep->initial_offset; 3592 } 3593#else 3594 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); 3595 ep->previous_offset = ep->offset = ep->initial_offset; 3596#endif 3597 3598 num_not_at_initial_offset = 0; 3599} 3600 3601/* Initialize the known label offsets. 3602 Set a known offset for each forced label to be at the initial offset 3603 of each elimination. We do this because we assume that all 3604 computed jumps occur from a location where each elimination is 3605 at its initial offset. 3606 For all other labels, show that we don't know the offsets. */ 3607 3608static void 3609set_initial_label_offsets () 3610{ 3611 rtx x; 3612 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels); 3613 3614 for (x = forced_labels; x; x = XEXP (x, 1)) 3615 if (XEXP (x, 0)) 3616 set_label_offsets (XEXP (x, 0), NULL_RTX, 1); 3617} 3618 3619/* Set all elimination offsets to the known values for the code label given 3620 by INSN. */ 3621static void 3622set_offsets_for_label (insn) 3623 rtx insn; 3624{ 3625 unsigned int i; 3626 int label_nr = CODE_LABEL_NUMBER (insn); 3627 struct elim_table *ep; 3628 3629 num_not_at_initial_offset = 0; 3630 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) 3631 { 3632 ep->offset = ep->previous_offset = offsets_at[label_nr][i]; 3633 if (ep->can_eliminate && ep->offset != ep->initial_offset) 3634 num_not_at_initial_offset++; 3635 } 3636} 3637 3638/* See if anything that happened changes which eliminations are valid. 3639 For example, on the Sparc, whether or not the frame pointer can 3640 be eliminated can depend on what registers have been used. We need 3641 not check some conditions again (such as flag_omit_frame_pointer) 3642 since they can't have changed. */ 3643 3644static void 3645update_eliminables (pset) 3646 HARD_REG_SET *pset; 3647{ 3648#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 3649 int previous_frame_pointer_needed = frame_pointer_needed; 3650#endif 3651 struct elim_table *ep; 3652 3653 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3654 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) 3655#ifdef ELIMINABLE_REGS 3656 || ! CAN_ELIMINATE (ep->from, ep->to) 3657#endif 3658 ) 3659 ep->can_eliminate = 0; 3660 3661 /* Look for the case where we have discovered that we can't replace 3662 register A with register B and that means that we will now be 3663 trying to replace register A with register C. This means we can 3664 no longer replace register C with register B and we need to disable 3665 such an elimination, if it exists. This occurs often with A == ap, 3666 B == sp, and C == fp. */ 3667 3668 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3669 { 3670 struct elim_table *op; 3671 register int new_to = -1; 3672 3673 if (! ep->can_eliminate && ep->can_eliminate_previous) 3674 { 3675 /* Find the current elimination for ep->from, if there is a 3676 new one. */ 3677 for (op = reg_eliminate; 3678 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) 3679 if (op->from == ep->from && op->can_eliminate) 3680 { 3681 new_to = op->to; 3682 break; 3683 } 3684 3685 /* See if there is an elimination of NEW_TO -> EP->TO. If so, 3686 disable it. */ 3687 for (op = reg_eliminate; 3688 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) 3689 if (op->from == new_to && op->to == ep->to) 3690 op->can_eliminate = 0; 3691 } 3692 } 3693 3694 /* See if any registers that we thought we could eliminate the previous 3695 time are no longer eliminable. If so, something has changed and we 3696 must spill the register. Also, recompute the number of eliminable 3697 registers and see if the frame pointer is needed; it is if there is 3698 no elimination of the frame pointer that we can perform. */ 3699 3700 frame_pointer_needed = 1; 3701 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3702 { 3703 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM 3704 && ep->to != HARD_FRAME_POINTER_REGNUM) 3705 frame_pointer_needed = 0; 3706 3707 if (! ep->can_eliminate && ep->can_eliminate_previous) 3708 { 3709 ep->can_eliminate_previous = 0; 3710 SET_HARD_REG_BIT (*pset, ep->from); 3711 num_eliminable--; 3712 } 3713 } 3714 3715#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 3716 /* If we didn't need a frame pointer last time, but we do now, spill 3717 the hard frame pointer. */ 3718 if (frame_pointer_needed && ! previous_frame_pointer_needed) 3719 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); 3720#endif 3721} 3722 3723/* Initialize the table of registers to eliminate. */ 3724static void 3725init_elim_table () 3726{ 3727 struct elim_table *ep; 3728#ifdef ELIMINABLE_REGS 3729 struct elim_table_1 *ep1; 3730#endif 3731 3732 if (!reg_eliminate) 3733 { 3734 reg_eliminate = (struct elim_table *) 3735 xmalloc(sizeof(struct elim_table) * NUM_ELIMINABLE_REGS); 3736 bzero ((PTR) reg_eliminate, 3737 sizeof(struct elim_table) * NUM_ELIMINABLE_REGS); 3738 } 3739 3740 /* Does this function require a frame pointer? */ 3741 3742 frame_pointer_needed = (! flag_omit_frame_pointer 3743#ifdef EXIT_IGNORE_STACK 3744 /* ?? If EXIT_IGNORE_STACK is set, we will not save 3745 and restore sp for alloca. So we can't eliminate 3746 the frame pointer in that case. At some point, 3747 we should improve this by emitting the 3748 sp-adjusting insns for this case. */ 3749 || (current_function_calls_alloca 3750 && EXIT_IGNORE_STACK) 3751#endif 3752 || FRAME_POINTER_REQUIRED); 3753 3754 num_eliminable = 0; 3755 3756#ifdef ELIMINABLE_REGS 3757 for (ep = reg_eliminate, ep1 = reg_eliminate_1; 3758 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) 3759 { 3760 ep->from = ep1->from; 3761 ep->to = ep1->to; 3762 ep->can_eliminate = ep->can_eliminate_previous 3763 = (CAN_ELIMINATE (ep->from, ep->to) 3764 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); 3765 } 3766#else 3767 reg_eliminate[0].from = reg_eliminate_1[0].from; 3768 reg_eliminate[0].to = reg_eliminate_1[0].to; 3769 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous 3770 = ! frame_pointer_needed; 3771#endif 3772 3773 /* Count the number of eliminable registers and build the FROM and TO 3774 REG rtx's. Note that code in gen_rtx will cause, e.g., 3775 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. 3776 We depend on this. */ 3777 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3778 { 3779 num_eliminable += ep->can_eliminate; 3780 ep->from_rtx = gen_rtx_REG (Pmode, ep->from); 3781 ep->to_rtx = gen_rtx_REG (Pmode, ep->to); 3782 } 3783} 3784 3785/* Kick all pseudos out of hard register REGNO. 3786 If DUMPFILE is nonzero, log actions taken on that file. 3787 3788 If CANT_ELIMINATE is nonzero, it means that we are doing this spill 3789 because we found we can't eliminate some register. In the case, no pseudos 3790 are allowed to be in the register, even if they are only in a block that 3791 doesn't require spill registers, unlike the case when we are spilling this 3792 hard reg to produce another spill register. 3793 3794 Return nonzero if any pseudos needed to be kicked out. */ 3795 3796static void 3797spill_hard_reg (regno, dumpfile, cant_eliminate) 3798 register int regno; 3799 FILE *dumpfile; 3800 int cant_eliminate; 3801{ 3802 register int i; 3803 3804 if (cant_eliminate) 3805 { 3806 SET_HARD_REG_BIT (bad_spill_regs_global, regno); 3807 regs_ever_live[regno] = 1; 3808 } 3809 3810 /* Spill every pseudo reg that was allocated to this reg 3811 or to something that overlaps this reg. */ 3812 3813 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3814 if (reg_renumber[i] >= 0 3815 && reg_renumber[i] <= regno 3816 && (reg_renumber[i] 3817 + HARD_REGNO_NREGS (reg_renumber[i], 3818 PSEUDO_REGNO_MODE (i)) 3819 > regno)) 3820 SET_REGNO_REG_SET (spilled_pseudos, i); 3821} 3822 3823/* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET 3824 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */ 3825static void 3826ior_hard_reg_set (set1, set2) 3827 HARD_REG_SET *set1, *set2; 3828{ 3829 IOR_HARD_REG_SET (*set1, *set2); 3830} 3831 3832/* After find_reload_regs has been run for all insn that need reloads, 3833 and/or spill_hard_regs was called, this function is used to actually 3834 spill pseudo registers and try to reallocate them. It also sets up the 3835 spill_regs array for use by choose_reload_regs. */ 3836 3837static int 3838finish_spills (global, dumpfile) 3839 int global; 3840 FILE *dumpfile; 3841{ 3842 struct insn_chain *chain; 3843 int something_changed = 0; 3844 int i; 3845 3846 /* Build the spill_regs array for the function. */ 3847 /* If there are some registers still to eliminate and one of the spill regs 3848 wasn't ever used before, additional stack space may have to be 3849 allocated to store this register. Thus, we may have changed the offset 3850 between the stack and frame pointers, so mark that something has changed. 3851 3852 One might think that we need only set VAL to 1 if this is a call-used 3853 register. However, the set of registers that must be saved by the 3854 prologue is not identical to the call-used set. For example, the 3855 register used by the call insn for the return PC is a call-used register, 3856 but must be saved by the prologue. */ 3857 3858 n_spills = 0; 3859 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3860 if (TEST_HARD_REG_BIT (used_spill_regs, i)) 3861 { 3862 spill_reg_order[i] = n_spills; 3863 spill_regs[n_spills++] = i; 3864 if (num_eliminable && ! regs_ever_live[i]) 3865 something_changed = 1; 3866 regs_ever_live[i] = 1; 3867 } 3868 else 3869 spill_reg_order[i] = -1; 3870 3871 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3872 if (REGNO_REG_SET_P (spilled_pseudos, i)) 3873 { 3874 /* Record the current hard register the pseudo is allocated to in 3875 pseudo_previous_regs so we avoid reallocating it to the same 3876 hard reg in a later pass. */ 3877 if (reg_renumber[i] < 0) 3878 abort (); 3879 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); 3880 /* Mark it as no longer having a hard register home. */ 3881 reg_renumber[i] = -1; 3882 /* We will need to scan everything again. */ 3883 something_changed = 1; 3884 } 3885 3886 /* Retry global register allocation if possible. */ 3887 if (global) 3888 { 3889 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET)); 3890 /* For every insn that needs reloads, set the registers used as spill 3891 regs in pseudo_forbidden_regs for every pseudo live across the 3892 insn. */ 3893 for (chain = insns_need_reload; chain; chain = chain->next_need_reload) 3894 { 3895 EXECUTE_IF_SET_IN_REG_SET 3896 (chain->live_before, FIRST_PSEUDO_REGISTER, i, 3897 { 3898 ior_hard_reg_set (pseudo_forbidden_regs + i, 3899 &chain->used_spill_regs); 3900 }); 3901 EXECUTE_IF_SET_IN_REG_SET 3902 (chain->live_after, FIRST_PSEUDO_REGISTER, i, 3903 { 3904 ior_hard_reg_set (pseudo_forbidden_regs + i, 3905 &chain->used_spill_regs); 3906 }); 3907 } 3908 3909 /* Retry allocating the spilled pseudos. For each reg, merge the 3910 various reg sets that indicate which hard regs can't be used, 3911 and call retry_global_alloc. 3912 We change spill_pseudos here to only contain pseudos that did not 3913 get a new hard register. */ 3914 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3915 if (reg_old_renumber[i] != reg_renumber[i]) 3916 { 3917 HARD_REG_SET forbidden; 3918 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); 3919 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); 3920 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); 3921 retry_global_alloc (i, forbidden); 3922 if (reg_renumber[i] >= 0) 3923 CLEAR_REGNO_REG_SET (spilled_pseudos, i); 3924 } 3925 } 3926 3927 /* Fix up the register information in the insn chain. 3928 This involves deleting those of the spilled pseudos which did not get 3929 a new hard register home from the live_{before,after} sets. */ 3930 for (chain = reload_insn_chain; chain; chain = chain->next) 3931 { 3932 HARD_REG_SET used_by_pseudos; 3933 HARD_REG_SET used_by_pseudos2; 3934 3935 AND_COMPL_REG_SET (chain->live_before, spilled_pseudos); 3936 AND_COMPL_REG_SET (chain->live_after, spilled_pseudos); 3937 3938 /* Mark any unallocated hard regs as available for spills. That 3939 makes inheritance work somewhat better. */ 3940 if (chain->need_reload) 3941 { 3942 REG_SET_TO_HARD_REG_SET (used_by_pseudos, chain->live_before); 3943 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, chain->live_after); 3944 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); 3945 3946 /* Save the old value for the sanity test below. */ 3947 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); 3948 3949 compute_use_by_pseudos (&used_by_pseudos, chain->live_before); 3950 compute_use_by_pseudos (&used_by_pseudos, chain->live_after); 3951 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); 3952 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); 3953 3954 /* Make sure we only enlarge the set. */ 3955 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok); 3956 abort (); 3957 ok:; 3958 } 3959 } 3960 3961 /* Let alter_reg modify the reg rtx's for the modified pseudos. */ 3962 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3963 { 3964 int regno = reg_renumber[i]; 3965 if (reg_old_renumber[i] == regno) 3966 continue; 3967 3968 alter_reg (i, reg_old_renumber[i]); 3969 reg_old_renumber[i] = regno; 3970 if (dumpfile) 3971 { 3972 if (regno == -1) 3973 fprintf (dumpfile, " Register %d now on stack.\n\n", i); 3974 else 3975 fprintf (dumpfile, " Register %d now in %d.\n\n", 3976 i, reg_renumber[i]); 3977 } 3978 } 3979 3980 return something_changed; 3981} 3982 3983/* Find all paradoxical subregs within X and update reg_max_ref_width. 3984 Also mark any hard registers used to store user variables as 3985 forbidden from being used for spill registers. */ 3986 3987static void 3988scan_paradoxical_subregs (x) 3989 register rtx x; 3990{ 3991 register int i; 3992 register char *fmt; 3993 register enum rtx_code code = GET_CODE (x); 3994 3995 switch (code) 3996 { 3997 case REG: 3998#if 0 3999 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER 4000 && REG_USERVAR_P (x)) 4001 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x)); 4002#endif 4003 return; 4004 4005 case CONST_INT: 4006 case CONST: 4007 case SYMBOL_REF: 4008 case LABEL_REF: 4009 case CONST_DOUBLE: 4010 case CC0: 4011 case PC: 4012 case USE: 4013 case CLOBBER: 4014 return; 4015 4016 case SUBREG: 4017 if (GET_CODE (SUBREG_REG (x)) == REG 4018 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 4019 reg_max_ref_width[REGNO (SUBREG_REG (x))] 4020 = GET_MODE_SIZE (GET_MODE (x)); 4021 return; 4022 4023 default: 4024 break; 4025 } 4026 4027 fmt = GET_RTX_FORMAT (code); 4028 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4029 { 4030 if (fmt[i] == 'e') 4031 scan_paradoxical_subregs (XEXP (x, i)); 4032 else if (fmt[i] == 'E') 4033 { 4034 register int j; 4035 for (j = XVECLEN (x, i) - 1; j >=0; j--) 4036 scan_paradoxical_subregs (XVECEXP (x, i, j)); 4037 } 4038 } 4039} 4040 4041static int 4042hard_reg_use_compare (p1p, p2p) 4043 const GENERIC_PTR p1p; 4044 const GENERIC_PTR p2p; 4045{ 4046 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p; 4047 struct hard_reg_n_uses *p2 = (struct hard_reg_n_uses *)p2p; 4048 int bad1 = TEST_HARD_REG_BIT (bad_spill_regs, p1->regno); 4049 int bad2 = TEST_HARD_REG_BIT (bad_spill_regs, p2->regno); 4050 if (bad1 && bad2) 4051 return p1->regno - p2->regno; 4052 if (bad1) 4053 return 1; 4054 if (bad2) 4055 return -1; 4056 if (p1->uses > p2->uses) 4057 return 1; 4058 if (p1->uses < p2->uses) 4059 return -1; 4060 /* If regs are equally good, sort by regno, 4061 so that the results of qsort leave nothing to chance. */ 4062 return p1->regno - p2->regno; 4063} 4064 4065/* Used for communication between order_regs_for_reload and count_pseudo. 4066 Used to avoid counting one pseudo twice. */ 4067static regset pseudos_counted; 4068 4069/* Update the costs in N_USES, considering that pseudo REG is live. */ 4070static void 4071count_pseudo (n_uses, reg) 4072 struct hard_reg_n_uses *n_uses; 4073 int reg; 4074{ 4075 int r = reg_renumber[reg]; 4076 int nregs; 4077 4078 if (REGNO_REG_SET_P (pseudos_counted, reg)) 4079 return; 4080 SET_REGNO_REG_SET (pseudos_counted, reg); 4081 4082 if (r < 0) 4083 abort (); 4084 4085 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); 4086 while (nregs-- > 0) 4087 n_uses[r++].uses += REG_N_REFS (reg); 4088} 4089/* Choose the order to consider regs for use as reload registers 4090 based on how much trouble would be caused by spilling one. 4091 Store them in order of decreasing preference in potential_reload_regs. */ 4092 4093static void 4094order_regs_for_reload (chain) 4095 struct insn_chain *chain; 4096{ 4097 register int i; 4098 register int o = 0; 4099 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER]; 4100 4101 pseudos_counted = ALLOCA_REG_SET (); 4102 4103 COPY_HARD_REG_SET (bad_spill_regs, bad_spill_regs_global); 4104 4105 /* Count number of uses of each hard reg by pseudo regs allocated to it 4106 and then order them by decreasing use. */ 4107 4108 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4109 { 4110 int j; 4111 4112 hard_reg_n_uses[i].regno = i; 4113 hard_reg_n_uses[i].uses = 0; 4114 4115 /* Test the various reasons why we can't use a register for 4116 spilling in this insn. */ 4117 if (fixed_regs[i] 4118 || REGNO_REG_SET_P (chain->live_before, i) 4119 || REGNO_REG_SET_P (chain->live_after, i)) 4120 { 4121 SET_HARD_REG_BIT (bad_spill_regs, i); 4122 continue; 4123 } 4124 4125 /* Now find out which pseudos are allocated to it, and update 4126 hard_reg_n_uses. */ 4127 CLEAR_REG_SET (pseudos_counted); 4128 4129 EXECUTE_IF_SET_IN_REG_SET 4130 (chain->live_before, FIRST_PSEUDO_REGISTER, j, 4131 { 4132 count_pseudo (hard_reg_n_uses, j); 4133 }); 4134 EXECUTE_IF_SET_IN_REG_SET 4135 (chain->live_after, FIRST_PSEUDO_REGISTER, j, 4136 { 4137 count_pseudo (hard_reg_n_uses, j); 4138 }); 4139 } 4140 4141 FREE_REG_SET (pseudos_counted); 4142 4143 /* Prefer registers not so far used, for use in temporary loading. 4144 Among them, if REG_ALLOC_ORDER is defined, use that order. 4145 Otherwise, prefer registers not preserved by calls. */ 4146 4147#ifdef REG_ALLOC_ORDER 4148 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4149 { 4150 int regno = reg_alloc_order[i]; 4151 4152 if (hard_reg_n_uses[regno].uses == 0 4153 && ! TEST_HARD_REG_BIT (bad_spill_regs, regno)) 4154 potential_reload_regs[o++] = regno; 4155 } 4156#else 4157 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4158 { 4159 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i] 4160 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)) 4161 potential_reload_regs[o++] = i; 4162 } 4163 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4164 { 4165 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i] 4166 && ! TEST_HARD_REG_BIT (bad_spill_regs, i)) 4167 potential_reload_regs[o++] = i; 4168 } 4169#endif 4170 4171 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER, 4172 sizeof hard_reg_n_uses[0], hard_reg_use_compare); 4173 4174 /* Now add the regs that are already used, 4175 preferring those used less often. The fixed and otherwise forbidden 4176 registers will be at the end of this list. */ 4177 4178 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4179 if (hard_reg_n_uses[i].uses != 0 4180 && ! TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno)) 4181 potential_reload_regs[o++] = hard_reg_n_uses[i].regno; 4182 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4183 if (TEST_HARD_REG_BIT (bad_spill_regs, hard_reg_n_uses[i].regno)) 4184 potential_reload_regs[o++] = hard_reg_n_uses[i].regno; 4185} 4186 4187/* Reload pseudo-registers into hard regs around each insn as needed. 4188 Additional register load insns are output before the insn that needs it 4189 and perhaps store insns after insns that modify the reloaded pseudo reg. 4190 4191 reg_last_reload_reg and reg_reloaded_contents keep track of 4192 which registers are already available in reload registers. 4193 We update these for the reloads that we perform, 4194 as the insns are scanned. */ 4195 4196static void 4197reload_as_needed (live_known) 4198 int live_known; 4199{ 4200 struct insn_chain *chain; 4201#if defined (AUTO_INC_DEC) || defined (INSN_CLOBBERS_REGNO_P) 4202 register int i; 4203#endif 4204 rtx x; 4205 4206 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx); 4207 bzero ((char *) spill_reg_store, sizeof spill_reg_store); 4208 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx)); 4209 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx)); 4210 reg_has_output_reload = (char *) alloca (max_regno); 4211 CLEAR_HARD_REG_SET (reg_reloaded_valid); 4212 4213 set_initial_elim_offsets (); 4214 4215 for (chain = reload_insn_chain; chain; chain = chain->next) 4216 { 4217 rtx prev; 4218 rtx insn = chain->insn; 4219 rtx old_next = NEXT_INSN (insn); 4220 4221 /* If we pass a label, copy the offsets from the label information 4222 into the current offsets of each elimination. */ 4223 if (GET_CODE (insn) == CODE_LABEL) 4224 set_offsets_for_label (insn); 4225 4226 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 4227 { 4228 rtx oldpat = PATTERN (insn); 4229 4230 /* If this is a USE and CLOBBER of a MEM, ensure that any 4231 references to eliminable registers have been removed. */ 4232 4233 if ((GET_CODE (PATTERN (insn)) == USE 4234 || GET_CODE (PATTERN (insn)) == CLOBBER) 4235 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) 4236 XEXP (XEXP (PATTERN (insn), 0), 0) 4237 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), 4238 GET_MODE (XEXP (PATTERN (insn), 0)), 4239 NULL_RTX); 4240 4241 /* If we need to do register elimination processing, do so. 4242 This might delete the insn, in which case we are done. */ 4243 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) 4244 { 4245 eliminate_regs_in_insn (insn, 1); 4246 if (GET_CODE (insn) == NOTE) 4247 { 4248 update_eliminable_offsets (); 4249 continue; 4250 } 4251 } 4252 4253 /* If need_elim is nonzero but need_reload is zero, one might think 4254 that we could simply set n_reloads to 0. However, find_reloads 4255 could have done some manipulation of the insn (such as swapping 4256 commutative operands), and these manipulations are lost during 4257 the first pass for every insn that needs register elimination. 4258 So the actions of find_reloads must be redone here. */ 4259 4260 if (! chain->need_elim && ! chain->need_reload 4261 && ! chain->need_operand_change) 4262 n_reloads = 0; 4263 /* First find the pseudo regs that must be reloaded for this insn. 4264 This info is returned in the tables reload_... (see reload.h). 4265 Also modify the body of INSN by substituting RELOAD 4266 rtx's for those pseudo regs. */ 4267 else 4268 { 4269 bzero (reg_has_output_reload, max_regno); 4270 CLEAR_HARD_REG_SET (reg_is_output_reload); 4271 4272 find_reloads (insn, 1, spill_indirect_levels, live_known, 4273 spill_reg_order); 4274 } 4275 4276 if (num_eliminable && chain->need_elim) 4277 update_eliminable_offsets (); 4278 4279 if (n_reloads > 0) 4280 { 4281 rtx next = NEXT_INSN (insn); 4282 rtx p; 4283 4284 prev = PREV_INSN (insn); 4285 4286 /* Now compute which reload regs to reload them into. Perhaps 4287 reusing reload regs from previous insns, or else output 4288 load insns to reload them. Maybe output store insns too. 4289 Record the choices of reload reg in reload_reg_rtx. */ 4290 choose_reload_regs (chain); 4291 4292 /* Merge any reloads that we didn't combine for fear of 4293 increasing the number of spill registers needed but now 4294 discover can be safely merged. */ 4295 if (SMALL_REGISTER_CLASSES) 4296 merge_assigned_reloads (insn); 4297 4298 /* Generate the insns to reload operands into or out of 4299 their reload regs. */ 4300 emit_reload_insns (chain); 4301 4302 /* Substitute the chosen reload regs from reload_reg_rtx 4303 into the insn's body (or perhaps into the bodies of other 4304 load and store insn that we just made for reloading 4305 and that we moved the structure into). */ 4306 subst_reloads (); 4307 4308 /* If this was an ASM, make sure that all the reload insns 4309 we have generated are valid. If not, give an error 4310 and delete them. */ 4311 4312 if (asm_noperands (PATTERN (insn)) >= 0) 4313 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) 4314 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i' 4315 && (recog_memoized (p) < 0 4316 || (extract_insn (p), ! constrain_operands (1)))) 4317 { 4318 error_for_asm (insn, 4319 "`asm' operand requires impossible reload"); 4320 PUT_CODE (p, NOTE); 4321 NOTE_SOURCE_FILE (p) = 0; 4322 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; 4323 } 4324 } 4325 /* Any previously reloaded spilled pseudo reg, stored in this insn, 4326 is no longer validly lying around to save a future reload. 4327 Note that this does not detect pseudos that were reloaded 4328 for this insn in order to be stored in 4329 (obeying register constraints). That is correct; such reload 4330 registers ARE still valid. */ 4331 note_stores (oldpat, forget_old_reloads_1); 4332 4333 /* There may have been CLOBBER insns placed after INSN. So scan 4334 between INSN and NEXT and use them to forget old reloads. */ 4335 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) 4336 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) 4337 note_stores (PATTERN (x), forget_old_reloads_1); 4338 4339#ifdef AUTO_INC_DEC 4340 /* Likewise for regs altered by auto-increment in this insn. 4341 REG_INC notes have been changed by reloading: 4342 find_reloads_address_1 records substitutions for them, 4343 which have been performed by subst_reloads above. */ 4344 for (i = n_reloads - 1; i >= 0; i--) 4345 { 4346 rtx in_reg = reload_in_reg[i]; 4347 if (in_reg) 4348 { 4349 enum rtx_code code = GET_CODE (in_reg); 4350 /* PRE_INC / PRE_DEC will have the reload register ending up 4351 with the same value as the stack slot, but that doesn't 4352 hold true for POST_INC / POST_DEC. Either we have to 4353 convert the memory access to a true POST_INC / POST_DEC, 4354 or we can't use the reload register for inheritance. */ 4355 if ((code == POST_INC || code == POST_DEC) 4356 && TEST_HARD_REG_BIT (reg_reloaded_valid, 4357 REGNO (reload_reg_rtx[i])) 4358 /* Make sure it is the inc/dec pseudo, and not 4359 some other (e.g. output operand) pseudo. */ 4360 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])] 4361 == REGNO (XEXP (in_reg, 0)))) 4362 4363 { 4364 rtx reload_reg = reload_reg_rtx[i]; 4365 enum machine_mode mode = GET_MODE (reload_reg); 4366 int n = 0; 4367 rtx p; 4368 4369 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) 4370 { 4371 /* We really want to ignore REG_INC notes here, so 4372 use PATTERN (p) as argument to reg_set_p . */ 4373 if (reg_set_p (reload_reg, PATTERN (p))) 4374 break; 4375 n = count_occurrences (PATTERN (p), reload_reg); 4376 if (! n) 4377 continue; 4378 if (n == 1) 4379 { 4380 n = validate_replace_rtx (reload_reg, 4381 gen_rtx (code, mode, 4382 reload_reg), 4383 p); 4384 4385 /* We must also verify that the constraints 4386 are met after the replacement. */ 4387 extract_insn (p); 4388 if (n) 4389 n = constrain_operands (1); 4390 else 4391 break; 4392 4393 /* If the constraints were not met, then 4394 undo the replacement. */ 4395 if (!n) 4396 { 4397 validate_replace_rtx (gen_rtx (code, mode, 4398 reload_reg), 4399 reload_reg, p); 4400 break; 4401 } 4402 4403 } 4404 break; 4405 } 4406 if (n == 1) 4407 { 4408 REG_NOTES (p) 4409 = gen_rtx_EXPR_LIST (REG_INC, reload_reg, 4410 REG_NOTES (p)); 4411 /* Mark this as having an output reload so that the 4412 REG_INC processing code below won't invalidate 4413 the reload for inheritance. */ 4414 SET_HARD_REG_BIT (reg_is_output_reload, 4415 REGNO (reload_reg)); 4416 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; 4417 } 4418 else 4419 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX); 4420 } 4421 else if ((code == PRE_INC || code == PRE_DEC) 4422 && TEST_HARD_REG_BIT (reg_reloaded_valid, 4423 REGNO (reload_reg_rtx[i])) 4424 /* Make sure it is the inc/dec pseudo, and not 4425 some other (e.g. output operand) pseudo. */ 4426 && (reg_reloaded_contents[REGNO (reload_reg_rtx[i])] 4427 == REGNO (XEXP (in_reg, 0)))) 4428 { 4429 SET_HARD_REG_BIT (reg_is_output_reload, 4430 REGNO (reload_reg_rtx[i])); 4431 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; 4432 } 4433 } 4434 } 4435 /* If a pseudo that got a hard register is auto-incremented, 4436 we must purge records of copying it into pseudos without 4437 hard registers. */ 4438 for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) 4439 if (REG_NOTE_KIND (x) == REG_INC) 4440 { 4441 /* See if this pseudo reg was reloaded in this insn. 4442 If so, its last-reload info is still valid 4443 because it is based on this insn's reload. */ 4444 for (i = 0; i < n_reloads; i++) 4445 if (reload_out[i] == XEXP (x, 0)) 4446 break; 4447 4448 if (i == n_reloads) 4449 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX); 4450 } 4451#endif 4452 } 4453 /* A reload reg's contents are unknown after a label. */ 4454 if (GET_CODE (insn) == CODE_LABEL) 4455 CLEAR_HARD_REG_SET (reg_reloaded_valid); 4456 4457 /* Don't assume a reload reg is still good after a call insn 4458 if it is a call-used reg. */ 4459 else if (GET_CODE (insn) == CALL_INSN) 4460 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set); 4461 4462 /* In case registers overlap, allow certain insns to invalidate 4463 particular hard registers. */ 4464 4465#ifdef INSN_CLOBBERS_REGNO_P 4466 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++) 4467 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i) 4468 && INSN_CLOBBERS_REGNO_P (insn, i)) 4469 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i); 4470#endif 4471 4472#ifdef USE_C_ALLOCA 4473 alloca (0); 4474#endif 4475 } 4476} 4477 4478/* Discard all record of any value reloaded from X, 4479 or reloaded in X from someplace else; 4480 unless X is an output reload reg of the current insn. 4481 4482 X may be a hard reg (the reload reg) 4483 or it may be a pseudo reg that was reloaded from. */ 4484 4485static void 4486forget_old_reloads_1 (x, ignored) 4487 rtx x; 4488 rtx ignored ATTRIBUTE_UNUSED; 4489{ 4490 register int regno; 4491 int nr; 4492 int offset = 0; 4493 4494 /* note_stores does give us subregs of hard regs. */ 4495 while (GET_CODE (x) == SUBREG) 4496 { 4497 offset += SUBREG_WORD (x); 4498 x = SUBREG_REG (x); 4499 } 4500 4501 if (GET_CODE (x) != REG) 4502 return; 4503 4504 regno = REGNO (x) + offset; 4505 4506 if (regno >= FIRST_PSEUDO_REGISTER) 4507 nr = 1; 4508 else 4509 { 4510 int i; 4511 nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); 4512 /* Storing into a spilled-reg invalidates its contents. 4513 This can happen if a block-local pseudo is allocated to that reg 4514 and it wasn't spilled because this block's total need is 0. 4515 Then some insn might have an optional reload and use this reg. */ 4516 for (i = 0; i < nr; i++) 4517 /* But don't do this if the reg actually serves as an output 4518 reload reg in the current instruction. */ 4519 if (n_reloads == 0 4520 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) 4521 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); 4522 } 4523 4524 /* Since value of X has changed, 4525 forget any value previously copied from it. */ 4526 4527 while (nr-- > 0) 4528 /* But don't forget a copy if this is the output reload 4529 that establishes the copy's validity. */ 4530 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) 4531 reg_last_reload_reg[regno + nr] = 0; 4532} 4533 4534/* For each reload, the mode of the reload register. */ 4535static enum machine_mode reload_mode[MAX_RELOADS]; 4536 4537/* For each reload, the largest number of registers it will require. */ 4538static int reload_nregs[MAX_RELOADS]; 4539 4540/* Comparison function for qsort to decide which of two reloads 4541 should be handled first. *P1 and *P2 are the reload numbers. */ 4542 4543static int 4544reload_reg_class_lower (r1p, r2p) 4545 const GENERIC_PTR r1p; 4546 const GENERIC_PTR r2p; 4547{ 4548 register int r1 = *(short *)r1p, r2 = *(short *)r2p; 4549 register int t; 4550 4551 /* Consider required reloads before optional ones. */ 4552 t = reload_optional[r1] - reload_optional[r2]; 4553 if (t != 0) 4554 return t; 4555 4556 /* Count all solitary classes before non-solitary ones. */ 4557 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1) 4558 - (reg_class_size[(int) reload_reg_class[r1]] == 1)); 4559 if (t != 0) 4560 return t; 4561 4562 /* Aside from solitaires, consider all multi-reg groups first. */ 4563 t = reload_nregs[r2] - reload_nregs[r1]; 4564 if (t != 0) 4565 return t; 4566 4567 /* Consider reloads in order of increasing reg-class number. */ 4568 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2]; 4569 if (t != 0) 4570 return t; 4571 4572 /* If reloads are equally urgent, sort by reload number, 4573 so that the results of qsort leave nothing to chance. */ 4574 return r1 - r2; 4575} 4576 4577/* The following HARD_REG_SETs indicate when each hard register is 4578 used for a reload of various parts of the current insn. */ 4579 4580/* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ 4581static HARD_REG_SET reload_reg_used; 4582/* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ 4583static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; 4584/* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ 4585static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; 4586/* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ 4587static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; 4588/* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ 4589static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; 4590/* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ 4591static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; 4592/* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ 4593static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; 4594/* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ 4595static HARD_REG_SET reload_reg_used_in_op_addr; 4596/* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ 4597static HARD_REG_SET reload_reg_used_in_op_addr_reload; 4598/* If reg is in use for a RELOAD_FOR_INSN reload. */ 4599static HARD_REG_SET reload_reg_used_in_insn; 4600/* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ 4601static HARD_REG_SET reload_reg_used_in_other_addr; 4602 4603/* If reg is in use as a reload reg for any sort of reload. */ 4604static HARD_REG_SET reload_reg_used_at_all; 4605 4606/* If reg is use as an inherited reload. We just mark the first register 4607 in the group. */ 4608static HARD_REG_SET reload_reg_used_for_inherit; 4609 4610/* Records which hard regs are used in any way, either as explicit use or 4611 by being allocated to a pseudo during any point of the current insn. */ 4612static HARD_REG_SET reg_used_in_insn; 4613 4614/* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and 4615 TYPE. MODE is used to indicate how many consecutive regs are 4616 actually used. */ 4617 4618static void 4619mark_reload_reg_in_use (regno, opnum, type, mode) 4620 int regno; 4621 int opnum; 4622 enum reload_type type; 4623 enum machine_mode mode; 4624{ 4625 int nregs = HARD_REGNO_NREGS (regno, mode); 4626 int i; 4627 4628 for (i = regno; i < nregs + regno; i++) 4629 { 4630 switch (type) 4631 { 4632 case RELOAD_OTHER: 4633 SET_HARD_REG_BIT (reload_reg_used, i); 4634 break; 4635 4636 case RELOAD_FOR_INPUT_ADDRESS: 4637 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); 4638 break; 4639 4640 case RELOAD_FOR_INPADDR_ADDRESS: 4641 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); 4642 break; 4643 4644 case RELOAD_FOR_OUTPUT_ADDRESS: 4645 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); 4646 break; 4647 4648 case RELOAD_FOR_OUTADDR_ADDRESS: 4649 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); 4650 break; 4651 4652 case RELOAD_FOR_OPERAND_ADDRESS: 4653 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); 4654 break; 4655 4656 case RELOAD_FOR_OPADDR_ADDR: 4657 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); 4658 break; 4659 4660 case RELOAD_FOR_OTHER_ADDRESS: 4661 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); 4662 break; 4663 4664 case RELOAD_FOR_INPUT: 4665 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); 4666 break; 4667 4668 case RELOAD_FOR_OUTPUT: 4669 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); 4670 break; 4671 4672 case RELOAD_FOR_INSN: 4673 SET_HARD_REG_BIT (reload_reg_used_in_insn, i); 4674 break; 4675 } 4676 4677 SET_HARD_REG_BIT (reload_reg_used_at_all, i); 4678 } 4679} 4680 4681/* Similarly, but show REGNO is no longer in use for a reload. */ 4682 4683static void 4684clear_reload_reg_in_use (regno, opnum, type, mode) 4685 int regno; 4686 int opnum; 4687 enum reload_type type; 4688 enum machine_mode mode; 4689{ 4690 int nregs = HARD_REGNO_NREGS (regno, mode); 4691 int start_regno, end_regno; 4692 int i; 4693 /* A complication is that for some reload types, inheritance might 4694 allow multiple reloads of the same types to share a reload register. 4695 We set check_opnum if we have to check only reloads with the same 4696 operand number, and check_any if we have to check all reloads. */ 4697 int check_opnum = 0; 4698 int check_any = 0; 4699 HARD_REG_SET *used_in_set; 4700 4701 switch (type) 4702 { 4703 case RELOAD_OTHER: 4704 used_in_set = &reload_reg_used; 4705 break; 4706 4707 case RELOAD_FOR_INPUT_ADDRESS: 4708 used_in_set = &reload_reg_used_in_input_addr[opnum]; 4709 break; 4710 4711 case RELOAD_FOR_INPADDR_ADDRESS: 4712 check_opnum = 1; 4713 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; 4714 break; 4715 4716 case RELOAD_FOR_OUTPUT_ADDRESS: 4717 used_in_set = &reload_reg_used_in_output_addr[opnum]; 4718 break; 4719 4720 case RELOAD_FOR_OUTADDR_ADDRESS: 4721 check_opnum = 1; 4722 used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; 4723 break; 4724 4725 case RELOAD_FOR_OPERAND_ADDRESS: 4726 used_in_set = &reload_reg_used_in_op_addr; 4727 break; 4728 4729 case RELOAD_FOR_OPADDR_ADDR: 4730 check_any = 1; 4731 used_in_set = &reload_reg_used_in_op_addr_reload; 4732 break; 4733 4734 case RELOAD_FOR_OTHER_ADDRESS: 4735 used_in_set = &reload_reg_used_in_other_addr; 4736 check_any = 1; 4737 break; 4738 4739 case RELOAD_FOR_INPUT: 4740 used_in_set = &reload_reg_used_in_input[opnum]; 4741 break; 4742 4743 case RELOAD_FOR_OUTPUT: 4744 used_in_set = &reload_reg_used_in_output[opnum]; 4745 break; 4746 4747 case RELOAD_FOR_INSN: 4748 used_in_set = &reload_reg_used_in_insn; 4749 break; 4750 default: 4751 abort (); 4752 } 4753 /* We resolve conflicts with remaining reloads of the same type by 4754 excluding the intervals of of reload registers by them from the 4755 interval of freed reload registers. Since we only keep track of 4756 one set of interval bounds, we might have to exclude somewhat 4757 more then what would be necessary if we used a HARD_REG_SET here. 4758 But this should only happen very infrequently, so there should 4759 be no reason to worry about it. */ 4760 4761 start_regno = regno; 4762 end_regno = regno + nregs; 4763 if (check_opnum || check_any) 4764 { 4765 for (i = n_reloads - 1; i >= 0; i--) 4766 { 4767 if (reload_when_needed[i] == type 4768 && (check_any || reload_opnum[i] == opnum) 4769 && reload_reg_rtx[i]) 4770 { 4771 int conflict_start = true_regnum (reload_reg_rtx[i]); 4772 int conflict_end 4773 = (conflict_start 4774 + HARD_REGNO_NREGS (conflict_start, reload_mode[i])); 4775 4776 /* If there is an overlap with the first to-be-freed register, 4777 adjust the interval start. */ 4778 if (conflict_start <= start_regno && conflict_end > start_regno) 4779 start_regno = conflict_end; 4780 /* Otherwise, if there is a conflict with one of the other 4781 to-be-freed registers, adjust the interval end. */ 4782 if (conflict_start > start_regno && conflict_start < end_regno) 4783 end_regno = conflict_start; 4784 } 4785 } 4786 } 4787 for (i = start_regno; i < end_regno; i++) 4788 CLEAR_HARD_REG_BIT (*used_in_set, i); 4789} 4790 4791/* 1 if reg REGNO is free as a reload reg for a reload of the sort 4792 specified by OPNUM and TYPE. */ 4793 4794static int 4795reload_reg_free_p (regno, opnum, type) 4796 int regno; 4797 int opnum; 4798 enum reload_type type; 4799{ 4800 int i; 4801 4802 /* In use for a RELOAD_OTHER means it's not available for anything. */ 4803 if (TEST_HARD_REG_BIT (reload_reg_used, regno)) 4804 return 0; 4805 4806 switch (type) 4807 { 4808 case RELOAD_OTHER: 4809 /* In use for anything means we can't use it for RELOAD_OTHER. */ 4810 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) 4811 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4812 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 4813 return 0; 4814 4815 for (i = 0; i < reload_n_operands; i++) 4816 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4817 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4818 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4819 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4820 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) 4821 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4822 return 0; 4823 4824 return 1; 4825 4826 case RELOAD_FOR_INPUT: 4827 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4828 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) 4829 return 0; 4830 4831 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 4832 return 0; 4833 4834 /* If it is used for some other input, can't use it. */ 4835 for (i = 0; i < reload_n_operands; i++) 4836 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4837 return 0; 4838 4839 /* If it is used in a later operand's address, can't use it. */ 4840 for (i = opnum + 1; i < reload_n_operands; i++) 4841 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4842 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 4843 return 0; 4844 4845 return 1; 4846 4847 case RELOAD_FOR_INPUT_ADDRESS: 4848 /* Can't use a register if it is used for an input address for this 4849 operand or used as an input in an earlier one. */ 4850 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) 4851 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 4852 return 0; 4853 4854 for (i = 0; i < opnum; i++) 4855 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4856 return 0; 4857 4858 return 1; 4859 4860 case RELOAD_FOR_INPADDR_ADDRESS: 4861 /* Can't use a register if it is used for an input address 4862 for this operand or used as an input in an earlier 4863 one. */ 4864 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 4865 return 0; 4866 4867 for (i = 0; i < opnum; i++) 4868 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4869 return 0; 4870 4871 return 1; 4872 4873 case RELOAD_FOR_OUTPUT_ADDRESS: 4874 /* Can't use a register if it is used for an output address for this 4875 operand or used as an output in this or a later operand. */ 4876 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) 4877 return 0; 4878 4879 for (i = opnum; i < reload_n_operands; i++) 4880 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4881 return 0; 4882 4883 return 1; 4884 4885 case RELOAD_FOR_OUTADDR_ADDRESS: 4886 /* Can't use a register if it is used for an output address 4887 for this operand or used as an output in this or a 4888 later operand. */ 4889 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) 4890 return 0; 4891 4892 for (i = opnum; i < reload_n_operands; i++) 4893 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4894 return 0; 4895 4896 return 1; 4897 4898 case RELOAD_FOR_OPERAND_ADDRESS: 4899 for (i = 0; i < reload_n_operands; i++) 4900 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4901 return 0; 4902 4903 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4904 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 4905 4906 case RELOAD_FOR_OPADDR_ADDR: 4907 for (i = 0; i < reload_n_operands; i++) 4908 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4909 return 0; 4910 4911 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); 4912 4913 case RELOAD_FOR_OUTPUT: 4914 /* This cannot share a register with RELOAD_FOR_INSN reloads, other 4915 outputs, or an operand address for this or an earlier output. */ 4916 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 4917 return 0; 4918 4919 for (i = 0; i < reload_n_operands; i++) 4920 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4921 return 0; 4922 4923 for (i = 0; i <= opnum; i++) 4924 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4925 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) 4926 return 0; 4927 4928 return 1; 4929 4930 case RELOAD_FOR_INSN: 4931 for (i = 0; i < reload_n_operands; i++) 4932 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) 4933 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4934 return 0; 4935 4936 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4937 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 4938 4939 case RELOAD_FOR_OTHER_ADDRESS: 4940 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); 4941 } 4942 abort (); 4943} 4944 4945/* Return 1 if the value in reload reg REGNO, as used by a reload 4946 needed for the part of the insn specified by OPNUM and TYPE, 4947 is still available in REGNO at the end of the insn. 4948 4949 We can assume that the reload reg was already tested for availability 4950 at the time it is needed, and we should not check this again, 4951 in case the reg has already been marked in use. */ 4952 4953static int 4954reload_reg_reaches_end_p (regno, opnum, type) 4955 int regno; 4956 int opnum; 4957 enum reload_type type; 4958{ 4959 int i; 4960 4961 switch (type) 4962 { 4963 case RELOAD_OTHER: 4964 /* Since a RELOAD_OTHER reload claims the reg for the entire insn, 4965 its value must reach the end. */ 4966 return 1; 4967 4968 /* If this use is for part of the insn, 4969 its value reaches if no subsequent part uses the same register. 4970 Just like the above function, don't try to do this with lots 4971 of fallthroughs. */ 4972 4973 case RELOAD_FOR_OTHER_ADDRESS: 4974 /* Here we check for everything else, since these don't conflict 4975 with anything else and everything comes later. */ 4976 4977 for (i = 0; i < reload_n_operands; i++) 4978 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4979 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4980 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) 4981 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4982 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4983 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4984 return 0; 4985 4986 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4987 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4988 && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); 4989 4990 case RELOAD_FOR_INPUT_ADDRESS: 4991 case RELOAD_FOR_INPADDR_ADDRESS: 4992 /* Similar, except that we check only for this and subsequent inputs 4993 and the address of only subsequent inputs and we do not need 4994 to check for RELOAD_OTHER objects since they are known not to 4995 conflict. */ 4996 4997 for (i = opnum; i < reload_n_operands; i++) 4998 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4999 return 0; 5000 5001 for (i = opnum + 1; i < reload_n_operands; i++) 5002 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 5003 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 5004 return 0; 5005 5006 for (i = 0; i < reload_n_operands; i++) 5007 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5008 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 5009 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5010 return 0; 5011 5012 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 5013 return 0; 5014 5015 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 5016 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)); 5017 5018 case RELOAD_FOR_INPUT: 5019 /* Similar to input address, except we start at the next operand for 5020 both input and input address and we do not check for 5021 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these 5022 would conflict. */ 5023 5024 for (i = opnum + 1; i < reload_n_operands; i++) 5025 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 5026 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 5027 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 5028 return 0; 5029 5030 /* ... fall through ... */ 5031 5032 case RELOAD_FOR_OPERAND_ADDRESS: 5033 /* Check outputs and their addresses. */ 5034 5035 for (i = 0; i < reload_n_operands; i++) 5036 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5037 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 5038 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5039 return 0; 5040 5041 return 1; 5042 5043 case RELOAD_FOR_OPADDR_ADDR: 5044 for (i = 0; i < reload_n_operands; i++) 5045 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5046 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 5047 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5048 return 0; 5049 5050 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 5051 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)); 5052 5053 case RELOAD_FOR_INSN: 5054 /* These conflict with other outputs with RELOAD_OTHER. So 5055 we need only check for output addresses. */ 5056 5057 opnum = -1; 5058 5059 /* ... fall through ... */ 5060 5061 case RELOAD_FOR_OUTPUT: 5062 case RELOAD_FOR_OUTPUT_ADDRESS: 5063 case RELOAD_FOR_OUTADDR_ADDRESS: 5064 /* We already know these can't conflict with a later output. So the 5065 only thing to check are later output addresses. */ 5066 for (i = opnum + 1; i < reload_n_operands; i++) 5067 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5068 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) 5069 return 0; 5070 5071 return 1; 5072 } 5073 5074 abort (); 5075} 5076 5077/* Return 1 if the reloads denoted by R1 and R2 cannot share a register. 5078 Return 0 otherwise. 5079 5080 This function uses the same algorithm as reload_reg_free_p above. */ 5081 5082int 5083reloads_conflict (r1, r2) 5084 int r1, r2; 5085{ 5086 enum reload_type r1_type = reload_when_needed[r1]; 5087 enum reload_type r2_type = reload_when_needed[r2]; 5088 int r1_opnum = reload_opnum[r1]; 5089 int r2_opnum = reload_opnum[r2]; 5090 5091 /* RELOAD_OTHER conflicts with everything. */ 5092 if (r2_type == RELOAD_OTHER) 5093 return 1; 5094 5095 /* Otherwise, check conflicts differently for each type. */ 5096 5097 switch (r1_type) 5098 { 5099 case RELOAD_FOR_INPUT: 5100 return (r2_type == RELOAD_FOR_INSN 5101 || r2_type == RELOAD_FOR_OPERAND_ADDRESS 5102 || r2_type == RELOAD_FOR_OPADDR_ADDR 5103 || r2_type == RELOAD_FOR_INPUT 5104 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS 5105 || r2_type == RELOAD_FOR_INPADDR_ADDRESS) 5106 && r2_opnum > r1_opnum)); 5107 5108 case RELOAD_FOR_INPUT_ADDRESS: 5109 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) 5110 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); 5111 5112 case RELOAD_FOR_INPADDR_ADDRESS: 5113 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) 5114 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); 5115 5116 case RELOAD_FOR_OUTPUT_ADDRESS: 5117 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) 5118 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum)); 5119 5120 case RELOAD_FOR_OUTADDR_ADDRESS: 5121 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) 5122 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum)); 5123 5124 case RELOAD_FOR_OPERAND_ADDRESS: 5125 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN 5126 || r2_type == RELOAD_FOR_OPERAND_ADDRESS); 5127 5128 case RELOAD_FOR_OPADDR_ADDR: 5129 return (r2_type == RELOAD_FOR_INPUT 5130 || r2_type == RELOAD_FOR_OPADDR_ADDR); 5131 5132 case RELOAD_FOR_OUTPUT: 5133 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT 5134 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS 5135 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) 5136 && r2_opnum >= r1_opnum)); 5137 5138 case RELOAD_FOR_INSN: 5139 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT 5140 || r2_type == RELOAD_FOR_INSN 5141 || r2_type == RELOAD_FOR_OPERAND_ADDRESS); 5142 5143 case RELOAD_FOR_OTHER_ADDRESS: 5144 return r2_type == RELOAD_FOR_OTHER_ADDRESS; 5145 5146 case RELOAD_OTHER: 5147 return 1; 5148 5149 default: 5150 abort (); 5151 } 5152} 5153 5154/* Vector of reload-numbers showing the order in which the reloads should 5155 be processed. */ 5156short reload_order[MAX_RELOADS]; 5157 5158/* Indexed by reload number, 1 if incoming value 5159 inherited from previous insns. */ 5160char reload_inherited[MAX_RELOADS]; 5161 5162/* For an inherited reload, this is the insn the reload was inherited from, 5163 if we know it. Otherwise, this is 0. */ 5164rtx reload_inheritance_insn[MAX_RELOADS]; 5165 5166/* If non-zero, this is a place to get the value of the reload, 5167 rather than using reload_in. */ 5168rtx reload_override_in[MAX_RELOADS]; 5169 5170/* For each reload, the hard register number of the register used, 5171 or -1 if we did not need a register for this reload. */ 5172int reload_spill_index[MAX_RELOADS]; 5173 5174/* Return 1 if the value in reload reg REGNO, as used by a reload 5175 needed for the part of the insn specified by OPNUM and TYPE, 5176 may be used to load VALUE into it. 5177 5178 Other read-only reloads with the same value do not conflict 5179 unless OUT is non-zero and these other reloads have to live while 5180 output reloads live. 5181 If OUT is CONST0_RTX, this is a special case: it means that the 5182 test should not be for using register REGNO as reload register, but 5183 for copying from register REGNO into the reload register. 5184 5185 RELOADNUM is the number of the reload we want to load this value for; 5186 a reload does not conflict with itself. 5187 5188 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with 5189 reloads that load an address for the very reload we are considering. 5190 5191 The caller has to make sure that there is no conflict with the return 5192 register. */ 5193static int 5194reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum, 5195 ignore_address_reloads) 5196 int regno; 5197 int opnum; 5198 enum reload_type type; 5199 rtx value, out; 5200 int reloadnum; 5201 int ignore_address_reloads; 5202{ 5203 int time1; 5204 int i; 5205 int copy = 0; 5206 5207 if (out == const0_rtx) 5208 { 5209 copy = 1; 5210 out = NULL_RTX; 5211 } 5212 5213 /* We use some pseudo 'time' value to check if the lifetimes of the 5214 new register use would overlap with the one of a previous reload 5215 that is not read-only or uses a different value. 5216 The 'time' used doesn't have to be linear in any shape or form, just 5217 monotonic. 5218 Some reload types use different 'buckets' for each operand. 5219 So there are MAX_RECOG_OPERANDS different time values for each 5220 such reload type. 5221 We compute TIME1 as the time when the register for the prospective 5222 new reload ceases to be live, and TIME2 for each existing 5223 reload as the time when that the reload register of that reload 5224 becomes live. 5225 Where there is little to be gained by exact lifetime calculations, 5226 we just make conservative assumptions, i.e. a longer lifetime; 5227 this is done in the 'default:' cases. */ 5228 switch (type) 5229 { 5230 case RELOAD_FOR_OTHER_ADDRESS: 5231 time1 = 0; 5232 break; 5233 case RELOAD_OTHER: 5234 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; 5235 break; 5236 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS, 5237 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , 5238 respectively, to the time values for these, we get distinct time 5239 values. To get distinct time values for each operand, we have to 5240 multiply opnum by at least three. We round that up to four because 5241 multiply by four is often cheaper. */ 5242 case RELOAD_FOR_INPADDR_ADDRESS: 5243 time1 = opnum * 4 + 2; 5244 break; 5245 case RELOAD_FOR_INPUT_ADDRESS: 5246 time1 = opnum * 4 + 3; 5247 break; 5248 case RELOAD_FOR_INPUT: 5249 /* All RELOAD_FOR_INPUT reloads remain live till the instruction 5250 executes (inclusive). */ 5251 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; 5252 break; 5253 case RELOAD_FOR_OPADDR_ADDR: 5254 /* opnum * 4 + 4 5255 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ 5256 time1 = MAX_RECOG_OPERANDS * 4 + 1; 5257 break; 5258 case RELOAD_FOR_OPERAND_ADDRESS: 5259 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn 5260 is executed. */ 5261 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; 5262 break; 5263 case RELOAD_FOR_OUTADDR_ADDRESS: 5264 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; 5265 break; 5266 case RELOAD_FOR_OUTPUT_ADDRESS: 5267 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; 5268 break; 5269 default: 5270 time1 = MAX_RECOG_OPERANDS * 5 + 5; 5271 } 5272 5273 for (i = 0; i < n_reloads; i++) 5274 { 5275 rtx reg = reload_reg_rtx[i]; 5276 if (reg && GET_CODE (reg) == REG 5277 && ((unsigned) regno - true_regnum (reg) 5278 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1) 5279 && i != reloadnum) 5280 { 5281 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value) 5282 || reload_out[i] || out) 5283 { 5284 int time2; 5285 switch (reload_when_needed[i]) 5286 { 5287 case RELOAD_FOR_OTHER_ADDRESS: 5288 time2 = 0; 5289 break; 5290 case RELOAD_FOR_INPADDR_ADDRESS: 5291 /* find_reloads makes sure that a 5292 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used 5293 by at most one - the first - 5294 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the 5295 address reload is inherited, the address address reload 5296 goes away, so we can ignore this conflict. */ 5297 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 5298 && ignore_address_reloads 5299 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. 5300 Then the address address is still needed to store 5301 back the new address. */ 5302 && ! reload_out[reloadnum]) 5303 continue; 5304 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its 5305 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS 5306 reloads go away. */ 5307 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i] 5308 && ignore_address_reloads 5309 /* Unless we are reloading an auto_inc expression. */ 5310 && ! reload_out[reloadnum]) 5311 continue; 5312 time2 = reload_opnum[i] * 4 + 2; 5313 break; 5314 case RELOAD_FOR_INPUT_ADDRESS: 5315 if (type == RELOAD_FOR_INPUT && opnum == reload_opnum[i] 5316 && ignore_address_reloads 5317 && ! reload_out[reloadnum]) 5318 continue; 5319 time2 = reload_opnum[i] * 4 + 3; 5320 break; 5321 case RELOAD_FOR_INPUT: 5322 time2 = reload_opnum[i] * 4 + 4; 5323 break; 5324 /* reload_opnum[i] * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 5325 == MAX_RECOG_OPERAND * 4 */ 5326 case RELOAD_FOR_OPADDR_ADDR: 5327 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 5328 && ignore_address_reloads 5329 && ! reload_out[reloadnum]) 5330 continue; 5331 time2 = MAX_RECOG_OPERANDS * 4 + 1; 5332 break; 5333 case RELOAD_FOR_OPERAND_ADDRESS: 5334 time2 = MAX_RECOG_OPERANDS * 4 + 2; 5335 break; 5336 case RELOAD_FOR_INSN: 5337 time2 = MAX_RECOG_OPERANDS * 4 + 3; 5338 break; 5339 case RELOAD_FOR_OUTPUT: 5340 /* All RELOAD_FOR_OUTPUT reloads become live just after the 5341 instruction is executed. */ 5342 time2 = MAX_RECOG_OPERANDS * 4 + 4; 5343 break; 5344 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with 5345 the RELOAD_FOR_OUTPUT reloads, so assign it the same time 5346 value. */ 5347 case RELOAD_FOR_OUTADDR_ADDRESS: 5348 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 5349 && ignore_address_reloads 5350 && ! reload_out[reloadnum]) 5351 continue; 5352 time2 = MAX_RECOG_OPERANDS * 4 + 4 + reload_opnum[i]; 5353 break; 5354 case RELOAD_FOR_OUTPUT_ADDRESS: 5355 time2 = MAX_RECOG_OPERANDS * 4 + 5 + reload_opnum[i]; 5356 break; 5357 case RELOAD_OTHER: 5358 /* If there is no conflict in the input part, handle this 5359 like an output reload. */ 5360 if (! reload_in[i] || rtx_equal_p (reload_in[i], value)) 5361 { 5362 time2 = MAX_RECOG_OPERANDS * 4 + 4; 5363 break; 5364 } 5365 time2 = 1; 5366 /* RELOAD_OTHER might be live beyond instruction execution, 5367 but this is not obvious when we set time2 = 1. So check 5368 here if there might be a problem with the new reload 5369 clobbering the register used by the RELOAD_OTHER. */ 5370 if (out) 5371 return 0; 5372 break; 5373 default: 5374 return 0; 5375 } 5376 if ((time1 >= time2 5377 && (! reload_in[i] || reload_out[i] 5378 || ! rtx_equal_p (reload_in[i], value))) 5379 || (out && reload_out_reg[reloadnum] 5380 && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) 5381 return 0; 5382 } 5383 } 5384 } 5385 return 1; 5386} 5387 5388/* Find a spill register to use as a reload register for reload R. 5389 LAST_RELOAD is non-zero if this is the last reload for the insn being 5390 processed. 5391 5392 Set reload_reg_rtx[R] to the register allocated. 5393 5394 If NOERROR is nonzero, we return 1 if successful, 5395 or 0 if we couldn't find a spill reg and we didn't change anything. */ 5396 5397static int 5398allocate_reload_reg (chain, r, last_reload, noerror) 5399 struct insn_chain *chain; 5400 int r; 5401 int last_reload; 5402 int noerror; 5403{ 5404 rtx insn = chain->insn; 5405 int i, pass, count, regno; 5406 rtx new; 5407 5408 /* If we put this reload ahead, thinking it is a group, 5409 then insist on finding a group. Otherwise we can grab a 5410 reg that some other reload needs. 5411 (That can happen when we have a 68000 DATA_OR_FP_REG 5412 which is a group of data regs or one fp reg.) 5413 We need not be so restrictive if there are no more reloads 5414 for this insn. 5415 5416 ??? Really it would be nicer to have smarter handling 5417 for that kind of reg class, where a problem like this is normal. 5418 Perhaps those classes should be avoided for reloading 5419 by use of more alternatives. */ 5420 5421 int force_group = reload_nregs[r] > 1 && ! last_reload; 5422 5423 /* If we want a single register and haven't yet found one, 5424 take any reg in the right class and not in use. 5425 If we want a consecutive group, here is where we look for it. 5426 5427 We use two passes so we can first look for reload regs to 5428 reuse, which are already in use for other reloads in this insn, 5429 and only then use additional registers. 5430 I think that maximizing reuse is needed to make sure we don't 5431 run out of reload regs. Suppose we have three reloads, and 5432 reloads A and B can share regs. These need two regs. 5433 Suppose A and B are given different regs. 5434 That leaves none for C. */ 5435 for (pass = 0; pass < 2; pass++) 5436 { 5437 /* I is the index in spill_regs. 5438 We advance it round-robin between insns to use all spill regs 5439 equally, so that inherited reloads have a chance 5440 of leapfrogging each other. Don't do this, however, when we have 5441 group needs and failure would be fatal; if we only have a relatively 5442 small number of spill registers, and more than one of them has 5443 group needs, then by starting in the middle, we may end up 5444 allocating the first one in such a way that we are not left with 5445 sufficient groups to handle the rest. */ 5446 5447 if (noerror || ! force_group) 5448 i = last_spill_reg; 5449 else 5450 i = -1; 5451 5452 for (count = 0; count < n_spills; count++) 5453 { 5454 int class = (int) reload_reg_class[r]; 5455 int regnum; 5456 5457 i++; 5458 if (i >= n_spills) 5459 i -= n_spills; 5460 regnum = spill_regs[i]; 5461 5462 if ((reload_reg_free_p (regnum, reload_opnum[r], 5463 reload_when_needed[r]) 5464 || (reload_in[r] 5465 /* We check reload_reg_used to make sure we 5466 don't clobber the return register. */ 5467 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) 5468 && reload_reg_free_for_value_p (regnum, 5469 reload_opnum[r], 5470 reload_when_needed[r], 5471 reload_in[r], 5472 reload_out[r], r, 1))) 5473 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) 5474 && HARD_REGNO_MODE_OK (regnum, reload_mode[r]) 5475 /* Look first for regs to share, then for unshared. But 5476 don't share regs used for inherited reloads; they are 5477 the ones we want to preserve. */ 5478 && (pass 5479 || (TEST_HARD_REG_BIT (reload_reg_used_at_all, 5480 regnum) 5481 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, 5482 regnum)))) 5483 { 5484 int nr = HARD_REGNO_NREGS (regnum, reload_mode[r]); 5485 /* Avoid the problem where spilling a GENERAL_OR_FP_REG 5486 (on 68000) got us two FP regs. If NR is 1, 5487 we would reject both of them. */ 5488 if (force_group) 5489 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]); 5490 /* If we need only one reg, we have already won. */ 5491 if (nr == 1) 5492 { 5493 /* But reject a single reg if we demand a group. */ 5494 if (force_group) 5495 continue; 5496 break; 5497 } 5498 /* Otherwise check that as many consecutive regs as we need 5499 are available here. 5500 Also, don't use for a group registers that are 5501 needed for nongroups. */ 5502 if (! TEST_HARD_REG_BIT (chain->counted_for_nongroups, regnum)) 5503 while (nr > 1) 5504 { 5505 regno = regnum + nr - 1; 5506 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) 5507 && spill_reg_order[regno] >= 0 5508 && reload_reg_free_p (regno, reload_opnum[r], 5509 reload_when_needed[r]) 5510 && ! TEST_HARD_REG_BIT (chain->counted_for_nongroups, 5511 regno))) 5512 break; 5513 nr--; 5514 } 5515 if (nr == 1) 5516 break; 5517 } 5518 } 5519 5520 /* If we found something on pass 1, omit pass 2. */ 5521 if (count < n_spills) 5522 break; 5523 } 5524 5525 /* We should have found a spill register by now. */ 5526 if (count == n_spills) 5527 { 5528 if (noerror) 5529 return 0; 5530 goto failure; 5531 } 5532 5533 /* I is the index in SPILL_REG_RTX of the reload register we are to 5534 allocate. Get an rtx for it and find its register number. */ 5535 5536 new = spill_reg_rtx[i]; 5537 5538 if (new == 0 || GET_MODE (new) != reload_mode[r]) 5539 spill_reg_rtx[i] = new 5540 = gen_rtx_REG (reload_mode[r], spill_regs[i]); 5541 5542 regno = true_regnum (new); 5543 5544 /* Detect when the reload reg can't hold the reload mode. 5545 This used to be one `if', but Sequent compiler can't handle that. */ 5546 if (HARD_REGNO_MODE_OK (regno, reload_mode[r])) 5547 { 5548 enum machine_mode test_mode = VOIDmode; 5549 if (reload_in[r]) 5550 test_mode = GET_MODE (reload_in[r]); 5551 /* If reload_in[r] has VOIDmode, it means we will load it 5552 in whatever mode the reload reg has: to wit, reload_mode[r]. 5553 We have already tested that for validity. */ 5554 /* Aside from that, we need to test that the expressions 5555 to reload from or into have modes which are valid for this 5556 reload register. Otherwise the reload insns would be invalid. */ 5557 if (! (reload_in[r] != 0 && test_mode != VOIDmode 5558 && ! HARD_REGNO_MODE_OK (regno, test_mode))) 5559 if (! (reload_out[r] != 0 5560 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r])))) 5561 { 5562 /* The reg is OK. */ 5563 last_spill_reg = i; 5564 5565 /* Mark as in use for this insn the reload regs we use 5566 for this. */ 5567 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r], 5568 reload_when_needed[r], reload_mode[r]); 5569 5570 reload_reg_rtx[r] = new; 5571 reload_spill_index[r] = spill_regs[i]; 5572 return 1; 5573 } 5574 } 5575 5576 /* The reg is not OK. */ 5577 if (noerror) 5578 return 0; 5579 5580 failure: 5581 if (asm_noperands (PATTERN (insn)) < 0) 5582 /* It's the compiler's fault. */ 5583 fatal_insn ("Could not find a spill register", insn); 5584 5585 /* It's the user's fault; the operand's mode and constraint 5586 don't match. Disable this reload so we don't crash in final. */ 5587 error_for_asm (insn, 5588 "`asm' operand constraint incompatible with operand size"); 5589 reload_in[r] = 0; 5590 reload_out[r] = 0; 5591 reload_reg_rtx[r] = 0; 5592 reload_optional[r] = 1; 5593 reload_secondary_p[r] = 1; 5594 5595 return 1; 5596} 5597 5598/* Assign hard reg targets for the pseudo-registers we must reload 5599 into hard regs for this insn. 5600 Also output the instructions to copy them in and out of the hard regs. 5601 5602 For machines with register classes, we are responsible for 5603 finding a reload reg in the proper class. */ 5604 5605static void 5606choose_reload_regs (chain) 5607 struct insn_chain *chain; 5608{ 5609 rtx insn = chain->insn; 5610 register int i, j; 5611 int max_group_size = 1; 5612 enum reg_class group_class = NO_REGS; 5613 int inheritance; 5614 int pass; 5615 5616 rtx save_reload_reg_rtx[MAX_RELOADS]; 5617 char save_reload_inherited[MAX_RELOADS]; 5618 rtx save_reload_inheritance_insn[MAX_RELOADS]; 5619 rtx save_reload_override_in[MAX_RELOADS]; 5620 int save_reload_spill_index[MAX_RELOADS]; 5621 HARD_REG_SET save_reload_reg_used; 5622 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; 5623 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; 5624 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; 5625 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; 5626 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS]; 5627 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS]; 5628 HARD_REG_SET save_reload_reg_used_in_op_addr; 5629 HARD_REG_SET save_reload_reg_used_in_op_addr_reload; 5630 HARD_REG_SET save_reload_reg_used_in_insn; 5631 HARD_REG_SET save_reload_reg_used_in_other_addr; 5632 HARD_REG_SET save_reload_reg_used_at_all; 5633 5634 bzero (reload_inherited, MAX_RELOADS); 5635 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx)); 5636 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx)); 5637 5638 CLEAR_HARD_REG_SET (reload_reg_used); 5639 CLEAR_HARD_REG_SET (reload_reg_used_at_all); 5640 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); 5641 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); 5642 CLEAR_HARD_REG_SET (reload_reg_used_in_insn); 5643 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); 5644 5645 CLEAR_HARD_REG_SET (reg_used_in_insn); 5646 { 5647 HARD_REG_SET tmp; 5648 REG_SET_TO_HARD_REG_SET (tmp, chain->live_before); 5649 IOR_HARD_REG_SET (reg_used_in_insn, tmp); 5650 REG_SET_TO_HARD_REG_SET (tmp, chain->live_after); 5651 IOR_HARD_REG_SET (reg_used_in_insn, tmp); 5652 compute_use_by_pseudos (®_used_in_insn, chain->live_before); 5653 compute_use_by_pseudos (®_used_in_insn, chain->live_after); 5654 } 5655 for (i = 0; i < reload_n_operands; i++) 5656 { 5657 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); 5658 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); 5659 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); 5660 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); 5661 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); 5662 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); 5663 } 5664 5665 IOR_COMPL_HARD_REG_SET (reload_reg_used, chain->used_spill_regs); 5666 5667#if 0 /* Not needed, now that we can always retry without inheritance. */ 5668 /* See if we have more mandatory reloads than spill regs. 5669 If so, then we cannot risk optimizations that could prevent 5670 reloads from sharing one spill register. 5671 5672 Since we will try finding a better register than reload_reg_rtx 5673 unless it is equal to reload_in or reload_out, count such reloads. */ 5674 5675 { 5676 int tem = 0; 5677 for (j = 0; j < n_reloads; j++) 5678 if (! reload_optional[j] 5679 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j]) 5680 && (reload_reg_rtx[j] == 0 5681 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j]) 5682 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j])))) 5683 tem++; 5684 if (tem > n_spills) 5685 must_reuse = 1; 5686 } 5687#endif 5688 5689 /* In order to be certain of getting the registers we need, 5690 we must sort the reloads into order of increasing register class. 5691 Then our grabbing of reload registers will parallel the process 5692 that provided the reload registers. 5693 5694 Also note whether any of the reloads wants a consecutive group of regs. 5695 If so, record the maximum size of the group desired and what 5696 register class contains all the groups needed by this insn. */ 5697 5698 for (j = 0; j < n_reloads; j++) 5699 { 5700 reload_order[j] = j; 5701 reload_spill_index[j] = -1; 5702 5703 reload_mode[j] 5704 = (reload_inmode[j] == VOIDmode 5705 || (GET_MODE_SIZE (reload_outmode[j]) 5706 > GET_MODE_SIZE (reload_inmode[j]))) 5707 ? reload_outmode[j] : reload_inmode[j]; 5708 5709 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]); 5710 5711 if (reload_nregs[j] > 1) 5712 { 5713 max_group_size = MAX (reload_nregs[j], max_group_size); 5714 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class]; 5715 } 5716 5717 /* If we have already decided to use a certain register, 5718 don't use it in another way. */ 5719 if (reload_reg_rtx[j]) 5720 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j], 5721 reload_when_needed[j], reload_mode[j]); 5722 } 5723 5724 if (n_reloads > 1) 5725 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); 5726 5727 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx, 5728 sizeof reload_reg_rtx); 5729 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited); 5730 bcopy ((char *) reload_inheritance_insn, 5731 (char *) save_reload_inheritance_insn, 5732 sizeof reload_inheritance_insn); 5733 bcopy ((char *) reload_override_in, (char *) save_reload_override_in, 5734 sizeof reload_override_in); 5735 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index, 5736 sizeof reload_spill_index); 5737 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used); 5738 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all); 5739 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr, 5740 reload_reg_used_in_op_addr); 5741 5742 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload, 5743 reload_reg_used_in_op_addr_reload); 5744 5745 COPY_HARD_REG_SET (save_reload_reg_used_in_insn, 5746 reload_reg_used_in_insn); 5747 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr, 5748 reload_reg_used_in_other_addr); 5749 5750 for (i = 0; i < reload_n_operands; i++) 5751 { 5752 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i], 5753 reload_reg_used_in_output[i]); 5754 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i], 5755 reload_reg_used_in_input[i]); 5756 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i], 5757 reload_reg_used_in_input_addr[i]); 5758 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i], 5759 reload_reg_used_in_inpaddr_addr[i]); 5760 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i], 5761 reload_reg_used_in_output_addr[i]); 5762 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i], 5763 reload_reg_used_in_outaddr_addr[i]); 5764 } 5765 5766 /* If -O, try first with inheritance, then turning it off. 5767 If not -O, don't do inheritance. 5768 Using inheritance when not optimizing leads to paradoxes 5769 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves 5770 because one side of the comparison might be inherited. */ 5771 5772 for (inheritance = optimize > 0; inheritance >= 0; inheritance--) 5773 { 5774 /* Process the reloads in order of preference just found. 5775 Beyond this point, subregs can be found in reload_reg_rtx. 5776 5777 This used to look for an existing reloaded home for all 5778 of the reloads, and only then perform any new reloads. 5779 But that could lose if the reloads were done out of reg-class order 5780 because a later reload with a looser constraint might have an old 5781 home in a register needed by an earlier reload with a tighter constraint. 5782 5783 To solve this, we make two passes over the reloads, in the order 5784 described above. In the first pass we try to inherit a reload 5785 from a previous insn. If there is a later reload that needs a 5786 class that is a proper subset of the class being processed, we must 5787 also allocate a spill register during the first pass. 5788 5789 Then make a second pass over the reloads to allocate any reloads 5790 that haven't been given registers yet. */ 5791 5792 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); 5793 5794 for (j = 0; j < n_reloads; j++) 5795 { 5796 register int r = reload_order[j]; 5797 rtx search_equiv = NULL_RTX; 5798 5799 /* Ignore reloads that got marked inoperative. */ 5800 if (reload_out[r] == 0 && reload_in[r] == 0 5801 && ! reload_secondary_p[r]) 5802 continue; 5803 5804 /* If find_reloads chose to use reload_in or reload_out as a reload 5805 register, we don't need to chose one. Otherwise, try even if it 5806 found one since we might save an insn if we find the value lying 5807 around. 5808 Try also when reload_in is a pseudo without a hard reg. */ 5809 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0 5810 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r]) 5811 || (rtx_equal_p (reload_out[r], reload_reg_rtx[r]) 5812 && GET_CODE (reload_in[r]) != MEM 5813 && true_regnum (reload_in[r]) < FIRST_PSEUDO_REGISTER))) 5814 continue; 5815 5816#if 0 /* No longer needed for correct operation. 5817 It might give better code, or might not; worth an experiment? */ 5818 /* If this is an optional reload, we can't inherit from earlier insns 5819 until we are sure that any non-optional reloads have been allocated. 5820 The following code takes advantage of the fact that optional reloads 5821 are at the end of reload_order. */ 5822 if (reload_optional[r] != 0) 5823 for (i = 0; i < j; i++) 5824 if ((reload_out[reload_order[i]] != 0 5825 || reload_in[reload_order[i]] != 0 5826 || reload_secondary_p[reload_order[i]]) 5827 && ! reload_optional[reload_order[i]] 5828 && reload_reg_rtx[reload_order[i]] == 0) 5829 allocate_reload_reg (chain, reload_order[i], 0, inheritance); 5830#endif 5831 5832 /* First see if this pseudo is already available as reloaded 5833 for a previous insn. We cannot try to inherit for reloads 5834 that are smaller than the maximum number of registers needed 5835 for groups unless the register we would allocate cannot be used 5836 for the groups. 5837 5838 We could check here to see if this is a secondary reload for 5839 an object that is already in a register of the desired class. 5840 This would avoid the need for the secondary reload register. 5841 But this is complex because we can't easily determine what 5842 objects might want to be loaded via this reload. So let a 5843 register be allocated here. In `emit_reload_insns' we suppress 5844 one of the loads in the case described above. */ 5845 5846 if (inheritance) 5847 { 5848 int word = 0; 5849 register int regno = -1; 5850 enum machine_mode mode; 5851 5852 if (reload_in[r] == 0) 5853 ; 5854 else if (GET_CODE (reload_in[r]) == REG) 5855 { 5856 regno = REGNO (reload_in[r]); 5857 mode = GET_MODE (reload_in[r]); 5858 } 5859 else if (GET_CODE (reload_in_reg[r]) == REG) 5860 { 5861 regno = REGNO (reload_in_reg[r]); 5862 mode = GET_MODE (reload_in_reg[r]); 5863 } 5864 else if (GET_CODE (reload_in_reg[r]) == SUBREG 5865 && GET_CODE (SUBREG_REG (reload_in_reg[r])) == REG) 5866 { 5867 word = SUBREG_WORD (reload_in_reg[r]); 5868 regno = REGNO (SUBREG_REG (reload_in_reg[r])); 5869 if (regno < FIRST_PSEUDO_REGISTER) 5870 regno += word; 5871 mode = GET_MODE (reload_in_reg[r]); 5872 } 5873#ifdef AUTO_INC_DEC 5874 else if ((GET_CODE (reload_in_reg[r]) == PRE_INC 5875 || GET_CODE (reload_in_reg[r]) == PRE_DEC 5876 || GET_CODE (reload_in_reg[r]) == POST_INC 5877 || GET_CODE (reload_in_reg[r]) == POST_DEC) 5878 && GET_CODE (XEXP (reload_in_reg[r], 0)) == REG) 5879 { 5880 regno = REGNO (XEXP (reload_in_reg[r], 0)); 5881 mode = GET_MODE (XEXP (reload_in_reg[r], 0)); 5882 reload_out[r] = reload_in[r]; 5883 } 5884#endif 5885#if 0 5886 /* This won't work, since REGNO can be a pseudo reg number. 5887 Also, it takes much more hair to keep track of all the things 5888 that can invalidate an inherited reload of part of a pseudoreg. */ 5889 else if (GET_CODE (reload_in[r]) == SUBREG 5890 && GET_CODE (SUBREG_REG (reload_in[r])) == REG) 5891 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]); 5892#endif 5893 5894 if (regno >= 0 && reg_last_reload_reg[regno] != 0) 5895 { 5896 enum reg_class class = reload_reg_class[r], last_class; 5897 rtx last_reg = reg_last_reload_reg[regno]; 5898 5899 i = REGNO (last_reg) + word; 5900 last_class = REGNO_REG_CLASS (i); 5901 if ((GET_MODE_SIZE (GET_MODE (last_reg)) 5902 >= GET_MODE_SIZE (mode) + word * UNITS_PER_WORD) 5903 && reg_reloaded_contents[i] == regno 5904 && TEST_HARD_REG_BIT (reg_reloaded_valid, i) 5905 && HARD_REGNO_MODE_OK (i, reload_mode[r]) 5906 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) 5907 /* Even if we can't use this register as a reload 5908 register, we might use it for reload_override_in, 5909 if copying it to the desired class is cheap 5910 enough. */ 5911 || ((REGISTER_MOVE_COST (last_class, class) 5912 < MEMORY_MOVE_COST (mode, class, 1)) 5913#ifdef SECONDARY_INPUT_RELOAD_CLASS 5914 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode, 5915 last_reg) 5916 == NO_REGS) 5917#endif 5918#ifdef SECONDARY_MEMORY_NEEDED 5919 && ! SECONDARY_MEMORY_NEEDED (last_class, class, 5920 mode) 5921#endif 5922 )) 5923 5924 && (reload_nregs[r] == max_group_size 5925 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], 5926 i)) 5927 && reload_reg_free_for_value_p (i, reload_opnum[r], 5928 reload_when_needed[r], 5929 reload_in[r], 5930 const0_rtx, r, 1)) 5931 { 5932 /* If a group is needed, verify that all the subsequent 5933 registers still have their values intact. */ 5934 int nr 5935 = HARD_REGNO_NREGS (i, reload_mode[r]); 5936 int k; 5937 5938 for (k = 1; k < nr; k++) 5939 if (reg_reloaded_contents[i + k] != regno 5940 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) 5941 break; 5942 5943 if (k == nr) 5944 { 5945 int i1; 5946 5947 last_reg = (GET_MODE (last_reg) == mode 5948 ? last_reg : gen_rtx_REG (mode, i)); 5949 5950 /* We found a register that contains the 5951 value we need. If this register is the 5952 same as an `earlyclobber' operand of the 5953 current insn, just mark it as a place to 5954 reload from since we can't use it as the 5955 reload register itself. */ 5956 5957 for (i1 = 0; i1 < n_earlyclobbers; i1++) 5958 if (reg_overlap_mentioned_for_reload_p 5959 (reg_last_reload_reg[regno], 5960 reload_earlyclobbers[i1])) 5961 break; 5962 5963 if (i1 != n_earlyclobbers 5964 || ! (reload_reg_free_for_value_p 5965 (i, reload_opnum[r], reload_when_needed[r], 5966 reload_in[r], reload_out[r], r, 1)) 5967 /* Don't use it if we'd clobber a pseudo reg. */ 5968 || (TEST_HARD_REG_BIT (reg_used_in_insn, i) 5969 && reload_out[r] 5970 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) 5971 /* Don't clobber the frame pointer. */ 5972 || (i == HARD_FRAME_POINTER_REGNUM 5973 && reload_out[r]) 5974 /* Don't really use the inherited spill reg 5975 if we need it wider than we've got it. */ 5976 || (GET_MODE_SIZE (reload_mode[r]) 5977 > GET_MODE_SIZE (mode)) 5978 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], 5979 i) 5980 5981 /* If find_reloads chose reload_out as reload 5982 register, stay with it - that leaves the 5983 inherited register for subsequent reloads. */ 5984 || (reload_out[r] && reload_reg_rtx[r] 5985 && rtx_equal_p (reload_out[r], 5986 reload_reg_rtx[r]))) 5987 { 5988 reload_override_in[r] = last_reg; 5989 reload_inheritance_insn[r] 5990 = reg_reloaded_insn[i]; 5991 } 5992 else 5993 { 5994 int k; 5995 /* We can use this as a reload reg. */ 5996 /* Mark the register as in use for this part of 5997 the insn. */ 5998 mark_reload_reg_in_use (i, 5999 reload_opnum[r], 6000 reload_when_needed[r], 6001 reload_mode[r]); 6002 reload_reg_rtx[r] = last_reg; 6003 reload_inherited[r] = 1; 6004 reload_inheritance_insn[r] 6005 = reg_reloaded_insn[i]; 6006 reload_spill_index[r] = i; 6007 for (k = 0; k < nr; k++) 6008 SET_HARD_REG_BIT (reload_reg_used_for_inherit, 6009 i + k); 6010 } 6011 } 6012 } 6013 } 6014 } 6015 6016 /* Here's another way to see if the value is already lying around. */ 6017 if (inheritance 6018 && reload_in[r] != 0 6019 && ! reload_inherited[r] 6020 && reload_out[r] == 0 6021 && (CONSTANT_P (reload_in[r]) 6022 || GET_CODE (reload_in[r]) == PLUS 6023 || GET_CODE (reload_in[r]) == REG 6024 || GET_CODE (reload_in[r]) == MEM) 6025 && (reload_nregs[r] == max_group_size 6026 || ! reg_classes_intersect_p (reload_reg_class[r], group_class))) 6027 search_equiv = reload_in[r]; 6028 /* If this is an output reload from a simple move insn, look 6029 if an equivalence for the input is available. */ 6030 else if (inheritance && reload_in[r] == 0 && reload_out[r] != 0) 6031 { 6032 rtx set = single_set (insn); 6033 6034 if (set 6035 && rtx_equal_p (reload_out[r], SET_DEST (set)) 6036 && CONSTANT_P (SET_SRC (set))) 6037 search_equiv = SET_SRC (set); 6038 } 6039 6040 if (search_equiv) 6041 { 6042 register rtx equiv 6043 = find_equiv_reg (search_equiv, insn, reload_reg_class[r], 6044 -1, NULL_PTR, 0, reload_mode[r]); 6045 int regno; 6046 6047 if (equiv != 0) 6048 { 6049 if (GET_CODE (equiv) == REG) 6050 regno = REGNO (equiv); 6051 else if (GET_CODE (equiv) == SUBREG) 6052 { 6053 /* This must be a SUBREG of a hard register. 6054 Make a new REG since this might be used in an 6055 address and not all machines support SUBREGs 6056 there. */ 6057 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv); 6058 equiv = gen_rtx_REG (reload_mode[r], regno); 6059 } 6060 else 6061 abort (); 6062 } 6063 6064 /* If we found a spill reg, reject it unless it is free 6065 and of the desired class. */ 6066 if (equiv != 0 6067 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno) 6068 && ! reload_reg_free_for_value_p (regno, reload_opnum[r], 6069 reload_when_needed[r], 6070 reload_in[r], 6071 reload_out[r], r, 1)) 6072 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], 6073 regno))) 6074 equiv = 0; 6075 6076 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r])) 6077 equiv = 0; 6078 6079 /* We found a register that contains the value we need. 6080 If this register is the same as an `earlyclobber' operand 6081 of the current insn, just mark it as a place to reload from 6082 since we can't use it as the reload register itself. */ 6083 6084 if (equiv != 0) 6085 for (i = 0; i < n_earlyclobbers; i++) 6086 if (reg_overlap_mentioned_for_reload_p (equiv, 6087 reload_earlyclobbers[i])) 6088 { 6089 reload_override_in[r] = equiv; 6090 equiv = 0; 6091 break; 6092 } 6093 6094 /* If the equiv register we have found is explicitly clobbered 6095 in the current insn, it depends on the reload type if we 6096 can use it, use it for reload_override_in, or not at all. 6097 In particular, we then can't use EQUIV for a 6098 RELOAD_FOR_OUTPUT_ADDRESS reload. */ 6099 6100 if (equiv != 0 && regno_clobbered_p (regno, insn)) 6101 { 6102 switch (reload_when_needed[r]) 6103 { 6104 case RELOAD_FOR_OTHER_ADDRESS: 6105 case RELOAD_FOR_INPADDR_ADDRESS: 6106 case RELOAD_FOR_INPUT_ADDRESS: 6107 case RELOAD_FOR_OPADDR_ADDR: 6108 break; 6109 case RELOAD_OTHER: 6110 case RELOAD_FOR_INPUT: 6111 case RELOAD_FOR_OPERAND_ADDRESS: 6112 reload_override_in[r] = equiv; 6113 /* Fall through. */ 6114 default: 6115 equiv = 0; 6116 break; 6117 } 6118 } 6119 6120 /* If we found an equivalent reg, say no code need be generated 6121 to load it, and use it as our reload reg. */ 6122 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM) 6123 { 6124 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]); 6125 int k; 6126 reload_reg_rtx[r] = equiv; 6127 reload_inherited[r] = 1; 6128 6129 /* If reg_reloaded_valid is not set for this register, 6130 there might be a stale spill_reg_store lying around. 6131 We must clear it, since otherwise emit_reload_insns 6132 might delete the store. */ 6133 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) 6134 spill_reg_store[regno] = NULL_RTX; 6135 /* If any of the hard registers in EQUIV are spill 6136 registers, mark them as in use for this insn. */ 6137 for (k = 0; k < nr; k++) 6138 { 6139 i = spill_reg_order[regno + k]; 6140 if (i >= 0) 6141 { 6142 mark_reload_reg_in_use (regno, reload_opnum[r], 6143 reload_when_needed[r], 6144 reload_mode[r]); 6145 SET_HARD_REG_BIT (reload_reg_used_for_inherit, 6146 regno + k); 6147 } 6148 } 6149 } 6150 } 6151 6152 /* If we found a register to use already, or if this is an optional 6153 reload, we are done. */ 6154 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0) 6155 continue; 6156 6157#if 0 /* No longer needed for correct operation. Might or might not 6158 give better code on the average. Want to experiment? */ 6159 6160 /* See if there is a later reload that has a class different from our 6161 class that intersects our class or that requires less register 6162 than our reload. If so, we must allocate a register to this 6163 reload now, since that reload might inherit a previous reload 6164 and take the only available register in our class. Don't do this 6165 for optional reloads since they will force all previous reloads 6166 to be allocated. Also don't do this for reloads that have been 6167 turned off. */ 6168 6169 for (i = j + 1; i < n_reloads; i++) 6170 { 6171 int s = reload_order[i]; 6172 6173 if ((reload_in[s] == 0 && reload_out[s] == 0 6174 && ! reload_secondary_p[s]) 6175 || reload_optional[s]) 6176 continue; 6177 6178 if ((reload_reg_class[s] != reload_reg_class[r] 6179 && reg_classes_intersect_p (reload_reg_class[r], 6180 reload_reg_class[s])) 6181 || reload_nregs[s] < reload_nregs[r]) 6182 break; 6183 } 6184 6185 if (i == n_reloads) 6186 continue; 6187 6188 allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance); 6189#endif 6190 } 6191 6192 /* Now allocate reload registers for anything non-optional that 6193 didn't get one yet. */ 6194 for (j = 0; j < n_reloads; j++) 6195 { 6196 register int r = reload_order[j]; 6197 6198 /* Ignore reloads that got marked inoperative. */ 6199 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r]) 6200 continue; 6201 6202 /* Skip reloads that already have a register allocated or are 6203 optional. */ 6204 if (reload_reg_rtx[r] != 0 || reload_optional[r]) 6205 continue; 6206 6207 if (! allocate_reload_reg (chain, r, j == n_reloads - 1, inheritance)) 6208 break; 6209 } 6210 6211 /* If that loop got all the way, we have won. */ 6212 if (j == n_reloads) 6213 break; 6214 6215 /* Loop around and try without any inheritance. */ 6216 /* First undo everything done by the failed attempt 6217 to allocate with inheritance. */ 6218 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx, 6219 sizeof reload_reg_rtx); 6220 bcopy ((char *) save_reload_inherited, (char *) reload_inherited, 6221 sizeof reload_inherited); 6222 bcopy ((char *) save_reload_inheritance_insn, 6223 (char *) reload_inheritance_insn, 6224 sizeof reload_inheritance_insn); 6225 bcopy ((char *) save_reload_override_in, (char *) reload_override_in, 6226 sizeof reload_override_in); 6227 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index, 6228 sizeof reload_spill_index); 6229 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used); 6230 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all); 6231 COPY_HARD_REG_SET (reload_reg_used_in_op_addr, 6232 save_reload_reg_used_in_op_addr); 6233 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload, 6234 save_reload_reg_used_in_op_addr_reload); 6235 COPY_HARD_REG_SET (reload_reg_used_in_insn, 6236 save_reload_reg_used_in_insn); 6237 COPY_HARD_REG_SET (reload_reg_used_in_other_addr, 6238 save_reload_reg_used_in_other_addr); 6239 6240 for (i = 0; i < reload_n_operands; i++) 6241 { 6242 COPY_HARD_REG_SET (reload_reg_used_in_input[i], 6243 save_reload_reg_used_in_input[i]); 6244 COPY_HARD_REG_SET (reload_reg_used_in_output[i], 6245 save_reload_reg_used_in_output[i]); 6246 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i], 6247 save_reload_reg_used_in_input_addr[i]); 6248 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i], 6249 save_reload_reg_used_in_inpaddr_addr[i]); 6250 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i], 6251 save_reload_reg_used_in_output_addr[i]); 6252 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i], 6253 save_reload_reg_used_in_outaddr_addr[i]); 6254 } 6255 } 6256 6257 /* If we thought we could inherit a reload, because it seemed that 6258 nothing else wanted the same reload register earlier in the insn, 6259 verify that assumption, now that all reloads have been assigned. 6260 Likewise for reloads where reload_override_in has been set. */ 6261 6262 /* If doing expensive optimizations, do one preliminary pass that doesn't 6263 cancel any inheritance, but removes reloads that have been needed only 6264 for reloads that we know can be inherited. */ 6265 for (pass = flag_expensive_optimizations; pass >= 0; pass--) 6266 { 6267 for (j = 0; j < n_reloads; j++) 6268 { 6269 register int r = reload_order[j]; 6270 rtx check_reg; 6271 if (reload_inherited[r] && reload_reg_rtx[r]) 6272 check_reg = reload_reg_rtx[r]; 6273 else if (reload_override_in[r] 6274 && (GET_CODE (reload_override_in[r]) == REG 6275 || GET_CODE (reload_override_in[r]) == SUBREG)) 6276 check_reg = reload_override_in[r]; 6277 else 6278 continue; 6279 if (! reload_reg_free_for_value_p (true_regnum (check_reg), 6280 reload_opnum[r], 6281 reload_when_needed[r], 6282 reload_in[r], 6283 (reload_inherited[r] 6284 ? reload_out[r] : const0_rtx), 6285 r, 1)) 6286 { 6287 if (pass) 6288 continue; 6289 reload_inherited[r] = 0; 6290 reload_override_in[r] = 0; 6291 } 6292 /* If we can inherit a RELOAD_FOR_INPUT, or can use a 6293 reload_override_in, then we do not need its related 6294 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; 6295 likewise for other reload types. 6296 We handle this by removing a reload when its only replacement 6297 is mentioned in reload_in of the reload we are going to inherit. 6298 A special case are auto_inc expressions; even if the input is 6299 inherited, we still need the address for the output. We can 6300 recognize them because they have RELOAD_OUT set but not 6301 RELOAD_OUT_REG. 6302 If we suceeded removing some reload and we are doing a preliminary 6303 pass just to remove such reloads, make another pass, since the 6304 removal of one reload might allow us to inherit another one. */ 6305 else if ((! reload_out[r] || reload_out_reg[r]) 6306 && reload_in[r] 6307 && remove_address_replacements (reload_in[r]) && pass) 6308 pass = 2; 6309 } 6310 } 6311 6312 /* Now that reload_override_in is known valid, 6313 actually override reload_in. */ 6314 for (j = 0; j < n_reloads; j++) 6315 if (reload_override_in[j]) 6316 reload_in[j] = reload_override_in[j]; 6317 6318 /* If this reload won't be done because it has been cancelled or is 6319 optional and not inherited, clear reload_reg_rtx so other 6320 routines (such as subst_reloads) don't get confused. */ 6321 for (j = 0; j < n_reloads; j++) 6322 if (reload_reg_rtx[j] != 0 6323 && ((reload_optional[j] && ! reload_inherited[j]) 6324 || (reload_in[j] == 0 && reload_out[j] == 0 6325 && ! reload_secondary_p[j]))) 6326 { 6327 int regno = true_regnum (reload_reg_rtx[j]); 6328 6329 if (spill_reg_order[regno] >= 0) 6330 clear_reload_reg_in_use (regno, reload_opnum[j], 6331 reload_when_needed[j], reload_mode[j]); 6332 reload_reg_rtx[j] = 0; 6333 } 6334 6335 /* Record which pseudos and which spill regs have output reloads. */ 6336 for (j = 0; j < n_reloads; j++) 6337 { 6338 register int r = reload_order[j]; 6339 6340 i = reload_spill_index[r]; 6341 6342 /* I is nonneg if this reload uses a register. 6343 If reload_reg_rtx[r] is 0, this is an optional reload 6344 that we opted to ignore. */ 6345 if (reload_out_reg[r] != 0 && GET_CODE (reload_out_reg[r]) == REG 6346 && reload_reg_rtx[r] != 0) 6347 { 6348 register int nregno = REGNO (reload_out_reg[r]); 6349 int nr = 1; 6350 6351 if (nregno < FIRST_PSEUDO_REGISTER) 6352 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]); 6353 6354 while (--nr >= 0) 6355 reg_has_output_reload[nregno + nr] = 1; 6356 6357 if (i >= 0) 6358 { 6359 nr = HARD_REGNO_NREGS (i, reload_mode[r]); 6360 while (--nr >= 0) 6361 SET_HARD_REG_BIT (reg_is_output_reload, i + nr); 6362 } 6363 6364 if (reload_when_needed[r] != RELOAD_OTHER 6365 && reload_when_needed[r] != RELOAD_FOR_OUTPUT 6366 && reload_when_needed[r] != RELOAD_FOR_INSN) 6367 abort (); 6368 } 6369 } 6370} 6371 6372/* Deallocate the reload register for reload R. This is called from 6373 remove_address_replacements. */ 6374void 6375deallocate_reload_reg (r) 6376 int r; 6377{ 6378 int regno; 6379 6380 if (! reload_reg_rtx[r]) 6381 return; 6382 regno = true_regnum (reload_reg_rtx[r]); 6383 reload_reg_rtx[r] = 0; 6384 if (spill_reg_order[regno] >= 0) 6385 clear_reload_reg_in_use (regno, reload_opnum[r], reload_when_needed[r], 6386 reload_mode[r]); 6387 reload_spill_index[r] = -1; 6388} 6389 6390/* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two 6391 reloads of the same item for fear that we might not have enough reload 6392 registers. However, normally they will get the same reload register 6393 and hence actually need not be loaded twice. 6394 6395 Here we check for the most common case of this phenomenon: when we have 6396 a number of reloads for the same object, each of which were allocated 6397 the same reload_reg_rtx, that reload_reg_rtx is not used for any other 6398 reload, and is not modified in the insn itself. If we find such, 6399 merge all the reloads and set the resulting reload to RELOAD_OTHER. 6400 This will not increase the number of spill registers needed and will 6401 prevent redundant code. */ 6402 6403static void 6404merge_assigned_reloads (insn) 6405 rtx insn; 6406{ 6407 int i, j; 6408 6409 /* Scan all the reloads looking for ones that only load values and 6410 are not already RELOAD_OTHER and ones whose reload_reg_rtx are 6411 assigned and not modified by INSN. */ 6412 6413 for (i = 0; i < n_reloads; i++) 6414 { 6415 int conflicting_input = 0; 6416 int max_input_address_opnum = -1; 6417 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; 6418 6419 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER 6420 || reload_out[i] != 0 || reload_reg_rtx[i] == 0 6421 || reg_set_p (reload_reg_rtx[i], insn)) 6422 continue; 6423 6424 /* Look at all other reloads. Ensure that the only use of this 6425 reload_reg_rtx is in a reload that just loads the same value 6426 as we do. Note that any secondary reloads must be of the identical 6427 class since the values, modes, and result registers are the 6428 same, so we need not do anything with any secondary reloads. */ 6429 6430 for (j = 0; j < n_reloads; j++) 6431 { 6432 if (i == j || reload_reg_rtx[j] == 0 6433 || ! reg_overlap_mentioned_p (reload_reg_rtx[j], 6434 reload_reg_rtx[i])) 6435 continue; 6436 6437 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS 6438 && reload_opnum[j] > max_input_address_opnum) 6439 max_input_address_opnum = reload_opnum[j]; 6440 6441 /* If the reload regs aren't exactly the same (e.g, different modes) 6442 or if the values are different, we can't merge this reload. 6443 But if it is an input reload, we might still merge 6444 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ 6445 6446 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]) 6447 || reload_out[j] != 0 || reload_in[j] == 0 6448 || ! rtx_equal_p (reload_in[i], reload_in[j])) 6449 { 6450 if (reload_when_needed[j] != RELOAD_FOR_INPUT 6451 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS 6452 || reload_opnum[i] > reload_opnum[j]) 6453 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS)) 6454 break; 6455 conflicting_input = 1; 6456 if (min_conflicting_input_opnum > reload_opnum[j]) 6457 min_conflicting_input_opnum = reload_opnum[j]; 6458 } 6459 } 6460 6461 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if 6462 we, in fact, found any matching reloads. */ 6463 6464 if (j == n_reloads 6465 && max_input_address_opnum <= min_conflicting_input_opnum) 6466 { 6467 for (j = 0; j < n_reloads; j++) 6468 if (i != j && reload_reg_rtx[j] != 0 6469 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]) 6470 && (! conflicting_input 6471 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS 6472 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS)) 6473 { 6474 reload_when_needed[i] = RELOAD_OTHER; 6475 reload_in[j] = 0; 6476 reload_spill_index[j] = -1; 6477 transfer_replacements (i, j); 6478 } 6479 6480 /* If this is now RELOAD_OTHER, look for any reloads that load 6481 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS 6482 if they were for inputs, RELOAD_OTHER for outputs. Note that 6483 this test is equivalent to looking for reloads for this operand 6484 number. */ 6485 6486 if (reload_when_needed[i] == RELOAD_OTHER) 6487 for (j = 0; j < n_reloads; j++) 6488 if (reload_in[j] != 0 6489 && reload_when_needed[i] != RELOAD_OTHER 6490 && reg_overlap_mentioned_for_reload_p (reload_in[j], 6491 reload_in[i])) 6492 reload_when_needed[j] 6493 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS 6494 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS) 6495 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); 6496 } 6497 } 6498} 6499 6500 6501/* Output insns to reload values in and out of the chosen reload regs. */ 6502 6503static void 6504emit_reload_insns (chain) 6505 struct insn_chain *chain; 6506{ 6507 rtx insn = chain->insn; 6508 6509 register int j; 6510 rtx input_reload_insns[MAX_RECOG_OPERANDS]; 6511 rtx other_input_address_reload_insns = 0; 6512 rtx other_input_reload_insns = 0; 6513 rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; 6514 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; 6515 rtx output_reload_insns[MAX_RECOG_OPERANDS]; 6516 rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; 6517 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; 6518 rtx operand_reload_insns = 0; 6519 rtx other_operand_reload_insns = 0; 6520 rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; 6521 rtx following_insn = NEXT_INSN (insn); 6522 rtx before_insn = PREV_INSN (insn); 6523 int special; 6524 /* Values to be put in spill_reg_store are put here first. */ 6525 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; 6526 HARD_REG_SET reg_reloaded_died; 6527 6528 CLEAR_HARD_REG_SET (reg_reloaded_died); 6529 6530 for (j = 0; j < reload_n_operands; j++) 6531 input_reload_insns[j] = input_address_reload_insns[j] 6532 = inpaddr_address_reload_insns[j] 6533 = output_reload_insns[j] = output_address_reload_insns[j] 6534 = outaddr_address_reload_insns[j] 6535 = other_output_reload_insns[j] = 0; 6536 6537 /* Now output the instructions to copy the data into and out of the 6538 reload registers. Do these in the order that the reloads were reported, 6539 since reloads of base and index registers precede reloads of operands 6540 and the operands may need the base and index registers reloaded. */ 6541 6542 for (j = 0; j < n_reloads; j++) 6543 { 6544 register rtx old; 6545 rtx oldequiv_reg = 0; 6546 rtx this_reload_insn = 0; 6547 int expect_occurrences = 1; 6548 6549 if (reload_reg_rtx[j] 6550 && REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER) 6551 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = 0; 6552 6553 old = (reload_in[j] && GET_CODE (reload_in[j]) == MEM 6554 ? reload_in_reg[j] : reload_in[j]); 6555 6556 if (old != 0 6557 /* AUTO_INC reloads need to be handled even if inherited. We got an 6558 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ 6559 && (! reload_inherited[j] || (reload_out[j] && ! reload_out_reg[j])) 6560 && ! rtx_equal_p (reload_reg_rtx[j], old) 6561 && reload_reg_rtx[j] != 0) 6562 { 6563 register rtx reloadreg = reload_reg_rtx[j]; 6564 rtx oldequiv = 0; 6565 enum machine_mode mode; 6566 rtx *where; 6567 6568 /* Determine the mode to reload in. 6569 This is very tricky because we have three to choose from. 6570 There is the mode the insn operand wants (reload_inmode[J]). 6571 There is the mode of the reload register RELOADREG. 6572 There is the intrinsic mode of the operand, which we could find 6573 by stripping some SUBREGs. 6574 It turns out that RELOADREG's mode is irrelevant: 6575 we can change that arbitrarily. 6576 6577 Consider (SUBREG:SI foo:QI) as an operand that must be SImode; 6578 then the reload reg may not support QImode moves, so use SImode. 6579 If foo is in memory due to spilling a pseudo reg, this is safe, 6580 because the QImode value is in the least significant part of a 6581 slot big enough for a SImode. If foo is some other sort of 6582 memory reference, then it is impossible to reload this case, 6583 so previous passes had better make sure this never happens. 6584 6585 Then consider a one-word union which has SImode and one of its 6586 members is a float, being fetched as (SUBREG:SF union:SI). 6587 We must fetch that as SFmode because we could be loading into 6588 a float-only register. In this case OLD's mode is correct. 6589 6590 Consider an immediate integer: it has VOIDmode. Here we need 6591 to get a mode from something else. 6592 6593 In some cases, there is a fourth mode, the operand's 6594 containing mode. If the insn specifies a containing mode for 6595 this operand, it overrides all others. 6596 6597 I am not sure whether the algorithm here is always right, 6598 but it does the right things in those cases. */ 6599 6600 mode = GET_MODE (old); 6601 if (mode == VOIDmode) 6602 mode = reload_inmode[j]; 6603 6604#ifdef SECONDARY_INPUT_RELOAD_CLASS 6605 /* If we need a secondary register for this operation, see if 6606 the value is already in a register in that class. Don't 6607 do this if the secondary register will be used as a scratch 6608 register. */ 6609 6610 if (reload_secondary_in_reload[j] >= 0 6611 && reload_secondary_in_icode[j] == CODE_FOR_nothing 6612 && optimize) 6613 oldequiv 6614 = find_equiv_reg (old, insn, 6615 reload_reg_class[reload_secondary_in_reload[j]], 6616 -1, NULL_PTR, 0, mode); 6617#endif 6618 6619 /* If reloading from memory, see if there is a register 6620 that already holds the same value. If so, reload from there. 6621 We can pass 0 as the reload_reg_p argument because 6622 any other reload has either already been emitted, 6623 in which case find_equiv_reg will see the reload-insn, 6624 or has yet to be emitted, in which case it doesn't matter 6625 because we will use this equiv reg right away. */ 6626 6627 if (oldequiv == 0 && optimize 6628 && (GET_CODE (old) == MEM 6629 || (GET_CODE (old) == REG 6630 && REGNO (old) >= FIRST_PSEUDO_REGISTER 6631 && reg_renumber[REGNO (old)] < 0))) 6632 oldequiv = find_equiv_reg (old, insn, ALL_REGS, 6633 -1, NULL_PTR, 0, mode); 6634 6635 if (oldequiv) 6636 { 6637 int regno = true_regnum (oldequiv); 6638 6639 /* Don't use OLDEQUIV if any other reload changes it at an 6640 earlier stage of this insn or at this stage. */ 6641 if (! reload_reg_free_for_value_p (regno, reload_opnum[j], 6642 reload_when_needed[j], 6643 reload_in[j], const0_rtx, j, 6644 0)) 6645 oldequiv = 0; 6646 6647 /* If it is no cheaper to copy from OLDEQUIV into the 6648 reload register than it would be to move from memory, 6649 don't use it. Likewise, if we need a secondary register 6650 or memory. */ 6651 6652 if (oldequiv != 0 6653 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j] 6654 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno), 6655 reload_reg_class[j]) 6656 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1))) 6657#ifdef SECONDARY_INPUT_RELOAD_CLASS 6658 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j], 6659 mode, oldequiv) 6660 != NO_REGS) 6661#endif 6662#ifdef SECONDARY_MEMORY_NEEDED 6663 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), 6664 reload_reg_class[j], 6665 mode) 6666#endif 6667 )) 6668 oldequiv = 0; 6669 } 6670 6671 /* delete_output_reload is only invoked properly if old contains 6672 the original pseudo register. Since this is replaced with a 6673 hard reg when RELOAD_OVERRIDE_IN is set, see if we can 6674 find the pseudo in RELOAD_IN_REG. */ 6675 if (oldequiv == 0 6676 && reload_override_in[j] 6677 && GET_CODE (reload_in_reg[j]) == REG) 6678 { 6679 oldequiv = old; 6680 old = reload_in_reg[j]; 6681 } 6682 if (oldequiv == 0) 6683 oldequiv = old; 6684 else if (GET_CODE (oldequiv) == REG) 6685 oldequiv_reg = oldequiv; 6686 else if (GET_CODE (oldequiv) == SUBREG) 6687 oldequiv_reg = SUBREG_REG (oldequiv); 6688 6689 /* If we are reloading from a register that was recently stored in 6690 with an output-reload, see if we can prove there was 6691 actually no need to store the old value in it. */ 6692 6693 if (optimize && GET_CODE (oldequiv) == REG 6694 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER 6695 && spill_reg_store[REGNO (oldequiv)] 6696 && GET_CODE (old) == REG 6697 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) 6698 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], 6699 reload_out_reg[j]))) 6700 delete_output_reload (insn, j, REGNO (oldequiv)); 6701 6702 /* Encapsulate both RELOADREG and OLDEQUIV into that mode, 6703 then load RELOADREG from OLDEQUIV. Note that we cannot use 6704 gen_lowpart_common since it can do the wrong thing when 6705 RELOADREG has a multi-word mode. Note that RELOADREG 6706 must always be a REG here. */ 6707 6708 if (GET_MODE (reloadreg) != mode) 6709 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); 6710 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) 6711 oldequiv = SUBREG_REG (oldequiv); 6712 if (GET_MODE (oldequiv) != VOIDmode 6713 && mode != GET_MODE (oldequiv)) 6714 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0); 6715 6716 /* Switch to the right place to emit the reload insns. */ 6717 switch (reload_when_needed[j]) 6718 { 6719 case RELOAD_OTHER: 6720 where = &other_input_reload_insns; 6721 break; 6722 case RELOAD_FOR_INPUT: 6723 where = &input_reload_insns[reload_opnum[j]]; 6724 break; 6725 case RELOAD_FOR_INPUT_ADDRESS: 6726 where = &input_address_reload_insns[reload_opnum[j]]; 6727 break; 6728 case RELOAD_FOR_INPADDR_ADDRESS: 6729 where = &inpaddr_address_reload_insns[reload_opnum[j]]; 6730 break; 6731 case RELOAD_FOR_OUTPUT_ADDRESS: 6732 where = &output_address_reload_insns[reload_opnum[j]]; 6733 break; 6734 case RELOAD_FOR_OUTADDR_ADDRESS: 6735 where = &outaddr_address_reload_insns[reload_opnum[j]]; 6736 break; 6737 case RELOAD_FOR_OPERAND_ADDRESS: 6738 where = &operand_reload_insns; 6739 break; 6740 case RELOAD_FOR_OPADDR_ADDR: 6741 where = &other_operand_reload_insns; 6742 break; 6743 case RELOAD_FOR_OTHER_ADDRESS: 6744 where = &other_input_address_reload_insns; 6745 break; 6746 default: 6747 abort (); 6748 } 6749 6750 push_to_sequence (*where); 6751 special = 0; 6752 6753 /* Auto-increment addresses must be reloaded in a special way. */ 6754 if (reload_out[j] && ! reload_out_reg[j]) 6755 { 6756 /* We are not going to bother supporting the case where a 6757 incremented register can't be copied directly from 6758 OLDEQUIV since this seems highly unlikely. */ 6759 if (reload_secondary_in_reload[j] >= 0) 6760 abort (); 6761 6762 if (reload_inherited[j]) 6763 oldequiv = reloadreg; 6764 6765 old = XEXP (reload_in_reg[j], 0); 6766 6767 if (optimize && GET_CODE (oldequiv) == REG 6768 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER 6769 && spill_reg_store[REGNO (oldequiv)] 6770 && GET_CODE (old) == REG 6771 && (dead_or_set_p (insn, 6772 spill_reg_stored_to[REGNO (oldequiv)]) 6773 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], 6774 old))) 6775 delete_output_reload (insn, j, REGNO (oldequiv)); 6776 6777 /* Prevent normal processing of this reload. */ 6778 special = 1; 6779 /* Output a special code sequence for this case. */ 6780 new_spill_reg_store[REGNO (reloadreg)] 6781 = inc_for_reload (reloadreg, oldequiv, reload_out[j], 6782 reload_inc[j]); 6783 } 6784 6785 /* If we are reloading a pseudo-register that was set by the previous 6786 insn, see if we can get rid of that pseudo-register entirely 6787 by redirecting the previous insn into our reload register. */ 6788 6789 else if (optimize && GET_CODE (old) == REG 6790 && REGNO (old) >= FIRST_PSEUDO_REGISTER 6791 && dead_or_set_p (insn, old) 6792 /* This is unsafe if some other reload 6793 uses the same reg first. */ 6794 && reload_reg_free_for_value_p (REGNO (reloadreg), 6795 reload_opnum[j], 6796 reload_when_needed[j], 6797 old, reload_out[j], 6798 j, 0)) 6799 { 6800 rtx temp = PREV_INSN (insn); 6801 while (temp && GET_CODE (temp) == NOTE) 6802 temp = PREV_INSN (temp); 6803 if (temp 6804 && GET_CODE (temp) == INSN 6805 && GET_CODE (PATTERN (temp)) == SET 6806 && SET_DEST (PATTERN (temp)) == old 6807 /* Make sure we can access insn_operand_constraint. */ 6808 && asm_noperands (PATTERN (temp)) < 0 6809 /* This is unsafe if prev insn rejects our reload reg. */ 6810 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0], 6811 reloadreg) 6812 /* This is unsafe if operand occurs more than once in current 6813 insn. Perhaps some occurrences aren't reloaded. */ 6814 && count_occurrences (PATTERN (insn), old) == 1 6815 /* Don't risk splitting a matching pair of operands. */ 6816 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) 6817 { 6818 /* Store into the reload register instead of the pseudo. */ 6819 SET_DEST (PATTERN (temp)) = reloadreg; 6820 6821 /* If the previous insn is an output reload, the source is 6822 a reload register, and its spill_reg_store entry will 6823 contain the previous destination. This is now 6824 invalid. */ 6825 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG 6826 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) 6827 { 6828 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; 6829 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; 6830 } 6831 6832 /* If these are the only uses of the pseudo reg, 6833 pretend for GDB it lives in the reload reg we used. */ 6834 if (REG_N_DEATHS (REGNO (old)) == 1 6835 && REG_N_SETS (REGNO (old)) == 1) 6836 { 6837 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]); 6838 alter_reg (REGNO (old), -1); 6839 } 6840 special = 1; 6841 } 6842 } 6843 6844 /* We can't do that, so output an insn to load RELOADREG. */ 6845 6846 if (! special) 6847 { 6848#ifdef SECONDARY_INPUT_RELOAD_CLASS 6849 rtx second_reload_reg = 0; 6850 enum insn_code icode; 6851 6852 /* If we have a secondary reload, pick up the secondary register 6853 and icode, if any. If OLDEQUIV and OLD are different or 6854 if this is an in-out reload, recompute whether or not we 6855 still need a secondary register and what the icode should 6856 be. If we still need a secondary register and the class or 6857 icode is different, go back to reloading from OLD if using 6858 OLDEQUIV means that we got the wrong type of register. We 6859 cannot have different class or icode due to an in-out reload 6860 because we don't make such reloads when both the input and 6861 output need secondary reload registers. */ 6862 6863 if (reload_secondary_in_reload[j] >= 0) 6864 { 6865 int secondary_reload = reload_secondary_in_reload[j]; 6866 rtx real_oldequiv = oldequiv; 6867 rtx real_old = old; 6868 rtx tmp; 6869 6870 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM 6871 and similarly for OLD. 6872 See comments in get_secondary_reload in reload.c. */ 6873 /* If it is a pseudo that cannot be replaced with its 6874 equivalent MEM, we must fall back to reload_in, which 6875 will have all the necessary substitutions registered. 6876 Likewise for a pseudo that can't be replaced with its 6877 equivalent constant. 6878 6879 Take extra care for subregs of such pseudos. Note that 6880 we cannot use reg_equiv_mem in this case because it is 6881 not in the right mode. */ 6882 6883 tmp = oldequiv; 6884 if (GET_CODE (tmp) == SUBREG) 6885 tmp = SUBREG_REG (tmp); 6886 if (GET_CODE (tmp) == REG 6887 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER 6888 && (reg_equiv_memory_loc[REGNO (tmp)] != 0 6889 || reg_equiv_constant[REGNO (tmp)] != 0)) 6890 { 6891 if (! reg_equiv_mem[REGNO (tmp)] 6892 || num_not_at_initial_offset 6893 || GET_CODE (oldequiv) == SUBREG) 6894 real_oldequiv = reload_in[j]; 6895 else 6896 real_oldequiv = reg_equiv_mem[REGNO (tmp)]; 6897 } 6898 6899 tmp = old; 6900 if (GET_CODE (tmp) == SUBREG) 6901 tmp = SUBREG_REG (tmp); 6902 if (GET_CODE (tmp) == REG 6903 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER 6904 && (reg_equiv_memory_loc[REGNO (tmp)] != 0 6905 || reg_equiv_constant[REGNO (tmp)] != 0)) 6906 { 6907 if (! reg_equiv_mem[REGNO (tmp)] 6908 || num_not_at_initial_offset 6909 || GET_CODE (old) == SUBREG) 6910 real_old = reload_in[j]; 6911 else 6912 real_old = reg_equiv_mem[REGNO (tmp)]; 6913 } 6914 6915 second_reload_reg = reload_reg_rtx[secondary_reload]; 6916 icode = reload_secondary_in_icode[j]; 6917 6918 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) 6919 || (reload_in[j] != 0 && reload_out[j] != 0)) 6920 { 6921 enum reg_class new_class 6922 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j], 6923 mode, real_oldequiv); 6924 6925 if (new_class == NO_REGS) 6926 second_reload_reg = 0; 6927 else 6928 { 6929 enum insn_code new_icode; 6930 enum machine_mode new_mode; 6931 6932 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], 6933 REGNO (second_reload_reg))) 6934 oldequiv = old, real_oldequiv = real_old; 6935 else 6936 { 6937 new_icode = reload_in_optab[(int) mode]; 6938 if (new_icode != CODE_FOR_nothing 6939 && ((insn_operand_predicate[(int) new_icode][0] 6940 && ! ((*insn_operand_predicate[(int) new_icode][0]) 6941 (reloadreg, mode))) 6942 || (insn_operand_predicate[(int) new_icode][1] 6943 && ! ((*insn_operand_predicate[(int) new_icode][1]) 6944 (real_oldequiv, mode))))) 6945 new_icode = CODE_FOR_nothing; 6946 6947 if (new_icode == CODE_FOR_nothing) 6948 new_mode = mode; 6949 else 6950 new_mode = insn_operand_mode[(int) new_icode][2]; 6951 6952 if (GET_MODE (second_reload_reg) != new_mode) 6953 { 6954 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), 6955 new_mode)) 6956 oldequiv = old, real_oldequiv = real_old; 6957 else 6958 second_reload_reg 6959 = gen_rtx_REG (new_mode, 6960 REGNO (second_reload_reg)); 6961 } 6962 } 6963 } 6964 } 6965 6966 /* If we still need a secondary reload register, check 6967 to see if it is being used as a scratch or intermediate 6968 register and generate code appropriately. If we need 6969 a scratch register, use REAL_OLDEQUIV since the form of 6970 the insn may depend on the actual address if it is 6971 a MEM. */ 6972 6973 if (second_reload_reg) 6974 { 6975 if (icode != CODE_FOR_nothing) 6976 { 6977 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, 6978 second_reload_reg)); 6979 special = 1; 6980 } 6981 else 6982 { 6983 /* See if we need a scratch register to load the 6984 intermediate register (a tertiary reload). */ 6985 enum insn_code tertiary_icode 6986 = reload_secondary_in_icode[secondary_reload]; 6987 6988 if (tertiary_icode != CODE_FOR_nothing) 6989 { 6990 rtx third_reload_reg 6991 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]]; 6992 6993 emit_insn ((GEN_FCN (tertiary_icode) 6994 (second_reload_reg, real_oldequiv, 6995 third_reload_reg))); 6996 } 6997 else 6998 gen_reload (second_reload_reg, real_oldequiv, 6999 reload_opnum[j], 7000 reload_when_needed[j]); 7001 7002 oldequiv = second_reload_reg; 7003 } 7004 } 7005 } 7006#endif 7007 7008 if (! special && ! rtx_equal_p (reloadreg, oldequiv)) 7009 { 7010 rtx real_oldequiv = oldequiv; 7011 7012 if ((GET_CODE (oldequiv) == REG 7013 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER 7014 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 7015 || reg_equiv_constant[REGNO (oldequiv)] != 0)) 7016 || (GET_CODE (oldequiv) == SUBREG 7017 && GET_CODE (SUBREG_REG (oldequiv)) == REG 7018 && (REGNO (SUBREG_REG (oldequiv)) 7019 >= FIRST_PSEUDO_REGISTER) 7020 && ((reg_equiv_memory_loc 7021 [REGNO (SUBREG_REG (oldequiv))] != 0) 7022 || (reg_equiv_constant 7023 [REGNO (SUBREG_REG (oldequiv))] != 0)))) 7024 real_oldequiv = reload_in[j]; 7025 gen_reload (reloadreg, real_oldequiv, reload_opnum[j], 7026 reload_when_needed[j]); 7027 } 7028 7029 } 7030 7031 this_reload_insn = get_last_insn (); 7032 /* End this sequence. */ 7033 *where = get_insns (); 7034 end_sequence (); 7035 7036 /* Update reload_override_in so that delete_address_reloads_1 7037 can see the actual register usage. */ 7038 if (oldequiv_reg) 7039 reload_override_in[j] = oldequiv; 7040 } 7041 7042 /* When inheriting a wider reload, we have a MEM in reload_in[j], 7043 e.g. inheriting a SImode output reload for 7044 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ 7045 if (optimize && reload_inherited[j] && reload_in[j] 7046 && GET_CODE (reload_in[j]) == MEM 7047 && GET_CODE (reload_in_reg[j]) == MEM 7048 && reload_spill_index[j] >= 0 7049 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) 7050 { 7051 expect_occurrences 7052 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1; 7053 reload_in[j] 7054 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; 7055 } 7056 7057 /* If we are reloading a register that was recently stored in with an 7058 output-reload, see if we can prove there was 7059 actually no need to store the old value in it. */ 7060 7061 if (optimize 7062 && (reload_inherited[j] || reload_override_in[j]) 7063 && reload_reg_rtx[j] 7064 && GET_CODE (reload_reg_rtx[j]) == REG 7065 && spill_reg_store[REGNO (reload_reg_rtx[j])] != 0 7066#if 0 7067 /* There doesn't seem to be any reason to restrict this to pseudos 7068 and doing so loses in the case where we are copying from a 7069 register of the wrong class. */ 7070 && REGNO (spill_reg_stored_to[REGNO (reload_reg_rtx[j])]) 7071 >= FIRST_PSEUDO_REGISTER 7072#endif 7073 /* The insn might have already some references to stackslots 7074 replaced by MEMs, while reload_out_reg still names the 7075 original pseudo. */ 7076 && (dead_or_set_p (insn, 7077 spill_reg_stored_to[REGNO (reload_reg_rtx[j])]) 7078 || rtx_equal_p (spill_reg_stored_to[REGNO (reload_reg_rtx[j])], 7079 reload_out_reg[j]))) 7080 delete_output_reload (insn, j, REGNO (reload_reg_rtx[j])); 7081 7082 /* Input-reloading is done. Now do output-reloading, 7083 storing the value from the reload-register after the main insn 7084 if reload_out[j] is nonzero. 7085 7086 ??? At some point we need to support handling output reloads of 7087 JUMP_INSNs or insns that set cc0. */ 7088 7089 /* If this is an output reload that stores something that is 7090 not loaded in this same reload, see if we can eliminate a previous 7091 store. */ 7092 { 7093 rtx pseudo = reload_out_reg[j]; 7094 7095 if (pseudo 7096 && GET_CODE (pseudo) == REG 7097 && ! rtx_equal_p (reload_in_reg[j], pseudo) 7098 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER 7099 && reg_last_reload_reg[REGNO (pseudo)]) 7100 { 7101 int pseudo_no = REGNO (pseudo); 7102 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); 7103 7104 /* We don't need to test full validity of last_regno for 7105 inherit here; we only want to know if the store actually 7106 matches the pseudo. */ 7107 if (reg_reloaded_contents[last_regno] == pseudo_no 7108 && spill_reg_store[last_regno] 7109 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) 7110 delete_output_reload (insn, j, last_regno); 7111 } 7112 } 7113 7114 old = reload_out_reg[j]; 7115 if (old != 0 7116 && reload_reg_rtx[j] != old 7117 && reload_reg_rtx[j] != 0) 7118 { 7119 register rtx reloadreg = reload_reg_rtx[j]; 7120#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 7121 register rtx second_reloadreg = 0; 7122#endif 7123 rtx note, p; 7124 enum machine_mode mode; 7125 int special = 0; 7126 7127 /* An output operand that dies right away does need a reload, 7128 but need not be copied from it. Show the new location in the 7129 REG_UNUSED note. */ 7130 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) 7131 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) 7132 { 7133 XEXP (note, 0) = reload_reg_rtx[j]; 7134 continue; 7135 } 7136 /* Likewise for a SUBREG of an operand that dies. */ 7137 else if (GET_CODE (old) == SUBREG 7138 && GET_CODE (SUBREG_REG (old)) == REG 7139 && 0 != (note = find_reg_note (insn, REG_UNUSED, 7140 SUBREG_REG (old)))) 7141 { 7142 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), 7143 reload_reg_rtx[j]); 7144 continue; 7145 } 7146 else if (GET_CODE (old) == SCRATCH) 7147 /* If we aren't optimizing, there won't be a REG_UNUSED note, 7148 but we don't want to make an output reload. */ 7149 continue; 7150 7151#if 0 7152 /* Strip off of OLD any size-increasing SUBREGs such as 7153 (SUBREG:SI foo:QI 0). */ 7154 7155 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0 7156 && (GET_MODE_SIZE (GET_MODE (old)) 7157 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old))))) 7158 old = SUBREG_REG (old); 7159#endif 7160 7161 /* If is a JUMP_INSN, we can't support output reloads yet. */ 7162 if (GET_CODE (insn) == JUMP_INSN) 7163 abort (); 7164 7165 if (reload_when_needed[j] == RELOAD_OTHER) 7166 start_sequence (); 7167 else 7168 push_to_sequence (output_reload_insns[reload_opnum[j]]); 7169 7170 old = reload_out[j]; 7171 7172 /* Determine the mode to reload in. 7173 See comments above (for input reloading). */ 7174 7175 mode = GET_MODE (old); 7176 if (mode == VOIDmode) 7177 { 7178 /* VOIDmode should never happen for an output. */ 7179 if (asm_noperands (PATTERN (insn)) < 0) 7180 /* It's the compiler's fault. */ 7181 fatal_insn ("VOIDmode on an output", insn); 7182 error_for_asm (insn, "output operand is constant in `asm'"); 7183 /* Prevent crash--use something we know is valid. */ 7184 mode = word_mode; 7185 old = gen_rtx_REG (mode, REGNO (reloadreg)); 7186 } 7187 7188 if (GET_MODE (reloadreg) != mode) 7189 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); 7190 7191#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 7192 7193 /* If we need two reload regs, set RELOADREG to the intermediate 7194 one, since it will be stored into OLD. We might need a secondary 7195 register only for an input reload, so check again here. */ 7196 7197 if (reload_secondary_out_reload[j] >= 0) 7198 { 7199 rtx real_old = old; 7200 7201 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER 7202 && reg_equiv_mem[REGNO (old)] != 0) 7203 real_old = reg_equiv_mem[REGNO (old)]; 7204 7205 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j], 7206 mode, real_old) 7207 != NO_REGS)) 7208 { 7209 second_reloadreg = reloadreg; 7210 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]]; 7211 7212 /* See if RELOADREG is to be used as a scratch register 7213 or as an intermediate register. */ 7214 if (reload_secondary_out_icode[j] != CODE_FOR_nothing) 7215 { 7216 emit_insn ((GEN_FCN (reload_secondary_out_icode[j]) 7217 (real_old, second_reloadreg, reloadreg))); 7218 special = 1; 7219 } 7220 else 7221 { 7222 /* See if we need both a scratch and intermediate reload 7223 register. */ 7224 7225 int secondary_reload = reload_secondary_out_reload[j]; 7226 enum insn_code tertiary_icode 7227 = reload_secondary_out_icode[secondary_reload]; 7228 7229 if (GET_MODE (reloadreg) != mode) 7230 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); 7231 7232 if (tertiary_icode != CODE_FOR_nothing) 7233 { 7234 rtx third_reloadreg 7235 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]]; 7236 rtx tem; 7237 7238 /* Copy primary reload reg to secondary reload reg. 7239 (Note that these have been swapped above, then 7240 secondary reload reg to OLD using our insn. */ 7241 7242 /* If REAL_OLD is a paradoxical SUBREG, remove it 7243 and try to put the opposite SUBREG on 7244 RELOADREG. */ 7245 if (GET_CODE (real_old) == SUBREG 7246 && (GET_MODE_SIZE (GET_MODE (real_old)) 7247 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) 7248 && 0 != (tem = gen_lowpart_common 7249 (GET_MODE (SUBREG_REG (real_old)), 7250 reloadreg))) 7251 real_old = SUBREG_REG (real_old), reloadreg = tem; 7252 7253 gen_reload (reloadreg, second_reloadreg, 7254 reload_opnum[j], reload_when_needed[j]); 7255 emit_insn ((GEN_FCN (tertiary_icode) 7256 (real_old, reloadreg, third_reloadreg))); 7257 special = 1; 7258 } 7259 7260 else 7261 /* Copy between the reload regs here and then to 7262 OUT later. */ 7263 7264 gen_reload (reloadreg, second_reloadreg, 7265 reload_opnum[j], reload_when_needed[j]); 7266 } 7267 } 7268 } 7269#endif 7270 7271 /* Output the last reload insn. */ 7272 if (! special) 7273 { 7274 rtx set; 7275 7276 /* Don't output the last reload if OLD is not the dest of 7277 INSN and is in the src and is clobbered by INSN. */ 7278 if (! flag_expensive_optimizations 7279 || GET_CODE (old) != REG 7280 || !(set = single_set (insn)) 7281 || rtx_equal_p (old, SET_DEST (set)) 7282 || !reg_mentioned_p (old, SET_SRC (set)) 7283 || !regno_clobbered_p (REGNO (old), insn)) 7284 gen_reload (old, reloadreg, reload_opnum[j], 7285 reload_when_needed[j]); 7286 } 7287 7288 /* Look at all insns we emitted, just to be safe. */ 7289 for (p = get_insns (); p; p = NEXT_INSN (p)) 7290 if (GET_RTX_CLASS (GET_CODE (p)) == 'i') 7291 { 7292 rtx pat = PATTERN (p); 7293 7294 /* If this output reload doesn't come from a spill reg, 7295 clear any memory of reloaded copies of the pseudo reg. 7296 If this output reload comes from a spill reg, 7297 reg_has_output_reload will make this do nothing. */ 7298 note_stores (pat, forget_old_reloads_1); 7299 7300 if (reg_mentioned_p (reload_reg_rtx[j], pat)) 7301 { 7302 rtx set = single_set (insn); 7303 if (reload_spill_index[j] < 0 7304 && set 7305 && SET_SRC (set) == reload_reg_rtx[j]) 7306 { 7307 int src = REGNO (SET_SRC (set)); 7308 7309 reload_spill_index[j] = src; 7310 SET_HARD_REG_BIT (reg_is_output_reload, src); 7311 if (find_regno_note (insn, REG_DEAD, src)) 7312 SET_HARD_REG_BIT (reg_reloaded_died, src); 7313 } 7314 if (REGNO (reload_reg_rtx[j]) < FIRST_PSEUDO_REGISTER) 7315 { 7316 int s = reload_secondary_out_reload[j]; 7317 set = single_set (p); 7318 /* If this reload copies only to the secondary reload 7319 register, the secondary reload does the actual 7320 store. */ 7321 if (s >= 0 && set == NULL_RTX) 7322 ; /* We can't tell what function the secondary reload 7323 has and where the actual store to the pseudo is 7324 made; leave new_spill_reg_store alone. */ 7325 else if (s >= 0 7326 && SET_SRC (set) == reload_reg_rtx[j] 7327 && SET_DEST (set) == reload_reg_rtx[s]) 7328 { 7329 /* Usually the next instruction will be the 7330 secondary reload insn; if we can confirm 7331 that it is, setting new_spill_reg_store to 7332 that insn will allow an extra optimization. */ 7333 rtx s_reg = reload_reg_rtx[s]; 7334 rtx next = NEXT_INSN (p); 7335 reload_out[s] = reload_out[j]; 7336 reload_out_reg[s] = reload_out_reg[j]; 7337 set = single_set (next); 7338 if (set && SET_SRC (set) == s_reg 7339 && ! new_spill_reg_store[REGNO (s_reg)]) 7340 { 7341 SET_HARD_REG_BIT (reg_is_output_reload, 7342 REGNO (s_reg)); 7343 new_spill_reg_store[REGNO (s_reg)] = next; 7344 } 7345 } 7346 else 7347 new_spill_reg_store[REGNO (reload_reg_rtx[j])] = p; 7348 } 7349 } 7350 } 7351 7352 if (reload_when_needed[j] == RELOAD_OTHER) 7353 { 7354 emit_insns (other_output_reload_insns[reload_opnum[j]]); 7355 other_output_reload_insns[reload_opnum[j]] = get_insns (); 7356 } 7357 else 7358 output_reload_insns[reload_opnum[j]] = get_insns (); 7359 7360 end_sequence (); 7361 } 7362 } 7363 7364 /* Now write all the insns we made for reloads in the order expected by 7365 the allocation functions. Prior to the insn being reloaded, we write 7366 the following reloads: 7367 7368 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. 7369 7370 RELOAD_OTHER reloads. 7371 7372 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed 7373 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the 7374 RELOAD_FOR_INPUT reload for the operand. 7375 7376 RELOAD_FOR_OPADDR_ADDRS reloads. 7377 7378 RELOAD_FOR_OPERAND_ADDRESS reloads. 7379 7380 After the insn being reloaded, we write the following: 7381 7382 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed 7383 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the 7384 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output 7385 reloads for the operand. The RELOAD_OTHER output reloads are 7386 output in descending order by reload number. */ 7387 7388 emit_insns_before (other_input_address_reload_insns, insn); 7389 emit_insns_before (other_input_reload_insns, insn); 7390 7391 for (j = 0; j < reload_n_operands; j++) 7392 { 7393 emit_insns_before (inpaddr_address_reload_insns[j], insn); 7394 emit_insns_before (input_address_reload_insns[j], insn); 7395 emit_insns_before (input_reload_insns[j], insn); 7396 } 7397 7398 emit_insns_before (other_operand_reload_insns, insn); 7399 emit_insns_before (operand_reload_insns, insn); 7400 7401 for (j = 0; j < reload_n_operands; j++) 7402 { 7403 emit_insns_before (outaddr_address_reload_insns[j], following_insn); 7404 emit_insns_before (output_address_reload_insns[j], following_insn); 7405 emit_insns_before (output_reload_insns[j], following_insn); 7406 emit_insns_before (other_output_reload_insns[j], following_insn); 7407 } 7408 7409 /* Keep basic block info up to date. */ 7410 if (n_basic_blocks) 7411 { 7412 if (BLOCK_HEAD (chain->block) == insn) 7413 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn); 7414 if (BLOCK_END (chain->block) == insn) 7415 BLOCK_END (chain->block) = PREV_INSN (following_insn); 7416 } 7417 7418 /* For all the spill regs newly reloaded in this instruction, 7419 record what they were reloaded from, so subsequent instructions 7420 can inherit the reloads. 7421 7422 Update spill_reg_store for the reloads of this insn. 7423 Copy the elements that were updated in the loop above. */ 7424 7425 for (j = 0; j < n_reloads; j++) 7426 { 7427 register int r = reload_order[j]; 7428 register int i = reload_spill_index[r]; 7429 7430 /* If this is a non-inherited input reload from a pseudo, we must 7431 clear any memory of a previous store to the same pseudo. Only do 7432 something if there will not be an output reload for the pseudo 7433 being reloaded. */ 7434 if (reload_in_reg[r] != 0 7435 && ! (reload_inherited[r] || reload_override_in[r])) 7436 { 7437 rtx reg = reload_in_reg[r]; 7438 7439 if (GET_CODE (reg) == SUBREG) 7440 reg = SUBREG_REG (reg); 7441 7442 if (GET_CODE (reg) == REG 7443 && REGNO (reg) >= FIRST_PSEUDO_REGISTER 7444 && ! reg_has_output_reload[REGNO (reg)]) 7445 { 7446 int nregno = REGNO (reg); 7447 7448 if (reg_last_reload_reg[nregno]) 7449 { 7450 int last_regno = REGNO (reg_last_reload_reg[nregno]); 7451 7452 if (reg_reloaded_contents[last_regno] == nregno) 7453 spill_reg_store[last_regno] = 0; 7454 } 7455 } 7456 } 7457 7458 /* I is nonneg if this reload used a register. 7459 If reload_reg_rtx[r] is 0, this is an optional reload 7460 that we opted to ignore. */ 7461 7462 if (i >= 0 && reload_reg_rtx[r] != 0) 7463 { 7464 int nr 7465 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r])); 7466 int k; 7467 int part_reaches_end = 0; 7468 int all_reaches_end = 1; 7469 7470 /* For a multi register reload, we need to check if all or part 7471 of the value lives to the end. */ 7472 for (k = 0; k < nr; k++) 7473 { 7474 if (reload_reg_reaches_end_p (i + k, reload_opnum[r], 7475 reload_when_needed[r])) 7476 part_reaches_end = 1; 7477 else 7478 all_reaches_end = 0; 7479 } 7480 7481 /* Ignore reloads that don't reach the end of the insn in 7482 entirety. */ 7483 if (all_reaches_end) 7484 { 7485 /* First, clear out memory of what used to be in this spill reg. 7486 If consecutive registers are used, clear them all. */ 7487 7488 for (k = 0; k < nr; k++) 7489 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); 7490 7491 /* Maybe the spill reg contains a copy of reload_out. */ 7492 if (reload_out[r] != 0 7493 && (GET_CODE (reload_out[r]) == REG 7494#ifdef AUTO_INC_DEC 7495 || ! reload_out_reg[r] 7496#endif 7497 || GET_CODE (reload_out_reg[r]) == REG)) 7498 { 7499 rtx out = (GET_CODE (reload_out[r]) == REG 7500 ? reload_out[r] 7501 : reload_out_reg[r] 7502 ? reload_out_reg[r] 7503/* AUTO_INC */ : XEXP (reload_in_reg[r], 0)); 7504 register int nregno = REGNO (out); 7505 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 7506 : HARD_REGNO_NREGS (nregno, 7507 GET_MODE (reload_reg_rtx[r]))); 7508 7509 spill_reg_store[i] = new_spill_reg_store[i]; 7510 spill_reg_stored_to[i] = out; 7511 reg_last_reload_reg[nregno] = reload_reg_rtx[r]; 7512 7513 /* If NREGNO is a hard register, it may occupy more than 7514 one register. If it does, say what is in the 7515 rest of the registers assuming that both registers 7516 agree on how many words the object takes. If not, 7517 invalidate the subsequent registers. */ 7518 7519 if (nregno < FIRST_PSEUDO_REGISTER) 7520 for (k = 1; k < nnr; k++) 7521 reg_last_reload_reg[nregno + k] 7522 = (nr == nnr 7523 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k], 7524 REGNO (reload_reg_rtx[r]) + k) 7525 : 0); 7526 7527 /* Now do the inverse operation. */ 7528 for (k = 0; k < nr; k++) 7529 { 7530 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); 7531 reg_reloaded_contents[i + k] 7532 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr 7533 ? nregno 7534 : nregno + k); 7535 reg_reloaded_insn[i + k] = insn; 7536 SET_HARD_REG_BIT (reg_reloaded_valid, i + k); 7537 } 7538 } 7539 7540 /* Maybe the spill reg contains a copy of reload_in. Only do 7541 something if there will not be an output reload for 7542 the register being reloaded. */ 7543 else if (reload_out_reg[r] == 0 7544 && reload_in[r] != 0 7545 && ((GET_CODE (reload_in[r]) == REG 7546 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER 7547 && ! reg_has_output_reload[REGNO (reload_in[r])]) 7548 || (GET_CODE (reload_in_reg[r]) == REG 7549 && ! reg_has_output_reload[REGNO (reload_in_reg[r])])) 7550 && ! reg_set_p (reload_reg_rtx[r], PATTERN (insn))) 7551 { 7552 register int nregno; 7553 int nnr; 7554 7555 if (GET_CODE (reload_in[r]) == REG 7556 && REGNO (reload_in[r]) >= FIRST_PSEUDO_REGISTER) 7557 nregno = REGNO (reload_in[r]); 7558 else if (GET_CODE (reload_in_reg[r]) == REG) 7559 nregno = REGNO (reload_in_reg[r]); 7560 else 7561 nregno = REGNO (XEXP (reload_in_reg[r], 0)); 7562 7563 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 7564 : HARD_REGNO_NREGS (nregno, 7565 GET_MODE (reload_reg_rtx[r]))); 7566 7567 reg_last_reload_reg[nregno] = reload_reg_rtx[r]; 7568 7569 if (nregno < FIRST_PSEUDO_REGISTER) 7570 for (k = 1; k < nnr; k++) 7571 reg_last_reload_reg[nregno + k] 7572 = (nr == nnr 7573 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k], 7574 REGNO (reload_reg_rtx[r]) + k) 7575 : 0); 7576 7577 /* Unless we inherited this reload, show we haven't 7578 recently done a store. 7579 Previous stores of inherited auto_inc expressions 7580 also have to be discarded. */ 7581 if (! reload_inherited[r] 7582 || (reload_out[r] && ! reload_out_reg[r])) 7583 spill_reg_store[i] = 0; 7584 7585 for (k = 0; k < nr; k++) 7586 { 7587 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); 7588 reg_reloaded_contents[i + k] 7589 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr 7590 ? nregno 7591 : nregno + k); 7592 reg_reloaded_insn[i + k] = insn; 7593 SET_HARD_REG_BIT (reg_reloaded_valid, i + k); 7594 } 7595 } 7596 } 7597 7598 /* However, if part of the reload reaches the end, then we must 7599 invalidate the old info for the part that survives to the end. */ 7600 else if (part_reaches_end) 7601 { 7602 for (k = 0; k < nr; k++) 7603 if (reload_reg_reaches_end_p (i + k, 7604 reload_opnum[r], 7605 reload_when_needed[r])) 7606 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); 7607 } 7608 } 7609 7610 /* The following if-statement was #if 0'd in 1.34 (or before...). 7611 It's reenabled in 1.35 because supposedly nothing else 7612 deals with this problem. */ 7613 7614 /* If a register gets output-reloaded from a non-spill register, 7615 that invalidates any previous reloaded copy of it. 7616 But forget_old_reloads_1 won't get to see it, because 7617 it thinks only about the original insn. So invalidate it here. */ 7618 if (i < 0 && reload_out[r] != 0 7619 && (GET_CODE (reload_out[r]) == REG 7620 || (GET_CODE (reload_out[r]) == MEM 7621 && GET_CODE (reload_out_reg[r]) == REG))) 7622 { 7623 rtx out = (GET_CODE (reload_out[r]) == REG 7624 ? reload_out[r] : reload_out_reg[r]); 7625 register int nregno = REGNO (out); 7626 if (nregno >= FIRST_PSEUDO_REGISTER) 7627 { 7628 rtx src_reg, store_insn; 7629 7630 reg_last_reload_reg[nregno] = 0; 7631 7632 /* If we can find a hard register that is stored, record 7633 the storing insn so that we may delete this insn with 7634 delete_output_reload. */ 7635 src_reg = reload_reg_rtx[r]; 7636 7637 /* If this is an optional reload, try to find the source reg 7638 from an input reload. */ 7639 if (! src_reg) 7640 { 7641 rtx set = single_set (insn); 7642 if (set && SET_DEST (set) == reload_out[r]) 7643 { 7644 int k; 7645 7646 src_reg = SET_SRC (set); 7647 store_insn = insn; 7648 for (k = 0; k < n_reloads; k++) 7649 { 7650 if (reload_in[k] == src_reg) 7651 { 7652 src_reg = reload_reg_rtx[k]; 7653 break; 7654 } 7655 } 7656 } 7657 } 7658 else 7659 store_insn = new_spill_reg_store[REGNO (src_reg)]; 7660 if (src_reg && GET_CODE (src_reg) == REG 7661 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) 7662 { 7663 int src_regno = REGNO (src_reg); 7664 int nr = HARD_REGNO_NREGS (src_regno, reload_mode[r]); 7665 /* The place where to find a death note varies with 7666 PRESERVE_DEATH_INFO_REGNO_P . The condition is not 7667 necessarily checked exactly in the code that moves 7668 notes, so just check both locations. */ 7669 rtx note = find_regno_note (insn, REG_DEAD, src_regno); 7670 if (! note) 7671 note = find_regno_note (store_insn, REG_DEAD, src_regno); 7672 while (nr-- > 0) 7673 { 7674 spill_reg_store[src_regno + nr] = store_insn; 7675 spill_reg_stored_to[src_regno + nr] = out; 7676 reg_reloaded_contents[src_regno + nr] = nregno; 7677 reg_reloaded_insn[src_regno + nr] = store_insn; 7678 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); 7679 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); 7680 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); 7681 if (note) 7682 SET_HARD_REG_BIT (reg_reloaded_died, src_regno); 7683 else 7684 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); 7685 } 7686 reg_last_reload_reg[nregno] = src_reg; 7687 } 7688 } 7689 else 7690 { 7691 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r])); 7692 7693 while (num_regs-- > 0) 7694 reg_last_reload_reg[nregno + num_regs] = 0; 7695 } 7696 } 7697 } 7698 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); 7699} 7700 7701/* Emit code to perform a reload from IN (which may be a reload register) to 7702 OUT (which may also be a reload register). IN or OUT is from operand 7703 OPNUM with reload type TYPE. 7704 7705 Returns first insn emitted. */ 7706 7707rtx 7708gen_reload (out, in, opnum, type) 7709 rtx out; 7710 rtx in; 7711 int opnum; 7712 enum reload_type type; 7713{ 7714 rtx last = get_last_insn (); 7715 rtx tem; 7716 7717 /* If IN is a paradoxical SUBREG, remove it and try to put the 7718 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ 7719 if (GET_CODE (in) == SUBREG 7720 && (GET_MODE_SIZE (GET_MODE (in)) 7721 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) 7722 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) 7723 in = SUBREG_REG (in), out = tem; 7724 else if (GET_CODE (out) == SUBREG 7725 && (GET_MODE_SIZE (GET_MODE (out)) 7726 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) 7727 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) 7728 out = SUBREG_REG (out), in = tem; 7729 7730 /* How to do this reload can get quite tricky. Normally, we are being 7731 asked to reload a simple operand, such as a MEM, a constant, or a pseudo 7732 register that didn't get a hard register. In that case we can just 7733 call emit_move_insn. 7734 7735 We can also be asked to reload a PLUS that adds a register or a MEM to 7736 another register, constant or MEM. This can occur during frame pointer 7737 elimination and while reloading addresses. This case is handled by 7738 trying to emit a single insn to perform the add. If it is not valid, 7739 we use a two insn sequence. 7740 7741 Finally, we could be called to handle an 'o' constraint by putting 7742 an address into a register. In that case, we first try to do this 7743 with a named pattern of "reload_load_address". If no such pattern 7744 exists, we just emit a SET insn and hope for the best (it will normally 7745 be valid on machines that use 'o'). 7746 7747 This entire process is made complex because reload will never 7748 process the insns we generate here and so we must ensure that 7749 they will fit their constraints and also by the fact that parts of 7750 IN might be being reloaded separately and replaced with spill registers. 7751 Because of this, we are, in some sense, just guessing the right approach 7752 here. The one listed above seems to work. 7753 7754 ??? At some point, this whole thing needs to be rethought. */ 7755 7756 if (GET_CODE (in) == PLUS 7757 && (GET_CODE (XEXP (in, 0)) == REG 7758 || GET_CODE (XEXP (in, 0)) == SUBREG 7759 || GET_CODE (XEXP (in, 0)) == MEM) 7760 && (GET_CODE (XEXP (in, 1)) == REG 7761 || GET_CODE (XEXP (in, 1)) == SUBREG 7762 || CONSTANT_P (XEXP (in, 1)) 7763 || GET_CODE (XEXP (in, 1)) == MEM)) 7764 { 7765 /* We need to compute the sum of a register or a MEM and another 7766 register, constant, or MEM, and put it into the reload 7767 register. The best possible way of doing this is if the machine 7768 has a three-operand ADD insn that accepts the required operands. 7769 7770 The simplest approach is to try to generate such an insn and see if it 7771 is recognized and matches its constraints. If so, it can be used. 7772 7773 It might be better not to actually emit the insn unless it is valid, 7774 but we need to pass the insn as an operand to `recog' and 7775 `extract_insn' and it is simpler to emit and then delete the insn if 7776 not valid than to dummy things up. */ 7777 7778 rtx op0, op1, tem, insn; 7779 int code; 7780 7781 op0 = find_replacement (&XEXP (in, 0)); 7782 op1 = find_replacement (&XEXP (in, 1)); 7783 7784 /* Since constraint checking is strict, commutativity won't be 7785 checked, so we need to do that here to avoid spurious failure 7786 if the add instruction is two-address and the second operand 7787 of the add is the same as the reload reg, which is frequently 7788 the case. If the insn would be A = B + A, rearrange it so 7789 it will be A = A + B as constrain_operands expects. */ 7790 7791 if (GET_CODE (XEXP (in, 1)) == REG 7792 && REGNO (out) == REGNO (XEXP (in, 1))) 7793 tem = op0, op0 = op1, op1 = tem; 7794 7795 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) 7796 in = gen_rtx_PLUS (GET_MODE (in), op0, op1); 7797 7798 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); 7799 code = recog_memoized (insn); 7800 7801 if (code >= 0) 7802 { 7803 extract_insn (insn); 7804 /* We want constrain operands to treat this insn strictly in 7805 its validity determination, i.e., the way it would after reload 7806 has completed. */ 7807 if (constrain_operands (1)) 7808 return insn; 7809 } 7810 7811 delete_insns_since (last); 7812 7813 /* If that failed, we must use a conservative two-insn sequence. 7814 use move to copy constant, MEM, or pseudo register to the reload 7815 register since "move" will be able to handle an arbitrary operand, 7816 unlike add which can't, in general. Then add the registers. 7817 7818 If there is another way to do this for a specific machine, a 7819 DEFINE_PEEPHOLE should be specified that recognizes the sequence 7820 we emit below. */ 7821 7822 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; 7823 7824 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG 7825 || (GET_CODE (op1) == REG 7826 && REGNO (op1) >= FIRST_PSEUDO_REGISTER) 7827 || (code != CODE_FOR_nothing 7828 && ! (*insn_operand_predicate[code][2]) (op1, insn_operand_mode[code][2]))) 7829 tem = op0, op0 = op1, op1 = tem; 7830 7831 gen_reload (out, op0, opnum, type); 7832 7833 /* If OP0 and OP1 are the same, we can use OUT for OP1. 7834 This fixes a problem on the 32K where the stack pointer cannot 7835 be used as an operand of an add insn. */ 7836 7837 if (rtx_equal_p (op0, op1)) 7838 op1 = out; 7839 7840 insn = emit_insn (gen_add2_insn (out, op1)); 7841 7842 /* If that failed, copy the address register to the reload register. 7843 Then add the constant to the reload register. */ 7844 7845 code = recog_memoized (insn); 7846 7847 if (code >= 0) 7848 { 7849 extract_insn (insn); 7850 /* We want constrain operands to treat this insn strictly in 7851 its validity determination, i.e., the way it would after reload 7852 has completed. */ 7853 if (constrain_operands (1)) 7854 { 7855 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ 7856 REG_NOTES (insn) 7857 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); 7858 return insn; 7859 } 7860 } 7861 7862 delete_insns_since (last); 7863 7864 gen_reload (out, op1, opnum, type); 7865 insn = emit_insn (gen_add2_insn (out, op0)); 7866 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); 7867 } 7868 7869#ifdef SECONDARY_MEMORY_NEEDED 7870 /* If we need a memory location to do the move, do it that way. */ 7871 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER 7872 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER 7873 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), 7874 REGNO_REG_CLASS (REGNO (out)), 7875 GET_MODE (out))) 7876 { 7877 /* Get the memory to use and rewrite both registers to its mode. */ 7878 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); 7879 7880 if (GET_MODE (loc) != GET_MODE (out)) 7881 out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); 7882 7883 if (GET_MODE (loc) != GET_MODE (in)) 7884 in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); 7885 7886 gen_reload (loc, in, opnum, type); 7887 gen_reload (out, loc, opnum, type); 7888 } 7889#endif 7890 7891 /* If IN is a simple operand, use gen_move_insn. */ 7892 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) 7893 emit_insn (gen_move_insn (out, in)); 7894 7895#ifdef HAVE_reload_load_address 7896 else if (HAVE_reload_load_address) 7897 emit_insn (gen_reload_load_address (out, in)); 7898#endif 7899 7900 /* Otherwise, just write (set OUT IN) and hope for the best. */ 7901 else 7902 emit_insn (gen_rtx_SET (VOIDmode, out, in)); 7903 7904 /* Return the first insn emitted. 7905 We can not just return get_last_insn, because there may have 7906 been multiple instructions emitted. Also note that gen_move_insn may 7907 emit more than one insn itself, so we can not assume that there is one 7908 insn emitted per emit_insn_before call. */ 7909 7910 return last ? NEXT_INSN (last) : get_insns (); 7911} 7912 7913/* Delete a previously made output-reload 7914 whose result we now believe is not needed. 7915 First we double-check. 7916 7917 INSN is the insn now being processed. 7918 LAST_RELOAD_REG is the hard register number for which we want to delete 7919 the last output reload. 7920 J is the reload-number that originally used REG. The caller has made 7921 certain that reload J doesn't use REG any longer for input. */ 7922 7923static void 7924delete_output_reload (insn, j, last_reload_reg) 7925 rtx insn; 7926 int j; 7927 int last_reload_reg; 7928{ 7929 rtx output_reload_insn = spill_reg_store[last_reload_reg]; 7930 rtx reg = spill_reg_stored_to[last_reload_reg]; 7931 int k; 7932 int n_occurrences; 7933 int n_inherited = 0; 7934 register rtx i1; 7935 rtx substed; 7936 7937 /* Get the raw pseudo-register referred to. */ 7938 7939 while (GET_CODE (reg) == SUBREG) 7940 reg = SUBREG_REG (reg); 7941 substed = reg_equiv_memory_loc[REGNO (reg)]; 7942 7943 /* This is unsafe if the operand occurs more often in the current 7944 insn than it is inherited. */ 7945 for (k = n_reloads - 1; k >= 0; k--) 7946 { 7947 rtx reg2 = reload_in[k]; 7948 if (! reg2) 7949 continue; 7950 if (GET_CODE (reg2) == MEM || reload_override_in[k]) 7951 reg2 = reload_in_reg[k]; 7952#ifdef AUTO_INC_DEC 7953 if (reload_out[k] && ! reload_out_reg[k]) 7954 reg2 = XEXP (reload_in_reg[k], 0); 7955#endif 7956 while (GET_CODE (reg2) == SUBREG) 7957 reg2 = SUBREG_REG (reg2); 7958 if (rtx_equal_p (reg2, reg)) 7959 { 7960 if (reload_inherited[k] || reload_override_in[k] || k == j) 7961 { 7962 n_inherited++; 7963 reg2 = reload_out_reg[k]; 7964 if (! reg2) 7965 continue; 7966 while (GET_CODE (reg2) == SUBREG) 7967 reg2 = XEXP (reg2, 0); 7968 if (rtx_equal_p (reg2, reg)) 7969 n_inherited++; 7970 } 7971 else 7972 return; 7973 } 7974 } 7975 n_occurrences = count_occurrences (PATTERN (insn), reg); 7976 if (substed) 7977 n_occurrences += count_occurrences (PATTERN (insn), substed); 7978 if (n_occurrences > n_inherited) 7979 return; 7980 7981 /* If the pseudo-reg we are reloading is no longer referenced 7982 anywhere between the store into it and here, 7983 and no jumps or labels intervene, then the value can get 7984 here through the reload reg alone. 7985 Otherwise, give up--return. */ 7986 for (i1 = NEXT_INSN (output_reload_insn); 7987 i1 != insn; i1 = NEXT_INSN (i1)) 7988 { 7989 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) 7990 return; 7991 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) 7992 && reg_mentioned_p (reg, PATTERN (i1))) 7993 { 7994 /* If this is USE in front of INSN, we only have to check that 7995 there are no more references than accounted for by inheritance. */ 7996 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE) 7997 { 7998 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; 7999 i1 = NEXT_INSN (i1); 8000 } 8001 if (n_occurrences <= n_inherited && i1 == insn) 8002 break; 8003 return; 8004 } 8005 } 8006 8007 /* The caller has already checked that REG dies or is set in INSN. 8008 It has also checked that we are optimizing, and thus some inaccurancies 8009 in the debugging information are acceptable. 8010 So we could just delete output_reload_insn. 8011 But in some cases we can improve the debugging information without 8012 sacrificing optimization - maybe even improving the code: 8013 See if the pseudo reg has been completely replaced 8014 with reload regs. If so, delete the store insn 8015 and forget we had a stack slot for the pseudo. */ 8016 if (reload_out[j] != reload_in[j] 8017 && REG_N_DEATHS (REGNO (reg)) == 1 8018 && REG_N_SETS (REGNO (reg)) == 1 8019 && REG_BASIC_BLOCK (REGNO (reg)) >= 0 8020 && find_regno_note (insn, REG_DEAD, REGNO (reg))) 8021 { 8022 rtx i2; 8023 8024 /* We know that it was used only between here 8025 and the beginning of the current basic block. 8026 (We also know that the last use before INSN was 8027 the output reload we are thinking of deleting, but never mind that.) 8028 Search that range; see if any ref remains. */ 8029 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) 8030 { 8031 rtx set = single_set (i2); 8032 8033 /* Uses which just store in the pseudo don't count, 8034 since if they are the only uses, they are dead. */ 8035 if (set != 0 && SET_DEST (set) == reg) 8036 continue; 8037 if (GET_CODE (i2) == CODE_LABEL 8038 || GET_CODE (i2) == JUMP_INSN) 8039 break; 8040 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) 8041 && reg_mentioned_p (reg, PATTERN (i2))) 8042 { 8043 /* Some other ref remains; just delete the output reload we 8044 know to be dead. */ 8045 delete_address_reloads (output_reload_insn, insn); 8046 PUT_CODE (output_reload_insn, NOTE); 8047 NOTE_SOURCE_FILE (output_reload_insn) = 0; 8048 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED; 8049 return; 8050 } 8051 } 8052 8053 /* Delete the now-dead stores into this pseudo. */ 8054 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) 8055 { 8056 rtx set = single_set (i2); 8057 8058 if (set != 0 && SET_DEST (set) == reg) 8059 { 8060 delete_address_reloads (i2, insn); 8061 /* This might be a basic block head, 8062 thus don't use delete_insn. */ 8063 PUT_CODE (i2, NOTE); 8064 NOTE_SOURCE_FILE (i2) = 0; 8065 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; 8066 } 8067 if (GET_CODE (i2) == CODE_LABEL 8068 || GET_CODE (i2) == JUMP_INSN) 8069 break; 8070 } 8071 8072 /* For the debugging info, 8073 say the pseudo lives in this reload reg. */ 8074 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]); 8075 alter_reg (REGNO (reg), -1); 8076 } 8077 delete_address_reloads (output_reload_insn, insn); 8078 PUT_CODE (output_reload_insn, NOTE); 8079 NOTE_SOURCE_FILE (output_reload_insn) = 0; 8080 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED; 8081 8082} 8083 8084/* We are going to delete DEAD_INSN. Recursively delete loads of 8085 reload registers used in DEAD_INSN that are not used till CURRENT_INSN. 8086 CURRENT_INSN is being reloaded, so we have to check its reloads too. */ 8087static void 8088delete_address_reloads (dead_insn, current_insn) 8089 rtx dead_insn, current_insn; 8090{ 8091 rtx set = single_set (dead_insn); 8092 rtx set2, dst, prev, next; 8093 if (set) 8094 { 8095 rtx dst = SET_DEST (set); 8096 if (GET_CODE (dst) == MEM) 8097 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); 8098 } 8099 /* If we deleted the store from a reloaded post_{in,de}c expression, 8100 we can delete the matching adds. */ 8101 prev = PREV_INSN (dead_insn); 8102 next = NEXT_INSN (dead_insn); 8103 if (! prev || ! next) 8104 return; 8105 set = single_set (next); 8106 set2 = single_set (prev); 8107 if (! set || ! set2 8108 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS 8109 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT 8110 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) 8111 return; 8112 dst = SET_DEST (set); 8113 if (! rtx_equal_p (dst, SET_DEST (set2)) 8114 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) 8115 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) 8116 || (INTVAL (XEXP (SET_SRC (set), 1)) 8117 != - INTVAL (XEXP (SET_SRC (set2), 1)))) 8118 return; 8119 delete_insn (prev); 8120 delete_insn (next); 8121} 8122 8123/* Subfunction of delete_address_reloads: process registers found in X. */ 8124static void 8125delete_address_reloads_1 (dead_insn, x, current_insn) 8126 rtx dead_insn, x, current_insn; 8127{ 8128 rtx prev, set, dst, i2; 8129 int i, j; 8130 enum rtx_code code = GET_CODE (x); 8131 8132 if (code != REG) 8133 { 8134 char *fmt= GET_RTX_FORMAT (code); 8135 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 8136 { 8137 if (fmt[i] == 'e') 8138 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); 8139 else if (fmt[i] == 'E') 8140 { 8141 for (j = XVECLEN (x, i) - 1; j >=0; j--) 8142 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), 8143 current_insn); 8144 } 8145 } 8146 return; 8147 } 8148 8149 if (spill_reg_order[REGNO (x)] < 0) 8150 return; 8151 8152 /* Scan backwards for the insn that sets x. This might be a way back due 8153 to inheritance. */ 8154 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) 8155 { 8156 code = GET_CODE (prev); 8157 if (code == CODE_LABEL || code == JUMP_INSN) 8158 return; 8159 if (GET_RTX_CLASS (code) != 'i') 8160 continue; 8161 if (reg_set_p (x, PATTERN (prev))) 8162 break; 8163 if (reg_referenced_p (x, PATTERN (prev))) 8164 return; 8165 } 8166 if (! prev || INSN_UID (prev) < reload_first_uid) 8167 return; 8168 /* Check that PREV only sets the reload register. */ 8169 set = single_set (prev); 8170 if (! set) 8171 return; 8172 dst = SET_DEST (set); 8173 if (GET_CODE (dst) != REG 8174 || ! rtx_equal_p (dst, x)) 8175 return; 8176 if (! reg_set_p (dst, PATTERN (dead_insn))) 8177 { 8178 /* Check if DST was used in a later insn - 8179 it might have been inherited. */ 8180 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) 8181 { 8182 if (GET_CODE (i2) == CODE_LABEL) 8183 break; 8184 if (GET_RTX_CLASS (GET_CODE (i2)) != 'i') 8185 continue; 8186 if (reg_referenced_p (dst, PATTERN (i2))) 8187 { 8188 /* If there is a reference to the register in the current insn, 8189 it might be loaded in a non-inherited reload. If no other 8190 reload uses it, that means the register is set before 8191 referenced. */ 8192 if (i2 == current_insn) 8193 { 8194 for (j = n_reloads - 1; j >= 0; j--) 8195 if ((reload_reg_rtx[j] == dst && reload_inherited[j]) 8196 || reload_override_in[j] == dst) 8197 return; 8198 for (j = n_reloads - 1; j >= 0; j--) 8199 if (reload_in[j] && reload_reg_rtx[j] == dst) 8200 break; 8201 if (j >= 0) 8202 break; 8203 } 8204 return; 8205 } 8206 if (GET_CODE (i2) == JUMP_INSN) 8207 break; 8208 /* If DST is still live at CURRENT_INSN, check if it is used for 8209 any reload. Note that even if CURRENT_INSN sets DST, we still 8210 have to check the reloads. */ 8211 if (i2 == current_insn) 8212 { 8213 for (j = n_reloads - 1; j >= 0; j--) 8214 if ((reload_reg_rtx[j] == dst && reload_inherited[j]) 8215 || reload_override_in[j] == dst) 8216 return; 8217 /* ??? We can't finish the loop here, because dst might be 8218 allocated to a pseudo in this block if no reload in this 8219 block needs any of the clsses containing DST - see 8220 spill_hard_reg. There is no easy way to tell this, so we 8221 have to scan till the end of the basic block. */ 8222 } 8223 if (reg_set_p (dst, PATTERN (i2))) 8224 break; 8225 } 8226 } 8227 delete_address_reloads_1 (prev, SET_SRC (set), current_insn); 8228 reg_reloaded_contents[REGNO (dst)] = -1; 8229 /* Can't use delete_insn here because PREV might be a basic block head. */ 8230 PUT_CODE (prev, NOTE); 8231 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED; 8232 NOTE_SOURCE_FILE (prev) = 0; 8233} 8234 8235/* Output reload-insns to reload VALUE into RELOADREG. 8236 VALUE is an autoincrement or autodecrement RTX whose operand 8237 is a register or memory location; 8238 so reloading involves incrementing that location. 8239 IN is either identical to VALUE, or some cheaper place to reload from. 8240 8241 INC_AMOUNT is the number to increment or decrement by (always positive). 8242 This cannot be deduced from VALUE. 8243 8244 Return the instruction that stores into RELOADREG. */ 8245 8246static rtx 8247inc_for_reload (reloadreg, in, value, inc_amount) 8248 rtx reloadreg; 8249 rtx in, value; 8250 int inc_amount; 8251{ 8252 /* REG or MEM to be copied and incremented. */ 8253 rtx incloc = XEXP (value, 0); 8254 /* Nonzero if increment after copying. */ 8255 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); 8256 rtx last; 8257 rtx inc; 8258 rtx add_insn; 8259 int code; 8260 rtx store; 8261 rtx real_in = in == value ? XEXP (in, 0) : in; 8262 8263 /* No hard register is equivalent to this register after 8264 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, 8265 we could inc/dec that register as well (maybe even using it for 8266 the source), but I'm not sure it's worth worrying about. */ 8267 if (GET_CODE (incloc) == REG) 8268 reg_last_reload_reg[REGNO (incloc)] = 0; 8269 8270 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) 8271 inc_amount = - inc_amount; 8272 8273 inc = GEN_INT (inc_amount); 8274 8275 /* If this is post-increment, first copy the location to the reload reg. */ 8276 if (post && real_in != reloadreg) 8277 emit_insn (gen_move_insn (reloadreg, real_in)); 8278 8279 if (in == value) 8280 { 8281 /* See if we can directly increment INCLOC. Use a method similar to 8282 that in gen_reload. */ 8283 8284 last = get_last_insn (); 8285 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, 8286 gen_rtx_PLUS (GET_MODE (incloc), 8287 incloc, inc))); 8288 8289 code = recog_memoized (add_insn); 8290 if (code >= 0) 8291 { 8292 extract_insn (add_insn); 8293 if (constrain_operands (1)) 8294 { 8295 /* If this is a pre-increment and we have incremented the value 8296 where it lives, copy the incremented value to RELOADREG to 8297 be used as an address. */ 8298 8299 if (! post) 8300 emit_insn (gen_move_insn (reloadreg, incloc)); 8301 8302 return add_insn; 8303 } 8304 } 8305 delete_insns_since (last); 8306 } 8307 8308 /* If couldn't do the increment directly, must increment in RELOADREG. 8309 The way we do this depends on whether this is pre- or post-increment. 8310 For pre-increment, copy INCLOC to the reload register, increment it 8311 there, then save back. */ 8312 8313 if (! post) 8314 { 8315 if (in != reloadreg) 8316 emit_insn (gen_move_insn (reloadreg, real_in)); 8317 emit_insn (gen_add2_insn (reloadreg, inc)); 8318 store = emit_insn (gen_move_insn (incloc, reloadreg)); 8319 } 8320 else 8321 { 8322 /* Postincrement. 8323 Because this might be a jump insn or a compare, and because RELOADREG 8324 may not be available after the insn in an input reload, we must do 8325 the incrementation before the insn being reloaded for. 8326 8327 We have already copied IN to RELOADREG. Increment the copy in 8328 RELOADREG, save that back, then decrement RELOADREG so it has 8329 the original value. */ 8330 8331 emit_insn (gen_add2_insn (reloadreg, inc)); 8332 store = emit_insn (gen_move_insn (incloc, reloadreg)); 8333 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); 8334 } 8335 8336 return store; 8337} 8338 8339/* Return 1 if we are certain that the constraint-string STRING allows 8340 the hard register REG. Return 0 if we can't be sure of this. */ 8341 8342static int 8343constraint_accepts_reg_p (string, reg) 8344 const char *string; 8345 rtx reg; 8346{ 8347 int value = 0; 8348 int regno = true_regnum (reg); 8349 int c; 8350 8351 /* Initialize for first alternative. */ 8352 value = 0; 8353 /* Check that each alternative contains `g' or `r'. */ 8354 while (1) 8355 switch (c = *string++) 8356 { 8357 case 0: 8358 /* If an alternative lacks `g' or `r', we lose. */ 8359 return value; 8360 case ',': 8361 /* If an alternative lacks `g' or `r', we lose. */ 8362 if (value == 0) 8363 return 0; 8364 /* Initialize for next alternative. */ 8365 value = 0; 8366 break; 8367 case 'g': 8368 case 'r': 8369 /* Any general reg wins for this alternative. */ 8370 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) 8371 value = 1; 8372 break; 8373 default: 8374 /* Any reg in specified class wins for this alternative. */ 8375 { 8376 enum reg_class class = REG_CLASS_FROM_LETTER (c); 8377 8378 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)) 8379 value = 1; 8380 } 8381 } 8382} 8383 8384/* Return the number of places FIND appears within X, but don't count 8385 an occurrence if some SET_DEST is FIND. */ 8386 8387int 8388count_occurrences (x, find) 8389 register rtx x, find; 8390{ 8391 register int i, j; 8392 register enum rtx_code code; 8393 register char *format_ptr; 8394 int count; 8395 8396 if (x == find) 8397 return 1; 8398 if (x == 0) 8399 return 0; 8400 8401 code = GET_CODE (x); 8402 8403 switch (code) 8404 { 8405 case REG: 8406 case QUEUED: 8407 case CONST_INT: 8408 case CONST_DOUBLE: 8409 case SYMBOL_REF: 8410 case CODE_LABEL: 8411 case PC: 8412 case CC0: 8413 return 0; 8414 8415 case MEM: 8416 if (GET_CODE (find) == MEM && rtx_equal_p (x, find)) 8417 return 1; 8418 break; 8419 case SET: 8420 if (SET_DEST (x) == find) 8421 return count_occurrences (SET_SRC (x), find); 8422 break; 8423 8424 default: 8425 break; 8426 } 8427 8428 format_ptr = GET_RTX_FORMAT (code); 8429 count = 0; 8430 8431 for (i = 0; i < GET_RTX_LENGTH (code); i++) 8432 { 8433 switch (*format_ptr++) 8434 { 8435 case 'e': 8436 count += count_occurrences (XEXP (x, i), find); 8437 break; 8438 8439 case 'E': 8440 if (XVEC (x, i) != NULL) 8441 { 8442 for (j = 0; j < XVECLEN (x, i); j++) 8443 count += count_occurrences (XVECEXP (x, i, j), find); 8444 } 8445 break; 8446 } 8447 } 8448 return count; 8449} 8450 8451/* This array holds values which are equivalent to a hard register 8452 during reload_cse_regs. Each array element is an EXPR_LIST of 8453 values. Each time a hard register is set, we set the corresponding 8454 array element to the value. Each time a hard register is copied 8455 into memory, we add the memory location to the corresponding array 8456 element. We don't store values or memory addresses with side 8457 effects in this array. 8458 8459 If the value is a CONST_INT, then the mode of the containing 8460 EXPR_LIST is the mode in which that CONST_INT was referenced. 8461 8462 We sometimes clobber a specific entry in a list. In that case, we 8463 just set XEXP (list-entry, 0) to 0. */ 8464 8465static rtx *reg_values; 8466 8467/* This is a preallocated REG rtx which we use as a temporary in 8468 reload_cse_invalidate_regno, so that we don't need to allocate a 8469 new one each time through a loop in that function. */ 8470 8471static rtx invalidate_regno_rtx; 8472 8473/* Invalidate any entries in reg_values which depend on REGNO, 8474 including those for REGNO itself. This is called if REGNO is 8475 changing. If CLOBBER is true, then always forget anything we 8476 currently know about REGNO. MODE is the mode of the assignment to 8477 REGNO, which is used to determine how many hard registers are being 8478 changed. If MODE is VOIDmode, then only REGNO is being changed; 8479 this is used when invalidating call clobbered registers across a 8480 call. */ 8481 8482static void 8483reload_cse_invalidate_regno (regno, mode, clobber) 8484 int regno; 8485 enum machine_mode mode; 8486 int clobber; 8487{ 8488 int endregno; 8489 register int i; 8490 8491 /* Our callers don't always go through true_regnum; we may see a 8492 pseudo-register here from a CLOBBER or the like. We probably 8493 won't ever see a pseudo-register that has a real register number, 8494 for we check anyhow for safety. */ 8495 if (regno >= FIRST_PSEUDO_REGISTER) 8496 regno = reg_renumber[regno]; 8497 if (regno < 0) 8498 return; 8499 8500 if (mode == VOIDmode) 8501 endregno = regno + 1; 8502 else 8503 endregno = regno + HARD_REGNO_NREGS (regno, mode); 8504 8505 if (clobber) 8506 for (i = regno; i < endregno; i++) 8507 reg_values[i] = 0; 8508 8509 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8510 { 8511 rtx x; 8512 8513 for (x = reg_values[i]; x; x = XEXP (x, 1)) 8514 { 8515 if (XEXP (x, 0) != 0 8516 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR)) 8517 { 8518 /* If this is the only entry on the list, clear 8519 reg_values[i]. Otherwise, just clear this entry on 8520 the list. */ 8521 if (XEXP (x, 1) == 0 && x == reg_values[i]) 8522 { 8523 reg_values[i] = 0; 8524 break; 8525 } 8526 XEXP (x, 0) = 0; 8527 } 8528 } 8529 } 8530 8531 /* We must look at earlier registers, in case REGNO is part of a 8532 multi word value but is not the first register. If an earlier 8533 register has a value in a mode which overlaps REGNO, then we must 8534 invalidate that earlier register. Note that we do not need to 8535 check REGNO or later registers (we must not check REGNO itself, 8536 because we would incorrectly conclude that there was a conflict). */ 8537 8538 for (i = 0; i < regno; i++) 8539 { 8540 rtx x; 8541 8542 for (x = reg_values[i]; x; x = XEXP (x, 1)) 8543 { 8544 if (XEXP (x, 0) != 0) 8545 { 8546 PUT_MODE (invalidate_regno_rtx, GET_MODE (x)); 8547 REGNO (invalidate_regno_rtx) = i; 8548 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx, 8549 NULL_PTR)) 8550 { 8551 reload_cse_invalidate_regno (i, VOIDmode, 1); 8552 break; 8553 } 8554 } 8555 } 8556 } 8557} 8558 8559/* The memory at address MEM_BASE is being changed. 8560 Return whether this change will invalidate VAL. */ 8561 8562static int 8563reload_cse_mem_conflict_p (mem_base, val) 8564 rtx mem_base; 8565 rtx val; 8566{ 8567 enum rtx_code code; 8568 char *fmt; 8569 int i; 8570 8571 code = GET_CODE (val); 8572 switch (code) 8573 { 8574 /* Get rid of a few simple cases quickly. */ 8575 case REG: 8576 case PC: 8577 case CC0: 8578 case SCRATCH: 8579 case CONST: 8580 case CONST_INT: 8581 case CONST_DOUBLE: 8582 case SYMBOL_REF: 8583 case LABEL_REF: 8584 return 0; 8585 8586 case MEM: 8587 if (GET_MODE (mem_base) == BLKmode 8588 || GET_MODE (val) == BLKmode) 8589 return 1; 8590 if (anti_dependence (val, mem_base)) 8591 return 1; 8592 /* The address may contain nested MEMs. */ 8593 break; 8594 8595 default: 8596 break; 8597 } 8598 8599 fmt = GET_RTX_FORMAT (code); 8600 8601 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 8602 { 8603 if (fmt[i] == 'e') 8604 { 8605 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i))) 8606 return 1; 8607 } 8608 else if (fmt[i] == 'E') 8609 { 8610 int j; 8611 8612 for (j = 0; j < XVECLEN (val, i); j++) 8613 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j))) 8614 return 1; 8615 } 8616 } 8617 8618 return 0; 8619} 8620 8621/* Invalidate any entries in reg_values which are changed because of a 8622 store to MEM_RTX. If this is called because of a non-const call 8623 instruction, MEM_RTX is (mem:BLK const0_rtx). */ 8624 8625static void 8626reload_cse_invalidate_mem (mem_rtx) 8627 rtx mem_rtx; 8628{ 8629 register int i; 8630 8631 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8632 { 8633 rtx x; 8634 8635 for (x = reg_values[i]; x; x = XEXP (x, 1)) 8636 { 8637 if (XEXP (x, 0) != 0 8638 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0))) 8639 { 8640 /* If this is the only entry on the list, clear 8641 reg_values[i]. Otherwise, just clear this entry on 8642 the list. */ 8643 if (XEXP (x, 1) == 0 && x == reg_values[i]) 8644 { 8645 reg_values[i] = 0; 8646 break; 8647 } 8648 XEXP (x, 0) = 0; 8649 } 8650 } 8651 } 8652} 8653 8654/* Invalidate DEST, which is being assigned to or clobbered. The 8655 second parameter exists so that this function can be passed to 8656 note_stores; it is ignored. */ 8657 8658static void 8659reload_cse_invalidate_rtx (dest, ignore) 8660 rtx dest; 8661 rtx ignore ATTRIBUTE_UNUSED; 8662{ 8663 while (GET_CODE (dest) == STRICT_LOW_PART 8664 || GET_CODE (dest) == SIGN_EXTRACT 8665 || GET_CODE (dest) == ZERO_EXTRACT 8666 || GET_CODE (dest) == SUBREG) 8667 dest = XEXP (dest, 0); 8668 8669 if (GET_CODE (dest) == REG) 8670 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1); 8671 else if (GET_CODE (dest) == MEM) 8672 reload_cse_invalidate_mem (dest); 8673} 8674 8675/* Do a very simple CSE pass over the hard registers. 8676 8677 This function detects no-op moves where we happened to assign two 8678 different pseudo-registers to the same hard register, and then 8679 copied one to the other. Reload will generate a useless 8680 instruction copying a register to itself. 8681 8682 This function also detects cases where we load a value from memory 8683 into two different registers, and (if memory is more expensive than 8684 registers) changes it to simply copy the first register into the 8685 second register. 8686 8687 Another optimization is performed that scans the operands of each 8688 instruction to see whether the value is already available in a 8689 hard register. It then replaces the operand with the hard register 8690 if possible, much like an optional reload would. */ 8691 8692static void 8693reload_cse_regs_1 (first) 8694 rtx first; 8695{ 8696 char *firstobj; 8697 rtx callmem; 8698 register int i; 8699 rtx insn; 8700 8701 init_alias_analysis (); 8702 8703 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx)); 8704 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx)); 8705 8706 /* Create our EXPR_LIST structures on reload_obstack, so that we can 8707 free them when we are done. */ 8708 push_obstacks (&reload_obstack, &reload_obstack); 8709 firstobj = (char *) obstack_alloc (&reload_obstack, 0); 8710 8711 /* We pass this to reload_cse_invalidate_mem to invalidate all of 8712 memory for a non-const call instruction. */ 8713 callmem = gen_rtx_MEM (BLKmode, const0_rtx); 8714 8715 /* This is used in reload_cse_invalidate_regno to avoid consing a 8716 new REG in a loop in that function. */ 8717 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0); 8718 8719 for (insn = first; insn; insn = NEXT_INSN (insn)) 8720 { 8721 rtx body; 8722 8723 if (GET_CODE (insn) == CODE_LABEL) 8724 { 8725 /* Forget all the register values at a code label. We don't 8726 try to do anything clever around jumps. */ 8727 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8728 reg_values[i] = 0; 8729 8730 continue; 8731 } 8732 8733#ifdef NON_SAVING_SETJMP 8734 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE 8735 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP) 8736 { 8737 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8738 reg_values[i] = 0; 8739 8740 continue; 8741 } 8742#endif 8743 8744 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') 8745 continue; 8746 8747 /* If this is a call instruction, forget anything stored in a 8748 call clobbered register, or, if this is not a const call, in 8749 memory. */ 8750 if (GET_CODE (insn) == CALL_INSN) 8751 { 8752 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8753 if (call_used_regs[i]) 8754 reload_cse_invalidate_regno (i, VOIDmode, 1); 8755 8756 if (! CONST_CALL_P (insn)) 8757 reload_cse_invalidate_mem (callmem); 8758 } 8759 8760 8761 /* Forget all the register values at a volatile asm. */ 8762 if (GET_CODE (insn) == INSN 8763 && GET_CODE (PATTERN (insn)) == ASM_OPERANDS 8764 && MEM_VOLATILE_P (PATTERN (insn))) 8765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8766 reg_values[i] = 0; 8767 8768 body = PATTERN (insn); 8769 if (GET_CODE (body) == SET) 8770 { 8771 int count = 0; 8772 if (reload_cse_noop_set_p (body, insn)) 8773 { 8774 /* If this sets the return value of the function, we must keep 8775 a USE around, in case this is in a different basic block 8776 than the final USE. Otherwise, we could loose important 8777 register lifeness information on SMALL_REGISTER_CLASSES 8778 machines, where return registers might be used as spills: 8779 subsequent passes assume that spill registers are dead at 8780 the end of a basic block. */ 8781 if (REG_FUNCTION_VALUE_P (SET_DEST (body))) 8782 { 8783 pop_obstacks (); 8784 PATTERN (insn) = gen_rtx_USE (VOIDmode, SET_DEST (body)); 8785 INSN_CODE (insn) = -1; 8786 REG_NOTES (insn) = NULL_RTX; 8787 push_obstacks (&reload_obstack, &reload_obstack); 8788 } 8789 else 8790 { 8791 PUT_CODE (insn, NOTE); 8792 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 8793 NOTE_SOURCE_FILE (insn) = 0; 8794 } 8795 8796 /* We're done with this insn. */ 8797 continue; 8798 } 8799 8800 /* It's not a no-op, but we can try to simplify it. */ 8801 count += reload_cse_simplify_set (body, insn); 8802 8803 if (count > 0) 8804 apply_change_group (); 8805 else 8806 reload_cse_simplify_operands (insn); 8807 8808 reload_cse_record_set (body, body); 8809 } 8810 else if (GET_CODE (body) == PARALLEL) 8811 { 8812 int count = 0; 8813 rtx value = NULL_RTX; 8814 8815 /* If every action in a PARALLEL is a noop, we can delete 8816 the entire PARALLEL. */ 8817 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 8818 { 8819 rtx part = XVECEXP (body, 0, i); 8820 if (GET_CODE (part) == SET) 8821 { 8822 if (! reload_cse_noop_set_p (part, insn)) 8823 break; 8824 if (REG_FUNCTION_VALUE_P (SET_DEST (part))) 8825 { 8826 if (value) 8827 break; 8828 value = SET_DEST (part); 8829 } 8830 } 8831 else if (GET_CODE (part) != CLOBBER) 8832 break; 8833 } 8834 if (i < 0) 8835 { 8836 if (value) 8837 { 8838 pop_obstacks (); 8839 PATTERN (insn) = gen_rtx_USE (VOIDmode, value); 8840 INSN_CODE (insn) = -1; 8841 REG_NOTES (insn) = NULL_RTX; 8842 push_obstacks (&reload_obstack, &reload_obstack); 8843 } 8844 else 8845 { 8846 PUT_CODE (insn, NOTE); 8847 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 8848 NOTE_SOURCE_FILE (insn) = 0; 8849 } 8850 8851 /* We're done with this insn. */ 8852 continue; 8853 } 8854 8855 /* It's not a no-op, but we can try to simplify it. */ 8856 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 8857 if (GET_CODE (XVECEXP (body, 0, i)) == SET) 8858 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); 8859 8860 if (count > 0) 8861 apply_change_group (); 8862 else 8863 reload_cse_simplify_operands (insn); 8864 8865 /* Look through the PARALLEL and record the values being 8866 set, if possible. Also handle any CLOBBERs. */ 8867 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 8868 { 8869 rtx x = XVECEXP (body, 0, i); 8870 8871 if (GET_CODE (x) == SET) 8872 reload_cse_record_set (x, body); 8873 else 8874 note_stores (x, reload_cse_invalidate_rtx); 8875 } 8876 } 8877 else 8878 note_stores (body, reload_cse_invalidate_rtx); 8879 8880#ifdef AUTO_INC_DEC 8881 /* Clobber any registers which appear in REG_INC notes. We 8882 could keep track of the changes to their values, but it is 8883 unlikely to help. */ 8884 { 8885 rtx x; 8886 8887 for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) 8888 if (REG_NOTE_KIND (x) == REG_INC) 8889 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX); 8890 } 8891#endif 8892 8893 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only 8894 after we have processed the insn. */ 8895 if (GET_CODE (insn) == CALL_INSN) 8896 { 8897 rtx x; 8898 8899 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1)) 8900 if (GET_CODE (XEXP (x, 0)) == CLOBBER) 8901 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX); 8902 } 8903 } 8904 8905 /* Free all the temporary structures we created, and go back to the 8906 regular obstacks. */ 8907 obstack_free (&reload_obstack, firstobj); 8908 pop_obstacks (); 8909} 8910 8911/* Call cse / combine like post-reload optimization phases. 8912 FIRST is the first instruction. */ 8913void 8914reload_cse_regs (first) 8915 rtx first; 8916{ 8917 reload_cse_regs_1 (first); 8918 reload_combine (); 8919 reload_cse_move2add (first); 8920 if (flag_expensive_optimizations) 8921 reload_cse_regs_1 (first); 8922} 8923 8924/* Return whether the values known for REGNO are equal to VAL. MODE 8925 is the mode of the object that VAL is being copied to; this matters 8926 if VAL is a CONST_INT. */ 8927 8928static int 8929reload_cse_regno_equal_p (regno, val, mode) 8930 int regno; 8931 rtx val; 8932 enum machine_mode mode; 8933{ 8934 rtx x; 8935 8936 if (val == 0) 8937 return 0; 8938 8939 for (x = reg_values[regno]; x; x = XEXP (x, 1)) 8940 if (XEXP (x, 0) != 0 8941 && rtx_equal_p (XEXP (x, 0), val) 8942 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM 8943 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT) 8944 && (GET_CODE (val) != CONST_INT 8945 || mode == GET_MODE (x) 8946 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x)) 8947 /* On a big endian machine if the value spans more than 8948 one register then this register holds the high part of 8949 it and we can't use it. 8950 8951 ??? We should also compare with the high part of the 8952 value. */ 8953 && !(WORDS_BIG_ENDIAN 8954 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) 8955 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 8956 GET_MODE_BITSIZE (GET_MODE (x)))))) 8957 return 1; 8958 8959 return 0; 8960} 8961 8962/* See whether a single set is a noop. SET is the set instruction we 8963 are should check, and INSN is the instruction from which it came. */ 8964 8965static int 8966reload_cse_noop_set_p (set, insn) 8967 rtx set; 8968 rtx insn; 8969{ 8970 rtx src, dest; 8971 enum machine_mode dest_mode; 8972 int dreg, sreg; 8973 int ret; 8974 8975 src = SET_SRC (set); 8976 dest = SET_DEST (set); 8977 dest_mode = GET_MODE (dest); 8978 8979 if (side_effects_p (src)) 8980 return 0; 8981 8982 dreg = true_regnum (dest); 8983 sreg = true_regnum (src); 8984 8985 /* Check for setting a register to itself. In this case, we don't 8986 have to worry about REG_DEAD notes. */ 8987 if (dreg >= 0 && dreg == sreg) 8988 return 1; 8989 8990 ret = 0; 8991 if (dreg >= 0) 8992 { 8993 /* Check for setting a register to itself. */ 8994 if (dreg == sreg) 8995 ret = 1; 8996 8997 /* Check for setting a register to a value which we already know 8998 is in the register. */ 8999 else if (reload_cse_regno_equal_p (dreg, src, dest_mode)) 9000 ret = 1; 9001 9002 /* Check for setting a register DREG to another register SREG 9003 where SREG is equal to a value which is already in DREG. */ 9004 else if (sreg >= 0) 9005 { 9006 rtx x; 9007 9008 for (x = reg_values[sreg]; x; x = XEXP (x, 1)) 9009 { 9010 rtx tmp; 9011 9012 if (XEXP (x, 0) == 0) 9013 continue; 9014 9015 if (dest_mode == GET_MODE (x)) 9016 tmp = XEXP (x, 0); 9017 else if (GET_MODE_BITSIZE (dest_mode) 9018 < GET_MODE_BITSIZE (GET_MODE (x))) 9019 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0)); 9020 else 9021 continue; 9022 9023 if (tmp 9024 && reload_cse_regno_equal_p (dreg, tmp, dest_mode)) 9025 { 9026 ret = 1; 9027 break; 9028 } 9029 } 9030 } 9031 } 9032 else if (GET_CODE (dest) == MEM) 9033 { 9034 /* Check for storing a register to memory when we know that the 9035 register is equivalent to the memory location. */ 9036 if (sreg >= 0 9037 && reload_cse_regno_equal_p (sreg, dest, dest_mode) 9038 && ! side_effects_p (dest)) 9039 ret = 1; 9040 } 9041 9042 return ret; 9043} 9044 9045/* Try to simplify a single SET instruction. SET is the set pattern. 9046 INSN is the instruction it came from. 9047 This function only handles one case: if we set a register to a value 9048 which is not a register, we try to find that value in some other register 9049 and change the set into a register copy. */ 9050 9051static int 9052reload_cse_simplify_set (set, insn) 9053 rtx set; 9054 rtx insn; 9055{ 9056 int dreg; 9057 rtx src; 9058 enum machine_mode dest_mode; 9059 enum reg_class dclass; 9060 register int i; 9061 9062 dreg = true_regnum (SET_DEST (set)); 9063 if (dreg < 0) 9064 return 0; 9065 9066 src = SET_SRC (set); 9067 if (side_effects_p (src) || true_regnum (src) >= 0) 9068 return 0; 9069 9070 dclass = REGNO_REG_CLASS (dreg); 9071 9072 /* If memory loads are cheaper than register copies, don't change them. */ 9073 if (GET_CODE (src) == MEM 9074 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2) 9075 return 0; 9076 9077 /* If the constant is cheaper than a register, don't change it. */ 9078 if (CONSTANT_P (src) 9079 && rtx_cost (src, SET) < 2) 9080 return 0; 9081 9082 dest_mode = GET_MODE (SET_DEST (set)); 9083 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 9084 { 9085 if (i != dreg 9086 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2 9087 && reload_cse_regno_equal_p (i, src, dest_mode)) 9088 { 9089 int validated; 9090 9091 /* Pop back to the real obstacks while changing the insn. */ 9092 pop_obstacks (); 9093 9094 validated = validate_change (insn, &SET_SRC (set), 9095 gen_rtx_REG (dest_mode, i), 1); 9096 9097 /* Go back to the obstack we are using for temporary 9098 storage. */ 9099 push_obstacks (&reload_obstack, &reload_obstack); 9100 9101 if (validated) 9102 return 1; 9103 } 9104 } 9105 return 0; 9106} 9107 9108/* Try to replace operands in INSN with equivalent values that are already 9109 in registers. This can be viewed as optional reloading. 9110 9111 For each non-register operand in the insn, see if any hard regs are 9112 known to be equivalent to that operand. Record the alternatives which 9113 can accept these hard registers. Among all alternatives, select the 9114 ones which are better or equal to the one currently matching, where 9115 "better" is in terms of '?' and '!' constraints. Among the remaining 9116 alternatives, select the one which replaces most operands with 9117 hard registers. */ 9118 9119static int 9120reload_cse_simplify_operands (insn) 9121 rtx insn; 9122{ 9123#ifdef REGISTER_CONSTRAINTS 9124 int i,j; 9125 9126 const char *constraints[MAX_RECOG_OPERANDS]; 9127 9128 /* Vector recording how bad an alternative is. */ 9129 int *alternative_reject; 9130 /* Vector recording how many registers can be introduced by choosing 9131 this alternative. */ 9132 int *alternative_nregs; 9133 /* Array of vectors recording, for each operand and each alternative, 9134 which hard register to substitute, or -1 if the operand should be 9135 left as it is. */ 9136 int *op_alt_regno[MAX_RECOG_OPERANDS]; 9137 /* Array of alternatives, sorted in order of decreasing desirability. */ 9138 int *alternative_order; 9139 rtx reg = gen_rtx_REG (VOIDmode, -1); 9140 9141 extract_insn (insn); 9142 9143 if (recog_n_alternatives == 0 || recog_n_operands == 0) 9144 return 0; 9145 9146 /* Figure out which alternative currently matches. */ 9147 if (! constrain_operands (1)) 9148 fatal_insn_not_found (insn); 9149 9150 alternative_reject = (int *) alloca (recog_n_alternatives * sizeof (int)); 9151 alternative_nregs = (int *) alloca (recog_n_alternatives * sizeof (int)); 9152 alternative_order = (int *) alloca (recog_n_alternatives * sizeof (int)); 9153 bzero ((char *)alternative_reject, recog_n_alternatives * sizeof (int)); 9154 bzero ((char *)alternative_nregs, recog_n_alternatives * sizeof (int)); 9155 9156 for (i = 0; i < recog_n_operands; i++) 9157 { 9158 enum machine_mode mode; 9159 int regno; 9160 const char *p; 9161 9162 op_alt_regno[i] = (int *) alloca (recog_n_alternatives * sizeof (int)); 9163 for (j = 0; j < recog_n_alternatives; j++) 9164 op_alt_regno[i][j] = -1; 9165 9166 p = constraints[i] = recog_constraints[i]; 9167 mode = recog_operand_mode[i]; 9168 9169 /* Add the reject values for each alternative given by the constraints 9170 for this operand. */ 9171 j = 0; 9172 while (*p != '\0') 9173 { 9174 char c = *p++; 9175 if (c == ',') 9176 j++; 9177 else if (c == '?') 9178 alternative_reject[j] += 3; 9179 else if (c == '!') 9180 alternative_reject[j] += 300; 9181 } 9182 9183 /* We won't change operands which are already registers. We 9184 also don't want to modify output operands. */ 9185 regno = true_regnum (recog_operand[i]); 9186 if (regno >= 0 9187 || constraints[i][0] == '=' 9188 || constraints[i][0] == '+') 9189 continue; 9190 9191 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 9192 { 9193 int class = (int) NO_REGS; 9194 9195 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode)) 9196 continue; 9197 9198 REGNO (reg) = regno; 9199 PUT_MODE (reg, mode); 9200 9201 /* We found a register equal to this operand. Now look for all 9202 alternatives that can accept this register and have not been 9203 assigned a register they can use yet. */ 9204 j = 0; 9205 p = constraints[i]; 9206 for (;;) 9207 { 9208 char c = *p++; 9209 9210 switch (c) 9211 { 9212 case '=': case '+': case '?': 9213 case '#': case '&': case '!': 9214 case '*': case '%': 9215 case '0': case '1': case '2': case '3': case '4': 9216 case 'm': case '<': case '>': case 'V': case 'o': 9217 case 'E': case 'F': case 'G': case 'H': 9218 case 's': case 'i': case 'n': 9219 case 'I': case 'J': case 'K': case 'L': 9220 case 'M': case 'N': case 'O': case 'P': 9221#ifdef EXTRA_CONSTRAINT 9222 case 'Q': case 'R': case 'S': case 'T': case 'U': 9223#endif 9224 case 'p': case 'X': 9225 /* These don't say anything we care about. */ 9226 break; 9227 9228 case 'g': case 'r': 9229 class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; 9230 break; 9231 9232 default: 9233 class 9234 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)]; 9235 break; 9236 9237 case ',': case '\0': 9238 /* See if REGNO fits this alternative, and set it up as the 9239 replacement register if we don't have one for this 9240 alternative yet and the operand being replaced is not 9241 a cheap CONST_INT. */ 9242 if (op_alt_regno[i][j] == -1 9243 && reg_fits_class_p (reg, class, 0, mode) 9244 && (GET_CODE (recog_operand[i]) != CONST_INT 9245 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET))) 9246 { 9247 alternative_nregs[j]++; 9248 op_alt_regno[i][j] = regno; 9249 } 9250 j++; 9251 break; 9252 } 9253 9254 if (c == '\0') 9255 break; 9256 } 9257 } 9258 } 9259 9260 /* Record all alternatives which are better or equal to the currently 9261 matching one in the alternative_order array. */ 9262 for (i = j = 0; i < recog_n_alternatives; i++) 9263 if (alternative_reject[i] <= alternative_reject[which_alternative]) 9264 alternative_order[j++] = i; 9265 recog_n_alternatives = j; 9266 9267 /* Sort it. Given a small number of alternatives, a dumb algorithm 9268 won't hurt too much. */ 9269 for (i = 0; i < recog_n_alternatives - 1; i++) 9270 { 9271 int best = i; 9272 int best_reject = alternative_reject[alternative_order[i]]; 9273 int best_nregs = alternative_nregs[alternative_order[i]]; 9274 int tmp; 9275 9276 for (j = i + 1; j < recog_n_alternatives; j++) 9277 { 9278 int this_reject = alternative_reject[alternative_order[j]]; 9279 int this_nregs = alternative_nregs[alternative_order[j]]; 9280 9281 if (this_reject < best_reject 9282 || (this_reject == best_reject && this_nregs < best_nregs)) 9283 { 9284 best = j; 9285 best_reject = this_reject; 9286 best_nregs = this_nregs; 9287 } 9288 } 9289 9290 tmp = alternative_order[best]; 9291 alternative_order[best] = alternative_order[i]; 9292 alternative_order[i] = tmp; 9293 } 9294 9295 /* Substitute the operands as determined by op_alt_regno for the best 9296 alternative. */ 9297 j = alternative_order[0]; 9298 9299 /* Pop back to the real obstacks while changing the insn. */ 9300 pop_obstacks (); 9301 9302 for (i = 0; i < recog_n_operands; i++) 9303 { 9304 enum machine_mode mode = recog_operand_mode[i]; 9305 if (op_alt_regno[i][j] == -1) 9306 continue; 9307 9308 validate_change (insn, recog_operand_loc[i], 9309 gen_rtx_REG (mode, op_alt_regno[i][j]), 1); 9310 } 9311 9312 for (i = recog_n_dups - 1; i >= 0; i--) 9313 { 9314 int op = recog_dup_num[i]; 9315 enum machine_mode mode = recog_operand_mode[op]; 9316 9317 if (op_alt_regno[op][j] == -1) 9318 continue; 9319 9320 validate_change (insn, recog_dup_loc[i], 9321 gen_rtx_REG (mode, op_alt_regno[op][j]), 1); 9322 } 9323 9324 /* Go back to the obstack we are using for temporary 9325 storage. */ 9326 push_obstacks (&reload_obstack, &reload_obstack); 9327 9328 return apply_change_group (); 9329#else 9330 return 0; 9331#endif 9332} 9333 9334/* These two variables are used to pass information from 9335 reload_cse_record_set to reload_cse_check_clobber. */ 9336 9337static int reload_cse_check_clobbered; 9338static rtx reload_cse_check_src; 9339 9340/* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set 9341 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The 9342 second argument, which is passed by note_stores, is ignored. */ 9343 9344static void 9345reload_cse_check_clobber (dest, ignore) 9346 rtx dest; 9347 rtx ignore ATTRIBUTE_UNUSED; 9348{ 9349 if (reg_overlap_mentioned_p (dest, reload_cse_check_src)) 9350 reload_cse_check_clobbered = 1; 9351} 9352 9353/* Record the result of a SET instruction. SET is the set pattern. 9354 BODY is the pattern of the insn that it came from. */ 9355 9356static void 9357reload_cse_record_set (set, body) 9358 rtx set; 9359 rtx body; 9360{ 9361 rtx dest, src, x; 9362 int dreg, sreg; 9363 enum machine_mode dest_mode; 9364 9365 dest = SET_DEST (set); 9366 src = SET_SRC (set); 9367 dreg = true_regnum (dest); 9368 sreg = true_regnum (src); 9369 dest_mode = GET_MODE (dest); 9370 9371 /* Some machines don't define AUTO_INC_DEC, but they still use push 9372 instructions. We need to catch that case here in order to 9373 invalidate the stack pointer correctly. Note that invalidating 9374 the stack pointer is different from invalidating DEST. */ 9375 x = dest; 9376 while (GET_CODE (x) == SUBREG 9377 || GET_CODE (x) == ZERO_EXTRACT 9378 || GET_CODE (x) == SIGN_EXTRACT 9379 || GET_CODE (x) == STRICT_LOW_PART) 9380 x = XEXP (x, 0); 9381 if (push_operand (x, GET_MODE (x))) 9382 { 9383 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX); 9384 reload_cse_invalidate_rtx (dest, NULL_RTX); 9385 return; 9386 } 9387 9388 /* We can only handle an assignment to a register, or a store of a 9389 register to a memory location. For other cases, we just clobber 9390 the destination. We also have to just clobber if there are side 9391 effects in SRC or DEST. */ 9392 if ((dreg < 0 && GET_CODE (dest) != MEM) 9393 || side_effects_p (src) 9394 || side_effects_p (dest)) 9395 { 9396 reload_cse_invalidate_rtx (dest, NULL_RTX); 9397 return; 9398 } 9399 9400#ifdef HAVE_cc0 9401 /* We don't try to handle values involving CC, because it's a pain 9402 to keep track of when they have to be invalidated. */ 9403 if (reg_mentioned_p (cc0_rtx, src) 9404 || reg_mentioned_p (cc0_rtx, dest)) 9405 { 9406 reload_cse_invalidate_rtx (dest, NULL_RTX); 9407 return; 9408 } 9409#endif 9410 9411 /* If BODY is a PARALLEL, then we need to see whether the source of 9412 SET is clobbered by some other instruction in the PARALLEL. */ 9413 if (GET_CODE (body) == PARALLEL) 9414 { 9415 int i; 9416 9417 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 9418 { 9419 rtx x; 9420 9421 x = XVECEXP (body, 0, i); 9422 if (x == set) 9423 continue; 9424 9425 reload_cse_check_clobbered = 0; 9426 reload_cse_check_src = src; 9427 note_stores (x, reload_cse_check_clobber); 9428 if (reload_cse_check_clobbered) 9429 { 9430 reload_cse_invalidate_rtx (dest, NULL_RTX); 9431 return; 9432 } 9433 } 9434 } 9435 9436 if (dreg >= 0) 9437 { 9438 int i; 9439 9440 /* This is an assignment to a register. Update the value we 9441 have stored for the register. */ 9442 if (sreg >= 0) 9443 { 9444 rtx x; 9445 9446 /* This is a copy from one register to another. Any values 9447 which were valid for SREG are now valid for DREG. If the 9448 mode changes, we use gen_lowpart_common to extract only 9449 the part of the value that is copied. */ 9450 reg_values[dreg] = 0; 9451 for (x = reg_values[sreg]; x; x = XEXP (x, 1)) 9452 { 9453 rtx tmp; 9454 9455 if (XEXP (x, 0) == 0) 9456 continue; 9457 if (dest_mode == GET_MODE (XEXP (x, 0))) 9458 tmp = XEXP (x, 0); 9459 else if (GET_MODE_BITSIZE (dest_mode) 9460 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 9461 continue; 9462 else 9463 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0)); 9464 if (tmp) 9465 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp, 9466 reg_values[dreg]); 9467 } 9468 } 9469 else 9470 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX); 9471 9472 /* We've changed DREG, so invalidate any values held by other 9473 registers that depend upon it. */ 9474 reload_cse_invalidate_regno (dreg, dest_mode, 0); 9475 9476 /* If this assignment changes more than one hard register, 9477 forget anything we know about the others. */ 9478 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++) 9479 reg_values[dreg + i] = 0; 9480 } 9481 else if (GET_CODE (dest) == MEM) 9482 { 9483 /* Invalidate conflicting memory locations. */ 9484 reload_cse_invalidate_mem (dest); 9485 9486 /* If we're storing a register to memory, add DEST to the list 9487 in REG_VALUES. */ 9488 if (sreg >= 0 && ! side_effects_p (dest)) 9489 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest, 9490 reg_values[sreg]); 9491 } 9492 else 9493 { 9494 /* We should have bailed out earlier. */ 9495 abort (); 9496 } 9497} 9498 9499/* If reload couldn't use reg+reg+offset addressing, try to use reg+reg 9500 addressing now. 9501 This code might also be useful when reload gave up on reg+reg addresssing 9502 because of clashes between the return register and INDEX_REG_CLASS. */ 9503 9504/* The maximum number of uses of a register we can keep track of to 9505 replace them with reg+reg addressing. */ 9506#define RELOAD_COMBINE_MAX_USES 6 9507 9508/* INSN is the insn where a register has ben used, and USEP points to the 9509 location of the register within the rtl. */ 9510struct reg_use { rtx insn, *usep; }; 9511 9512/* If the register is used in some unknown fashion, USE_INDEX is negative. 9513 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID 9514 indicates where it becomes live again. 9515 Otherwise, USE_INDEX is the index of the last encountered use of the 9516 register (which is first among these we have seen since we scan backwards), 9517 OFFSET contains the constant offset that is added to the register in 9518 all encountered uses, and USE_RUID indicates the first encountered, i.e. 9519 last, of these uses. 9520 STORE_RUID is always meaningful if we only want to use a value in a 9521 register in a different place: it denotes the next insn in the insn 9522 stream (i.e. the last ecountered) that sets or clobbers the register. */ 9523static struct 9524 { 9525 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; 9526 int use_index; 9527 rtx offset; 9528 int store_ruid; 9529 int use_ruid; 9530 } reg_state[FIRST_PSEUDO_REGISTER]; 9531 9532/* Reverse linear uid. This is increased in reload_combine while scanning 9533 the instructions from last to first. It is used to set last_label_ruid 9534 and the store_ruid / use_ruid fields in reg_state. */ 9535static int reload_combine_ruid; 9536 9537#define LABEL_LIVE(LABEL) \ 9538 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) 9539 9540static void 9541reload_combine () 9542{ 9543 rtx insn, set; 9544 int first_index_reg = 1, last_index_reg = 0; 9545 int i; 9546 int last_label_ruid; 9547 int min_labelno, n_labels; 9548 HARD_REG_SET ever_live_at_start, *label_live; 9549 9550 /* If reg+reg can be used in offsetable memory adresses, the main chunk of 9551 reload has already used it where appropriate, so there is no use in 9552 trying to generate it now. */ 9553 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) 9554 return; 9555 9556 /* To avoid wasting too much time later searching for an index register, 9557 determine the minimum and maximum index register numbers. */ 9558 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) 9559 { 9560 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i)) 9561 { 9562 if (! last_index_reg) 9563 last_index_reg = i; 9564 first_index_reg = i; 9565 } 9566 } 9567 /* If no index register is available, we can quit now. */ 9568 if (first_index_reg > last_index_reg) 9569 return; 9570 9571 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime 9572 information is a bit fuzzy immediately after reload, but it's 9573 still good enough to determine which registers are live at a jump 9574 destination. */ 9575 min_labelno = get_first_label_num (); 9576 n_labels = max_label_num () - min_labelno; 9577 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET)); 9578 CLEAR_HARD_REG_SET (ever_live_at_start); 9579 for (i = n_basic_blocks - 1; i >= 0; i--) 9580 { 9581 insn = BLOCK_HEAD (i); 9582 if (GET_CODE (insn) == CODE_LABEL) 9583 { 9584 HARD_REG_SET live; 9585 9586 REG_SET_TO_HARD_REG_SET (live, BASIC_BLOCK (i)->global_live_at_start); 9587 compute_use_by_pseudos (&live, BASIC_BLOCK (i)->global_live_at_start); 9588 COPY_HARD_REG_SET (LABEL_LIVE (insn), live); 9589 IOR_HARD_REG_SET (ever_live_at_start, live); 9590 } 9591 } 9592 9593 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ 9594 last_label_ruid = reload_combine_ruid = 0; 9595 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) 9596 { 9597 reg_state[i].store_ruid = reload_combine_ruid; 9598 if (fixed_regs[i]) 9599 reg_state[i].use_index = -1; 9600 else 9601 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; 9602 } 9603 9604 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) 9605 { 9606 rtx note; 9607 9608 /* We cannot do our optimization across labels. Invalidating all the use 9609 information we have would be costly, so we just note where the label 9610 is and then later disable any optimization that would cross it. */ 9611 if (GET_CODE (insn) == CODE_LABEL) 9612 last_label_ruid = reload_combine_ruid; 9613 if (GET_CODE (insn) == BARRIER) 9614 { 9615 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) 9616 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; 9617 } 9618 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') 9619 continue; 9620 reload_combine_ruid++; 9621 9622 /* Look for (set (REGX) (CONST_INT)) 9623 (set (REGX) (PLUS (REGX) (REGY))) 9624 ... 9625 ... (MEM (REGX)) ... 9626 and convert it to 9627 (set (REGZ) (CONST_INT)) 9628 ... 9629 ... (MEM (PLUS (REGZ) (REGY)))... . 9630 9631 First, check that we have (set (REGX) (PLUS (REGX) (REGY))) 9632 and that we know all uses of REGX before it dies. */ 9633 set = single_set (insn); 9634 if (set != NULL_RTX 9635 && GET_CODE (SET_DEST (set)) == REG 9636 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)), 9637 GET_MODE (SET_DEST (set))) 9638 == 1) 9639 && GET_CODE (SET_SRC (set)) == PLUS 9640 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG 9641 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) 9642 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) 9643 { 9644 rtx reg = SET_DEST (set); 9645 rtx plus = SET_SRC (set); 9646 rtx base = XEXP (plus, 1); 9647 rtx prev = prev_nonnote_insn (insn); 9648 rtx prev_set = prev ? single_set (prev) : NULL_RTX; 9649 int regno = REGNO (reg); 9650 rtx const_reg; 9651 rtx reg_sum = NULL_RTX; 9652 9653 /* Now, we need an index register. 9654 We'll set index_reg to this index register, const_reg to the 9655 register that is to be loaded with the constant 9656 (denoted as REGZ in the substitution illustration above), 9657 and reg_sum to the register-register that we want to use to 9658 substitute uses of REG (typically in MEMs) with. 9659 First check REG and BASE for being index registers; 9660 we can use them even if they are not dead. */ 9661 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) 9662 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], 9663 REGNO (base))) 9664 { 9665 const_reg = reg; 9666 reg_sum = plus; 9667 } 9668 else 9669 { 9670 /* Otherwise, look for a free index register. Since we have 9671 checked above that neiter REG nor BASE are index registers, 9672 if we find anything at all, it will be different from these 9673 two registers. */ 9674 for (i = first_index_reg; i <= last_index_reg; i++) 9675 { 9676 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) 9677 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES 9678 && reg_state[i].store_ruid <= reg_state[regno].use_ruid 9679 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1) 9680 { 9681 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i); 9682 const_reg = index_reg; 9683 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); 9684 break; 9685 } 9686 } 9687 } 9688 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that 9689 (REGY), i.e. BASE, is not clobbered before the last use we'll 9690 create. */ 9691 if (prev_set 9692 && GET_CODE (SET_SRC (prev_set)) == CONST_INT 9693 && rtx_equal_p (SET_DEST (prev_set), reg) 9694 && reg_state[regno].use_index >= 0 9695 && reg_state[REGNO (base)].store_ruid <= reg_state[regno].use_ruid 9696 && reg_sum) 9697 { 9698 int i; 9699 9700 /* Change destination register and - if necessary - the 9701 constant value in PREV, the constant loading instruction. */ 9702 validate_change (prev, &SET_DEST (prev_set), const_reg, 1); 9703 if (reg_state[regno].offset != const0_rtx) 9704 validate_change (prev, 9705 &SET_SRC (prev_set), 9706 GEN_INT (INTVAL (SET_SRC (prev_set)) 9707 + INTVAL (reg_state[regno].offset)), 9708 1); 9709 /* Now for every use of REG that we have recorded, replace REG 9710 with REG_SUM. */ 9711 for (i = reg_state[regno].use_index; 9712 i < RELOAD_COMBINE_MAX_USES; i++) 9713 validate_change (reg_state[regno].reg_use[i].insn, 9714 reg_state[regno].reg_use[i].usep, 9715 reg_sum, 1); 9716 9717 if (apply_change_group ()) 9718 { 9719 rtx *np; 9720 9721 /* Delete the reg-reg addition. */ 9722 PUT_CODE (insn, NOTE); 9723 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 9724 NOTE_SOURCE_FILE (insn) = 0; 9725 9726 if (reg_state[regno].offset != const0_rtx) 9727 { 9728 /* Previous REG_EQUIV / REG_EQUAL notes for PREV 9729 are now invalid. */ 9730 for (np = ®_NOTES (prev); *np; ) 9731 { 9732 if (REG_NOTE_KIND (*np) == REG_EQUAL 9733 || REG_NOTE_KIND (*np) == REG_EQUIV) 9734 *np = XEXP (*np, 1); 9735 else 9736 np = &XEXP (*np, 1); 9737 } 9738 } 9739 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; 9740 reg_state[REGNO (const_reg)].store_ruid = reload_combine_ruid; 9741 continue; 9742 } 9743 } 9744 } 9745 note_stores (PATTERN (insn), reload_combine_note_store); 9746 if (GET_CODE (insn) == CALL_INSN) 9747 { 9748 rtx link; 9749 9750 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) 9751 { 9752 if (call_used_regs[i]) 9753 { 9754 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; 9755 reg_state[i].store_ruid = reload_combine_ruid; 9756 } 9757 } 9758 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; 9759 link = XEXP (link, 1)) 9760 { 9761 rtx use = XEXP (link, 0); 9762 int regno = REGNO (XEXP (use, 0)); 9763 if (GET_CODE (use) == CLOBBER) 9764 { 9765 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; 9766 reg_state[regno].store_ruid = reload_combine_ruid; 9767 } 9768 else 9769 reg_state[regno].use_index = -1; 9770 } 9771 } 9772 if (GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != RETURN) 9773 { 9774 /* Non-spill registers might be used at the call destination in 9775 some unknown fashion, so we have to mark the unknown use. */ 9776 HARD_REG_SET *live; 9777 if ((condjump_p (insn) || condjump_in_parallel_p (insn)) 9778 && JUMP_LABEL (insn)) 9779 live = &LABEL_LIVE (JUMP_LABEL (insn)); 9780 else 9781 live = &ever_live_at_start; 9782 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) 9783 { 9784 if (TEST_HARD_REG_BIT (*live, i)) 9785 reg_state[i].use_index = -1; 9786 } 9787 } 9788 reload_combine_note_use (&PATTERN (insn), insn); 9789 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 9790 { 9791 if (REG_NOTE_KIND (note) == REG_INC 9792 && GET_CODE (XEXP (note, 0)) == REG) 9793 { 9794 int regno = REGNO (XEXP (note, 0)); 9795 9796 reg_state[regno].store_ruid = reload_combine_ruid; 9797 reg_state[regno].use_index = -1; 9798 } 9799 } 9800 } 9801 free (label_live); 9802} 9803 9804/* Check if DST is a register or a subreg of a register; if it is, 9805 update reg_state[regno].store_ruid and reg_state[regno].use_index 9806 accordingly. Called via note_stores from reload_combine. */ 9807static void 9808reload_combine_note_store (dst, set) 9809 rtx dst, set; 9810{ 9811 int regno = 0; 9812 int i; 9813 unsigned size = GET_MODE_SIZE (GET_MODE (dst)); 9814 9815 if (GET_CODE (dst) == SUBREG) 9816 { 9817 regno = SUBREG_WORD (dst); 9818 dst = SUBREG_REG (dst); 9819 } 9820 if (GET_CODE (dst) != REG) 9821 return; 9822 regno += REGNO (dst); 9823 9824 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be 9825 careful with registers / register parts that are not full words. 9826 9827 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */ 9828 if (GET_CODE (set) != SET 9829 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT 9830 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT 9831 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) 9832 { 9833 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--) 9834 { 9835 reg_state[i].use_index = -1; 9836 reg_state[i].store_ruid = reload_combine_ruid; 9837 } 9838 } 9839 else 9840 { 9841 for (i = (size - 1) / UNITS_PER_WORD + regno; i >= regno; i--) 9842 { 9843 reg_state[i].store_ruid = reload_combine_ruid; 9844 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; 9845 } 9846 } 9847} 9848 9849/* XP points to a piece of rtl that has to be checked for any uses of 9850 registers. 9851 *XP is the pattern of INSN, or a part of it. 9852 Called from reload_combine, and recursively by itself. */ 9853static void 9854reload_combine_note_use (xp, insn) 9855 rtx *xp, insn; 9856{ 9857 rtx x = *xp; 9858 enum rtx_code code = x->code; 9859 char *fmt; 9860 int i, j; 9861 rtx offset = const0_rtx; /* For the REG case below. */ 9862 9863 switch (code) 9864 { 9865 case SET: 9866 if (GET_CODE (SET_DEST (x)) == REG) 9867 { 9868 reload_combine_note_use (&SET_SRC (x), insn); 9869 return; 9870 } 9871 break; 9872 9873 case CLOBBER: 9874 if (GET_CODE (SET_DEST (x)) == REG) 9875 return; 9876 break; 9877 9878 case PLUS: 9879 /* We are interested in (plus (reg) (const_int)) . */ 9880 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT) 9881 break; 9882 offset = XEXP (x, 1); 9883 x = XEXP (x, 0); 9884 /* Fall through. */ 9885 case REG: 9886 { 9887 int regno = REGNO (x); 9888 int use_index; 9889 9890 /* Some spurious USEs of pseudo registers might remain. 9891 Just ignore them. */ 9892 if (regno >= FIRST_PSEUDO_REGISTER) 9893 return; 9894 9895 /* If this register is already used in some unknown fashion, we 9896 can't do anything. 9897 If we decrement the index from zero to -1, we can't store more 9898 uses, so this register becomes used in an unknown fashion. */ 9899 use_index = --reg_state[regno].use_index; 9900 if (use_index < 0) 9901 return; 9902 9903 if (use_index != RELOAD_COMBINE_MAX_USES - 1) 9904 { 9905 /* We have found another use for a register that is already 9906 used later. Check if the offsets match; if not, mark the 9907 register as used in an unknown fashion. */ 9908 if (! rtx_equal_p (offset, reg_state[regno].offset)) 9909 { 9910 reg_state[regno].use_index = -1; 9911 return; 9912 } 9913 } 9914 else 9915 { 9916 /* This is the first use of this register we have seen since we 9917 marked it as dead. */ 9918 reg_state[regno].offset = offset; 9919 reg_state[regno].use_ruid = reload_combine_ruid; 9920 } 9921 reg_state[regno].reg_use[use_index].insn = insn; 9922 reg_state[regno].reg_use[use_index].usep = xp; 9923 return; 9924 } 9925 9926 default: 9927 break; 9928 } 9929 9930 /* Recursively process the components of X. */ 9931 fmt = GET_RTX_FORMAT (code); 9932 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 9933 { 9934 if (fmt[i] == 'e') 9935 reload_combine_note_use (&XEXP (x, i), insn); 9936 else if (fmt[i] == 'E') 9937 { 9938 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 9939 reload_combine_note_use (&XVECEXP (x, i, j), insn); 9940 } 9941 } 9942} 9943 9944/* See if we can reduce the cost of a constant by replacing a move with 9945 an add. */ 9946/* We cannot do our optimization across labels. Invalidating all the 9947 information about register contents we have would be costly, so we 9948 use last_label_luid (local variable of reload_cse_move2add) to note 9949 where the label is and then later disable any optimization that would 9950 cross it. 9951 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if 9952 reg_set_luid[n] is larger than last_label_luid[n] . */ 9953static int reg_set_luid[FIRST_PSEUDO_REGISTER]; 9954/* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] / 9955 reg_mode[n] to be valid. 9956 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n 9957 has been set to reg_offset[n] in mode reg_mode[n] . 9958 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative, 9959 register n has been set to the sum of reg_offset[n] and register 9960 reg_base_reg[n], calculated in mode reg_mode[n] . */ 9961static rtx reg_offset[FIRST_PSEUDO_REGISTER]; 9962static int reg_base_reg[FIRST_PSEUDO_REGISTER]; 9963static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; 9964/* move2add_luid is linearily increased while scanning the instructions 9965 from first to last. It is used to set reg_set_luid in 9966 reload_cse_move2add and move2add_note_store. */ 9967static int move2add_luid; 9968 9969/* Generate a CONST_INT and force it in the range of MODE. */ 9970static rtx 9971gen_mode_int (mode, value) 9972 enum machine_mode mode; 9973 HOST_WIDE_INT value; 9974{ 9975 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode); 9976 int width = GET_MODE_BITSIZE (mode); 9977 9978 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number, 9979 sign extend it. */ 9980 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 9981 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 9982 cval |= (HOST_WIDE_INT) -1 << width; 9983 9984 return GEN_INT (cval); 9985} 9986 9987static void 9988reload_cse_move2add (first) 9989 rtx first; 9990{ 9991 int i; 9992 rtx insn; 9993 int last_label_luid; 9994 9995 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--) 9996 reg_set_luid[i] = 0; 9997 9998 last_label_luid = 0; 9999 move2add_luid = 1; 10000 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) 10001 { 10002 rtx pat, note; 10003 10004 if (GET_CODE (insn) == CODE_LABEL) 10005 last_label_luid = move2add_luid; 10006 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') 10007 continue; 10008 pat = PATTERN (insn); 10009 /* For simplicity, we only perform this optimization on 10010 straightforward SETs. */ 10011 if (GET_CODE (pat) == SET 10012 && GET_CODE (SET_DEST (pat)) == REG) 10013 { 10014 rtx reg = SET_DEST (pat); 10015 int regno = REGNO (reg); 10016 rtx src = SET_SRC (pat); 10017 10018 /* Check if we have valid information on the contents of this 10019 register in the mode of REG. */ 10020 /* ??? We don't know how zero / sign extension is handled, hence 10021 we can't go from a narrower to a wider mode. */ 10022 if (reg_set_luid[regno] > last_label_luid 10023 && (GET_MODE_SIZE (GET_MODE (reg)) 10024 <= GET_MODE_SIZE (reg_mode[regno])) 10025 && GET_CODE (reg_offset[regno]) == CONST_INT) 10026 { 10027 /* Try to transform (set (REGX) (CONST_INT A)) 10028 ... 10029 (set (REGX) (CONST_INT B)) 10030 to 10031 (set (REGX) (CONST_INT A)) 10032 ... 10033 (set (REGX) (plus (REGX) (CONST_INT B-A))) */ 10034 10035 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0) 10036 { 10037 int success = 0; 10038 rtx new_src 10039 = gen_mode_int (GET_MODE (reg), 10040 INTVAL (src) - INTVAL (reg_offset[regno])); 10041 /* (set (reg) (plus (reg) (const_int 0))) is not canonical; 10042 use (set (reg) (reg)) instead. 10043 We don't delete this insn, nor do we convert it into a 10044 note, to avoid losing register notes or the return 10045 value flag. jump2 already knowns how to get rid of 10046 no-op moves. */ 10047 if (new_src == const0_rtx) 10048 success = validate_change (insn, &SET_SRC (pat), reg, 0); 10049 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET) 10050 && have_add2_insn (GET_MODE (reg))) 10051 success = validate_change (insn, &PATTERN (insn), 10052 gen_add2_insn (reg, new_src), 0); 10053 reg_set_luid[regno] = move2add_luid; 10054 reg_mode[regno] = GET_MODE (reg); 10055 reg_offset[regno] = src; 10056 continue; 10057 } 10058 10059 /* Try to transform (set (REGX) (REGY)) 10060 (set (REGX) (PLUS (REGX) (CONST_INT A))) 10061 ... 10062 (set (REGX) (REGY)) 10063 (set (REGX) (PLUS (REGX) (CONST_INT B))) 10064 to 10065 (REGX) (REGY)) 10066 (set (REGX) (PLUS (REGX) (CONST_INT A))) 10067 ... 10068 (set (REGX) (plus (REGX) (CONST_INT B-A))) */ 10069 else if (GET_CODE (src) == REG 10070 && reg_base_reg[regno] == REGNO (src) 10071 && reg_set_luid[regno] > reg_set_luid[REGNO (src)]) 10072 { 10073 rtx next = next_nonnote_insn (insn); 10074 rtx set; 10075 if (next) 10076 set = single_set (next); 10077 if (next 10078 && set 10079 && SET_DEST (set) == reg 10080 && GET_CODE (SET_SRC (set)) == PLUS 10081 && XEXP (SET_SRC (set), 0) == reg 10082 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) 10083 { 10084 rtx src3 = XEXP (SET_SRC (set), 1); 10085 rtx new_src 10086 = gen_mode_int (GET_MODE (reg), 10087 INTVAL (src3) 10088 - INTVAL (reg_offset[regno])); 10089 int success = 0; 10090 10091 if (new_src == const0_rtx) 10092 /* See above why we create (set (reg) (reg)) here. */ 10093 success 10094 = validate_change (next, &SET_SRC (set), reg, 0); 10095 else if ((rtx_cost (new_src, PLUS) 10096 < 2 + rtx_cost (src3, SET)) 10097 && have_add2_insn (GET_MODE (reg))) 10098 success 10099 = validate_change (next, &PATTERN (next), 10100 gen_add2_insn (reg, new_src), 0); 10101 if (success) 10102 { 10103 /* INSN might be the first insn in a basic block 10104 if the preceding insn is a conditional jump 10105 or a possible-throwing call. */ 10106 PUT_CODE (insn, NOTE); 10107 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 10108 NOTE_SOURCE_FILE (insn) = 0; 10109 } 10110 insn = next; 10111 reg_set_luid[regno] = move2add_luid; 10112 reg_mode[regno] = GET_MODE (reg); 10113 reg_offset[regno] = src3; 10114 continue; 10115 } 10116 } 10117 } 10118 } 10119 10120 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 10121 { 10122 if (REG_NOTE_KIND (note) == REG_INC 10123 && GET_CODE (XEXP (note, 0)) == REG) 10124 { 10125 /* Indicate that this register has been recently written to, 10126 but the exact contents are not available. */ 10127 int regno = REGNO (XEXP (note, 0)); 10128 if (regno < FIRST_PSEUDO_REGISTER) 10129 { 10130 reg_set_luid[regno] = move2add_luid; 10131 reg_offset[regno] = note; 10132 } 10133 } 10134 } 10135 note_stores (PATTERN (insn), move2add_note_store); 10136 /* If this is a CALL_INSN, all call used registers are stored with 10137 unknown values. */ 10138 if (GET_CODE (insn) == CALL_INSN) 10139 { 10140 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--) 10141 { 10142 if (call_used_regs[i]) 10143 { 10144 reg_set_luid[i] = move2add_luid; 10145 reg_offset[i] = insn; /* Invalidate contents. */ 10146 } 10147 } 10148 } 10149 } 10150} 10151 10152/* SET is a SET or CLOBBER that sets DST. 10153 Update reg_set_luid, reg_offset and reg_base_reg accordingly. 10154 Called from reload_cse_move2add via note_stores. */ 10155static void 10156move2add_note_store (dst, set) 10157 rtx dst, set; 10158{ 10159 int regno = 0; 10160 int i; 10161 10162 enum machine_mode mode = GET_MODE (dst); 10163 if (GET_CODE (dst) == SUBREG) 10164 { 10165 regno = SUBREG_WORD (dst); 10166 dst = SUBREG_REG (dst); 10167 } 10168 if (GET_CODE (dst) != REG) 10169 return; 10170 10171 regno += REGNO (dst); 10172 10173 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET 10174 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT 10175 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT 10176 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) 10177 { 10178 rtx src = SET_SRC (set); 10179 10180 reg_mode[regno] = mode; 10181 switch (GET_CODE (src)) 10182 { 10183 case PLUS: 10184 { 10185 rtx src0 = XEXP (src, 0); 10186 if (GET_CODE (src0) == REG) 10187 { 10188 if (REGNO (src0) != regno 10189 || reg_offset[regno] != const0_rtx) 10190 { 10191 reg_base_reg[regno] = REGNO (src0); 10192 reg_set_luid[regno] = move2add_luid; 10193 } 10194 reg_offset[regno] = XEXP (src, 1); 10195 break; 10196 } 10197 reg_set_luid[regno] = move2add_luid; 10198 reg_offset[regno] = set; /* Invalidate contents. */ 10199 break; 10200 } 10201 10202 case REG: 10203 reg_base_reg[regno] = REGNO (SET_SRC (set)); 10204 reg_offset[regno] = const0_rtx; 10205 reg_set_luid[regno] = move2add_luid; 10206 break; 10207 10208 default: 10209 reg_base_reg[regno] = -1; 10210 reg_offset[regno] = SET_SRC (set); 10211 reg_set_luid[regno] = move2add_luid; 10212 break; 10213 } 10214 } 10215 else 10216 { 10217 for (i = regno + HARD_REGNO_NREGS (regno, mode) - 1; i >= regno; i--) 10218 { 10219 /* Indicate that this register has been recently written to, 10220 but the exact contents are not available. */ 10221 reg_set_luid[i] = move2add_luid; 10222 reg_offset[i] = dst; 10223 } 10224 } 10225} 10226 10227#ifdef AUTO_INC_DEC 10228static void 10229add_auto_inc_notes (insn, x) 10230 rtx insn; 10231 rtx x; 10232{ 10233 enum rtx_code code = GET_CODE (x); 10234 char *fmt; 10235 int i, j; 10236 10237 if (code == MEM && auto_inc_p (XEXP (x, 0))) 10238 { 10239 REG_NOTES (insn) 10240 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); 10241 return; 10242 } 10243 10244 /* Scan all the operand sub-expressions. */ 10245 fmt = GET_RTX_FORMAT (code); 10246 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 10247 { 10248 if (fmt[i] == 'e') 10249 add_auto_inc_notes (insn, XEXP (x, i)); 10250 else if (fmt[i] == 'E') 10251 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 10252 add_auto_inc_notes (insn, XVECEXP (x, i, j)); 10253 } 10254} 10255#endif 10256