reload1.c revision 50397
1/* Reload pseudo regs into hard regs for insns that require hard regs. 2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc. 3 4This file is part of GNU CC. 5 6GNU CC is free software; you can redistribute it and/or modify 7it under the terms of the GNU General Public License as published by 8the Free Software Foundation; either version 2, or (at your option) 9any later version. 10 11GNU CC is distributed in the hope that it will be useful, 12but WITHOUT ANY WARRANTY; without even the implied warranty of 13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14GNU General Public License for more details. 15 16You should have received a copy of the GNU General Public License 17along with GNU CC; see the file COPYING. If not, write to 18the Free Software Foundation, 59 Temple Place - Suite 330, 19Boston, MA 02111-1307, USA. */ 20 21 22#include "config.h" 23#include "system.h" 24 25#include "machmode.h" 26#include "hard-reg-set.h" 27#include "rtl.h" 28#include "obstack.h" 29#include "insn-config.h" 30#include "insn-flags.h" 31#include "insn-codes.h" 32#include "flags.h" 33#include "expr.h" 34#include "regs.h" 35#include "reload.h" 36#include "recog.h" 37#include "basic-block.h" 38#include "output.h" 39#include "real.h" 40#include "toplev.h" 41 42/* This file contains the reload pass of the compiler, which is 43 run after register allocation has been done. It checks that 44 each insn is valid (operands required to be in registers really 45 are in registers of the proper class) and fixes up invalid ones 46 by copying values temporarily into registers for the insns 47 that need them. 48 49 The results of register allocation are described by the vector 50 reg_renumber; the insns still contain pseudo regs, but reg_renumber 51 can be used to find which hard reg, if any, a pseudo reg is in. 52 53 The technique we always use is to free up a few hard regs that are 54 called ``reload regs'', and for each place where a pseudo reg 55 must be in a hard reg, copy it temporarily into one of the reload regs. 56 57 All the pseudos that were formerly allocated to the hard regs that 58 are now in use as reload regs must be ``spilled''. This means 59 that they go to other hard regs, or to stack slots if no other 60 available hard regs can be found. Spilling can invalidate more 61 insns, requiring additional need for reloads, so we must keep checking 62 until the process stabilizes. 63 64 For machines with different classes of registers, we must keep track 65 of the register class needed for each reload, and make sure that 66 we allocate enough reload registers of each class. 67 68 The file reload.c contains the code that checks one insn for 69 validity and reports the reloads that it needs. This file 70 is in charge of scanning the entire rtl code, accumulating the 71 reload needs, spilling, assigning reload registers to use for 72 fixing up each insn, and generating the new insns to copy values 73 into the reload registers. */ 74 75 76#ifndef REGISTER_MOVE_COST 77#define REGISTER_MOVE_COST(x, y) 2 78#endif 79 80/* During reload_as_needed, element N contains a REG rtx for the hard reg 81 into which reg N has been reloaded (perhaps for a previous insn). */ 82static rtx *reg_last_reload_reg; 83 84/* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn 85 for an output reload that stores into reg N. */ 86static char *reg_has_output_reload; 87 88/* Indicates which hard regs are reload-registers for an output reload 89 in the current insn. */ 90static HARD_REG_SET reg_is_output_reload; 91 92/* Element N is the constant value to which pseudo reg N is equivalent, 93 or zero if pseudo reg N is not equivalent to a constant. 94 find_reloads looks at this in order to replace pseudo reg N 95 with the constant it stands for. */ 96rtx *reg_equiv_constant; 97 98/* Element N is a memory location to which pseudo reg N is equivalent, 99 prior to any register elimination (such as frame pointer to stack 100 pointer). Depending on whether or not it is a valid address, this value 101 is transferred to either reg_equiv_address or reg_equiv_mem. */ 102rtx *reg_equiv_memory_loc; 103 104/* Element N is the address of stack slot to which pseudo reg N is equivalent. 105 This is used when the address is not valid as a memory address 106 (because its displacement is too big for the machine.) */ 107rtx *reg_equiv_address; 108 109/* Element N is the memory slot to which pseudo reg N is equivalent, 110 or zero if pseudo reg N is not equivalent to a memory slot. */ 111rtx *reg_equiv_mem; 112 113/* Widest width in which each pseudo reg is referred to (via subreg). */ 114static int *reg_max_ref_width; 115 116/* Element N is the insn that initialized reg N from its equivalent 117 constant or memory slot. */ 118static rtx *reg_equiv_init; 119 120/* During reload_as_needed, element N contains the last pseudo regno reloaded 121 into hard register N. If that pseudo reg occupied more than one register, 122 reg_reloaded_contents points to that pseudo for each spill register in 123 use; all of these must remain set for an inheritance to occur. */ 124static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; 125 126/* During reload_as_needed, element N contains the insn for which 127 hard register N was last used. Its contents are significant only 128 when reg_reloaded_valid is set for this register. */ 129static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; 130 131/* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */ 132static HARD_REG_SET reg_reloaded_valid; 133/* Indicate if the register was dead at the end of the reload. 134 This is only valid if reg_reloaded_contents is set and valid. */ 135static HARD_REG_SET reg_reloaded_dead; 136 137/* Number of spill-regs so far; number of valid elements of spill_regs. */ 138static int n_spills; 139 140/* In parallel with spill_regs, contains REG rtx's for those regs. 141 Holds the last rtx used for any given reg, or 0 if it has never 142 been used for spilling yet. This rtx is reused, provided it has 143 the proper mode. */ 144static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; 145 146/* In parallel with spill_regs, contains nonzero for a spill reg 147 that was stored after the last time it was used. 148 The precise value is the insn generated to do the store. */ 149static rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; 150 151/* This table is the inverse mapping of spill_regs: 152 indexed by hard reg number, 153 it contains the position of that reg in spill_regs, 154 or -1 for something that is not in spill_regs. */ 155static short spill_reg_order[FIRST_PSEUDO_REGISTER]; 156 157/* This reg set indicates registers that may not be used for retrying global 158 allocation. The registers that may not be used include all spill registers 159 and the frame pointer (if we are using one). */ 160HARD_REG_SET forbidden_regs; 161 162/* This reg set indicates registers that are not good for spill registers. 163 They will not be used to complete groups of spill registers. This includes 164 all fixed registers, registers that may be eliminated, and, if 165 SMALL_REGISTER_CLASSES is zero, registers explicitly used in the rtl. 166 167 (spill_reg_order prevents these registers from being used to start a 168 group.) */ 169static HARD_REG_SET bad_spill_regs; 170 171/* Describes order of use of registers for reloading 172 of spilled pseudo-registers. `spills' is the number of 173 elements that are actually valid; new ones are added at the end. */ 174static short spill_regs[FIRST_PSEUDO_REGISTER]; 175 176/* This reg set indicates those registers that have been used a spill 177 registers. This information is used in reorg.c, to help figure out 178 what registers are live at any point. It is assumed that all spill_regs 179 are dead at every CODE_LABEL. */ 180 181HARD_REG_SET used_spill_regs; 182 183/* Index of last register assigned as a spill register. We allocate in 184 a round-robin fashion. */ 185 186static int last_spill_reg; 187 188/* Describes order of preference for putting regs into spill_regs. 189 Contains the numbers of all the hard regs, in order most preferred first. 190 This order is different for each function. 191 It is set up by order_regs_for_reload. 192 Empty elements at the end contain -1. */ 193static short potential_reload_regs[FIRST_PSEUDO_REGISTER]; 194 195/* 1 for a hard register that appears explicitly in the rtl 196 (for example, function value registers, special registers 197 used by insns, structure value pointer registers). */ 198static char regs_explicitly_used[FIRST_PSEUDO_REGISTER]; 199 200/* Indicates if a register was counted against the need for 201 groups. 0 means it can count against max_nongroup instead. */ 202static HARD_REG_SET counted_for_groups; 203 204/* Indicates if a register was counted against the need for 205 non-groups. 0 means it can become part of a new group. 206 During choose_reload_regs, 1 here means don't use this reg 207 as part of a group, even if it seems to be otherwise ok. */ 208static HARD_REG_SET counted_for_nongroups; 209 210/* Nonzero if indirect addressing is supported on the machine; this means 211 that spilling (REG n) does not require reloading it into a register in 212 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The 213 value indicates the level of indirect addressing supported, e.g., two 214 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get 215 a hard register. */ 216 217static char spill_indirect_levels; 218 219/* Nonzero if indirect addressing is supported when the innermost MEM is 220 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to 221 which these are valid is the same as spill_indirect_levels, above. */ 222 223char indirect_symref_ok; 224 225/* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ 226 227char double_reg_address_ok; 228 229/* Record the stack slot for each spilled hard register. */ 230 231static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; 232 233/* Width allocated so far for that stack slot. */ 234 235static int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; 236 237/* Indexed by register class and basic block number, nonzero if there is 238 any need for a spill register of that class in that basic block. 239 The pointer is 0 if we did stupid allocation and don't know 240 the structure of basic blocks. */ 241 242char *basic_block_needs[N_REG_CLASSES]; 243 244/* First uid used by insns created by reload in this function. 245 Used in find_equiv_reg. */ 246int reload_first_uid; 247 248/* Flag set by local-alloc or global-alloc if anything is live in 249 a call-clobbered reg across calls. */ 250 251int caller_save_needed; 252 253/* The register class to use for a base register when reloading an 254 address. This is normally BASE_REG_CLASS, but it may be different 255 when using SMALL_REGISTER_CLASSES and passing parameters in 256 registers. */ 257enum reg_class reload_address_base_reg_class; 258 259/* The register class to use for an index register when reloading an 260 address. This is normally INDEX_REG_CLASS, but it may be different 261 when using SMALL_REGISTER_CLASSES and passing parameters in 262 registers. */ 263enum reg_class reload_address_index_reg_class; 264 265/* Set to 1 while reload_as_needed is operating. 266 Required by some machines to handle any generated moves differently. */ 267 268int reload_in_progress = 0; 269 270/* These arrays record the insn_code of insns that may be needed to 271 perform input and output reloads of special objects. They provide a 272 place to pass a scratch register. */ 273 274enum insn_code reload_in_optab[NUM_MACHINE_MODES]; 275enum insn_code reload_out_optab[NUM_MACHINE_MODES]; 276 277/* This obstack is used for allocation of rtl during register elimination. 278 The allocated storage can be freed once find_reloads has processed the 279 insn. */ 280 281struct obstack reload_obstack; 282char *reload_firstobj; 283 284#define obstack_chunk_alloc xmalloc 285#define obstack_chunk_free free 286 287/* List of labels that must never be deleted. */ 288extern rtx forced_labels; 289 290/* Allocation number table from global register allocation. */ 291extern int *reg_allocno; 292 293/* This structure is used to record information about register eliminations. 294 Each array entry describes one possible way of eliminating a register 295 in favor of another. If there is more than one way of eliminating a 296 particular register, the most preferred should be specified first. */ 297 298static struct elim_table 299{ 300 int from; /* Register number to be eliminated. */ 301 int to; /* Register number used as replacement. */ 302 int initial_offset; /* Initial difference between values. */ 303 int can_eliminate; /* Non-zero if this elimination can be done. */ 304 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over 305 insns made by reload. */ 306 int offset; /* Current offset between the two regs. */ 307 int max_offset; /* Maximum offset between the two regs. */ 308 int previous_offset; /* Offset at end of previous insn. */ 309 int ref_outside_mem; /* "to" has been referenced outside a MEM. */ 310 rtx from_rtx; /* REG rtx for the register to be eliminated. 311 We cannot simply compare the number since 312 we might then spuriously replace a hard 313 register corresponding to a pseudo 314 assigned to the reg to be eliminated. */ 315 rtx to_rtx; /* REG rtx for the replacement. */ 316} reg_eliminate[] = 317 318/* If a set of eliminable registers was specified, define the table from it. 319 Otherwise, default to the normal case of the frame pointer being 320 replaced by the stack pointer. */ 321 322#ifdef ELIMINABLE_REGS 323 ELIMINABLE_REGS; 324#else 325 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; 326#endif 327 328#define NUM_ELIMINABLE_REGS (sizeof reg_eliminate / sizeof reg_eliminate[0]) 329 330/* Record the number of pending eliminations that have an offset not equal 331 to their initial offset. If non-zero, we use a new copy of each 332 replacement result in any insns encountered. */ 333static int num_not_at_initial_offset; 334 335/* Count the number of registers that we may be able to eliminate. */ 336static int num_eliminable; 337 338/* For each label, we record the offset of each elimination. If we reach 339 a label by more than one path and an offset differs, we cannot do the 340 elimination. This information is indexed by the number of the label. 341 The first table is an array of flags that records whether we have yet 342 encountered a label and the second table is an array of arrays, one 343 entry in the latter array for each elimination. */ 344 345static char *offsets_known_at; 346static int (*offsets_at)[NUM_ELIMINABLE_REGS]; 347 348/* Number of labels in the current function. */ 349 350static int num_labels; 351 352struct hard_reg_n_uses { int regno; int uses; }; 353 354static int possible_group_p PROTO((int, int *)); 355static void count_possible_groups PROTO((int *, enum machine_mode *, 356 int *, int)); 357static int modes_equiv_for_class_p PROTO((enum machine_mode, 358 enum machine_mode, 359 enum reg_class)); 360static void spill_failure PROTO((rtx)); 361static int new_spill_reg PROTO((int, int, int *, int *, int, 362 FILE *)); 363static void delete_dead_insn PROTO((rtx)); 364static void alter_reg PROTO((int, int)); 365static void mark_scratch_live PROTO((rtx)); 366static void set_label_offsets PROTO((rtx, rtx, int)); 367static int eliminate_regs_in_insn PROTO((rtx, int)); 368static void mark_not_eliminable PROTO((rtx, rtx)); 369static int spill_hard_reg PROTO((int, int, FILE *, int)); 370static void scan_paradoxical_subregs PROTO((rtx)); 371static int hard_reg_use_compare PROTO((const GENERIC_PTR, const GENERIC_PTR)); 372static void order_regs_for_reload PROTO((int)); 373static int compare_spill_regs PROTO((const GENERIC_PTR, const GENERIC_PTR)); 374static void reload_as_needed PROTO((rtx, int)); 375static void forget_old_reloads_1 PROTO((rtx, rtx)); 376static int reload_reg_class_lower PROTO((const GENERIC_PTR, const GENERIC_PTR)); 377static void mark_reload_reg_in_use PROTO((int, int, enum reload_type, 378 enum machine_mode)); 379static void clear_reload_reg_in_use PROTO((int, int, enum reload_type, 380 enum machine_mode)); 381static int reload_reg_free_p PROTO((int, int, enum reload_type)); 382static int reload_reg_free_before_p PROTO((int, int, enum reload_type)); 383static int reload_reg_free_for_value_p PROTO((int, int, enum reload_type, rtx, rtx, int)); 384static int reload_reg_reaches_end_p PROTO((int, int, enum reload_type)); 385static int allocate_reload_reg PROTO((int, rtx, int, int)); 386static void choose_reload_regs PROTO((rtx, rtx)); 387static void merge_assigned_reloads PROTO((rtx)); 388static void emit_reload_insns PROTO((rtx)); 389static void delete_output_reload PROTO((rtx, int, rtx)); 390static void inc_for_reload PROTO((rtx, rtx, int)); 391static int constraint_accepts_reg_p PROTO((char *, rtx)); 392static void reload_cse_invalidate_regno PROTO((int, enum machine_mode, int)); 393static int reload_cse_mem_conflict_p PROTO((rtx, rtx)); 394static void reload_cse_invalidate_mem PROTO((rtx)); 395static void reload_cse_invalidate_rtx PROTO((rtx, rtx)); 396static int reload_cse_regno_equal_p PROTO((int, rtx, enum machine_mode)); 397static int reload_cse_noop_set_p PROTO((rtx, rtx)); 398static int reload_cse_simplify_set PROTO((rtx, rtx)); 399static int reload_cse_simplify_operands PROTO((rtx)); 400static void reload_cse_check_clobber PROTO((rtx, rtx)); 401static void reload_cse_record_set PROTO((rtx, rtx)); 402static void reload_cse_delete_death_notes PROTO((rtx)); 403static void reload_cse_no_longer_dead PROTO((int, enum machine_mode)); 404 405/* Initialize the reload pass once per compilation. */ 406 407void 408init_reload () 409{ 410 register int i; 411 412 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. 413 Set spill_indirect_levels to the number of levels such addressing is 414 permitted, zero if it is not permitted at all. */ 415 416 register rtx tem 417 = gen_rtx_MEM (Pmode, 418 gen_rtx_PLUS (Pmode, 419 gen_rtx_REG (Pmode, LAST_VIRTUAL_REGISTER + 1), 420 GEN_INT (4))); 421 spill_indirect_levels = 0; 422 423 while (memory_address_p (QImode, tem)) 424 { 425 spill_indirect_levels++; 426 tem = gen_rtx_MEM (Pmode, tem); 427 } 428 429 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ 430 431 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); 432 indirect_symref_ok = memory_address_p (QImode, tem); 433 434 /* See if reg+reg is a valid (and offsettable) address. */ 435 436 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 437 { 438 tem = gen_rtx_PLUS (Pmode, 439 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), 440 gen_rtx_REG (Pmode, i)); 441 /* This way, we make sure that reg+reg is an offsettable address. */ 442 tem = plus_constant (tem, 4); 443 444 if (memory_address_p (QImode, tem)) 445 { 446 double_reg_address_ok = 1; 447 break; 448 } 449 } 450 451 /* Initialize obstack for our rtl allocation. */ 452 gcc_obstack_init (&reload_obstack); 453 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); 454 455 /* Decide which register class should be used when reloading 456 addresses. If we are using SMALL_REGISTER_CLASSES, and any 457 parameters are passed in registers, then we do not want to use 458 those registers when reloading an address. Otherwise, if a 459 function argument needs a reload, we may wind up clobbering 460 another argument to the function which was already computed. If 461 we find a subset class which simply avoids those registers, we 462 use it instead. ??? It would be better to only use the 463 restricted class when we actually are loading function arguments, 464 but that is hard to determine. */ 465 reload_address_base_reg_class = BASE_REG_CLASS; 466 reload_address_index_reg_class = INDEX_REG_CLASS; 467 if (SMALL_REGISTER_CLASSES) 468 { 469 int regno; 470 HARD_REG_SET base, index; 471 enum reg_class *p; 472 473 COPY_HARD_REG_SET (base, reg_class_contents[BASE_REG_CLASS]); 474 COPY_HARD_REG_SET (index, reg_class_contents[INDEX_REG_CLASS]); 475 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 476 { 477 if (FUNCTION_ARG_REGNO_P (regno)) 478 { 479 CLEAR_HARD_REG_BIT (base, regno); 480 CLEAR_HARD_REG_BIT (index, regno); 481 } 482 } 483 484 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[BASE_REG_CLASS], 485 baseok); 486 for (p = reg_class_subclasses[BASE_REG_CLASS]; 487 *p != LIM_REG_CLASSES; 488 p++) 489 { 490 GO_IF_HARD_REG_EQUAL (base, reg_class_contents[*p], usebase); 491 continue; 492 usebase: 493 reload_address_base_reg_class = *p; 494 break; 495 } 496 baseok:; 497 498 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[INDEX_REG_CLASS], 499 indexok); 500 for (p = reg_class_subclasses[INDEX_REG_CLASS]; 501 *p != LIM_REG_CLASSES; 502 p++) 503 { 504 GO_IF_HARD_REG_EQUAL (index, reg_class_contents[*p], useindex); 505 continue; 506 useindex: 507 reload_address_index_reg_class = *p; 508 break; 509 } 510 indexok:; 511 } 512} 513 514/* Main entry point for the reload pass. 515 516 FIRST is the first insn of the function being compiled. 517 518 GLOBAL nonzero means we were called from global_alloc 519 and should attempt to reallocate any pseudoregs that we 520 displace from hard regs we will use for reloads. 521 If GLOBAL is zero, we do not have enough information to do that, 522 so any pseudo reg that is spilled must go to the stack. 523 524 DUMPFILE is the global-reg debugging dump file stream, or 0. 525 If it is nonzero, messages are written to it to describe 526 which registers are seized as reload regs, which pseudo regs 527 are spilled from them, and where the pseudo regs are reallocated to. 528 529 Return value is nonzero if reload failed 530 and we must not do any more for this function. */ 531 532int 533reload (first, global, dumpfile) 534 rtx first; 535 int global; 536 FILE *dumpfile; 537{ 538 register int class; 539 register int i, j, k; 540 register rtx insn; 541 register struct elim_table *ep; 542 543 /* The two pointers used to track the true location of the memory used 544 for label offsets. */ 545 char *real_known_ptr = NULL_PTR; 546 int (*real_at_ptr)[NUM_ELIMINABLE_REGS]; 547 548 int something_changed; 549 int something_needs_reloads; 550 int something_needs_elimination; 551 int new_basic_block_needs; 552 enum reg_class caller_save_spill_class = NO_REGS; 553 int caller_save_group_size = 1; 554 555 /* Nonzero means we couldn't get enough spill regs. */ 556 int failure = 0; 557 558 /* The basic block number currently being processed for INSN. */ 559 int this_block; 560 561 /* Make sure even insns with volatile mem refs are recognizable. */ 562 init_recog (); 563 564 /* Enable find_equiv_reg to distinguish insns made by reload. */ 565 reload_first_uid = get_max_uid (); 566 567 for (i = 0; i < N_REG_CLASSES; i++) 568 basic_block_needs[i] = 0; 569 570#ifdef SECONDARY_MEMORY_NEEDED 571 /* Initialize the secondary memory table. */ 572 clear_secondary_mem (); 573#endif 574 575 /* Remember which hard regs appear explicitly 576 before we merge into `regs_ever_live' the ones in which 577 pseudo regs have been allocated. */ 578 bcopy (regs_ever_live, regs_explicitly_used, sizeof regs_ever_live); 579 580 /* We don't have a stack slot for any spill reg yet. */ 581 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot); 582 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width); 583 584 /* Initialize the save area information for caller-save, in case some 585 are needed. */ 586 init_save_areas (); 587 588 /* Compute which hard registers are now in use 589 as homes for pseudo registers. 590 This is done here rather than (eg) in global_alloc 591 because this point is reached even if not optimizing. */ 592 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 593 mark_home_live (i); 594 595 /* A function that receives a nonlocal goto must save all call-saved 596 registers. */ 597 if (current_function_has_nonlocal_label) 598 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 599 { 600 if (! call_used_regs[i] && ! fixed_regs[i]) 601 regs_ever_live[i] = 1; 602 } 603 604 for (i = 0; i < scratch_list_length; i++) 605 if (scratch_list[i]) 606 mark_scratch_live (scratch_list[i]); 607 608 /* Make sure that the last insn in the chain 609 is not something that needs reloading. */ 610 emit_note (NULL_PTR, NOTE_INSN_DELETED); 611 612 /* Find all the pseudo registers that didn't get hard regs 613 but do have known equivalent constants or memory slots. 614 These include parameters (known equivalent to parameter slots) 615 and cse'd or loop-moved constant memory addresses. 616 617 Record constant equivalents in reg_equiv_constant 618 so they will be substituted by find_reloads. 619 Record memory equivalents in reg_mem_equiv so they can 620 be substituted eventually by altering the REG-rtx's. */ 621 622 reg_equiv_constant = (rtx *) alloca (max_regno * sizeof (rtx)); 623 bzero ((char *) reg_equiv_constant, max_regno * sizeof (rtx)); 624 reg_equiv_memory_loc = (rtx *) alloca (max_regno * sizeof (rtx)); 625 bzero ((char *) reg_equiv_memory_loc, max_regno * sizeof (rtx)); 626 reg_equiv_mem = (rtx *) alloca (max_regno * sizeof (rtx)); 627 bzero ((char *) reg_equiv_mem, max_regno * sizeof (rtx)); 628 reg_equiv_init = (rtx *) alloca (max_regno * sizeof (rtx)); 629 bzero ((char *) reg_equiv_init, max_regno * sizeof (rtx)); 630 reg_equiv_address = (rtx *) alloca (max_regno * sizeof (rtx)); 631 bzero ((char *) reg_equiv_address, max_regno * sizeof (rtx)); 632 reg_max_ref_width = (int *) alloca (max_regno * sizeof (int)); 633 bzero ((char *) reg_max_ref_width, max_regno * sizeof (int)); 634 635 if (SMALL_REGISTER_CLASSES) 636 CLEAR_HARD_REG_SET (forbidden_regs); 637 638 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. 639 Also find all paradoxical subregs and find largest such for each pseudo. 640 On machines with small register classes, record hard registers that 641 are used for user variables. These can never be used for spills. 642 Also look for a "constant" NOTE_INSN_SETJMP. This means that all 643 caller-saved registers must be marked live. */ 644 645 for (insn = first; insn; insn = NEXT_INSN (insn)) 646 { 647 rtx set = single_set (insn); 648 649 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn) 650 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP) 651 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 652 if (! call_used_regs[i]) 653 regs_ever_live[i] = 1; 654 655 if (set != 0 && GET_CODE (SET_DEST (set)) == REG) 656 { 657 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); 658 if (note 659#ifdef LEGITIMATE_PIC_OPERAND_P 660 && (! CONSTANT_P (XEXP (note, 0)) || ! flag_pic 661 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0))) 662#endif 663 ) 664 { 665 rtx x = XEXP (note, 0); 666 i = REGNO (SET_DEST (set)); 667 if (i > LAST_VIRTUAL_REGISTER) 668 { 669 if (GET_CODE (x) == MEM) 670 { 671 /* If the operand is a PLUS, the MEM may be shared, 672 so make sure we have an unshared copy here. */ 673 if (GET_CODE (XEXP (x, 0)) == PLUS) 674 x = copy_rtx (x); 675 676 reg_equiv_memory_loc[i] = x; 677 } 678 else if (CONSTANT_P (x)) 679 { 680 if (LEGITIMATE_CONSTANT_P (x)) 681 reg_equiv_constant[i] = x; 682 else 683 reg_equiv_memory_loc[i] 684 = force_const_mem (GET_MODE (SET_DEST (set)), x); 685 } 686 else 687 continue; 688 689 /* If this register is being made equivalent to a MEM 690 and the MEM is not SET_SRC, the equivalencing insn 691 is one with the MEM as a SET_DEST and it occurs later. 692 So don't mark this insn now. */ 693 if (GET_CODE (x) != MEM 694 || rtx_equal_p (SET_SRC (set), x)) 695 reg_equiv_init[i] = insn; 696 } 697 } 698 } 699 700 /* If this insn is setting a MEM from a register equivalent to it, 701 this is the equivalencing insn. */ 702 else if (set && GET_CODE (SET_DEST (set)) == MEM 703 && GET_CODE (SET_SRC (set)) == REG 704 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] 705 && rtx_equal_p (SET_DEST (set), 706 reg_equiv_memory_loc[REGNO (SET_SRC (set))])) 707 reg_equiv_init[REGNO (SET_SRC (set))] = insn; 708 709 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 710 scan_paradoxical_subregs (PATTERN (insn)); 711 } 712 713 /* Does this function require a frame pointer? */ 714 715 frame_pointer_needed = (! flag_omit_frame_pointer 716#ifdef EXIT_IGNORE_STACK 717 /* ?? If EXIT_IGNORE_STACK is set, we will not save 718 and restore sp for alloca. So we can't eliminate 719 the frame pointer in that case. At some point, 720 we should improve this by emitting the 721 sp-adjusting insns for this case. */ 722 || (current_function_calls_alloca 723 && EXIT_IGNORE_STACK) 724#endif 725 || FRAME_POINTER_REQUIRED); 726 727 num_eliminable = 0; 728 729 /* Initialize the table of registers to eliminate. The way we do this 730 depends on how the eliminable registers were defined. */ 731#ifdef ELIMINABLE_REGS 732 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 733 { 734 ep->can_eliminate = ep->can_eliminate_previous 735 = (CAN_ELIMINATE (ep->from, ep->to) 736 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); 737 } 738#else 739 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous 740 = ! frame_pointer_needed; 741#endif 742 743 /* Count the number of eliminable registers and build the FROM and TO 744 REG rtx's. Note that code in gen_rtx will cause, e.g., 745 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. 746 We depend on this. */ 747 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 748 { 749 num_eliminable += ep->can_eliminate; 750 ep->from_rtx = gen_rtx_REG (Pmode, ep->from); 751 ep->to_rtx = gen_rtx_REG (Pmode, ep->to); 752 } 753 754 num_labels = max_label_num () - get_first_label_num (); 755 756 /* Allocate the tables used to store offset information at labels. */ 757 /* We used to use alloca here, but the size of what it would try to 758 allocate would occasionally cause it to exceed the stack limit and 759 cause a core dump. */ 760 real_known_ptr = xmalloc (num_labels); 761 real_at_ptr 762 = (int (*)[NUM_ELIMINABLE_REGS]) 763 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); 764 765 offsets_known_at = real_known_ptr - get_first_label_num (); 766 offsets_at 767 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ()); 768 769 /* Alter each pseudo-reg rtx to contain its hard reg number. 770 Assign stack slots to the pseudos that lack hard regs or equivalents. 771 Do not touch virtual registers. */ 772 773 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) 774 alter_reg (i, -1); 775 776 /* If we have some registers we think can be eliminated, scan all insns to 777 see if there is an insn that sets one of these registers to something 778 other than itself plus a constant. If so, the register cannot be 779 eliminated. Doing this scan here eliminates an extra pass through the 780 main reload loop in the most common case where register elimination 781 cannot be done. */ 782 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) 783 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN 784 || GET_CODE (insn) == CALL_INSN) 785 note_stores (PATTERN (insn), mark_not_eliminable); 786 787#ifndef REGISTER_CONSTRAINTS 788 /* If all the pseudo regs have hard regs, 789 except for those that are never referenced, 790 we know that no reloads are needed. */ 791 /* But that is not true if there are register constraints, since 792 in that case some pseudos might be in the wrong kind of hard reg. */ 793 794 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 795 if (reg_renumber[i] == -1 && REG_N_REFS (i) != 0) 796 break; 797 798 if (i == max_regno && num_eliminable == 0 && ! caller_save_needed) 799 { 800 free (real_known_ptr); 801 free (real_at_ptr); 802 return; 803 } 804#endif 805 806 /* Compute the order of preference for hard registers to spill. 807 Store them by decreasing preference in potential_reload_regs. */ 808 809 order_regs_for_reload (global); 810 811 /* So far, no hard regs have been spilled. */ 812 n_spills = 0; 813 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 814 spill_reg_order[i] = -1; 815 816 /* Initialize to -1, which means take the first spill register. */ 817 last_spill_reg = -1; 818 819 /* On most machines, we can't use any register explicitly used in the 820 rtl as a spill register. But on some, we have to. Those will have 821 taken care to keep the life of hard regs as short as possible. */ 822 823 if (! SMALL_REGISTER_CLASSES) 824 COPY_HARD_REG_SET (forbidden_regs, bad_spill_regs); 825 826 /* Spill any hard regs that we know we can't eliminate. */ 827 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 828 if (! ep->can_eliminate) 829 spill_hard_reg (ep->from, global, dumpfile, 1); 830 831#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 832 if (frame_pointer_needed) 833 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1); 834#endif 835 836 if (global) 837 for (i = 0; i < N_REG_CLASSES; i++) 838 { 839 basic_block_needs[i] = (char *) alloca (n_basic_blocks); 840 bzero (basic_block_needs[i], n_basic_blocks); 841 } 842 843 /* From now on, we need to emit any moves without making new pseudos. */ 844 reload_in_progress = 1; 845 846 /* This loop scans the entire function each go-round 847 and repeats until one repetition spills no additional hard regs. */ 848 849 /* This flag is set when a pseudo reg is spilled, 850 to require another pass. Note that getting an additional reload 851 reg does not necessarily imply any pseudo reg was spilled; 852 sometimes we find a reload reg that no pseudo reg was allocated in. */ 853 something_changed = 1; 854 /* This flag is set if there are any insns that require reloading. */ 855 something_needs_reloads = 0; 856 /* This flag is set if there are any insns that require register 857 eliminations. */ 858 something_needs_elimination = 0; 859 while (something_changed) 860 { 861 rtx after_call = 0; 862 863 /* For each class, number of reload regs needed in that class. 864 This is the maximum over all insns of the needs in that class 865 of the individual insn. */ 866 int max_needs[N_REG_CLASSES]; 867 /* For each class, size of group of consecutive regs 868 that is needed for the reloads of this class. */ 869 int group_size[N_REG_CLASSES]; 870 /* For each class, max number of consecutive groups needed. 871 (Each group contains group_size[CLASS] consecutive registers.) */ 872 int max_groups[N_REG_CLASSES]; 873 /* For each class, max number needed of regs that don't belong 874 to any of the groups. */ 875 int max_nongroups[N_REG_CLASSES]; 876 /* For each class, the machine mode which requires consecutive 877 groups of regs of that class. 878 If two different modes ever require groups of one class, 879 they must be the same size and equally restrictive for that class, 880 otherwise we can't handle the complexity. */ 881 enum machine_mode group_mode[N_REG_CLASSES]; 882 /* Record the insn where each maximum need is first found. */ 883 rtx max_needs_insn[N_REG_CLASSES]; 884 rtx max_groups_insn[N_REG_CLASSES]; 885 rtx max_nongroups_insn[N_REG_CLASSES]; 886 rtx x; 887 HOST_WIDE_INT starting_frame_size; 888#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 889 int previous_frame_pointer_needed = frame_pointer_needed; 890#endif 891 static char *reg_class_names[] = REG_CLASS_NAMES; 892 893 something_changed = 0; 894 bzero ((char *) max_needs, sizeof max_needs); 895 bzero ((char *) max_groups, sizeof max_groups); 896 bzero ((char *) max_nongroups, sizeof max_nongroups); 897 bzero ((char *) max_needs_insn, sizeof max_needs_insn); 898 bzero ((char *) max_groups_insn, sizeof max_groups_insn); 899 bzero ((char *) max_nongroups_insn, sizeof max_nongroups_insn); 900 bzero ((char *) group_size, sizeof group_size); 901 for (i = 0; i < N_REG_CLASSES; i++) 902 group_mode[i] = VOIDmode; 903 904 /* Keep track of which basic blocks are needing the reloads. */ 905 this_block = 0; 906 907 /* Remember whether any element of basic_block_needs 908 changes from 0 to 1 in this pass. */ 909 new_basic_block_needs = 0; 910 911 /* Round size of stack frame to BIGGEST_ALIGNMENT. This must be done 912 here because the stack size may be a part of the offset computation 913 for register elimination, and there might have been new stack slots 914 created in the last iteration of this loop. */ 915 assign_stack_local (BLKmode, 0, 0); 916 917 starting_frame_size = get_frame_size (); 918 919 /* Reset all offsets on eliminable registers to their initial values. */ 920#ifdef ELIMINABLE_REGS 921 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 922 { 923 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); 924 ep->previous_offset = ep->offset 925 = ep->max_offset = ep->initial_offset; 926 } 927#else 928#ifdef INITIAL_FRAME_POINTER_OFFSET 929 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset); 930#else 931 if (!FRAME_POINTER_REQUIRED) 932 abort (); 933 reg_eliminate[0].initial_offset = 0; 934#endif 935 reg_eliminate[0].previous_offset = reg_eliminate[0].max_offset 936 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset; 937#endif 938 939 num_not_at_initial_offset = 0; 940 941 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels); 942 943 /* Set a known offset for each forced label to be at the initial offset 944 of each elimination. We do this because we assume that all 945 computed jumps occur from a location where each elimination is 946 at its initial offset. */ 947 948 for (x = forced_labels; x; x = XEXP (x, 1)) 949 if (XEXP (x, 0)) 950 set_label_offsets (XEXP (x, 0), NULL_RTX, 1); 951 952 /* For each pseudo register that has an equivalent location defined, 953 try to eliminate any eliminable registers (such as the frame pointer) 954 assuming initial offsets for the replacement register, which 955 is the normal case. 956 957 If the resulting location is directly addressable, substitute 958 the MEM we just got directly for the old REG. 959 960 If it is not addressable but is a constant or the sum of a hard reg 961 and constant, it is probably not addressable because the constant is 962 out of range, in that case record the address; we will generate 963 hairy code to compute the address in a register each time it is 964 needed. Similarly if it is a hard register, but one that is not 965 valid as an address register. 966 967 If the location is not addressable, but does not have one of the 968 above forms, assign a stack slot. We have to do this to avoid the 969 potential of producing lots of reloads if, e.g., a location involves 970 a pseudo that didn't get a hard register and has an equivalent memory 971 location that also involves a pseudo that didn't get a hard register. 972 973 Perhaps at some point we will improve reload_when_needed handling 974 so this problem goes away. But that's very hairy. */ 975 976 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 977 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) 978 { 979 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); 980 981 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), 982 XEXP (x, 0))) 983 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; 984 else if (CONSTANT_P (XEXP (x, 0)) 985 || (GET_CODE (XEXP (x, 0)) == REG 986 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) 987 || (GET_CODE (XEXP (x, 0)) == PLUS 988 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG 989 && (REGNO (XEXP (XEXP (x, 0), 0)) 990 < FIRST_PSEUDO_REGISTER) 991 && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) 992 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; 993 else 994 { 995 /* Make a new stack slot. Then indicate that something 996 changed so we go back and recompute offsets for 997 eliminable registers because the allocation of memory 998 below might change some offset. reg_equiv_{mem,address} 999 will be set up for this pseudo on the next pass around 1000 the loop. */ 1001 reg_equiv_memory_loc[i] = 0; 1002 reg_equiv_init[i] = 0; 1003 alter_reg (i, -1); 1004 something_changed = 1; 1005 } 1006 } 1007 1008 /* If we allocated another pseudo to the stack, redo elimination 1009 bookkeeping. */ 1010 if (something_changed) 1011 continue; 1012 1013 /* If caller-saves needs a group, initialize the group to include 1014 the size and mode required for caller-saves. */ 1015 1016 if (caller_save_group_size > 1) 1017 { 1018 group_mode[(int) caller_save_spill_class] = Pmode; 1019 group_size[(int) caller_save_spill_class] = caller_save_group_size; 1020 } 1021 1022 /* Compute the most additional registers needed by any instruction. 1023 Collect information separately for each class of regs. */ 1024 1025 for (insn = first; insn; insn = NEXT_INSN (insn)) 1026 { 1027 if (global && this_block + 1 < n_basic_blocks 1028 && insn == basic_block_head[this_block+1]) 1029 ++this_block; 1030 1031 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which 1032 might include REG_LABEL), we need to see what effects this 1033 has on the known offsets at labels. */ 1034 1035 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN 1036 || (GET_RTX_CLASS (GET_CODE (insn)) == 'i' 1037 && REG_NOTES (insn) != 0)) 1038 set_label_offsets (insn, insn, 0); 1039 1040 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 1041 { 1042 /* Nonzero means don't use a reload reg that overlaps 1043 the place where a function value can be returned. */ 1044 rtx avoid_return_reg = 0; 1045 1046 rtx old_body = PATTERN (insn); 1047 int old_code = INSN_CODE (insn); 1048 rtx old_notes = REG_NOTES (insn); 1049 int did_elimination = 0; 1050 1051 /* To compute the number of reload registers of each class 1052 needed for an insn, we must simulate what choose_reload_regs 1053 can do. We do this by splitting an insn into an "input" and 1054 an "output" part. RELOAD_OTHER reloads are used in both. 1055 The input part uses those reloads, RELOAD_FOR_INPUT reloads, 1056 which must be live over the entire input section of reloads, 1057 and the maximum of all the RELOAD_FOR_INPUT_ADDRESS and 1058 RELOAD_FOR_OPERAND_ADDRESS reloads, which conflict with the 1059 inputs. 1060 1061 The registers needed for output are RELOAD_OTHER and 1062 RELOAD_FOR_OUTPUT, which are live for the entire output 1063 portion, and the maximum of all the RELOAD_FOR_OUTPUT_ADDRESS 1064 reloads for each operand. 1065 1066 The total number of registers needed is the maximum of the 1067 inputs and outputs. */ 1068 1069 struct needs 1070 { 1071 /* [0] is normal, [1] is nongroup. */ 1072 int regs[2][N_REG_CLASSES]; 1073 int groups[N_REG_CLASSES]; 1074 }; 1075 1076 /* Each `struct needs' corresponds to one RELOAD_... type. */ 1077 struct { 1078 struct needs other; 1079 struct needs input; 1080 struct needs output; 1081 struct needs insn; 1082 struct needs other_addr; 1083 struct needs op_addr; 1084 struct needs op_addr_reload; 1085 struct needs in_addr[MAX_RECOG_OPERANDS]; 1086 struct needs in_addr_addr[MAX_RECOG_OPERANDS]; 1087 struct needs out_addr[MAX_RECOG_OPERANDS]; 1088 struct needs out_addr_addr[MAX_RECOG_OPERANDS]; 1089 } insn_needs; 1090 1091 /* If needed, eliminate any eliminable registers. */ 1092 if (num_eliminable) 1093 did_elimination = eliminate_regs_in_insn (insn, 0); 1094 1095 /* Set avoid_return_reg if this is an insn 1096 that might use the value of a function call. */ 1097 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN) 1098 { 1099 if (GET_CODE (PATTERN (insn)) == SET) 1100 after_call = SET_DEST (PATTERN (insn)); 1101 else if (GET_CODE (PATTERN (insn)) == PARALLEL 1102 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 1103 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); 1104 else 1105 after_call = 0; 1106 } 1107 else if (SMALL_REGISTER_CLASSES && after_call != 0 1108 && !(GET_CODE (PATTERN (insn)) == SET 1109 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx) 1110 && GET_CODE (PATTERN (insn)) != USE) 1111 { 1112 if (reg_referenced_p (after_call, PATTERN (insn))) 1113 avoid_return_reg = after_call; 1114 after_call = 0; 1115 } 1116 1117 /* Analyze the instruction. */ 1118 find_reloads (insn, 0, spill_indirect_levels, global, 1119 spill_reg_order); 1120 1121 /* Remember for later shortcuts which insns had any reloads or 1122 register eliminations. 1123 1124 One might think that it would be worthwhile to mark insns 1125 that need register replacements but not reloads, but this is 1126 not safe because find_reloads may do some manipulation of 1127 the insn (such as swapping commutative operands), which would 1128 be lost when we restore the old pattern after register 1129 replacement. So the actions of find_reloads must be redone in 1130 subsequent passes or in reload_as_needed. 1131 1132 However, it is safe to mark insns that need reloads 1133 but not register replacement. */ 1134 1135 PUT_MODE (insn, (did_elimination ? QImode 1136 : n_reloads ? HImode 1137 : GET_MODE (insn) == DImode ? DImode 1138 : VOIDmode)); 1139 1140 /* Discard any register replacements done. */ 1141 if (did_elimination) 1142 { 1143 obstack_free (&reload_obstack, reload_firstobj); 1144 PATTERN (insn) = old_body; 1145 INSN_CODE (insn) = old_code; 1146 REG_NOTES (insn) = old_notes; 1147 something_needs_elimination = 1; 1148 } 1149 1150 /* If this insn has no reloads, we need not do anything except 1151 in the case of a CALL_INSN when we have caller-saves and 1152 caller-save needs reloads. */ 1153 1154 if (n_reloads == 0 1155 && ! (GET_CODE (insn) == CALL_INSN 1156 && caller_save_spill_class != NO_REGS)) 1157 continue; 1158 1159 something_needs_reloads = 1; 1160 bzero ((char *) &insn_needs, sizeof insn_needs); 1161 1162 /* Count each reload once in every class 1163 containing the reload's own class. */ 1164 1165 for (i = 0; i < n_reloads; i++) 1166 { 1167 register enum reg_class *p; 1168 enum reg_class class = reload_reg_class[i]; 1169 int size; 1170 enum machine_mode mode; 1171 struct needs *this_needs; 1172 1173 /* Don't count the dummy reloads, for which one of the 1174 regs mentioned in the insn can be used for reloading. 1175 Don't count optional reloads. 1176 Don't count reloads that got combined with others. */ 1177 if (reload_reg_rtx[i] != 0 1178 || reload_optional[i] != 0 1179 || (reload_out[i] == 0 && reload_in[i] == 0 1180 && ! reload_secondary_p[i])) 1181 continue; 1182 1183 /* Show that a reload register of this class is needed 1184 in this basic block. We do not use insn_needs and 1185 insn_groups because they are overly conservative for 1186 this purpose. */ 1187 if (global && ! basic_block_needs[(int) class][this_block]) 1188 { 1189 basic_block_needs[(int) class][this_block] = 1; 1190 new_basic_block_needs = 1; 1191 } 1192 1193 mode = reload_inmode[i]; 1194 if (GET_MODE_SIZE (reload_outmode[i]) > GET_MODE_SIZE (mode)) 1195 mode = reload_outmode[i]; 1196 size = CLASS_MAX_NREGS (class, mode); 1197 1198 /* Decide which time-of-use to count this reload for. */ 1199 switch (reload_when_needed[i]) 1200 { 1201 case RELOAD_OTHER: 1202 this_needs = &insn_needs.other; 1203 break; 1204 case RELOAD_FOR_INPUT: 1205 this_needs = &insn_needs.input; 1206 break; 1207 case RELOAD_FOR_OUTPUT: 1208 this_needs = &insn_needs.output; 1209 break; 1210 case RELOAD_FOR_INSN: 1211 this_needs = &insn_needs.insn; 1212 break; 1213 case RELOAD_FOR_OTHER_ADDRESS: 1214 this_needs = &insn_needs.other_addr; 1215 break; 1216 case RELOAD_FOR_INPUT_ADDRESS: 1217 this_needs = &insn_needs.in_addr[reload_opnum[i]]; 1218 break; 1219 case RELOAD_FOR_INPADDR_ADDRESS: 1220 this_needs = &insn_needs.in_addr_addr[reload_opnum[i]]; 1221 break; 1222 case RELOAD_FOR_OUTPUT_ADDRESS: 1223 this_needs = &insn_needs.out_addr[reload_opnum[i]]; 1224 break; 1225 case RELOAD_FOR_OUTADDR_ADDRESS: 1226 this_needs = &insn_needs.out_addr_addr[reload_opnum[i]]; 1227 break; 1228 case RELOAD_FOR_OPERAND_ADDRESS: 1229 this_needs = &insn_needs.op_addr; 1230 break; 1231 case RELOAD_FOR_OPADDR_ADDR: 1232 this_needs = &insn_needs.op_addr_reload; 1233 break; 1234 } 1235 1236 if (size > 1) 1237 { 1238 enum machine_mode other_mode, allocate_mode; 1239 1240 /* Count number of groups needed separately from 1241 number of individual regs needed. */ 1242 this_needs->groups[(int) class]++; 1243 p = reg_class_superclasses[(int) class]; 1244 while (*p != LIM_REG_CLASSES) 1245 this_needs->groups[(int) *p++]++; 1246 1247 /* Record size and mode of a group of this class. */ 1248 /* If more than one size group is needed, 1249 make all groups the largest needed size. */ 1250 if (group_size[(int) class] < size) 1251 { 1252 other_mode = group_mode[(int) class]; 1253 allocate_mode = mode; 1254 1255 group_size[(int) class] = size; 1256 group_mode[(int) class] = mode; 1257 } 1258 else 1259 { 1260 other_mode = mode; 1261 allocate_mode = group_mode[(int) class]; 1262 } 1263 1264 /* Crash if two dissimilar machine modes both need 1265 groups of consecutive regs of the same class. */ 1266 1267 if (other_mode != VOIDmode && other_mode != allocate_mode 1268 && ! modes_equiv_for_class_p (allocate_mode, 1269 other_mode, class)) 1270 fatal_insn ("Two dissimilar machine modes both need groups of consecutive regs of the same class", 1271 insn); 1272 } 1273 else if (size == 1) 1274 { 1275 this_needs->regs[reload_nongroup[i]][(int) class] += 1; 1276 p = reg_class_superclasses[(int) class]; 1277 while (*p != LIM_REG_CLASSES) 1278 this_needs->regs[reload_nongroup[i]][(int) *p++] += 1; 1279 } 1280 else 1281 abort (); 1282 } 1283 1284 /* All reloads have been counted for this insn; 1285 now merge the various times of use. 1286 This sets insn_needs, etc., to the maximum total number 1287 of registers needed at any point in this insn. */ 1288 1289 for (i = 0; i < N_REG_CLASSES; i++) 1290 { 1291 int in_max, out_max; 1292 1293 /* Compute normal and nongroup needs. */ 1294 for (j = 0; j <= 1; j++) 1295 { 1296 for (in_max = 0, out_max = 0, k = 0; 1297 k < reload_n_operands; k++) 1298 { 1299 in_max 1300 = MAX (in_max, 1301 (insn_needs.in_addr[k].regs[j][i] 1302 + insn_needs.in_addr_addr[k].regs[j][i])); 1303 out_max 1304 = MAX (out_max, insn_needs.out_addr[k].regs[j][i]); 1305 out_max 1306 = MAX (out_max, 1307 insn_needs.out_addr_addr[k].regs[j][i]); 1308 } 1309 1310 /* RELOAD_FOR_INSN reloads conflict with inputs, outputs, 1311 and operand addresses but not things used to reload 1312 them. Similarly, RELOAD_FOR_OPERAND_ADDRESS reloads 1313 don't conflict with things needed to reload inputs or 1314 outputs. */ 1315 1316 in_max = MAX (MAX (insn_needs.op_addr.regs[j][i], 1317 insn_needs.op_addr_reload.regs[j][i]), 1318 in_max); 1319 1320 out_max = MAX (out_max, insn_needs.insn.regs[j][i]); 1321 1322 insn_needs.input.regs[j][i] 1323 = MAX (insn_needs.input.regs[j][i] 1324 + insn_needs.op_addr.regs[j][i] 1325 + insn_needs.insn.regs[j][i], 1326 in_max + insn_needs.input.regs[j][i]); 1327 1328 insn_needs.output.regs[j][i] += out_max; 1329 insn_needs.other.regs[j][i] 1330 += MAX (MAX (insn_needs.input.regs[j][i], 1331 insn_needs.output.regs[j][i]), 1332 insn_needs.other_addr.regs[j][i]); 1333 1334 } 1335 1336 /* Now compute group needs. */ 1337 for (in_max = 0, out_max = 0, j = 0; 1338 j < reload_n_operands; j++) 1339 { 1340 in_max = MAX (in_max, insn_needs.in_addr[j].groups[i]); 1341 in_max = MAX (in_max, 1342 insn_needs.in_addr_addr[j].groups[i]); 1343 out_max 1344 = MAX (out_max, insn_needs.out_addr[j].groups[i]); 1345 out_max 1346 = MAX (out_max, insn_needs.out_addr_addr[j].groups[i]); 1347 } 1348 1349 in_max = MAX (MAX (insn_needs.op_addr.groups[i], 1350 insn_needs.op_addr_reload.groups[i]), 1351 in_max); 1352 out_max = MAX (out_max, insn_needs.insn.groups[i]); 1353 1354 insn_needs.input.groups[i] 1355 = MAX (insn_needs.input.groups[i] 1356 + insn_needs.op_addr.groups[i] 1357 + insn_needs.insn.groups[i], 1358 in_max + insn_needs.input.groups[i]); 1359 1360 insn_needs.output.groups[i] += out_max; 1361 insn_needs.other.groups[i] 1362 += MAX (MAX (insn_needs.input.groups[i], 1363 insn_needs.output.groups[i]), 1364 insn_needs.other_addr.groups[i]); 1365 } 1366 1367 /* If this is a CALL_INSN and caller-saves will need 1368 a spill register, act as if the spill register is 1369 needed for this insn. However, the spill register 1370 can be used by any reload of this insn, so we only 1371 need do something if no need for that class has 1372 been recorded. 1373 1374 The assumption that every CALL_INSN will trigger a 1375 caller-save is highly conservative, however, the number 1376 of cases where caller-saves will need a spill register but 1377 a block containing a CALL_INSN won't need a spill register 1378 of that class should be quite rare. 1379 1380 If a group is needed, the size and mode of the group will 1381 have been set up at the beginning of this loop. */ 1382 1383 if (GET_CODE (insn) == CALL_INSN 1384 && caller_save_spill_class != NO_REGS) 1385 { 1386 /* See if this register would conflict with any reload that 1387 needs a group or any reload that needs a nongroup. */ 1388 int nongroup_need = 0; 1389 int *caller_save_needs; 1390 1391 for (j = 0; j < n_reloads; j++) 1392 if (reg_classes_intersect_p (caller_save_spill_class, 1393 reload_reg_class[j]) 1394 && ((CLASS_MAX_NREGS 1395 (reload_reg_class[j], 1396 (GET_MODE_SIZE (reload_outmode[j]) 1397 > GET_MODE_SIZE (reload_inmode[j])) 1398 ? reload_outmode[j] : reload_inmode[j]) 1399 > 1) 1400 || reload_nongroup[j])) 1401 { 1402 nongroup_need = 1; 1403 break; 1404 } 1405 1406 caller_save_needs 1407 = (caller_save_group_size > 1 1408 ? insn_needs.other.groups 1409 : insn_needs.other.regs[nongroup_need]); 1410 1411 if (caller_save_needs[(int) caller_save_spill_class] == 0) 1412 { 1413 register enum reg_class *p 1414 = reg_class_superclasses[(int) caller_save_spill_class]; 1415 1416 caller_save_needs[(int) caller_save_spill_class]++; 1417 1418 while (*p != LIM_REG_CLASSES) 1419 caller_save_needs[(int) *p++] += 1; 1420 } 1421 1422 /* Show that this basic block will need a register of 1423 this class. */ 1424 1425 if (global 1426 && ! (basic_block_needs[(int) caller_save_spill_class] 1427 [this_block])) 1428 { 1429 basic_block_needs[(int) caller_save_spill_class] 1430 [this_block] = 1; 1431 new_basic_block_needs = 1; 1432 } 1433 } 1434 1435 /* If this insn stores the value of a function call, 1436 and that value is in a register that has been spilled, 1437 and if the insn needs a reload in a class 1438 that might use that register as the reload register, 1439 then add an extra need in that class. 1440 This makes sure we have a register available that does 1441 not overlap the return value. */ 1442 1443 if (SMALL_REGISTER_CLASSES && avoid_return_reg) 1444 { 1445 int regno = REGNO (avoid_return_reg); 1446 int nregs 1447 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); 1448 int r; 1449 int basic_needs[N_REG_CLASSES], basic_groups[N_REG_CLASSES]; 1450 1451 /* First compute the "basic needs", which counts a 1452 need only in the smallest class in which it 1453 is required. */ 1454 1455 bcopy ((char *) insn_needs.other.regs[0], 1456 (char *) basic_needs, sizeof basic_needs); 1457 bcopy ((char *) insn_needs.other.groups, 1458 (char *) basic_groups, sizeof basic_groups); 1459 1460 for (i = 0; i < N_REG_CLASSES; i++) 1461 { 1462 enum reg_class *p; 1463 1464 if (basic_needs[i] >= 0) 1465 for (p = reg_class_superclasses[i]; 1466 *p != LIM_REG_CLASSES; p++) 1467 basic_needs[(int) *p] -= basic_needs[i]; 1468 1469 if (basic_groups[i] >= 0) 1470 for (p = reg_class_superclasses[i]; 1471 *p != LIM_REG_CLASSES; p++) 1472 basic_groups[(int) *p] -= basic_groups[i]; 1473 } 1474 1475 /* Now count extra regs if there might be a conflict with 1476 the return value register. */ 1477 1478 for (r = regno; r < regno + nregs; r++) 1479 if (spill_reg_order[r] >= 0) 1480 for (i = 0; i < N_REG_CLASSES; i++) 1481 if (TEST_HARD_REG_BIT (reg_class_contents[i], r)) 1482 { 1483 if (basic_needs[i] > 0) 1484 { 1485 enum reg_class *p; 1486 1487 insn_needs.other.regs[0][i]++; 1488 p = reg_class_superclasses[i]; 1489 while (*p != LIM_REG_CLASSES) 1490 insn_needs.other.regs[0][(int) *p++]++; 1491 } 1492 if (basic_groups[i] > 0) 1493 { 1494 enum reg_class *p; 1495 1496 insn_needs.other.groups[i]++; 1497 p = reg_class_superclasses[i]; 1498 while (*p != LIM_REG_CLASSES) 1499 insn_needs.other.groups[(int) *p++]++; 1500 } 1501 } 1502 } 1503 1504 /* For each class, collect maximum need of any insn. */ 1505 1506 for (i = 0; i < N_REG_CLASSES; i++) 1507 { 1508 if (max_needs[i] < insn_needs.other.regs[0][i]) 1509 { 1510 max_needs[i] = insn_needs.other.regs[0][i]; 1511 max_needs_insn[i] = insn; 1512 } 1513 if (max_groups[i] < insn_needs.other.groups[i]) 1514 { 1515 max_groups[i] = insn_needs.other.groups[i]; 1516 max_groups_insn[i] = insn; 1517 } 1518 if (max_nongroups[i] < insn_needs.other.regs[1][i]) 1519 { 1520 max_nongroups[i] = insn_needs.other.regs[1][i]; 1521 max_nongroups_insn[i] = insn; 1522 } 1523 } 1524 } 1525 /* Note that there is a continue statement above. */ 1526 } 1527 1528 /* If we allocated any new memory locations, make another pass 1529 since it might have changed elimination offsets. */ 1530 if (starting_frame_size != get_frame_size ()) 1531 something_changed = 1; 1532 1533 if (dumpfile) 1534 for (i = 0; i < N_REG_CLASSES; i++) 1535 { 1536 if (max_needs[i] > 0) 1537 fprintf (dumpfile, 1538 ";; Need %d reg%s of class %s (for insn %d).\n", 1539 max_needs[i], max_needs[i] == 1 ? "" : "s", 1540 reg_class_names[i], INSN_UID (max_needs_insn[i])); 1541 if (max_nongroups[i] > 0) 1542 fprintf (dumpfile, 1543 ";; Need %d nongroup reg%s of class %s (for insn %d).\n", 1544 max_nongroups[i], max_nongroups[i] == 1 ? "" : "s", 1545 reg_class_names[i], INSN_UID (max_nongroups_insn[i])); 1546 if (max_groups[i] > 0) 1547 fprintf (dumpfile, 1548 ";; Need %d group%s (%smode) of class %s (for insn %d).\n", 1549 max_groups[i], max_groups[i] == 1 ? "" : "s", 1550 mode_name[(int) group_mode[i]], 1551 reg_class_names[i], INSN_UID (max_groups_insn[i])); 1552 } 1553 1554 /* If we have caller-saves, set up the save areas and see if caller-save 1555 will need a spill register. */ 1556 1557 if (caller_save_needed) 1558 { 1559 /* Set the offsets for setup_save_areas. */ 1560 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 1561 ep++) 1562 ep->previous_offset = ep->max_offset; 1563 1564 if ( ! setup_save_areas (&something_changed) 1565 && caller_save_spill_class == NO_REGS) 1566 { 1567 /* The class we will need depends on whether the machine 1568 supports the sum of two registers for an address; see 1569 find_address_reloads for details. */ 1570 1571 caller_save_spill_class 1572 = double_reg_address_ok ? INDEX_REG_CLASS : BASE_REG_CLASS; 1573 caller_save_group_size 1574 = CLASS_MAX_NREGS (caller_save_spill_class, Pmode); 1575 something_changed = 1; 1576 } 1577 } 1578 1579 /* See if anything that happened changes which eliminations are valid. 1580 For example, on the Sparc, whether or not the frame pointer can 1581 be eliminated can depend on what registers have been used. We need 1582 not check some conditions again (such as flag_omit_frame_pointer) 1583 since they can't have changed. */ 1584 1585 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 1586 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) 1587#ifdef ELIMINABLE_REGS 1588 || ! CAN_ELIMINATE (ep->from, ep->to) 1589#endif 1590 ) 1591 ep->can_eliminate = 0; 1592 1593 /* Look for the case where we have discovered that we can't replace 1594 register A with register B and that means that we will now be 1595 trying to replace register A with register C. This means we can 1596 no longer replace register C with register B and we need to disable 1597 such an elimination, if it exists. This occurs often with A == ap, 1598 B == sp, and C == fp. */ 1599 1600 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 1601 { 1602 struct elim_table *op; 1603 register int new_to = -1; 1604 1605 if (! ep->can_eliminate && ep->can_eliminate_previous) 1606 { 1607 /* Find the current elimination for ep->from, if there is a 1608 new one. */ 1609 for (op = reg_eliminate; 1610 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) 1611 if (op->from == ep->from && op->can_eliminate) 1612 { 1613 new_to = op->to; 1614 break; 1615 } 1616 1617 /* See if there is an elimination of NEW_TO -> EP->TO. If so, 1618 disable it. */ 1619 for (op = reg_eliminate; 1620 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) 1621 if (op->from == new_to && op->to == ep->to) 1622 op->can_eliminate = 0; 1623 } 1624 } 1625 1626 /* See if any registers that we thought we could eliminate the previous 1627 time are no longer eliminable. If so, something has changed and we 1628 must spill the register. Also, recompute the number of eliminable 1629 registers and see if the frame pointer is needed; it is if there is 1630 no elimination of the frame pointer that we can perform. */ 1631 1632 frame_pointer_needed = 1; 1633 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 1634 { 1635 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM 1636 && ep->to != HARD_FRAME_POINTER_REGNUM) 1637 frame_pointer_needed = 0; 1638 1639 if (! ep->can_eliminate && ep->can_eliminate_previous) 1640 { 1641 ep->can_eliminate_previous = 0; 1642 spill_hard_reg (ep->from, global, dumpfile, 1); 1643 something_changed = 1; 1644 num_eliminable--; 1645 } 1646 } 1647 1648#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 1649 /* If we didn't need a frame pointer last time, but we do now, spill 1650 the hard frame pointer. */ 1651 if (frame_pointer_needed && ! previous_frame_pointer_needed) 1652 { 1653 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, global, dumpfile, 1); 1654 something_changed = 1; 1655 } 1656#endif 1657 1658 /* If all needs are met, we win. */ 1659 1660 for (i = 0; i < N_REG_CLASSES; i++) 1661 if (max_needs[i] > 0 || max_groups[i] > 0 || max_nongroups[i] > 0) 1662 break; 1663 if (i == N_REG_CLASSES && !new_basic_block_needs && ! something_changed) 1664 break; 1665 1666 /* Not all needs are met; must spill some hard regs. */ 1667 1668 /* Put all registers spilled so far back in potential_reload_regs, but 1669 put them at the front, since we've already spilled most of the 1670 pseudos in them (we might have left some pseudos unspilled if they 1671 were in a block that didn't need any spill registers of a conflicting 1672 class. We used to try to mark off the need for those registers, 1673 but doing so properly is very complex and reallocating them is the 1674 simpler approach. First, "pack" potential_reload_regs by pushing 1675 any nonnegative entries towards the end. That will leave room 1676 for the registers we already spilled. 1677 1678 Also, undo the marking of the spill registers from the last time 1679 around in FORBIDDEN_REGS since we will be probably be allocating 1680 them again below. 1681 1682 ??? It is theoretically possible that we might end up not using one 1683 of our previously-spilled registers in this allocation, even though 1684 they are at the head of the list. It's not clear what to do about 1685 this, but it was no better before, when we marked off the needs met 1686 by the previously-spilled registers. With the current code, globals 1687 can be allocated into these registers, but locals cannot. */ 1688 1689 if (n_spills) 1690 { 1691 for (i = j = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) 1692 if (potential_reload_regs[i] != -1) 1693 potential_reload_regs[j--] = potential_reload_regs[i]; 1694 1695 for (i = 0; i < n_spills; i++) 1696 { 1697 potential_reload_regs[i] = spill_regs[i]; 1698 spill_reg_order[spill_regs[i]] = -1; 1699 CLEAR_HARD_REG_BIT (forbidden_regs, spill_regs[i]); 1700 } 1701 1702 n_spills = 0; 1703 } 1704 1705 /* Now find more reload regs to satisfy the remaining need 1706 Do it by ascending class number, since otherwise a reg 1707 might be spilled for a big class and might fail to count 1708 for a smaller class even though it belongs to that class. 1709 1710 Count spilled regs in `spills', and add entries to 1711 `spill_regs' and `spill_reg_order'. 1712 1713 ??? Note there is a problem here. 1714 When there is a need for a group in a high-numbered class, 1715 and also need for non-group regs that come from a lower class, 1716 the non-group regs are chosen first. If there aren't many regs, 1717 they might leave no room for a group. 1718 1719 This was happening on the 386. To fix it, we added the code 1720 that calls possible_group_p, so that the lower class won't 1721 break up the last possible group. 1722 1723 Really fixing the problem would require changes above 1724 in counting the regs already spilled, and in choose_reload_regs. 1725 It might be hard to avoid introducing bugs there. */ 1726 1727 CLEAR_HARD_REG_SET (counted_for_groups); 1728 CLEAR_HARD_REG_SET (counted_for_nongroups); 1729 1730 for (class = 0; class < N_REG_CLASSES; class++) 1731 { 1732 /* First get the groups of registers. 1733 If we got single registers first, we might fragment 1734 possible groups. */ 1735 while (max_groups[class] > 0) 1736 { 1737 /* If any single spilled regs happen to form groups, 1738 count them now. Maybe we don't really need 1739 to spill another group. */ 1740 count_possible_groups (group_size, group_mode, max_groups, 1741 class); 1742 1743 if (max_groups[class] <= 0) 1744 break; 1745 1746 /* Groups of size 2 (the only groups used on most machines) 1747 are treated specially. */ 1748 if (group_size[class] == 2) 1749 { 1750 /* First, look for a register that will complete a group. */ 1751 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1752 { 1753 int other; 1754 1755 j = potential_reload_regs[i]; 1756 if (j >= 0 && ! TEST_HARD_REG_BIT (bad_spill_regs, j) 1757 && 1758 ((j > 0 && (other = j - 1, spill_reg_order[other] >= 0) 1759 && TEST_HARD_REG_BIT (reg_class_contents[class], j) 1760 && TEST_HARD_REG_BIT (reg_class_contents[class], other) 1761 && HARD_REGNO_MODE_OK (other, group_mode[class]) 1762 && ! TEST_HARD_REG_BIT (counted_for_nongroups, 1763 other) 1764 /* We don't want one part of another group. 1765 We could get "two groups" that overlap! */ 1766 && ! TEST_HARD_REG_BIT (counted_for_groups, other)) 1767 || 1768 (j < FIRST_PSEUDO_REGISTER - 1 1769 && (other = j + 1, spill_reg_order[other] >= 0) 1770 && TEST_HARD_REG_BIT (reg_class_contents[class], j) 1771 && TEST_HARD_REG_BIT (reg_class_contents[class], other) 1772 && HARD_REGNO_MODE_OK (j, group_mode[class]) 1773 && ! TEST_HARD_REG_BIT (counted_for_nongroups, 1774 other) 1775 && ! TEST_HARD_REG_BIT (counted_for_groups, 1776 other)))) 1777 { 1778 register enum reg_class *p; 1779 1780 /* We have found one that will complete a group, 1781 so count off one group as provided. */ 1782 max_groups[class]--; 1783 p = reg_class_superclasses[class]; 1784 while (*p != LIM_REG_CLASSES) 1785 { 1786 if (group_size [(int) *p] <= group_size [class]) 1787 max_groups[(int) *p]--; 1788 p++; 1789 } 1790 1791 /* Indicate both these regs are part of a group. */ 1792 SET_HARD_REG_BIT (counted_for_groups, j); 1793 SET_HARD_REG_BIT (counted_for_groups, other); 1794 break; 1795 } 1796 } 1797 /* We can't complete a group, so start one. */ 1798 /* Look for a pair neither of which is explicitly used. */ 1799 if (SMALL_REGISTER_CLASSES && i == FIRST_PSEUDO_REGISTER) 1800 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1801 { 1802 int k; 1803 j = potential_reload_regs[i]; 1804 /* Verify that J+1 is a potential reload reg. */ 1805 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++) 1806 if (potential_reload_regs[k] == j + 1) 1807 break; 1808 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER 1809 && k < FIRST_PSEUDO_REGISTER 1810 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0 1811 && TEST_HARD_REG_BIT (reg_class_contents[class], j) 1812 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1) 1813 && HARD_REGNO_MODE_OK (j, group_mode[class]) 1814 && ! TEST_HARD_REG_BIT (counted_for_nongroups, 1815 j + 1) 1816 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1) 1817 /* Reject J at this stage 1818 if J+1 was explicitly used. */ 1819 && ! regs_explicitly_used[j + 1]) 1820 break; 1821 } 1822 /* Now try any group at all 1823 whose registers are not in bad_spill_regs. */ 1824 if (i == FIRST_PSEUDO_REGISTER) 1825 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1826 { 1827 int k; 1828 j = potential_reload_regs[i]; 1829 /* Verify that J+1 is a potential reload reg. */ 1830 for (k = 0; k < FIRST_PSEUDO_REGISTER; k++) 1831 if (potential_reload_regs[k] == j + 1) 1832 break; 1833 if (j >= 0 && j + 1 < FIRST_PSEUDO_REGISTER 1834 && k < FIRST_PSEUDO_REGISTER 1835 && spill_reg_order[j] < 0 && spill_reg_order[j + 1] < 0 1836 && TEST_HARD_REG_BIT (reg_class_contents[class], j) 1837 && TEST_HARD_REG_BIT (reg_class_contents[class], j + 1) 1838 && HARD_REGNO_MODE_OK (j, group_mode[class]) 1839 && ! TEST_HARD_REG_BIT (counted_for_nongroups, 1840 j + 1) 1841 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + 1)) 1842 break; 1843 } 1844 1845 /* I should be the index in potential_reload_regs 1846 of the new reload reg we have found. */ 1847 1848 if (i >= FIRST_PSEUDO_REGISTER) 1849 { 1850 /* There are no groups left to spill. */ 1851 spill_failure (max_groups_insn[class]); 1852 failure = 1; 1853 goto failed; 1854 } 1855 else 1856 something_changed 1857 |= new_spill_reg (i, class, max_needs, NULL_PTR, 1858 global, dumpfile); 1859 } 1860 else 1861 { 1862 /* For groups of more than 2 registers, 1863 look for a sufficient sequence of unspilled registers, 1864 and spill them all at once. */ 1865 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1866 { 1867 int k; 1868 1869 j = potential_reload_regs[i]; 1870 if (j >= 0 1871 && j + group_size[class] <= FIRST_PSEUDO_REGISTER 1872 && HARD_REGNO_MODE_OK (j, group_mode[class])) 1873 { 1874 /* Check each reg in the sequence. */ 1875 for (k = 0; k < group_size[class]; k++) 1876 if (! (spill_reg_order[j + k] < 0 1877 && ! TEST_HARD_REG_BIT (bad_spill_regs, j + k) 1878 && TEST_HARD_REG_BIT (reg_class_contents[class], j + k))) 1879 break; 1880 /* We got a full sequence, so spill them all. */ 1881 if (k == group_size[class]) 1882 { 1883 register enum reg_class *p; 1884 for (k = 0; k < group_size[class]; k++) 1885 { 1886 int idx; 1887 SET_HARD_REG_BIT (counted_for_groups, j + k); 1888 for (idx = 0; idx < FIRST_PSEUDO_REGISTER; idx++) 1889 if (potential_reload_regs[idx] == j + k) 1890 break; 1891 something_changed 1892 |= new_spill_reg (idx, class, 1893 max_needs, NULL_PTR, 1894 global, dumpfile); 1895 } 1896 1897 /* We have found one that will complete a group, 1898 so count off one group as provided. */ 1899 max_groups[class]--; 1900 p = reg_class_superclasses[class]; 1901 while (*p != LIM_REG_CLASSES) 1902 { 1903 if (group_size [(int) *p] 1904 <= group_size [class]) 1905 max_groups[(int) *p]--; 1906 p++; 1907 } 1908 break; 1909 } 1910 } 1911 } 1912 /* We couldn't find any registers for this reload. 1913 Avoid going into an infinite loop. */ 1914 if (i >= FIRST_PSEUDO_REGISTER) 1915 { 1916 /* There are no groups left. */ 1917 spill_failure (max_groups_insn[class]); 1918 failure = 1; 1919 goto failed; 1920 } 1921 } 1922 } 1923 1924 /* Now similarly satisfy all need for single registers. */ 1925 1926 while (max_needs[class] > 0 || max_nongroups[class] > 0) 1927 { 1928 /* If we spilled enough regs, but they weren't counted 1929 against the non-group need, see if we can count them now. 1930 If so, we can avoid some actual spilling. */ 1931 if (max_needs[class] <= 0 && max_nongroups[class] > 0) 1932 for (i = 0; i < n_spills; i++) 1933 if (TEST_HARD_REG_BIT (reg_class_contents[class], 1934 spill_regs[i]) 1935 && !TEST_HARD_REG_BIT (counted_for_groups, 1936 spill_regs[i]) 1937 && !TEST_HARD_REG_BIT (counted_for_nongroups, 1938 spill_regs[i]) 1939 && max_nongroups[class] > 0) 1940 { 1941 register enum reg_class *p; 1942 1943 SET_HARD_REG_BIT (counted_for_nongroups, spill_regs[i]); 1944 max_nongroups[class]--; 1945 p = reg_class_superclasses[class]; 1946 while (*p != LIM_REG_CLASSES) 1947 max_nongroups[(int) *p++]--; 1948 } 1949 if (max_needs[class] <= 0 && max_nongroups[class] <= 0) 1950 break; 1951 1952 /* Consider the potential reload regs that aren't 1953 yet in use as reload regs, in order of preference. 1954 Find the most preferred one that's in this class. */ 1955 1956 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1957 if (potential_reload_regs[i] >= 0 1958 && TEST_HARD_REG_BIT (reg_class_contents[class], 1959 potential_reload_regs[i]) 1960 /* If this reg will not be available for groups, 1961 pick one that does not foreclose possible groups. 1962 This is a kludge, and not very general, 1963 but it should be sufficient to make the 386 work, 1964 and the problem should not occur on machines with 1965 more registers. */ 1966 && (max_nongroups[class] == 0 1967 || possible_group_p (potential_reload_regs[i], max_groups))) 1968 break; 1969 1970 /* If we couldn't get a register, try to get one even if we 1971 might foreclose possible groups. This may cause problems 1972 later, but that's better than aborting now, since it is 1973 possible that we will, in fact, be able to form the needed 1974 group even with this allocation. */ 1975 1976 if (i >= FIRST_PSEUDO_REGISTER 1977 && (asm_noperands (max_needs[class] > 0 1978 ? max_needs_insn[class] 1979 : max_nongroups_insn[class]) 1980 < 0)) 1981 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1982 if (potential_reload_regs[i] >= 0 1983 && TEST_HARD_REG_BIT (reg_class_contents[class], 1984 potential_reload_regs[i])) 1985 break; 1986 1987 /* I should be the index in potential_reload_regs 1988 of the new reload reg we have found. */ 1989 1990 if (i >= FIRST_PSEUDO_REGISTER) 1991 { 1992 /* There are no possible registers left to spill. */ 1993 spill_failure (max_needs[class] > 0 ? max_needs_insn[class] 1994 : max_nongroups_insn[class]); 1995 failure = 1; 1996 goto failed; 1997 } 1998 else 1999 something_changed 2000 |= new_spill_reg (i, class, max_needs, max_nongroups, 2001 global, dumpfile); 2002 } 2003 } 2004 } 2005 2006 /* If global-alloc was run, notify it of any register eliminations we have 2007 done. */ 2008 if (global) 2009 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2010 if (ep->can_eliminate) 2011 mark_elimination (ep->from, ep->to); 2012 2013 /* Insert code to save and restore call-clobbered hard regs 2014 around calls. Tell if what mode to use so that we will process 2015 those insns in reload_as_needed if we have to. */ 2016 2017 if (caller_save_needed) 2018 save_call_clobbered_regs (num_eliminable ? QImode 2019 : caller_save_spill_class != NO_REGS ? HImode 2020 : VOIDmode); 2021 2022 /* If a pseudo has no hard reg, delete the insns that made the equivalence. 2023 If that insn didn't set the register (i.e., it copied the register to 2024 memory), just delete that insn instead of the equivalencing insn plus 2025 anything now dead. If we call delete_dead_insn on that insn, we may 2026 delete the insn that actually sets the register if the register die 2027 there and that is incorrect. */ 2028 2029 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 2030 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0 2031 && GET_CODE (reg_equiv_init[i]) != NOTE) 2032 { 2033 if (reg_set_p (regno_reg_rtx[i], PATTERN (reg_equiv_init[i]))) 2034 delete_dead_insn (reg_equiv_init[i]); 2035 else 2036 { 2037 PUT_CODE (reg_equiv_init[i], NOTE); 2038 NOTE_SOURCE_FILE (reg_equiv_init[i]) = 0; 2039 NOTE_LINE_NUMBER (reg_equiv_init[i]) = NOTE_INSN_DELETED; 2040 } 2041 } 2042 2043 /* Use the reload registers where necessary 2044 by generating move instructions to move the must-be-register 2045 values into or out of the reload registers. */ 2046 2047 if (something_needs_reloads || something_needs_elimination 2048 || (caller_save_needed && num_eliminable) 2049 || caller_save_spill_class != NO_REGS) 2050 reload_as_needed (first, global); 2051 2052 /* If we were able to eliminate the frame pointer, show that it is no 2053 longer live at the start of any basic block. If it ls live by 2054 virtue of being in a pseudo, that pseudo will be marked live 2055 and hence the frame pointer will be known to be live via that 2056 pseudo. */ 2057 2058 if (! frame_pointer_needed) 2059 for (i = 0; i < n_basic_blocks; i++) 2060 CLEAR_REGNO_REG_SET (basic_block_live_at_start[i], 2061 HARD_FRAME_POINTER_REGNUM); 2062 2063 /* Come here (with failure set nonzero) if we can't get enough spill regs 2064 and we decide not to abort about it. */ 2065 failed: 2066 2067 reload_in_progress = 0; 2068 2069 /* Now eliminate all pseudo regs by modifying them into 2070 their equivalent memory references. 2071 The REG-rtx's for the pseudos are modified in place, 2072 so all insns that used to refer to them now refer to memory. 2073 2074 For a reg that has a reg_equiv_address, all those insns 2075 were changed by reloading so that no insns refer to it any longer; 2076 but the DECL_RTL of a variable decl may refer to it, 2077 and if so this causes the debugging info to mention the variable. */ 2078 2079 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 2080 { 2081 rtx addr = 0; 2082 int in_struct = 0; 2083 int is_readonly = 0; 2084 2085 if (reg_equiv_memory_loc[i]) 2086 { 2087 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]); 2088 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]); 2089 } 2090 2091 if (reg_equiv_mem[i]) 2092 addr = XEXP (reg_equiv_mem[i], 0); 2093 2094 if (reg_equiv_address[i]) 2095 addr = reg_equiv_address[i]; 2096 2097 if (addr) 2098 { 2099 if (reg_renumber[i] < 0) 2100 { 2101 rtx reg = regno_reg_rtx[i]; 2102 XEXP (reg, 0) = addr; 2103 REG_USERVAR_P (reg) = 0; 2104 RTX_UNCHANGING_P (reg) = is_readonly; 2105 MEM_IN_STRUCT_P (reg) = in_struct; 2106 /* We have no alias information about this newly created 2107 MEM. */ 2108 MEM_ALIAS_SET (reg) = 0; 2109 PUT_CODE (reg, MEM); 2110 } 2111 else if (reg_equiv_mem[i]) 2112 XEXP (reg_equiv_mem[i], 0) = addr; 2113 } 2114 } 2115 2116 /* Make a pass over all the insns and delete all USEs which we inserted 2117 only to tag a REG_EQUAL note on them; if PRESERVE_DEATH_INFO_REGNO_P 2118 is defined, also remove death notes for things that are no longer 2119 registers or no longer die in the insn (e.g., an input and output 2120 pseudo being tied). */ 2121 2122 for (insn = first; insn; insn = NEXT_INSN (insn)) 2123 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 2124 { 2125#ifdef PRESERVE_DEATH_INFO_REGNO_P 2126 rtx note, next; 2127#endif 2128 2129 if (GET_CODE (PATTERN (insn)) == USE 2130 && find_reg_note (insn, REG_EQUAL, NULL_RTX)) 2131 { 2132 PUT_CODE (insn, NOTE); 2133 NOTE_SOURCE_FILE (insn) = 0; 2134 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 2135 continue; 2136 } 2137#ifdef PRESERVE_DEATH_INFO_REGNO_P 2138 for (note = REG_NOTES (insn); note; note = next) 2139 { 2140 next = XEXP (note, 1); 2141 if (REG_NOTE_KIND (note) == REG_DEAD 2142 && (GET_CODE (XEXP (note, 0)) != REG 2143 || reg_set_p (XEXP (note, 0), PATTERN (insn)))) 2144 remove_note (insn, note); 2145 } 2146#endif 2147 } 2148 2149 /* If we are doing stack checking, give a warning if this function's 2150 frame size is larger than we expect. */ 2151 if (flag_stack_check && ! STACK_CHECK_BUILTIN) 2152 { 2153 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; 2154 2155 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2156 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) 2157 size += UNITS_PER_WORD; 2158 2159 if (size > STACK_CHECK_MAX_FRAME_SIZE) 2160 warning ("frame size too large for reliable stack checking"); 2161 } 2162 2163 /* Indicate that we no longer have known memory locations or constants. */ 2164 reg_equiv_constant = 0; 2165 reg_equiv_memory_loc = 0; 2166 2167 if (real_known_ptr) 2168 free (real_known_ptr); 2169 if (real_at_ptr) 2170 free (real_at_ptr); 2171 2172 if (scratch_list) 2173 free (scratch_list); 2174 scratch_list = 0; 2175 if (scratch_block) 2176 free (scratch_block); 2177 scratch_block = 0; 2178 2179 CLEAR_HARD_REG_SET (used_spill_regs); 2180 for (i = 0; i < n_spills; i++) 2181 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); 2182 2183 return failure; 2184} 2185 2186/* Nonzero if, after spilling reg REGNO for non-groups, 2187 it will still be possible to find a group if we still need one. */ 2188 2189static int 2190possible_group_p (regno, max_groups) 2191 int regno; 2192 int *max_groups; 2193{ 2194 int i; 2195 int class = (int) NO_REGS; 2196 2197 for (i = 0; i < (int) N_REG_CLASSES; i++) 2198 if (max_groups[i] > 0) 2199 { 2200 class = i; 2201 break; 2202 } 2203 2204 if (class == (int) NO_REGS) 2205 return 1; 2206 2207 /* Consider each pair of consecutive registers. */ 2208 for (i = 0; i < FIRST_PSEUDO_REGISTER - 1; i++) 2209 { 2210 /* Ignore pairs that include reg REGNO. */ 2211 if (i == regno || i + 1 == regno) 2212 continue; 2213 2214 /* Ignore pairs that are outside the class that needs the group. 2215 ??? Here we fail to handle the case where two different classes 2216 independently need groups. But this never happens with our 2217 current machine descriptions. */ 2218 if (! (TEST_HARD_REG_BIT (reg_class_contents[class], i) 2219 && TEST_HARD_REG_BIT (reg_class_contents[class], i + 1))) 2220 continue; 2221 2222 /* A pair of consecutive regs we can still spill does the trick. */ 2223 if (spill_reg_order[i] < 0 && spill_reg_order[i + 1] < 0 2224 && ! TEST_HARD_REG_BIT (bad_spill_regs, i) 2225 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1)) 2226 return 1; 2227 2228 /* A pair of one already spilled and one we can spill does it 2229 provided the one already spilled is not otherwise reserved. */ 2230 if (spill_reg_order[i] < 0 2231 && ! TEST_HARD_REG_BIT (bad_spill_regs, i) 2232 && spill_reg_order[i + 1] >= 0 2233 && ! TEST_HARD_REG_BIT (counted_for_groups, i + 1) 2234 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i + 1)) 2235 return 1; 2236 if (spill_reg_order[i + 1] < 0 2237 && ! TEST_HARD_REG_BIT (bad_spill_regs, i + 1) 2238 && spill_reg_order[i] >= 0 2239 && ! TEST_HARD_REG_BIT (counted_for_groups, i) 2240 && ! TEST_HARD_REG_BIT (counted_for_nongroups, i)) 2241 return 1; 2242 } 2243 2244 return 0; 2245} 2246 2247/* Count any groups of CLASS that can be formed from the registers recently 2248 spilled. */ 2249 2250static void 2251count_possible_groups (group_size, group_mode, max_groups, class) 2252 int *group_size; 2253 enum machine_mode *group_mode; 2254 int *max_groups; 2255 int class; 2256{ 2257 HARD_REG_SET new; 2258 int i, j; 2259 2260 /* Now find all consecutive groups of spilled registers 2261 and mark each group off against the need for such groups. 2262 But don't count them against ordinary need, yet. */ 2263 2264 if (group_size[class] == 0) 2265 return; 2266 2267 CLEAR_HARD_REG_SET (new); 2268 2269 /* Make a mask of all the regs that are spill regs in class I. */ 2270 for (i = 0; i < n_spills; i++) 2271 if (TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i]) 2272 && ! TEST_HARD_REG_BIT (counted_for_groups, spill_regs[i]) 2273 && ! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i])) 2274 SET_HARD_REG_BIT (new, spill_regs[i]); 2275 2276 /* Find each consecutive group of them. */ 2277 for (i = 0; i < FIRST_PSEUDO_REGISTER && max_groups[class] > 0; i++) 2278 if (TEST_HARD_REG_BIT (new, i) 2279 && i + group_size[class] <= FIRST_PSEUDO_REGISTER 2280 && HARD_REGNO_MODE_OK (i, group_mode[class])) 2281 { 2282 for (j = 1; j < group_size[class]; j++) 2283 if (! TEST_HARD_REG_BIT (new, i + j)) 2284 break; 2285 2286 if (j == group_size[class]) 2287 { 2288 /* We found a group. Mark it off against this class's need for 2289 groups, and against each superclass too. */ 2290 register enum reg_class *p; 2291 2292 max_groups[class]--; 2293 p = reg_class_superclasses[class]; 2294 while (*p != LIM_REG_CLASSES) 2295 { 2296 if (group_size [(int) *p] <= group_size [class]) 2297 max_groups[(int) *p]--; 2298 p++; 2299 } 2300 2301 /* Don't count these registers again. */ 2302 for (j = 0; j < group_size[class]; j++) 2303 SET_HARD_REG_BIT (counted_for_groups, i + j); 2304 } 2305 2306 /* Skip to the last reg in this group. When i is incremented above, 2307 it will then point to the first reg of the next possible group. */ 2308 i += j - 1; 2309 } 2310} 2311 2312/* ALLOCATE_MODE is a register mode that needs to be reloaded. OTHER_MODE is 2313 another mode that needs to be reloaded for the same register class CLASS. 2314 If any reg in CLASS allows ALLOCATE_MODE but not OTHER_MODE, fail. 2315 ALLOCATE_MODE will never be smaller than OTHER_MODE. 2316 2317 This code used to also fail if any reg in CLASS allows OTHER_MODE but not 2318 ALLOCATE_MODE. This test is unnecessary, because we will never try to put 2319 something of mode ALLOCATE_MODE into an OTHER_MODE register. Testing this 2320 causes unnecessary failures on machines requiring alignment of register 2321 groups when the two modes are different sizes, because the larger mode has 2322 more strict alignment rules than the smaller mode. */ 2323 2324static int 2325modes_equiv_for_class_p (allocate_mode, other_mode, class) 2326 enum machine_mode allocate_mode, other_mode; 2327 enum reg_class class; 2328{ 2329 register int regno; 2330 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 2331 { 2332 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno) 2333 && HARD_REGNO_MODE_OK (regno, allocate_mode) 2334 && ! HARD_REGNO_MODE_OK (regno, other_mode)) 2335 return 0; 2336 } 2337 return 1; 2338} 2339 2340/* Handle the failure to find a register to spill. 2341 INSN should be one of the insns which needed this particular spill reg. */ 2342 2343static void 2344spill_failure (insn) 2345 rtx insn; 2346{ 2347 if (asm_noperands (PATTERN (insn)) >= 0) 2348 error_for_asm (insn, "`asm' needs too many reloads"); 2349 else 2350 fatal_insn ("Unable to find a register to spill.", insn); 2351} 2352 2353/* Add a new register to the tables of available spill-registers 2354 (as well as spilling all pseudos allocated to the register). 2355 I is the index of this register in potential_reload_regs. 2356 CLASS is the regclass whose need is being satisfied. 2357 MAX_NEEDS and MAX_NONGROUPS are the vectors of needs, 2358 so that this register can count off against them. 2359 MAX_NONGROUPS is 0 if this register is part of a group. 2360 GLOBAL and DUMPFILE are the same as the args that `reload' got. */ 2361 2362static int 2363new_spill_reg (i, class, max_needs, max_nongroups, global, dumpfile) 2364 int i; 2365 int class; 2366 int *max_needs; 2367 int *max_nongroups; 2368 int global; 2369 FILE *dumpfile; 2370{ 2371 register enum reg_class *p; 2372 int val; 2373 int regno = potential_reload_regs[i]; 2374 2375 if (i >= FIRST_PSEUDO_REGISTER) 2376 abort (); /* Caller failed to find any register. */ 2377 2378 if (fixed_regs[regno] || TEST_HARD_REG_BIT (forbidden_regs, regno)) 2379 { 2380 static char *reg_class_names[] = REG_CLASS_NAMES; 2381 fatal ("fixed or forbidden register %d (%s) was spilled for class %s.\n\ 2382This may be due to a compiler bug or to impossible asm\n\ 2383statements or clauses.", regno, reg_names[regno], reg_class_names[class]); 2384 } 2385 2386 /* Make reg REGNO an additional reload reg. */ 2387 2388 potential_reload_regs[i] = -1; 2389 spill_regs[n_spills] = regno; 2390 spill_reg_order[regno] = n_spills; 2391 if (dumpfile) 2392 fprintf (dumpfile, "Spilling reg %d.\n", spill_regs[n_spills]); 2393 2394 /* Clear off the needs we just satisfied. */ 2395 2396 max_needs[class]--; 2397 p = reg_class_superclasses[class]; 2398 while (*p != LIM_REG_CLASSES) 2399 max_needs[(int) *p++]--; 2400 2401 if (max_nongroups && max_nongroups[class] > 0) 2402 { 2403 SET_HARD_REG_BIT (counted_for_nongroups, regno); 2404 max_nongroups[class]--; 2405 p = reg_class_superclasses[class]; 2406 while (*p != LIM_REG_CLASSES) 2407 max_nongroups[(int) *p++]--; 2408 } 2409 2410 /* Spill every pseudo reg that was allocated to this reg 2411 or to something that overlaps this reg. */ 2412 2413 val = spill_hard_reg (spill_regs[n_spills], global, dumpfile, 0); 2414 2415 /* If there are some registers still to eliminate and this register 2416 wasn't ever used before, additional stack space may have to be 2417 allocated to store this register. Thus, we may have changed the offset 2418 between the stack and frame pointers, so mark that something has changed. 2419 (If new pseudos were spilled, thus requiring more space, VAL would have 2420 been set non-zero by the call to spill_hard_reg above since additional 2421 reloads may be needed in that case. 2422 2423 One might think that we need only set VAL to 1 if this is a call-used 2424 register. However, the set of registers that must be saved by the 2425 prologue is not identical to the call-used set. For example, the 2426 register used by the call insn for the return PC is a call-used register, 2427 but must be saved by the prologue. */ 2428 if (num_eliminable && ! regs_ever_live[spill_regs[n_spills]]) 2429 val = 1; 2430 2431 regs_ever_live[spill_regs[n_spills]] = 1; 2432 n_spills++; 2433 2434 return val; 2435} 2436 2437/* Delete an unneeded INSN and any previous insns who sole purpose is loading 2438 data that is dead in INSN. */ 2439 2440static void 2441delete_dead_insn (insn) 2442 rtx insn; 2443{ 2444 rtx prev = prev_real_insn (insn); 2445 rtx prev_dest; 2446 2447 /* If the previous insn sets a register that dies in our insn, delete it 2448 too. */ 2449 if (prev && GET_CODE (PATTERN (prev)) == SET 2450 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) 2451 && reg_mentioned_p (prev_dest, PATTERN (insn)) 2452 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) 2453 && ! side_effects_p (SET_SRC (PATTERN (prev)))) 2454 delete_dead_insn (prev); 2455 2456 PUT_CODE (insn, NOTE); 2457 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 2458 NOTE_SOURCE_FILE (insn) = 0; 2459} 2460 2461/* Modify the home of pseudo-reg I. 2462 The new home is present in reg_renumber[I]. 2463 2464 FROM_REG may be the hard reg that the pseudo-reg is being spilled from; 2465 or it may be -1, meaning there is none or it is not relevant. 2466 This is used so that all pseudos spilled from a given hard reg 2467 can share one stack slot. */ 2468 2469static void 2470alter_reg (i, from_reg) 2471 register int i; 2472 int from_reg; 2473{ 2474 /* When outputting an inline function, this can happen 2475 for a reg that isn't actually used. */ 2476 if (regno_reg_rtx[i] == 0) 2477 return; 2478 2479 /* If the reg got changed to a MEM at rtl-generation time, 2480 ignore it. */ 2481 if (GET_CODE (regno_reg_rtx[i]) != REG) 2482 return; 2483 2484 /* Modify the reg-rtx to contain the new hard reg 2485 number or else to contain its pseudo reg number. */ 2486 REGNO (regno_reg_rtx[i]) 2487 = reg_renumber[i] >= 0 ? reg_renumber[i] : i; 2488 2489 /* If we have a pseudo that is needed but has no hard reg or equivalent, 2490 allocate a stack slot for it. */ 2491 2492 if (reg_renumber[i] < 0 2493 && REG_N_REFS (i) > 0 2494 && reg_equiv_constant[i] == 0 2495 && reg_equiv_memory_loc[i] == 0) 2496 { 2497 register rtx x; 2498 int inherent_size = PSEUDO_REGNO_BYTES (i); 2499 int total_size = MAX (inherent_size, reg_max_ref_width[i]); 2500 int adjust = 0; 2501 2502 /* Each pseudo reg has an inherent size which comes from its own mode, 2503 and a total size which provides room for paradoxical subregs 2504 which refer to the pseudo reg in wider modes. 2505 2506 We can use a slot already allocated if it provides both 2507 enough inherent space and enough total space. 2508 Otherwise, we allocate a new slot, making sure that it has no less 2509 inherent space, and no less total space, then the previous slot. */ 2510 if (from_reg == -1) 2511 { 2512 /* No known place to spill from => no slot to reuse. */ 2513 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, 2514 inherent_size == total_size ? 0 : -1); 2515 if (BYTES_BIG_ENDIAN) 2516 /* Cancel the big-endian correction done in assign_stack_local. 2517 Get the address of the beginning of the slot. 2518 This is so we can do a big-endian correction unconditionally 2519 below. */ 2520 adjust = inherent_size - total_size; 2521 2522 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); 2523 } 2524 /* Reuse a stack slot if possible. */ 2525 else if (spill_stack_slot[from_reg] != 0 2526 && spill_stack_slot_width[from_reg] >= total_size 2527 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) 2528 >= inherent_size)) 2529 x = spill_stack_slot[from_reg]; 2530 /* Allocate a bigger slot. */ 2531 else 2532 { 2533 /* Compute maximum size needed, both for inherent size 2534 and for total size. */ 2535 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); 2536 rtx stack_slot; 2537 if (spill_stack_slot[from_reg]) 2538 { 2539 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) 2540 > inherent_size) 2541 mode = GET_MODE (spill_stack_slot[from_reg]); 2542 if (spill_stack_slot_width[from_reg] > total_size) 2543 total_size = spill_stack_slot_width[from_reg]; 2544 } 2545 /* Make a slot with that size. */ 2546 x = assign_stack_local (mode, total_size, 2547 inherent_size == total_size ? 0 : -1); 2548 stack_slot = x; 2549 if (BYTES_BIG_ENDIAN) 2550 { 2551 /* Cancel the big-endian correction done in assign_stack_local. 2552 Get the address of the beginning of the slot. 2553 This is so we can do a big-endian correction unconditionally 2554 below. */ 2555 adjust = GET_MODE_SIZE (mode) - total_size; 2556 if (adjust) 2557 stack_slot = gen_rtx_MEM (mode_for_size (total_size 2558 * BITS_PER_UNIT, 2559 MODE_INT, 1), 2560 plus_constant (XEXP (x, 0), adjust)); 2561 } 2562 spill_stack_slot[from_reg] = stack_slot; 2563 spill_stack_slot_width[from_reg] = total_size; 2564 } 2565 2566 /* On a big endian machine, the "address" of the slot 2567 is the address of the low part that fits its inherent mode. */ 2568 if (BYTES_BIG_ENDIAN && inherent_size < total_size) 2569 adjust += (total_size - inherent_size); 2570 2571 /* If we have any adjustment to make, or if the stack slot is the 2572 wrong mode, make a new stack slot. */ 2573 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i])) 2574 { 2575 x = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]), 2576 plus_constant (XEXP (x, 0), adjust)); 2577 2578 /* If this was shared among registers, must ensure we never 2579 set it readonly since that can cause scheduling 2580 problems. Note we would only have in this adjustment 2581 case in any event, since the code above doesn't set it. */ 2582 2583 if (from_reg == -1) 2584 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); 2585 } 2586 2587 /* Save the stack slot for later. */ 2588 reg_equiv_memory_loc[i] = x; 2589 } 2590} 2591 2592/* Mark the slots in regs_ever_live for the hard regs 2593 used by pseudo-reg number REGNO. */ 2594 2595void 2596mark_home_live (regno) 2597 int regno; 2598{ 2599 register int i, lim; 2600 i = reg_renumber[regno]; 2601 if (i < 0) 2602 return; 2603 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); 2604 while (i < lim) 2605 regs_ever_live[i++] = 1; 2606} 2607 2608/* Mark the registers used in SCRATCH as being live. */ 2609 2610static void 2611mark_scratch_live (scratch) 2612 rtx scratch; 2613{ 2614 register int i; 2615 int regno = REGNO (scratch); 2616 int lim = regno + HARD_REGNO_NREGS (regno, GET_MODE (scratch)); 2617 2618 for (i = regno; i < lim; i++) 2619 regs_ever_live[i] = 1; 2620} 2621 2622/* This function handles the tracking of elimination offsets around branches. 2623 2624 X is a piece of RTL being scanned. 2625 2626 INSN is the insn that it came from, if any. 2627 2628 INITIAL_P is non-zero if we are to set the offset to be the initial 2629 offset and zero if we are setting the offset of the label to be the 2630 current offset. */ 2631 2632static void 2633set_label_offsets (x, insn, initial_p) 2634 rtx x; 2635 rtx insn; 2636 int initial_p; 2637{ 2638 enum rtx_code code = GET_CODE (x); 2639 rtx tem; 2640 int i; 2641 struct elim_table *p; 2642 2643 switch (code) 2644 { 2645 case LABEL_REF: 2646 if (LABEL_REF_NONLOCAL_P (x)) 2647 return; 2648 2649 x = XEXP (x, 0); 2650 2651 /* ... fall through ... */ 2652 2653 case CODE_LABEL: 2654 /* If we know nothing about this label, set the desired offsets. Note 2655 that this sets the offset at a label to be the offset before a label 2656 if we don't know anything about the label. This is not correct for 2657 the label after a BARRIER, but is the best guess we can make. If 2658 we guessed wrong, we will suppress an elimination that might have 2659 been possible had we been able to guess correctly. */ 2660 2661 if (! offsets_known_at[CODE_LABEL_NUMBER (x)]) 2662 { 2663 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2664 offsets_at[CODE_LABEL_NUMBER (x)][i] 2665 = (initial_p ? reg_eliminate[i].initial_offset 2666 : reg_eliminate[i].offset); 2667 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1; 2668 } 2669 2670 /* Otherwise, if this is the definition of a label and it is 2671 preceded by a BARRIER, set our offsets to the known offset of 2672 that label. */ 2673 2674 else if (x == insn 2675 && (tem = prev_nonnote_insn (insn)) != 0 2676 && GET_CODE (tem) == BARRIER) 2677 { 2678 num_not_at_initial_offset = 0; 2679 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2680 { 2681 reg_eliminate[i].offset = reg_eliminate[i].previous_offset 2682 = offsets_at[CODE_LABEL_NUMBER (x)][i]; 2683 if (reg_eliminate[i].can_eliminate 2684 && (reg_eliminate[i].offset 2685 != reg_eliminate[i].initial_offset)) 2686 num_not_at_initial_offset++; 2687 } 2688 } 2689 2690 else 2691 /* If neither of the above cases is true, compare each offset 2692 with those previously recorded and suppress any eliminations 2693 where the offsets disagree. */ 2694 2695 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2696 if (offsets_at[CODE_LABEL_NUMBER (x)][i] 2697 != (initial_p ? reg_eliminate[i].initial_offset 2698 : reg_eliminate[i].offset)) 2699 reg_eliminate[i].can_eliminate = 0; 2700 2701 return; 2702 2703 case JUMP_INSN: 2704 set_label_offsets (PATTERN (insn), insn, initial_p); 2705 2706 /* ... fall through ... */ 2707 2708 case INSN: 2709 case CALL_INSN: 2710 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly 2711 and hence must have all eliminations at their initial offsets. */ 2712 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) 2713 if (REG_NOTE_KIND (tem) == REG_LABEL) 2714 set_label_offsets (XEXP (tem, 0), insn, 1); 2715 return; 2716 2717 case ADDR_VEC: 2718 case ADDR_DIFF_VEC: 2719 /* Each of the labels in the address vector must be at their initial 2720 offsets. We want the first field for ADDR_VEC and the second 2721 field for ADDR_DIFF_VEC. */ 2722 2723 for (i = 0; i < XVECLEN (x, code == ADDR_DIFF_VEC); i++) 2724 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), 2725 insn, initial_p); 2726 return; 2727 2728 case SET: 2729 /* We only care about setting PC. If the source is not RETURN, 2730 IF_THEN_ELSE, or a label, disable any eliminations not at 2731 their initial offsets. Similarly if any arm of the IF_THEN_ELSE 2732 isn't one of those possibilities. For branches to a label, 2733 call ourselves recursively. 2734 2735 Note that this can disable elimination unnecessarily when we have 2736 a non-local goto since it will look like a non-constant jump to 2737 someplace in the current function. This isn't a significant 2738 problem since such jumps will normally be when all elimination 2739 pairs are back to their initial offsets. */ 2740 2741 if (SET_DEST (x) != pc_rtx) 2742 return; 2743 2744 switch (GET_CODE (SET_SRC (x))) 2745 { 2746 case PC: 2747 case RETURN: 2748 return; 2749 2750 case LABEL_REF: 2751 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); 2752 return; 2753 2754 case IF_THEN_ELSE: 2755 tem = XEXP (SET_SRC (x), 1); 2756 if (GET_CODE (tem) == LABEL_REF) 2757 set_label_offsets (XEXP (tem, 0), insn, initial_p); 2758 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) 2759 break; 2760 2761 tem = XEXP (SET_SRC (x), 2); 2762 if (GET_CODE (tem) == LABEL_REF) 2763 set_label_offsets (XEXP (tem, 0), insn, initial_p); 2764 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) 2765 break; 2766 return; 2767 2768 default: 2769 break; 2770 } 2771 2772 /* If we reach here, all eliminations must be at their initial 2773 offset because we are doing a jump to a variable address. */ 2774 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) 2775 if (p->offset != p->initial_offset) 2776 p->can_eliminate = 0; 2777 break; 2778 2779 default: 2780 break; 2781 } 2782} 2783 2784/* Used for communication between the next two function to properly share 2785 the vector for an ASM_OPERANDS. */ 2786 2787static struct rtvec_def *old_asm_operands_vec, *new_asm_operands_vec; 2788 2789/* Scan X and replace any eliminable registers (such as fp) with a 2790 replacement (such as sp), plus an offset. 2791 2792 MEM_MODE is the mode of an enclosing MEM. We need this to know how 2793 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a 2794 MEM, we are allowed to replace a sum of a register and the constant zero 2795 with the register, which we cannot do outside a MEM. In addition, we need 2796 to record the fact that a register is referenced outside a MEM. 2797 2798 If INSN is an insn, it is the insn containing X. If we replace a REG 2799 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a 2800 CLOBBER of the pseudo after INSN so find_equiv_regs will know that 2801 the REG is being modified. 2802 2803 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). 2804 That's used when we eliminate in expressions stored in notes. 2805 This means, do not set ref_outside_mem even if the reference 2806 is outside of MEMs. 2807 2808 If we see a modification to a register we know about, take the 2809 appropriate action (see case SET, below). 2810 2811 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had 2812 replacements done assuming all offsets are at their initial values. If 2813 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we 2814 encounter, return the actual location so that find_reloads will do 2815 the proper thing. */ 2816 2817rtx 2818eliminate_regs (x, mem_mode, insn) 2819 rtx x; 2820 enum machine_mode mem_mode; 2821 rtx insn; 2822{ 2823 enum rtx_code code = GET_CODE (x); 2824 struct elim_table *ep; 2825 int regno; 2826 rtx new; 2827 int i, j; 2828 char *fmt; 2829 int copied = 0; 2830 2831 switch (code) 2832 { 2833 case CONST_INT: 2834 case CONST_DOUBLE: 2835 case CONST: 2836 case SYMBOL_REF: 2837 case CODE_LABEL: 2838 case PC: 2839 case CC0: 2840 case ASM_INPUT: 2841 case ADDR_VEC: 2842 case ADDR_DIFF_VEC: 2843 case RETURN: 2844 return x; 2845 2846 case ADDRESSOF: 2847 /* This is only for the benefit of the debugging backends, which call 2848 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are 2849 removed after CSE. */ 2850 new = eliminate_regs (XEXP (x, 0), 0, insn); 2851 if (GET_CODE (new) == MEM) 2852 return XEXP (new, 0); 2853 return x; 2854 2855 case REG: 2856 regno = REGNO (x); 2857 2858 /* First handle the case where we encounter a bare register that 2859 is eliminable. Replace it with a PLUS. */ 2860 if (regno < FIRST_PSEUDO_REGISTER) 2861 { 2862 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2863 ep++) 2864 if (ep->from_rtx == x && ep->can_eliminate) 2865 { 2866 if (! mem_mode 2867 /* Refs inside notes don't count for this purpose. */ 2868 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST 2869 || GET_CODE (insn) == INSN_LIST))) 2870 ep->ref_outside_mem = 1; 2871 return plus_constant (ep->to_rtx, ep->previous_offset); 2872 } 2873 2874 } 2875 else if (reg_equiv_memory_loc && reg_equiv_memory_loc[regno] 2876 && (reg_equiv_address[regno] || num_not_at_initial_offset)) 2877 { 2878 /* In this case, find_reloads would attempt to either use an 2879 incorrect address (if something is not at its initial offset) 2880 or substitute an replaced address into an insn (which loses 2881 if the offset is changed by some later action). So we simply 2882 return the replaced stack slot (assuming it is changed by 2883 elimination) and ignore the fact that this is actually a 2884 reference to the pseudo. Ensure we make a copy of the 2885 address in case it is shared. */ 2886 new = eliminate_regs (reg_equiv_memory_loc[regno], mem_mode, insn); 2887 if (new != reg_equiv_memory_loc[regno]) 2888 { 2889 if (insn != 0 && GET_CODE (insn) != EXPR_LIST 2890 && GET_CODE (insn) != INSN_LIST) 2891 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, x), insn)) 2892 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX); 2893 return copy_rtx (new); 2894 } 2895 } 2896 return x; 2897 2898 case PLUS: 2899 /* If this is the sum of an eliminable register and a constant, rework 2900 the sum. */ 2901 if (GET_CODE (XEXP (x, 0)) == REG 2902 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 2903 && CONSTANT_P (XEXP (x, 1))) 2904 { 2905 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2906 ep++) 2907 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) 2908 { 2909 if (! mem_mode 2910 /* Refs inside notes don't count for this purpose. */ 2911 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST 2912 || GET_CODE (insn) == INSN_LIST))) 2913 ep->ref_outside_mem = 1; 2914 2915 /* The only time we want to replace a PLUS with a REG (this 2916 occurs when the constant operand of the PLUS is the negative 2917 of the offset) is when we are inside a MEM. We won't want 2918 to do so at other times because that would change the 2919 structure of the insn in a way that reload can't handle. 2920 We special-case the commonest situation in 2921 eliminate_regs_in_insn, so just replace a PLUS with a 2922 PLUS here, unless inside a MEM. */ 2923 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT 2924 && INTVAL (XEXP (x, 1)) == - ep->previous_offset) 2925 return ep->to_rtx; 2926 else 2927 return gen_rtx_PLUS (Pmode, ep->to_rtx, 2928 plus_constant (XEXP (x, 1), 2929 ep->previous_offset)); 2930 } 2931 2932 /* If the register is not eliminable, we are done since the other 2933 operand is a constant. */ 2934 return x; 2935 } 2936 2937 /* If this is part of an address, we want to bring any constant to the 2938 outermost PLUS. We will do this by doing register replacement in 2939 our operands and seeing if a constant shows up in one of them. 2940 2941 We assume here this is part of an address (or a "load address" insn) 2942 since an eliminable register is not likely to appear in any other 2943 context. 2944 2945 If we have (plus (eliminable) (reg)), we want to produce 2946 (plus (plus (replacement) (reg) (const))). If this was part of a 2947 normal add insn, (plus (replacement) (reg)) will be pushed as a 2948 reload. This is the desired action. */ 2949 2950 { 2951 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2952 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); 2953 2954 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) 2955 { 2956 /* If one side is a PLUS and the other side is a pseudo that 2957 didn't get a hard register but has a reg_equiv_constant, 2958 we must replace the constant here since it may no longer 2959 be in the position of any operand. */ 2960 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG 2961 && REGNO (new1) >= FIRST_PSEUDO_REGISTER 2962 && reg_renumber[REGNO (new1)] < 0 2963 && reg_equiv_constant != 0 2964 && reg_equiv_constant[REGNO (new1)] != 0) 2965 new1 = reg_equiv_constant[REGNO (new1)]; 2966 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG 2967 && REGNO (new0) >= FIRST_PSEUDO_REGISTER 2968 && reg_renumber[REGNO (new0)] < 0 2969 && reg_equiv_constant[REGNO (new0)] != 0) 2970 new0 = reg_equiv_constant[REGNO (new0)]; 2971 2972 new = form_sum (new0, new1); 2973 2974 /* As above, if we are not inside a MEM we do not want to 2975 turn a PLUS into something else. We might try to do so here 2976 for an addition of 0 if we aren't optimizing. */ 2977 if (! mem_mode && GET_CODE (new) != PLUS) 2978 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); 2979 else 2980 return new; 2981 } 2982 } 2983 return x; 2984 2985 case MULT: 2986 /* If this is the product of an eliminable register and a 2987 constant, apply the distribute law and move the constant out 2988 so that we have (plus (mult ..) ..). This is needed in order 2989 to keep load-address insns valid. This case is pathological. 2990 We ignore the possibility of overflow here. */ 2991 if (GET_CODE (XEXP (x, 0)) == REG 2992 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 2993 && GET_CODE (XEXP (x, 1)) == CONST_INT) 2994 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2995 ep++) 2996 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) 2997 { 2998 if (! mem_mode 2999 /* Refs inside notes don't count for this purpose. */ 3000 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST 3001 || GET_CODE (insn) == INSN_LIST))) 3002 ep->ref_outside_mem = 1; 3003 3004 return 3005 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), 3006 ep->previous_offset * INTVAL (XEXP (x, 1))); 3007 } 3008 3009 /* ... fall through ... */ 3010 3011 case CALL: 3012 case COMPARE: 3013 case MINUS: 3014 case DIV: case UDIV: 3015 case MOD: case UMOD: 3016 case AND: case IOR: case XOR: 3017 case ROTATERT: case ROTATE: 3018 case ASHIFTRT: case LSHIFTRT: case ASHIFT: 3019 case NE: case EQ: 3020 case GE: case GT: case GEU: case GTU: 3021 case LE: case LT: case LEU: case LTU: 3022 { 3023 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); 3024 rtx new1 3025 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; 3026 3027 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) 3028 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); 3029 } 3030 return x; 3031 3032 case EXPR_LIST: 3033 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ 3034 if (XEXP (x, 0)) 3035 { 3036 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 3037 if (new != XEXP (x, 0)) 3038 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); 3039 } 3040 3041 /* ... fall through ... */ 3042 3043 case INSN_LIST: 3044 /* Now do eliminations in the rest of the chain. If this was 3045 an EXPR_LIST, this might result in allocating more memory than is 3046 strictly needed, but it simplifies the code. */ 3047 if (XEXP (x, 1)) 3048 { 3049 new = eliminate_regs (XEXP (x, 1), mem_mode, insn); 3050 if (new != XEXP (x, 1)) 3051 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); 3052 } 3053 return x; 3054 3055 case PRE_INC: 3056 case POST_INC: 3057 case PRE_DEC: 3058 case POST_DEC: 3059 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3060 if (ep->to_rtx == XEXP (x, 0)) 3061 { 3062 int size = GET_MODE_SIZE (mem_mode); 3063 3064 /* If more bytes than MEM_MODE are pushed, account for them. */ 3065#ifdef PUSH_ROUNDING 3066 if (ep->to_rtx == stack_pointer_rtx) 3067 size = PUSH_ROUNDING (size); 3068#endif 3069 if (code == PRE_DEC || code == POST_DEC) 3070 ep->offset += size; 3071 else 3072 ep->offset -= size; 3073 } 3074 3075 /* Fall through to generic unary operation case. */ 3076 case STRICT_LOW_PART: 3077 case NEG: case NOT: 3078 case SIGN_EXTEND: case ZERO_EXTEND: 3079 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: 3080 case FLOAT: case FIX: 3081 case UNSIGNED_FIX: case UNSIGNED_FLOAT: 3082 case ABS: 3083 case SQRT: 3084 case FFS: 3085 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 3086 if (new != XEXP (x, 0)) 3087 return gen_rtx_fmt_e (code, GET_MODE (x), new); 3088 return x; 3089 3090 case SUBREG: 3091 /* Similar to above processing, but preserve SUBREG_WORD. 3092 Convert (subreg (mem)) to (mem) if not paradoxical. 3093 Also, if we have a non-paradoxical (subreg (pseudo)) and the 3094 pseudo didn't get a hard reg, we must replace this with the 3095 eliminated version of the memory location because push_reloads 3096 may do the replacement in certain circumstances. */ 3097 if (GET_CODE (SUBREG_REG (x)) == REG 3098 && (GET_MODE_SIZE (GET_MODE (x)) 3099 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 3100 && reg_equiv_memory_loc != 0 3101 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) 3102 { 3103 new = eliminate_regs (reg_equiv_memory_loc[REGNO (SUBREG_REG (x))], 3104 mem_mode, insn); 3105 3106 /* If we didn't change anything, we must retain the pseudo. */ 3107 if (new == reg_equiv_memory_loc[REGNO (SUBREG_REG (x))]) 3108 new = SUBREG_REG (x); 3109 else 3110 { 3111 /* In this case, we must show that the pseudo is used in this 3112 insn so that delete_output_reload will do the right thing. */ 3113 if (insn != 0 && GET_CODE (insn) != EXPR_LIST 3114 && GET_CODE (insn) != INSN_LIST) 3115 REG_NOTES (emit_insn_before (gen_rtx_USE (VOIDmode, 3116 SUBREG_REG (x)), 3117 insn)) 3118 = gen_rtx_EXPR_LIST (REG_EQUAL, new, NULL_RTX); 3119 3120 /* Ensure NEW isn't shared in case we have to reload it. */ 3121 new = copy_rtx (new); 3122 } 3123 } 3124 else 3125 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); 3126 3127 if (new != XEXP (x, 0)) 3128 { 3129 int x_size = GET_MODE_SIZE (GET_MODE (x)); 3130 int new_size = GET_MODE_SIZE (GET_MODE (new)); 3131 3132 if (GET_CODE (new) == MEM 3133 && ((x_size < new_size 3134#ifdef WORD_REGISTER_OPERATIONS 3135 /* On these machines, combine can create rtl of the form 3136 (set (subreg:m1 (reg:m2 R) 0) ...) 3137 where m1 < m2, and expects something interesting to 3138 happen to the entire word. Moreover, it will use the 3139 (reg:m2 R) later, expecting all bits to be preserved. 3140 So if the number of words is the same, preserve the 3141 subreg so that push_reloads can see it. */ 3142 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD) 3143#endif 3144 ) 3145 || (x_size == new_size)) 3146 ) 3147 { 3148 int offset = SUBREG_WORD (x) * UNITS_PER_WORD; 3149 enum machine_mode mode = GET_MODE (x); 3150 3151 if (BYTES_BIG_ENDIAN) 3152 offset += (MIN (UNITS_PER_WORD, 3153 GET_MODE_SIZE (GET_MODE (new))) 3154 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))); 3155 3156 PUT_MODE (new, mode); 3157 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset); 3158 return new; 3159 } 3160 else 3161 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x)); 3162 } 3163 3164 return x; 3165 3166 case USE: 3167 /* If using a register that is the source of an eliminate we still 3168 think can be performed, note it cannot be performed since we don't 3169 know how this register is used. */ 3170 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3171 if (ep->from_rtx == XEXP (x, 0)) 3172 ep->can_eliminate = 0; 3173 3174 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 3175 if (new != XEXP (x, 0)) 3176 return gen_rtx_fmt_e (code, GET_MODE (x), new); 3177 return x; 3178 3179 case CLOBBER: 3180 /* If clobbering a register that is the replacement register for an 3181 elimination we still think can be performed, note that it cannot 3182 be performed. Otherwise, we need not be concerned about it. */ 3183 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3184 if (ep->to_rtx == XEXP (x, 0)) 3185 ep->can_eliminate = 0; 3186 3187 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 3188 if (new != XEXP (x, 0)) 3189 return gen_rtx_fmt_e (code, GET_MODE (x), new); 3190 return x; 3191 3192 case ASM_OPERANDS: 3193 { 3194 rtx *temp_vec; 3195 /* Properly handle sharing input and constraint vectors. */ 3196 if (ASM_OPERANDS_INPUT_VEC (x) != old_asm_operands_vec) 3197 { 3198 /* When we come to a new vector not seen before, 3199 scan all its elements; keep the old vector if none 3200 of them changes; otherwise, make a copy. */ 3201 old_asm_operands_vec = ASM_OPERANDS_INPUT_VEC (x); 3202 temp_vec = (rtx *) alloca (XVECLEN (x, 3) * sizeof (rtx)); 3203 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) 3204 temp_vec[i] = eliminate_regs (ASM_OPERANDS_INPUT (x, i), 3205 mem_mode, insn); 3206 3207 for (i = 0; i < ASM_OPERANDS_INPUT_LENGTH (x); i++) 3208 if (temp_vec[i] != ASM_OPERANDS_INPUT (x, i)) 3209 break; 3210 3211 if (i == ASM_OPERANDS_INPUT_LENGTH (x)) 3212 new_asm_operands_vec = old_asm_operands_vec; 3213 else 3214 new_asm_operands_vec 3215 = gen_rtvec_v (ASM_OPERANDS_INPUT_LENGTH (x), temp_vec); 3216 } 3217 3218 /* If we had to copy the vector, copy the entire ASM_OPERANDS. */ 3219 if (new_asm_operands_vec == old_asm_operands_vec) 3220 return x; 3221 3222 new = gen_rtx_ASM_OPERANDS (VOIDmode, ASM_OPERANDS_TEMPLATE (x), 3223 ASM_OPERANDS_OUTPUT_CONSTRAINT (x), 3224 ASM_OPERANDS_OUTPUT_IDX (x), 3225 new_asm_operands_vec, 3226 ASM_OPERANDS_INPUT_CONSTRAINT_VEC (x), 3227 ASM_OPERANDS_SOURCE_FILE (x), 3228 ASM_OPERANDS_SOURCE_LINE (x)); 3229 new->volatil = x->volatil; 3230 return new; 3231 } 3232 3233 case SET: 3234 /* Check for setting a register that we know about. */ 3235 if (GET_CODE (SET_DEST (x)) == REG) 3236 { 3237 /* See if this is setting the replacement register for an 3238 elimination. 3239 3240 If DEST is the hard frame pointer, we do nothing because we 3241 assume that all assignments to the frame pointer are for 3242 non-local gotos and are being done at a time when they are valid 3243 and do not disturb anything else. Some machines want to 3244 eliminate a fake argument pointer (or even a fake frame pointer) 3245 with either the real frame or the stack pointer. Assignments to 3246 the hard frame pointer must not prevent this elimination. */ 3247 3248 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3249 ep++) 3250 if (ep->to_rtx == SET_DEST (x) 3251 && SET_DEST (x) != hard_frame_pointer_rtx) 3252 { 3253 /* If it is being incremented, adjust the offset. Otherwise, 3254 this elimination can't be done. */ 3255 rtx src = SET_SRC (x); 3256 3257 if (GET_CODE (src) == PLUS 3258 && XEXP (src, 0) == SET_DEST (x) 3259 && GET_CODE (XEXP (src, 1)) == CONST_INT) 3260 ep->offset -= INTVAL (XEXP (src, 1)); 3261 else 3262 ep->can_eliminate = 0; 3263 } 3264 3265 /* Now check to see we are assigning to a register that can be 3266 eliminated. If so, it must be as part of a PARALLEL, since we 3267 will not have been called if this is a single SET. So indicate 3268 that we can no longer eliminate this reg. */ 3269 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3270 ep++) 3271 if (ep->from_rtx == SET_DEST (x) && ep->can_eliminate) 3272 ep->can_eliminate = 0; 3273 } 3274 3275 /* Now avoid the loop below in this common case. */ 3276 { 3277 rtx new0 = eliminate_regs (SET_DEST (x), 0, insn); 3278 rtx new1 = eliminate_regs (SET_SRC (x), 0, insn); 3279 3280 /* If SET_DEST changed from a REG to a MEM and INSN is an insn, 3281 write a CLOBBER insn. */ 3282 if (GET_CODE (SET_DEST (x)) == REG && GET_CODE (new0) == MEM 3283 && insn != 0 && GET_CODE (insn) != EXPR_LIST 3284 && GET_CODE (insn) != INSN_LIST) 3285 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, SET_DEST (x)), insn); 3286 3287 if (new0 != SET_DEST (x) || new1 != SET_SRC (x)) 3288 return gen_rtx_SET (VOIDmode, new0, new1); 3289 } 3290 3291 return x; 3292 3293 case MEM: 3294 /* This is only for the benefit of the debugging backends, which call 3295 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are 3296 removed after CSE. */ 3297 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) 3298 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); 3299 3300 /* Our only special processing is to pass the mode of the MEM to our 3301 recursive call and copy the flags. While we are here, handle this 3302 case more efficiently. */ 3303 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn); 3304 if (new != XEXP (x, 0)) 3305 { 3306 new = gen_rtx_MEM (GET_MODE (x), new); 3307 new->volatil = x->volatil; 3308 new->unchanging = x->unchanging; 3309 new->in_struct = x->in_struct; 3310 return new; 3311 } 3312 else 3313 return x; 3314 3315 default: 3316 break; 3317 } 3318 3319 /* Process each of our operands recursively. If any have changed, make a 3320 copy of the rtx. */ 3321 fmt = GET_RTX_FORMAT (code); 3322 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 3323 { 3324 if (*fmt == 'e') 3325 { 3326 new = eliminate_regs (XEXP (x, i), mem_mode, insn); 3327 if (new != XEXP (x, i) && ! copied) 3328 { 3329 rtx new_x = rtx_alloc (code); 3330 bcopy ((char *) x, (char *) new_x, 3331 (sizeof (*new_x) - sizeof (new_x->fld) 3332 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code))); 3333 x = new_x; 3334 copied = 1; 3335 } 3336 XEXP (x, i) = new; 3337 } 3338 else if (*fmt == 'E') 3339 { 3340 int copied_vec = 0; 3341 for (j = 0; j < XVECLEN (x, i); j++) 3342 { 3343 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); 3344 if (new != XVECEXP (x, i, j) && ! copied_vec) 3345 { 3346 rtvec new_v = gen_rtvec_vv (XVECLEN (x, i), 3347 XVEC (x, i)->elem); 3348 if (! copied) 3349 { 3350 rtx new_x = rtx_alloc (code); 3351 bcopy ((char *) x, (char *) new_x, 3352 (sizeof (*new_x) - sizeof (new_x->fld) 3353 + (sizeof (new_x->fld[0]) 3354 * GET_RTX_LENGTH (code)))); 3355 x = new_x; 3356 copied = 1; 3357 } 3358 XVEC (x, i) = new_v; 3359 copied_vec = 1; 3360 } 3361 XVECEXP (x, i, j) = new; 3362 } 3363 } 3364 } 3365 3366 return x; 3367} 3368 3369/* Scan INSN and eliminate all eliminable registers in it. 3370 3371 If REPLACE is nonzero, do the replacement destructively. Also 3372 delete the insn as dead it if it is setting an eliminable register. 3373 3374 If REPLACE is zero, do all our allocations in reload_obstack. 3375 3376 If no eliminations were done and this insn doesn't require any elimination 3377 processing (these are not identical conditions: it might be updating sp, 3378 but not referencing fp; this needs to be seen during reload_as_needed so 3379 that the offset between fp and sp can be taken into consideration), zero 3380 is returned. Otherwise, 1 is returned. */ 3381 3382static int 3383eliminate_regs_in_insn (insn, replace) 3384 rtx insn; 3385 int replace; 3386{ 3387 rtx old_body = PATTERN (insn); 3388 rtx old_set = single_set (insn); 3389 rtx new_body; 3390 int val = 0; 3391 struct elim_table *ep; 3392 3393 if (! replace) 3394 push_obstacks (&reload_obstack, &reload_obstack); 3395 3396 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG 3397 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) 3398 { 3399 /* Check for setting an eliminable register. */ 3400 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3401 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) 3402 { 3403#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 3404 /* If this is setting the frame pointer register to the 3405 hardware frame pointer register and this is an elimination 3406 that will be done (tested above), this insn is really 3407 adjusting the frame pointer downward to compensate for 3408 the adjustment done before a nonlocal goto. */ 3409 if (ep->from == FRAME_POINTER_REGNUM 3410 && ep->to == HARD_FRAME_POINTER_REGNUM) 3411 { 3412 rtx src = SET_SRC (old_set); 3413 int offset, ok = 0; 3414 rtx prev_insn, prev_set; 3415 3416 if (src == ep->to_rtx) 3417 offset = 0, ok = 1; 3418 else if (GET_CODE (src) == PLUS 3419 && GET_CODE (XEXP (src, 0)) == CONST_INT 3420 && XEXP (src, 1) == ep->to_rtx) 3421 offset = INTVAL (XEXP (src, 0)), ok = 1; 3422 else if (GET_CODE (src) == PLUS 3423 && GET_CODE (XEXP (src, 1)) == CONST_INT 3424 && XEXP (src, 0) == ep->to_rtx) 3425 offset = INTVAL (XEXP (src, 1)), ok = 1; 3426 else if ((prev_insn = prev_nonnote_insn (insn)) != 0 3427 && (prev_set = single_set (prev_insn)) != 0 3428 && rtx_equal_p (SET_DEST (prev_set), src)) 3429 { 3430 src = SET_SRC (prev_set); 3431 if (src == ep->to_rtx) 3432 offset = 0, ok = 1; 3433 else if (GET_CODE (src) == PLUS 3434 && GET_CODE (XEXP (src, 0)) == CONST_INT 3435 && XEXP (src, 1) == ep->to_rtx) 3436 offset = INTVAL (XEXP (src, 0)), ok = 1; 3437 else if (GET_CODE (src) == PLUS 3438 && GET_CODE (XEXP (src, 1)) == CONST_INT 3439 && XEXP (src, 0) == ep->to_rtx) 3440 offset = INTVAL (XEXP (src, 1)), ok = 1; 3441 } 3442 3443 if (ok) 3444 { 3445 if (replace) 3446 { 3447 rtx src 3448 = plus_constant (ep->to_rtx, offset - ep->offset); 3449 3450 /* First see if this insn remains valid when we 3451 make the change. If not, keep the INSN_CODE 3452 the same and let reload fit it up. */ 3453 validate_change (insn, &SET_SRC (old_set), src, 1); 3454 validate_change (insn, &SET_DEST (old_set), 3455 ep->to_rtx, 1); 3456 if (! apply_change_group ()) 3457 { 3458 SET_SRC (old_set) = src; 3459 SET_DEST (old_set) = ep->to_rtx; 3460 } 3461 } 3462 3463 val = 1; 3464 goto done; 3465 } 3466 } 3467#endif 3468 3469 /* In this case this insn isn't serving a useful purpose. We 3470 will delete it in reload_as_needed once we know that this 3471 elimination is, in fact, being done. 3472 3473 If REPLACE isn't set, we can't delete this insn, but needn't 3474 process it since it won't be used unless something changes. */ 3475 if (replace) 3476 delete_dead_insn (insn); 3477 val = 1; 3478 goto done; 3479 } 3480 3481 /* Check for (set (reg) (plus (reg from) (offset))) where the offset 3482 in the insn is the negative of the offset in FROM. Substitute 3483 (set (reg) (reg to)) for the insn and change its code. 3484 3485 We have to do this here, rather than in eliminate_regs, do that we can 3486 change the insn code. */ 3487 3488 if (GET_CODE (SET_SRC (old_set)) == PLUS 3489 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG 3490 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT) 3491 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3492 ep++) 3493 if (ep->from_rtx == XEXP (SET_SRC (old_set), 0) 3494 && ep->can_eliminate) 3495 { 3496 /* We must stop at the first elimination that will be used. 3497 If this one would replace the PLUS with a REG, do it 3498 now. Otherwise, quit the loop and let eliminate_regs 3499 do its normal replacement. */ 3500 if (ep->offset == - INTVAL (XEXP (SET_SRC (old_set), 1))) 3501 { 3502 /* We assume here that we don't need a PARALLEL of 3503 any CLOBBERs for this assignment. There's not 3504 much we can do if we do need it. */ 3505 PATTERN (insn) = gen_rtx_SET (VOIDmode, 3506 SET_DEST (old_set), 3507 ep->to_rtx); 3508 INSN_CODE (insn) = -1; 3509 val = 1; 3510 goto done; 3511 } 3512 3513 break; 3514 } 3515 } 3516 3517 old_asm_operands_vec = 0; 3518 3519 /* Replace the body of this insn with a substituted form. If we changed 3520 something, return non-zero. 3521 3522 If we are replacing a body that was a (set X (plus Y Z)), try to 3523 re-recognize the insn. We do this in case we had a simple addition 3524 but now can do this as a load-address. This saves an insn in this 3525 common case. */ 3526 3527 new_body = eliminate_regs (old_body, 0, replace ? insn : NULL_RTX); 3528 if (new_body != old_body) 3529 { 3530 /* If we aren't replacing things permanently and we changed something, 3531 make another copy to ensure that all the RTL is new. Otherwise 3532 things can go wrong if find_reload swaps commutative operands 3533 and one is inside RTL that has been copied while the other is not. */ 3534 3535 /* Don't copy an asm_operands because (1) there's no need and (2) 3536 copy_rtx can't do it properly when there are multiple outputs. */ 3537 if (! replace && asm_noperands (old_body) < 0) 3538 new_body = copy_rtx (new_body); 3539 3540 /* If we had a move insn but now we don't, rerecognize it. This will 3541 cause spurious re-recognition if the old move had a PARALLEL since 3542 the new one still will, but we can't call single_set without 3543 having put NEW_BODY into the insn and the re-recognition won't 3544 hurt in this rare case. */ 3545 if (old_set != 0 3546 && ((GET_CODE (SET_SRC (old_set)) == REG 3547 && (GET_CODE (new_body) != SET 3548 || GET_CODE (SET_SRC (new_body)) != REG)) 3549 /* If this was a load from or store to memory, compare 3550 the MEM in recog_operand to the one in the insn. If they 3551 are not equal, then rerecognize the insn. */ 3552 || (old_set != 0 3553 && ((GET_CODE (SET_SRC (old_set)) == MEM 3554 && SET_SRC (old_set) != recog_operand[1]) 3555 || (GET_CODE (SET_DEST (old_set)) == MEM 3556 && SET_DEST (old_set) != recog_operand[0]))) 3557 /* If this was an add insn before, rerecognize. */ 3558 || GET_CODE (SET_SRC (old_set)) == PLUS)) 3559 { 3560 if (! validate_change (insn, &PATTERN (insn), new_body, 0)) 3561 /* If recognition fails, store the new body anyway. 3562 It's normal to have recognition failures here 3563 due to bizarre memory addresses; reloading will fix them. */ 3564 PATTERN (insn) = new_body; 3565 } 3566 else 3567 PATTERN (insn) = new_body; 3568 3569 val = 1; 3570 } 3571 3572 /* Loop through all elimination pairs. See if any have changed and 3573 recalculate the number not at initial offset. 3574 3575 Compute the maximum offset (minimum offset if the stack does not 3576 grow downward) for each elimination pair. 3577 3578 We also detect a cases where register elimination cannot be done, 3579 namely, if a register would be both changed and referenced outside a MEM 3580 in the resulting insn since such an insn is often undefined and, even if 3581 not, we cannot know what meaning will be given to it. Note that it is 3582 valid to have a register used in an address in an insn that changes it 3583 (presumably with a pre- or post-increment or decrement). 3584 3585 If anything changes, return nonzero. */ 3586 3587 num_not_at_initial_offset = 0; 3588 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3589 { 3590 if (ep->previous_offset != ep->offset && ep->ref_outside_mem) 3591 ep->can_eliminate = 0; 3592 3593 ep->ref_outside_mem = 0; 3594 3595 if (ep->previous_offset != ep->offset) 3596 val = 1; 3597 3598 ep->previous_offset = ep->offset; 3599 if (ep->can_eliminate && ep->offset != ep->initial_offset) 3600 num_not_at_initial_offset++; 3601 3602#ifdef STACK_GROWS_DOWNWARD 3603 ep->max_offset = MAX (ep->max_offset, ep->offset); 3604#else 3605 ep->max_offset = MIN (ep->max_offset, ep->offset); 3606#endif 3607 } 3608 3609 done: 3610 /* If we changed something, perform elimination in REG_NOTES. This is 3611 needed even when REPLACE is zero because a REG_DEAD note might refer 3612 to a register that we eliminate and could cause a different number 3613 of spill registers to be needed in the final reload pass than in 3614 the pre-passes. */ 3615 if (val && REG_NOTES (insn) != 0) 3616 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); 3617 3618 if (! replace) 3619 pop_obstacks (); 3620 3621 return val; 3622} 3623 3624/* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register 3625 replacement we currently believe is valid, mark it as not eliminable if X 3626 modifies DEST in any way other than by adding a constant integer to it. 3627 3628 If DEST is the frame pointer, we do nothing because we assume that 3629 all assignments to the hard frame pointer are nonlocal gotos and are being 3630 done at a time when they are valid and do not disturb anything else. 3631 Some machines want to eliminate a fake argument pointer with either the 3632 frame or stack pointer. Assignments to the hard frame pointer must not 3633 prevent this elimination. 3634 3635 Called via note_stores from reload before starting its passes to scan 3636 the insns of the function. */ 3637 3638static void 3639mark_not_eliminable (dest, x) 3640 rtx dest; 3641 rtx x; 3642{ 3643 register int i; 3644 3645 /* A SUBREG of a hard register here is just changing its mode. We should 3646 not see a SUBREG of an eliminable hard register, but check just in 3647 case. */ 3648 if (GET_CODE (dest) == SUBREG) 3649 dest = SUBREG_REG (dest); 3650 3651 if (dest == hard_frame_pointer_rtx) 3652 return; 3653 3654 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 3655 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx 3656 && (GET_CODE (x) != SET 3657 || GET_CODE (SET_SRC (x)) != PLUS 3658 || XEXP (SET_SRC (x), 0) != dest 3659 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) 3660 { 3661 reg_eliminate[i].can_eliminate_previous 3662 = reg_eliminate[i].can_eliminate = 0; 3663 num_eliminable--; 3664 } 3665} 3666 3667/* Kick all pseudos out of hard register REGNO. 3668 If GLOBAL is nonzero, try to find someplace else to put them. 3669 If DUMPFILE is nonzero, log actions taken on that file. 3670 3671 If CANT_ELIMINATE is nonzero, it means that we are doing this spill 3672 because we found we can't eliminate some register. In the case, no pseudos 3673 are allowed to be in the register, even if they are only in a block that 3674 doesn't require spill registers, unlike the case when we are spilling this 3675 hard reg to produce another spill register. 3676 3677 Return nonzero if any pseudos needed to be kicked out. */ 3678 3679static int 3680spill_hard_reg (regno, global, dumpfile, cant_eliminate) 3681 register int regno; 3682 int global; 3683 FILE *dumpfile; 3684 int cant_eliminate; 3685{ 3686 enum reg_class class = REGNO_REG_CLASS (regno); 3687 int something_changed = 0; 3688 register int i; 3689 3690 SET_HARD_REG_BIT (forbidden_regs, regno); 3691 3692 if (cant_eliminate) 3693 regs_ever_live[regno] = 1; 3694 3695 /* Spill every pseudo reg that was allocated to this reg 3696 or to something that overlaps this reg. */ 3697 3698 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3699 if (reg_renumber[i] >= 0 3700 && reg_renumber[i] <= regno 3701 && (reg_renumber[i] 3702 + HARD_REGNO_NREGS (reg_renumber[i], 3703 PSEUDO_REGNO_MODE (i)) 3704 > regno)) 3705 { 3706 /* If this register belongs solely to a basic block which needed no 3707 spilling of any class that this register is contained in, 3708 leave it be, unless we are spilling this register because 3709 it was a hard register that can't be eliminated. */ 3710 3711 if (! cant_eliminate 3712 && basic_block_needs[0] 3713 && REG_BASIC_BLOCK (i) >= 0 3714 && basic_block_needs[(int) class][REG_BASIC_BLOCK (i)] == 0) 3715 { 3716 enum reg_class *p; 3717 3718 for (p = reg_class_superclasses[(int) class]; 3719 *p != LIM_REG_CLASSES; p++) 3720 if (basic_block_needs[(int) *p][REG_BASIC_BLOCK (i)] > 0) 3721 break; 3722 3723 if (*p == LIM_REG_CLASSES) 3724 continue; 3725 } 3726 3727 /* Mark it as no longer having a hard register home. */ 3728 reg_renumber[i] = -1; 3729 /* We will need to scan everything again. */ 3730 something_changed = 1; 3731 if (global) 3732 retry_global_alloc (i, forbidden_regs); 3733 3734 alter_reg (i, regno); 3735 if (dumpfile) 3736 { 3737 if (reg_renumber[i] == -1) 3738 fprintf (dumpfile, " Register %d now on stack.\n\n", i); 3739 else 3740 fprintf (dumpfile, " Register %d now in %d.\n\n", 3741 i, reg_renumber[i]); 3742 } 3743 } 3744 for (i = 0; i < scratch_list_length; i++) 3745 { 3746 if (scratch_list[i] 3747 && regno >= REGNO (scratch_list[i]) 3748 && regno < REGNO (scratch_list[i]) 3749 + HARD_REGNO_NREGS (REGNO (scratch_list[i]), 3750 GET_MODE (scratch_list[i]))) 3751 { 3752 if (! cant_eliminate && basic_block_needs[0] 3753 && ! basic_block_needs[(int) class][scratch_block[i]]) 3754 { 3755 enum reg_class *p; 3756 3757 for (p = reg_class_superclasses[(int) class]; 3758 *p != LIM_REG_CLASSES; p++) 3759 if (basic_block_needs[(int) *p][scratch_block[i]] > 0) 3760 break; 3761 3762 if (*p == LIM_REG_CLASSES) 3763 continue; 3764 } 3765 PUT_CODE (scratch_list[i], SCRATCH); 3766 scratch_list[i] = 0; 3767 something_changed = 1; 3768 continue; 3769 } 3770 } 3771 3772 return something_changed; 3773} 3774 3775/* Find all paradoxical subregs within X and update reg_max_ref_width. 3776 Also mark any hard registers used to store user variables as 3777 forbidden from being used for spill registers. */ 3778 3779static void 3780scan_paradoxical_subregs (x) 3781 register rtx x; 3782{ 3783 register int i; 3784 register char *fmt; 3785 register enum rtx_code code = GET_CODE (x); 3786 3787 switch (code) 3788 { 3789 case REG: 3790 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER 3791 && REG_USERVAR_P (x)) 3792 SET_HARD_REG_BIT (forbidden_regs, REGNO (x)); 3793 return; 3794 3795 case CONST_INT: 3796 case CONST: 3797 case SYMBOL_REF: 3798 case LABEL_REF: 3799 case CONST_DOUBLE: 3800 case CC0: 3801 case PC: 3802 case USE: 3803 case CLOBBER: 3804 return; 3805 3806 case SUBREG: 3807 if (GET_CODE (SUBREG_REG (x)) == REG 3808 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 3809 reg_max_ref_width[REGNO (SUBREG_REG (x))] 3810 = GET_MODE_SIZE (GET_MODE (x)); 3811 return; 3812 3813 default: 3814 break; 3815 } 3816 3817 fmt = GET_RTX_FORMAT (code); 3818 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3819 { 3820 if (fmt[i] == 'e') 3821 scan_paradoxical_subregs (XEXP (x, i)); 3822 else if (fmt[i] == 'E') 3823 { 3824 register int j; 3825 for (j = XVECLEN (x, i) - 1; j >=0; j--) 3826 scan_paradoxical_subregs (XVECEXP (x, i, j)); 3827 } 3828 } 3829} 3830 3831static int 3832hard_reg_use_compare (p1p, p2p) 3833 const GENERIC_PTR p1p; 3834 const GENERIC_PTR p2p; 3835{ 3836 struct hard_reg_n_uses *p1 = (struct hard_reg_n_uses *)p1p, 3837 *p2 = (struct hard_reg_n_uses *)p2p; 3838 int tem = p1->uses - p2->uses; 3839 if (tem != 0) return tem; 3840 /* If regs are equally good, sort by regno, 3841 so that the results of qsort leave nothing to chance. */ 3842 return p1->regno - p2->regno; 3843} 3844 3845/* Choose the order to consider regs for use as reload registers 3846 based on how much trouble would be caused by spilling one. 3847 Store them in order of decreasing preference in potential_reload_regs. */ 3848 3849static void 3850order_regs_for_reload (global) 3851 int global; 3852{ 3853 register int i; 3854 register int o = 0; 3855 int large = 0; 3856 3857 struct hard_reg_n_uses hard_reg_n_uses[FIRST_PSEUDO_REGISTER]; 3858 3859 CLEAR_HARD_REG_SET (bad_spill_regs); 3860 3861 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3862 potential_reload_regs[i] = -1; 3863 3864 /* Count number of uses of each hard reg by pseudo regs allocated to it 3865 and then order them by decreasing use. */ 3866 3867 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3868 { 3869 hard_reg_n_uses[i].uses = 0; 3870 hard_reg_n_uses[i].regno = i; 3871 } 3872 3873 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3874 { 3875 int regno = reg_renumber[i]; 3876 if (regno >= 0) 3877 { 3878 int lim = regno + HARD_REGNO_NREGS (regno, PSEUDO_REGNO_MODE (i)); 3879 while (regno < lim) 3880 { 3881 /* If allocated by local-alloc, show more uses since 3882 we're not going to be able to reallocate it, but 3883 we might if allocated by global alloc. */ 3884 if (global && reg_allocno[i] < 0) 3885 hard_reg_n_uses[regno].uses += (REG_N_REFS (i) + 1) / 2; 3886 3887 hard_reg_n_uses[regno++].uses += REG_N_REFS (i); 3888 } 3889 } 3890 large += REG_N_REFS (i); 3891 } 3892 3893 /* Now fixed registers (which cannot safely be used for reloading) 3894 get a very high use count so they will be considered least desirable. 3895 Registers used explicitly in the rtl code are almost as bad. */ 3896 3897 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3898 { 3899 if (fixed_regs[i]) 3900 { 3901 hard_reg_n_uses[i].uses += 2 * large + 2; 3902 SET_HARD_REG_BIT (bad_spill_regs, i); 3903 } 3904 else if (regs_explicitly_used[i]) 3905 { 3906 hard_reg_n_uses[i].uses += large + 1; 3907 if (! SMALL_REGISTER_CLASSES) 3908 /* ??? We are doing this here because of the potential 3909 that bad code may be generated if a register explicitly 3910 used in an insn was used as a spill register for that 3911 insn. But not using these are spill registers may lose 3912 on some machine. We'll have to see how this works out. */ 3913 SET_HARD_REG_BIT (bad_spill_regs, i); 3914 } 3915 } 3916 hard_reg_n_uses[HARD_FRAME_POINTER_REGNUM].uses += 2 * large + 2; 3917 SET_HARD_REG_BIT (bad_spill_regs, HARD_FRAME_POINTER_REGNUM); 3918 3919#ifdef ELIMINABLE_REGS 3920 /* If registers other than the frame pointer are eliminable, mark them as 3921 poor choices. */ 3922 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 3923 { 3924 hard_reg_n_uses[reg_eliminate[i].from].uses += 2 * large + 2; 3925 SET_HARD_REG_BIT (bad_spill_regs, reg_eliminate[i].from); 3926 } 3927#endif 3928 3929 /* Prefer registers not so far used, for use in temporary loading. 3930 Among them, if REG_ALLOC_ORDER is defined, use that order. 3931 Otherwise, prefer registers not preserved by calls. */ 3932 3933#ifdef REG_ALLOC_ORDER 3934 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3935 { 3936 int regno = reg_alloc_order[i]; 3937 3938 if (hard_reg_n_uses[regno].uses == 0) 3939 potential_reload_regs[o++] = regno; 3940 } 3941#else 3942 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3943 { 3944 if (hard_reg_n_uses[i].uses == 0 && call_used_regs[i]) 3945 potential_reload_regs[o++] = i; 3946 } 3947 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3948 { 3949 if (hard_reg_n_uses[i].uses == 0 && ! call_used_regs[i]) 3950 potential_reload_regs[o++] = i; 3951 } 3952#endif 3953 3954 qsort (hard_reg_n_uses, FIRST_PSEUDO_REGISTER, 3955 sizeof hard_reg_n_uses[0], hard_reg_use_compare); 3956 3957 /* Now add the regs that are already used, 3958 preferring those used less often. The fixed and otherwise forbidden 3959 registers will be at the end of this list. */ 3960 3961 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3962 if (hard_reg_n_uses[i].uses != 0) 3963 potential_reload_regs[o++] = hard_reg_n_uses[i].regno; 3964} 3965 3966/* Used in reload_as_needed to sort the spilled regs. */ 3967 3968static int 3969compare_spill_regs (r1p, r2p) 3970 const GENERIC_PTR r1p; 3971 const GENERIC_PTR r2p; 3972{ 3973 short r1 = *(short *)r1p, r2 = *(short *)r2p; 3974 return r1 - r2; 3975} 3976 3977/* Reload pseudo-registers into hard regs around each insn as needed. 3978 Additional register load insns are output before the insn that needs it 3979 and perhaps store insns after insns that modify the reloaded pseudo reg. 3980 3981 reg_last_reload_reg and reg_reloaded_contents keep track of 3982 which registers are already available in reload registers. 3983 We update these for the reloads that we perform, 3984 as the insns are scanned. */ 3985 3986static void 3987reload_as_needed (first, live_known) 3988 rtx first; 3989 int live_known; 3990{ 3991 register rtx insn; 3992 register int i; 3993 int this_block = 0; 3994 rtx x; 3995 rtx after_call = 0; 3996 3997 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx); 3998 bzero ((char *) spill_reg_store, sizeof spill_reg_store); 3999 reg_last_reload_reg = (rtx *) alloca (max_regno * sizeof (rtx)); 4000 bzero ((char *) reg_last_reload_reg, max_regno * sizeof (rtx)); 4001 reg_has_output_reload = (char *) alloca (max_regno); 4002 CLEAR_HARD_REG_SET (reg_reloaded_valid); 4003 4004 /* Reset all offsets on eliminable registers to their initial values. */ 4005#ifdef ELIMINABLE_REGS 4006 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 4007 { 4008 INITIAL_ELIMINATION_OFFSET (reg_eliminate[i].from, reg_eliminate[i].to, 4009 reg_eliminate[i].initial_offset); 4010 reg_eliminate[i].previous_offset 4011 = reg_eliminate[i].offset = reg_eliminate[i].initial_offset; 4012 } 4013#else 4014 INITIAL_FRAME_POINTER_OFFSET (reg_eliminate[0].initial_offset); 4015 reg_eliminate[0].previous_offset 4016 = reg_eliminate[0].offset = reg_eliminate[0].initial_offset; 4017#endif 4018 4019 num_not_at_initial_offset = 0; 4020 4021 /* Order the spilled regs, so that allocate_reload_regs can guarantee to 4022 pack registers with group needs. */ 4023 if (n_spills > 1) 4024 { 4025 qsort (spill_regs, n_spills, sizeof (short), compare_spill_regs); 4026 for (i = 0; i < n_spills; i++) 4027 spill_reg_order[spill_regs[i]] = i; 4028 } 4029 4030 for (insn = first; insn;) 4031 { 4032 register rtx next = NEXT_INSN (insn); 4033 4034 /* Notice when we move to a new basic block. */ 4035 if (live_known && this_block + 1 < n_basic_blocks 4036 && insn == basic_block_head[this_block+1]) 4037 ++this_block; 4038 4039 /* If we pass a label, copy the offsets from the label information 4040 into the current offsets of each elimination. */ 4041 if (GET_CODE (insn) == CODE_LABEL) 4042 { 4043 num_not_at_initial_offset = 0; 4044 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 4045 { 4046 reg_eliminate[i].offset = reg_eliminate[i].previous_offset 4047 = offsets_at[CODE_LABEL_NUMBER (insn)][i]; 4048 if (reg_eliminate[i].can_eliminate 4049 && (reg_eliminate[i].offset 4050 != reg_eliminate[i].initial_offset)) 4051 num_not_at_initial_offset++; 4052 } 4053 } 4054 4055 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i') 4056 { 4057 rtx avoid_return_reg = 0; 4058 rtx oldpat = PATTERN (insn); 4059 4060 /* Set avoid_return_reg if this is an insn 4061 that might use the value of a function call. */ 4062 if (SMALL_REGISTER_CLASSES && GET_CODE (insn) == CALL_INSN) 4063 { 4064 if (GET_CODE (PATTERN (insn)) == SET) 4065 after_call = SET_DEST (PATTERN (insn)); 4066 else if (GET_CODE (PATTERN (insn)) == PARALLEL 4067 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET) 4068 after_call = SET_DEST (XVECEXP (PATTERN (insn), 0, 0)); 4069 else 4070 after_call = 0; 4071 } 4072 else if (SMALL_REGISTER_CLASSES && after_call != 0 4073 && !(GET_CODE (PATTERN (insn)) == SET 4074 && SET_DEST (PATTERN (insn)) == stack_pointer_rtx) 4075 && GET_CODE (PATTERN (insn)) != USE) 4076 { 4077 if (reg_referenced_p (after_call, PATTERN (insn))) 4078 avoid_return_reg = after_call; 4079 after_call = 0; 4080 } 4081 4082 /* If this is a USE and CLOBBER of a MEM, ensure that any 4083 references to eliminable registers have been removed. */ 4084 4085 if ((GET_CODE (PATTERN (insn)) == USE 4086 || GET_CODE (PATTERN (insn)) == CLOBBER) 4087 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) 4088 XEXP (XEXP (PATTERN (insn), 0), 0) 4089 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), 4090 GET_MODE (XEXP (PATTERN (insn), 0)), 4091 NULL_RTX); 4092 4093 /* If we need to do register elimination processing, do so. 4094 This might delete the insn, in which case we are done. */ 4095 if (num_eliminable && GET_MODE (insn) == QImode) 4096 { 4097 eliminate_regs_in_insn (insn, 1); 4098 if (GET_CODE (insn) == NOTE) 4099 { 4100 insn = next; 4101 continue; 4102 } 4103 } 4104 4105 if (GET_MODE (insn) == VOIDmode) 4106 n_reloads = 0; 4107 /* First find the pseudo regs that must be reloaded for this insn. 4108 This info is returned in the tables reload_... (see reload.h). 4109 Also modify the body of INSN by substituting RELOAD 4110 rtx's for those pseudo regs. */ 4111 else 4112 { 4113 bzero (reg_has_output_reload, max_regno); 4114 CLEAR_HARD_REG_SET (reg_is_output_reload); 4115 4116 find_reloads (insn, 1, spill_indirect_levels, live_known, 4117 spill_reg_order); 4118 } 4119 4120 if (n_reloads > 0) 4121 { 4122 rtx prev = PREV_INSN (insn), next = NEXT_INSN (insn); 4123 rtx p; 4124 int class; 4125 4126 /* If this block has not had spilling done for a 4127 particular clas and we have any non-optionals that need a 4128 spill reg in that class, abort. */ 4129 4130 for (class = 0; class < N_REG_CLASSES; class++) 4131 if (basic_block_needs[class] != 0 4132 && basic_block_needs[class][this_block] == 0) 4133 for (i = 0; i < n_reloads; i++) 4134 if (class == (int) reload_reg_class[i] 4135 && reload_reg_rtx[i] == 0 4136 && ! reload_optional[i] 4137 && (reload_in[i] != 0 || reload_out[i] != 0 4138 || reload_secondary_p[i] != 0)) 4139 fatal_insn ("Non-optional registers need a spill register", insn); 4140 4141 /* Now compute which reload regs to reload them into. Perhaps 4142 reusing reload regs from previous insns, or else output 4143 load insns to reload them. Maybe output store insns too. 4144 Record the choices of reload reg in reload_reg_rtx. */ 4145 choose_reload_regs (insn, avoid_return_reg); 4146 4147 /* Merge any reloads that we didn't combine for fear of 4148 increasing the number of spill registers needed but now 4149 discover can be safely merged. */ 4150 if (SMALL_REGISTER_CLASSES) 4151 merge_assigned_reloads (insn); 4152 4153 /* Generate the insns to reload operands into or out of 4154 their reload regs. */ 4155 emit_reload_insns (insn); 4156 4157 /* Substitute the chosen reload regs from reload_reg_rtx 4158 into the insn's body (or perhaps into the bodies of other 4159 load and store insn that we just made for reloading 4160 and that we moved the structure into). */ 4161 subst_reloads (); 4162 4163 /* If this was an ASM, make sure that all the reload insns 4164 we have generated are valid. If not, give an error 4165 and delete them. */ 4166 4167 if (asm_noperands (PATTERN (insn)) >= 0) 4168 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) 4169 if (p != insn && GET_RTX_CLASS (GET_CODE (p)) == 'i' 4170 && (recog_memoized (p) < 0 4171 || (insn_extract (p), 4172 ! constrain_operands (INSN_CODE (p), 1)))) 4173 { 4174 error_for_asm (insn, 4175 "`asm' operand requires impossible reload"); 4176 PUT_CODE (p, NOTE); 4177 NOTE_SOURCE_FILE (p) = 0; 4178 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED; 4179 } 4180 } 4181 /* Any previously reloaded spilled pseudo reg, stored in this insn, 4182 is no longer validly lying around to save a future reload. 4183 Note that this does not detect pseudos that were reloaded 4184 for this insn in order to be stored in 4185 (obeying register constraints). That is correct; such reload 4186 registers ARE still valid. */ 4187 note_stores (oldpat, forget_old_reloads_1); 4188 4189 /* There may have been CLOBBER insns placed after INSN. So scan 4190 between INSN and NEXT and use them to forget old reloads. */ 4191 for (x = NEXT_INSN (insn); x != next; x = NEXT_INSN (x)) 4192 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) 4193 note_stores (PATTERN (x), forget_old_reloads_1); 4194 4195#ifdef AUTO_INC_DEC 4196 /* Likewise for regs altered by auto-increment in this insn. 4197 But note that the reg-notes are not changed by reloading: 4198 they still contain the pseudo-regs, not the spill regs. */ 4199 for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) 4200 if (REG_NOTE_KIND (x) == REG_INC) 4201 { 4202 /* See if this pseudo reg was reloaded in this insn. 4203 If so, its last-reload info is still valid 4204 because it is based on this insn's reload. */ 4205 for (i = 0; i < n_reloads; i++) 4206 if (reload_out[i] == XEXP (x, 0)) 4207 break; 4208 4209 if (i == n_reloads) 4210 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX); 4211 } 4212#endif 4213 } 4214 /* A reload reg's contents are unknown after a label. */ 4215 if (GET_CODE (insn) == CODE_LABEL) 4216 CLEAR_HARD_REG_SET (reg_reloaded_valid); 4217 4218 /* Don't assume a reload reg is still good after a call insn 4219 if it is a call-used reg. */ 4220 else if (GET_CODE (insn) == CALL_INSN) 4221 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set); 4222 4223 /* In case registers overlap, allow certain insns to invalidate 4224 particular hard registers. */ 4225 4226#ifdef INSN_CLOBBERS_REGNO_P 4227 for (i = 0 ; i < FIRST_PSEUDO_REGISTER; i++) 4228 if (TEST_HARD_REG_BIT (reg_reloaded_valid, i) 4229 && INSN_CLOBBERS_REGNO_P (insn, i)) 4230 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i); 4231#endif 4232 4233 insn = next; 4234 4235#ifdef USE_C_ALLOCA 4236 alloca (0); 4237#endif 4238 } 4239} 4240 4241/* Discard all record of any value reloaded from X, 4242 or reloaded in X from someplace else; 4243 unless X is an output reload reg of the current insn. 4244 4245 X may be a hard reg (the reload reg) 4246 or it may be a pseudo reg that was reloaded from. */ 4247 4248static void 4249forget_old_reloads_1 (x, ignored) 4250 rtx x; 4251 rtx ignored ATTRIBUTE_UNUSED; 4252{ 4253 register int regno; 4254 enum machine_mode mode = GET_MODE (x); 4255 int nr; 4256 4257 /* note_stores does give us subregs of hard regs. 4258 4259 This is a egcs-1.1 tree hack only. A better solution is being 4260 developed for mainline sources. Do not import this back to the 4261 mainline tree. 4262 4263 We want to strip all the SUBREGs, but also keep track of the 4264 largest mode we encounter so that we can invalidate all the 4265 hard regs which are needed to hold the widest mode. 4266 4267 This avoids a bug in choose_reload_regs (which is where the real 4268 fix for the mainline tree will be). */ 4269 4270 while (GET_CODE (x) == SUBREG) 4271 { 4272 if (GET_MODE_BITSIZE (GET_MODE (x)) > GET_MODE_BITSIZE (mode)) 4273 mode = GET_MODE (x); 4274 x = SUBREG_REG (x); 4275 } 4276 4277 if (GET_MODE_BITSIZE (GET_MODE (x)) > GET_MODE_BITSIZE (mode)) 4278 mode = GET_MODE (x); 4279 4280 if (GET_CODE (x) != REG) 4281 return; 4282 4283 regno = REGNO (x); 4284 4285 if (regno >= FIRST_PSEUDO_REGISTER) 4286 nr = 1; 4287 else 4288 { 4289 int i; 4290 nr = HARD_REGNO_NREGS (regno, mode); 4291 /* Storing into a spilled-reg invalidates its contents. 4292 This can happen if a block-local pseudo is allocated to that reg 4293 and it wasn't spilled because this block's total need is 0. 4294 Then some insn might have an optional reload and use this reg. */ 4295 for (i = 0; i < nr; i++) 4296 /* But don't do this if the reg actually serves as an output 4297 reload reg in the current instruction. */ 4298 if (n_reloads == 0 4299 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) 4300 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); 4301 } 4302 4303 /* Since value of X has changed, 4304 forget any value previously copied from it. */ 4305 4306 while (nr-- > 0) 4307 /* But don't forget a copy if this is the output reload 4308 that establishes the copy's validity. */ 4309 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) 4310 reg_last_reload_reg[regno + nr] = 0; 4311} 4312 4313/* For each reload, the mode of the reload register. */ 4314static enum machine_mode reload_mode[MAX_RELOADS]; 4315 4316/* For each reload, the largest number of registers it will require. */ 4317static int reload_nregs[MAX_RELOADS]; 4318 4319/* Comparison function for qsort to decide which of two reloads 4320 should be handled first. *P1 and *P2 are the reload numbers. */ 4321 4322static int 4323reload_reg_class_lower (r1p, r2p) 4324 const GENERIC_PTR r1p; 4325 const GENERIC_PTR r2p; 4326{ 4327 register int r1 = *(short *)r1p, r2 = *(short *)r2p; 4328 register int t; 4329 4330 /* Consider required reloads before optional ones. */ 4331 t = reload_optional[r1] - reload_optional[r2]; 4332 if (t != 0) 4333 return t; 4334 4335 /* Count all solitary classes before non-solitary ones. */ 4336 t = ((reg_class_size[(int) reload_reg_class[r2]] == 1) 4337 - (reg_class_size[(int) reload_reg_class[r1]] == 1)); 4338 if (t != 0) 4339 return t; 4340 4341 /* Aside from solitaires, consider all multi-reg groups first. */ 4342 t = reload_nregs[r2] - reload_nregs[r1]; 4343 if (t != 0) 4344 return t; 4345 4346 /* Consider reloads in order of increasing reg-class number. */ 4347 t = (int) reload_reg_class[r1] - (int) reload_reg_class[r2]; 4348 if (t != 0) 4349 return t; 4350 4351 /* If reloads are equally urgent, sort by reload number, 4352 so that the results of qsort leave nothing to chance. */ 4353 return r1 - r2; 4354} 4355 4356/* The following HARD_REG_SETs indicate when each hard register is 4357 used for a reload of various parts of the current insn. */ 4358 4359/* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ 4360static HARD_REG_SET reload_reg_used; 4361/* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ 4362static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; 4363/* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ 4364static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; 4365/* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ 4366static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; 4367/* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ 4368static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; 4369/* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ 4370static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; 4371/* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ 4372static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; 4373/* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ 4374static HARD_REG_SET reload_reg_used_in_op_addr; 4375/* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ 4376static HARD_REG_SET reload_reg_used_in_op_addr_reload; 4377/* If reg is in use for a RELOAD_FOR_INSN reload. */ 4378static HARD_REG_SET reload_reg_used_in_insn; 4379/* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ 4380static HARD_REG_SET reload_reg_used_in_other_addr; 4381 4382/* If reg is in use as a reload reg for any sort of reload. */ 4383static HARD_REG_SET reload_reg_used_at_all; 4384 4385/* If reg is use as an inherited reload. We just mark the first register 4386 in the group. */ 4387static HARD_REG_SET reload_reg_used_for_inherit; 4388 4389/* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and 4390 TYPE. MODE is used to indicate how many consecutive regs are 4391 actually used. */ 4392 4393static void 4394mark_reload_reg_in_use (regno, opnum, type, mode) 4395 int regno; 4396 int opnum; 4397 enum reload_type type; 4398 enum machine_mode mode; 4399{ 4400 int nregs = HARD_REGNO_NREGS (regno, mode); 4401 int i; 4402 4403 for (i = regno; i < nregs + regno; i++) 4404 { 4405 switch (type) 4406 { 4407 case RELOAD_OTHER: 4408 SET_HARD_REG_BIT (reload_reg_used, i); 4409 break; 4410 4411 case RELOAD_FOR_INPUT_ADDRESS: 4412 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); 4413 break; 4414 4415 case RELOAD_FOR_INPADDR_ADDRESS: 4416 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); 4417 break; 4418 4419 case RELOAD_FOR_OUTPUT_ADDRESS: 4420 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); 4421 break; 4422 4423 case RELOAD_FOR_OUTADDR_ADDRESS: 4424 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); 4425 break; 4426 4427 case RELOAD_FOR_OPERAND_ADDRESS: 4428 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); 4429 break; 4430 4431 case RELOAD_FOR_OPADDR_ADDR: 4432 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); 4433 break; 4434 4435 case RELOAD_FOR_OTHER_ADDRESS: 4436 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); 4437 break; 4438 4439 case RELOAD_FOR_INPUT: 4440 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); 4441 break; 4442 4443 case RELOAD_FOR_OUTPUT: 4444 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); 4445 break; 4446 4447 case RELOAD_FOR_INSN: 4448 SET_HARD_REG_BIT (reload_reg_used_in_insn, i); 4449 break; 4450 } 4451 4452 SET_HARD_REG_BIT (reload_reg_used_at_all, i); 4453 } 4454} 4455 4456/* Similarly, but show REGNO is no longer in use for a reload. */ 4457 4458static void 4459clear_reload_reg_in_use (regno, opnum, type, mode) 4460 int regno; 4461 int opnum; 4462 enum reload_type type; 4463 enum machine_mode mode; 4464{ 4465 int nregs = HARD_REGNO_NREGS (regno, mode); 4466 int i; 4467 4468 for (i = regno; i < nregs + regno; i++) 4469 { 4470 switch (type) 4471 { 4472 case RELOAD_OTHER: 4473 CLEAR_HARD_REG_BIT (reload_reg_used, i); 4474 break; 4475 4476 case RELOAD_FOR_INPUT_ADDRESS: 4477 CLEAR_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); 4478 break; 4479 4480 case RELOAD_FOR_INPADDR_ADDRESS: 4481 CLEAR_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); 4482 break; 4483 4484 case RELOAD_FOR_OUTPUT_ADDRESS: 4485 CLEAR_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); 4486 break; 4487 4488 case RELOAD_FOR_OUTADDR_ADDRESS: 4489 CLEAR_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); 4490 break; 4491 4492 case RELOAD_FOR_OPERAND_ADDRESS: 4493 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr, i); 4494 break; 4495 4496 case RELOAD_FOR_OPADDR_ADDR: 4497 CLEAR_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); 4498 break; 4499 4500 case RELOAD_FOR_OTHER_ADDRESS: 4501 CLEAR_HARD_REG_BIT (reload_reg_used_in_other_addr, i); 4502 break; 4503 4504 case RELOAD_FOR_INPUT: 4505 CLEAR_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); 4506 break; 4507 4508 case RELOAD_FOR_OUTPUT: 4509 CLEAR_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); 4510 break; 4511 4512 case RELOAD_FOR_INSN: 4513 CLEAR_HARD_REG_BIT (reload_reg_used_in_insn, i); 4514 break; 4515 } 4516 } 4517} 4518 4519/* 1 if reg REGNO is free as a reload reg for a reload of the sort 4520 specified by OPNUM and TYPE. */ 4521 4522static int 4523reload_reg_free_p (regno, opnum, type) 4524 int regno; 4525 int opnum; 4526 enum reload_type type; 4527{ 4528 int i; 4529 4530 /* In use for a RELOAD_OTHER means it's not available for anything. */ 4531 if (TEST_HARD_REG_BIT (reload_reg_used, regno)) 4532 return 0; 4533 4534 switch (type) 4535 { 4536 case RELOAD_OTHER: 4537 /* In use for anything means we can't use it for RELOAD_OTHER. */ 4538 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) 4539 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4540 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 4541 return 0; 4542 4543 for (i = 0; i < reload_n_operands; i++) 4544 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4545 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4546 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4547 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4548 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) 4549 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4550 return 0; 4551 4552 return 1; 4553 4554 case RELOAD_FOR_INPUT: 4555 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4556 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) 4557 return 0; 4558 4559 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 4560 return 0; 4561 4562 /* If it is used for some other input, can't use it. */ 4563 for (i = 0; i < reload_n_operands; i++) 4564 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4565 return 0; 4566 4567 /* If it is used in a later operand's address, can't use it. */ 4568 for (i = opnum + 1; i < reload_n_operands; i++) 4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4570 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 4571 return 0; 4572 4573 return 1; 4574 4575 case RELOAD_FOR_INPUT_ADDRESS: 4576 /* Can't use a register if it is used for an input address for this 4577 operand or used as an input in an earlier one. */ 4578 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) 4579 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 4580 return 0; 4581 4582 for (i = 0; i < opnum; i++) 4583 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4584 return 0; 4585 4586 return 1; 4587 4588 case RELOAD_FOR_INPADDR_ADDRESS: 4589 /* Can't use a register if it is used for an input address 4590 for this operand or used as an input in an earlier 4591 one. */ 4592 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 4593 return 0; 4594 4595 for (i = 0; i < opnum; i++) 4596 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4597 return 0; 4598 4599 return 1; 4600 4601 case RELOAD_FOR_OUTPUT_ADDRESS: 4602 /* Can't use a register if it is used for an output address for this 4603 operand or used as an output in this or a later operand. */ 4604 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) 4605 return 0; 4606 4607 for (i = opnum; i < reload_n_operands; i++) 4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4609 return 0; 4610 4611 return 1; 4612 4613 case RELOAD_FOR_OUTADDR_ADDRESS: 4614 /* Can't use a register if it is used for an output address 4615 for this operand or used as an output in this or a 4616 later operand. */ 4617 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) 4618 return 0; 4619 4620 for (i = opnum; i < reload_n_operands; i++) 4621 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4622 return 0; 4623 4624 return 1; 4625 4626 case RELOAD_FOR_OPERAND_ADDRESS: 4627 for (i = 0; i < reload_n_operands; i++) 4628 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4629 return 0; 4630 4631 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4632 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 4633 4634 case RELOAD_FOR_OPADDR_ADDR: 4635 for (i = 0; i < reload_n_operands; i++) 4636 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4637 return 0; 4638 4639 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); 4640 4641 case RELOAD_FOR_OUTPUT: 4642 /* This cannot share a register with RELOAD_FOR_INSN reloads, other 4643 outputs, or an operand address for this or an earlier output. */ 4644 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 4645 return 0; 4646 4647 for (i = 0; i < reload_n_operands; i++) 4648 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4649 return 0; 4650 4651 for (i = 0; i <= opnum; i++) 4652 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4653 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) 4654 return 0; 4655 4656 return 1; 4657 4658 case RELOAD_FOR_INSN: 4659 for (i = 0; i < reload_n_operands; i++) 4660 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) 4661 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4662 return 0; 4663 4664 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4665 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 4666 4667 case RELOAD_FOR_OTHER_ADDRESS: 4668 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); 4669 } 4670 abort (); 4671} 4672 4673/* Return 1 if the value in reload reg REGNO, as used by a reload 4674 needed for the part of the insn specified by OPNUM and TYPE, 4675 is not in use for a reload in any prior part of the insn. 4676 4677 We can assume that the reload reg was already tested for availability 4678 at the time it is needed, and we should not check this again, 4679 in case the reg has already been marked in use. */ 4680 4681static int 4682reload_reg_free_before_p (regno, opnum, type) 4683 int regno; 4684 int opnum; 4685 enum reload_type type; 4686{ 4687 int i; 4688 4689 switch (type) 4690 { 4691 case RELOAD_FOR_OTHER_ADDRESS: 4692 /* These always come first. */ 4693 return 1; 4694 4695 case RELOAD_OTHER: 4696 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); 4697 4698 /* If this use is for part of the insn, 4699 check the reg is not in use for any prior part. It is tempting 4700 to try to do this by falling through from objecs that occur 4701 later in the insn to ones that occur earlier, but that will not 4702 correctly take into account the fact that here we MUST ignore 4703 things that would prevent the register from being allocated in 4704 the first place, since we know that it was allocated. */ 4705 4706 case RELOAD_FOR_OUTPUT_ADDRESS: 4707 /* Earlier reloads include RELOAD_FOR_OUTADDR_ADDRESS reloads. */ 4708 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) 4709 return 0; 4710 /* ... fall through ... */ 4711 case RELOAD_FOR_OUTADDR_ADDRESS: 4712 /* Earlier reloads are for earlier outputs or their addresses, 4713 any RELOAD_FOR_INSN reloads, any inputs or their addresses, or any 4714 RELOAD_FOR_OTHER_ADDRESS reloads (we know it can't conflict with 4715 RELOAD_OTHER).. */ 4716 for (i = 0; i < opnum; i++) 4717 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4718 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4719 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4720 return 0; 4721 4722 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 4723 return 0; 4724 4725 for (i = 0; i < reload_n_operands; i++) 4726 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4727 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4728 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4729 return 0; 4730 4731 return (! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) 4732 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4733 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) 4734 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 4735 4736 case RELOAD_FOR_OUTPUT: 4737 /* There is no reason to call this function for output reloads, thus 4738 anything we'd put here wouldn't be tested. So just abort. */ 4739 abort (); 4740 4741 case RELOAD_FOR_OPERAND_ADDRESS: 4742 /* Earlier reloads include RELOAD_FOR_OPADDR_ADDR reloads. */ 4743 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 4744 return 0; 4745 4746 /* ... fall through ... */ 4747 4748 case RELOAD_FOR_OPADDR_ADDR: 4749 case RELOAD_FOR_INSN: 4750 /* These can't conflict with inputs, or each other, so all we have to 4751 test is input addresses and the addresses of OTHER items. */ 4752 4753 for (i = 0; i < reload_n_operands; i++) 4754 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4755 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 4756 return 0; 4757 4758 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); 4759 4760 case RELOAD_FOR_INPUT: 4761 /* The only things earlier are the address for this and 4762 earlier inputs, other inputs (which we know we don't conflict 4763 with), and addresses of RELOAD_OTHER objects. */ 4764 4765 for (i = 0; i <= opnum; i++) 4766 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4767 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 4768 return 0; 4769 4770 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); 4771 4772 case RELOAD_FOR_INPUT_ADDRESS: 4773 /* Earlier reloads include RELOAD_FOR_INPADDR_ADDRESS reloads. */ 4774 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 4775 return 0; 4776 /* ... fall through ... */ 4777 case RELOAD_FOR_INPADDR_ADDRESS: 4778 /* Similarly, all we have to check is for use in earlier inputs' 4779 addresses. */ 4780 for (i = 0; i < opnum; i++) 4781 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4782 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 4783 return 0; 4784 4785 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); 4786 } 4787 abort (); 4788} 4789 4790/* Return 1 if the value in reload reg REGNO, as used by a reload 4791 needed for the part of the insn specified by OPNUM and TYPE, 4792 is still available in REGNO at the end of the insn. 4793 4794 We can assume that the reload reg was already tested for availability 4795 at the time it is needed, and we should not check this again, 4796 in case the reg has already been marked in use. */ 4797 4798static int 4799reload_reg_reaches_end_p (regno, opnum, type) 4800 int regno; 4801 int opnum; 4802 enum reload_type type; 4803{ 4804 int i; 4805 4806 switch (type) 4807 { 4808 case RELOAD_OTHER: 4809 /* Since a RELOAD_OTHER reload claims the reg for the entire insn, 4810 its value must reach the end. */ 4811 return 1; 4812 4813 /* If this use is for part of the insn, 4814 its value reaches if no subsequent part uses the same register. 4815 Just like the above function, don't try to do this with lots 4816 of fallthroughs. */ 4817 4818 case RELOAD_FOR_OTHER_ADDRESS: 4819 /* Here we check for everything else, since these don't conflict 4820 with anything else and everything comes later. */ 4821 4822 for (i = 0; i < reload_n_operands; i++) 4823 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4824 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4825 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) 4826 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4827 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4828 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4829 return 0; 4830 4831 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4832 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4833 && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); 4834 4835 case RELOAD_FOR_INPUT_ADDRESS: 4836 case RELOAD_FOR_INPADDR_ADDRESS: 4837 /* Similar, except that we check only for this and subsequent inputs 4838 and the address of only subsequent inputs and we do not need 4839 to check for RELOAD_OTHER objects since they are known not to 4840 conflict. */ 4841 4842 for (i = opnum; i < reload_n_operands; i++) 4843 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4844 return 0; 4845 4846 for (i = opnum + 1; i < reload_n_operands; i++) 4847 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4848 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 4849 return 0; 4850 4851 for (i = 0; i < reload_n_operands; i++) 4852 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4853 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4854 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4855 return 0; 4856 4857 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 4858 return 0; 4859 4860 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4861 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)); 4862 4863 case RELOAD_FOR_INPUT: 4864 /* Similar to input address, except we start at the next operand for 4865 both input and input address and we do not check for 4866 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these 4867 would conflict. */ 4868 4869 for (i = opnum + 1; i < reload_n_operands; i++) 4870 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4871 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4872 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4873 return 0; 4874 4875 /* ... fall through ... */ 4876 4877 case RELOAD_FOR_OPERAND_ADDRESS: 4878 /* Check outputs and their addresses. */ 4879 4880 for (i = 0; i < reload_n_operands; i++) 4881 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4882 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4883 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4884 return 0; 4885 4886 return 1; 4887 4888 case RELOAD_FOR_OPADDR_ADDR: 4889 for (i = 0; i < reload_n_operands; i++) 4890 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4891 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4892 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4893 return 0; 4894 4895 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4896 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)); 4897 4898 case RELOAD_FOR_INSN: 4899 /* These conflict with other outputs with RELOAD_OTHER. So 4900 we need only check for output addresses. */ 4901 4902 opnum = -1; 4903 4904 /* ... fall through ... */ 4905 4906 case RELOAD_FOR_OUTPUT: 4907 case RELOAD_FOR_OUTPUT_ADDRESS: 4908 case RELOAD_FOR_OUTADDR_ADDRESS: 4909 /* We already know these can't conflict with a later output. So the 4910 only thing to check are later output addresses. */ 4911 for (i = opnum + 1; i < reload_n_operands; i++) 4912 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4913 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) 4914 return 0; 4915 4916 return 1; 4917 } 4918 4919 abort (); 4920} 4921 4922/* Return 1 if the reloads denoted by R1 and R2 cannot share a register. 4923 Return 0 otherwise. 4924 4925 This function uses the same algorithm as reload_reg_free_p above. */ 4926 4927int 4928reloads_conflict (r1, r2) 4929 int r1, r2; 4930{ 4931 enum reload_type r1_type = reload_when_needed[r1]; 4932 enum reload_type r2_type = reload_when_needed[r2]; 4933 int r1_opnum = reload_opnum[r1]; 4934 int r2_opnum = reload_opnum[r2]; 4935 4936 /* RELOAD_OTHER conflicts with everything. */ 4937 if (r2_type == RELOAD_OTHER) 4938 return 1; 4939 4940 /* Otherwise, check conflicts differently for each type. */ 4941 4942 switch (r1_type) 4943 { 4944 case RELOAD_FOR_INPUT: 4945 return (r2_type == RELOAD_FOR_INSN 4946 || r2_type == RELOAD_FOR_OPERAND_ADDRESS 4947 || r2_type == RELOAD_FOR_OPADDR_ADDR 4948 || r2_type == RELOAD_FOR_INPUT 4949 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS 4950 || r2_type == RELOAD_FOR_INPADDR_ADDRESS) 4951 && r2_opnum > r1_opnum)); 4952 4953 case RELOAD_FOR_INPUT_ADDRESS: 4954 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) 4955 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); 4956 4957 case RELOAD_FOR_INPADDR_ADDRESS: 4958 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) 4959 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); 4960 4961 case RELOAD_FOR_OUTPUT_ADDRESS: 4962 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) 4963 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum)); 4964 4965 case RELOAD_FOR_OUTADDR_ADDRESS: 4966 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) 4967 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum)); 4968 4969 case RELOAD_FOR_OPERAND_ADDRESS: 4970 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN 4971 || r2_type == RELOAD_FOR_OPERAND_ADDRESS); 4972 4973 case RELOAD_FOR_OPADDR_ADDR: 4974 return (r2_type == RELOAD_FOR_INPUT 4975 || r2_type == RELOAD_FOR_OPADDR_ADDR); 4976 4977 case RELOAD_FOR_OUTPUT: 4978 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT 4979 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS 4980 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) 4981 && r2_opnum >= r1_opnum)); 4982 4983 case RELOAD_FOR_INSN: 4984 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT 4985 || r2_type == RELOAD_FOR_INSN 4986 || r2_type == RELOAD_FOR_OPERAND_ADDRESS); 4987 4988 case RELOAD_FOR_OTHER_ADDRESS: 4989 return r2_type == RELOAD_FOR_OTHER_ADDRESS; 4990 4991 case RELOAD_OTHER: 4992 return 1; 4993 4994 default: 4995 abort (); 4996 } 4997} 4998 4999/* Vector of reload-numbers showing the order in which the reloads should 5000 be processed. */ 5001short reload_order[MAX_RELOADS]; 5002 5003/* Indexed by reload number, 1 if incoming value 5004 inherited from previous insns. */ 5005char reload_inherited[MAX_RELOADS]; 5006 5007/* For an inherited reload, this is the insn the reload was inherited from, 5008 if we know it. Otherwise, this is 0. */ 5009rtx reload_inheritance_insn[MAX_RELOADS]; 5010 5011/* If non-zero, this is a place to get the value of the reload, 5012 rather than using reload_in. */ 5013rtx reload_override_in[MAX_RELOADS]; 5014 5015/* For each reload, the hard register number of the register used, 5016 or -1 if we did not need a register for this reload. */ 5017int reload_spill_index[MAX_RELOADS]; 5018 5019/* Return 1 if the value in reload reg REGNO, as used by a reload 5020 needed for the part of the insn specified by OPNUM and TYPE, 5021 may be used to load VALUE into it. 5022 5023 Other read-only reloads with the same value do not conflict 5024 unless OUT is non-zero and these other reloads have to live while 5025 output reloads live. 5026 5027 RELOADNUM is the number of the reload we want to load this value for; 5028 a reload does not conflict with itself. 5029 5030 The caller has to make sure that there is no conflict with the return 5031 register. */ 5032static int 5033reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum) 5034 int regno; 5035 int opnum; 5036 enum reload_type type; 5037 rtx value, out; 5038 int reloadnum; 5039{ 5040 int time1; 5041 int i; 5042 5043 /* We use some pseudo 'time' value to check if the lifetimes of the 5044 new register use would overlap with the one of a previous reload 5045 that is not read-only or uses a different value. 5046 The 'time' used doesn't have to be linear in any shape or form, just 5047 monotonic. 5048 Some reload types use different 'buckets' for each operand. 5049 So there are MAX_RECOG_OPERANDS different time values for each 5050 such reload type. 5051 We compute TIME1 as the time when the register for the prospective 5052 new reload ceases to be live, and TIME2 for each existing 5053 reload as the time when that the reload register of that reload 5054 becomes live. 5055 Where there is little to be gained by exact lifetime calculations, 5056 we just make conservative assumptions, i.e. a longer lifetime; 5057 this is done in the 'default:' cases. */ 5058 switch (type) 5059 { 5060 case RELOAD_FOR_OTHER_ADDRESS: 5061 time1 = 0; 5062 break; 5063 /* For each input, we might have a sequence of RELOAD_FOR_INPADDR_ADDRESS, 5064 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , 5065 respectively, to the time values for these, we get distinct time 5066 values. To get distinct time values for each operand, we have to 5067 multiply opnum by at least three. We round that up to four because 5068 multiply by four is often cheaper. */ 5069 case RELOAD_FOR_INPADDR_ADDRESS: 5070 time1 = opnum * 4 + 1; 5071 break; 5072 case RELOAD_FOR_INPUT_ADDRESS: 5073 time1 = opnum * 4 + 2; 5074 break; 5075 case RELOAD_FOR_INPUT: 5076 /* All RELOAD_FOR_INPUT reloads remain live till just before the 5077 instruction is executed. */ 5078 time1 = (MAX_RECOG_OPERANDS - 1) * 4 + 3; 5079 break; 5080 /* opnum * 4 + 3 < opnum * 4 + 4 5081 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ 5082 case RELOAD_FOR_OUTPUT_ADDRESS: 5083 time1 = MAX_RECOG_OPERANDS * 4 + opnum; 5084 break; 5085 default: 5086 time1 = MAX_RECOG_OPERANDS * 5; 5087 } 5088 5089 for (i = 0; i < n_reloads; i++) 5090 { 5091 rtx reg = reload_reg_rtx[i]; 5092 if (reg && GET_CODE (reg) == REG 5093 && ((unsigned) regno - true_regnum (reg) 5094 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1) 5095 && i != reloadnum) 5096 { 5097 if (out 5098 && reload_when_needed[i] != RELOAD_FOR_INPUT 5099 && reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS 5100 && reload_when_needed[i] != RELOAD_FOR_INPADDR_ADDRESS) 5101 return 0; 5102 if (! reload_in[i] || ! rtx_equal_p (reload_in[i], value) 5103 || reload_out[i]) 5104 { 5105 int time2; 5106 switch (reload_when_needed[i]) 5107 { 5108 case RELOAD_FOR_OTHER_ADDRESS: 5109 time2 = 0; 5110 break; 5111 case RELOAD_FOR_INPADDR_ADDRESS: 5112 time2 = reload_opnum[i] * 4 + 1; 5113 break; 5114 case RELOAD_FOR_INPUT_ADDRESS: 5115 time2 = reload_opnum[i] * 4 + 2; 5116 break; 5117 case RELOAD_FOR_INPUT: 5118 time2 = reload_opnum[i] * 4 + 3; 5119 break; 5120 case RELOAD_FOR_OUTPUT: 5121 /* All RELOAD_FOR_OUTPUT reloads become live just after the 5122 instruction is executed. */ 5123 time2 = MAX_RECOG_OPERANDS * 4; 5124 break; 5125 /* The first RELOAD_FOR_OUTPUT_ADDRESS reload conflicts with the 5126 RELOAD_FOR_OUTPUT reloads, so assign it the same time value. */ 5127 case RELOAD_FOR_OUTPUT_ADDRESS: 5128 time2 = MAX_RECOG_OPERANDS * 4 + reload_opnum[i]; 5129 break; 5130 case RELOAD_OTHER: 5131 if (! reload_in[i] || rtx_equal_p (reload_in[i], value)) 5132 { 5133 time2 = MAX_RECOG_OPERANDS * 4; 5134 break; 5135 } 5136 default: 5137 time2 = 0; 5138 } 5139 if (time1 >= time2) 5140 return 0; 5141 } 5142 } 5143 } 5144 return 1; 5145} 5146 5147/* Find a spill register to use as a reload register for reload R. 5148 LAST_RELOAD is non-zero if this is the last reload for the insn being 5149 processed. 5150 5151 Set reload_reg_rtx[R] to the register allocated. 5152 5153 If NOERROR is nonzero, we return 1 if successful, 5154 or 0 if we couldn't find a spill reg and we didn't change anything. */ 5155 5156static int 5157allocate_reload_reg (r, insn, last_reload, noerror) 5158 int r; 5159 rtx insn; 5160 int last_reload; 5161 int noerror; 5162{ 5163 int i; 5164 int pass; 5165 int count; 5166 rtx new; 5167 int regno; 5168 5169 /* If we put this reload ahead, thinking it is a group, 5170 then insist on finding a group. Otherwise we can grab a 5171 reg that some other reload needs. 5172 (That can happen when we have a 68000 DATA_OR_FP_REG 5173 which is a group of data regs or one fp reg.) 5174 We need not be so restrictive if there are no more reloads 5175 for this insn. 5176 5177 ??? Really it would be nicer to have smarter handling 5178 for that kind of reg class, where a problem like this is normal. 5179 Perhaps those classes should be avoided for reloading 5180 by use of more alternatives. */ 5181 5182 int force_group = reload_nregs[r] > 1 && ! last_reload; 5183 5184 /* If we want a single register and haven't yet found one, 5185 take any reg in the right class and not in use. 5186 If we want a consecutive group, here is where we look for it. 5187 5188 We use two passes so we can first look for reload regs to 5189 reuse, which are already in use for other reloads in this insn, 5190 and only then use additional registers. 5191 I think that maximizing reuse is needed to make sure we don't 5192 run out of reload regs. Suppose we have three reloads, and 5193 reloads A and B can share regs. These need two regs. 5194 Suppose A and B are given different regs. 5195 That leaves none for C. */ 5196 for (pass = 0; pass < 2; pass++) 5197 { 5198 /* I is the index in spill_regs. 5199 We advance it round-robin between insns to use all spill regs 5200 equally, so that inherited reloads have a chance 5201 of leapfrogging each other. Don't do this, however, when we have 5202 group needs and failure would be fatal; if we only have a relatively 5203 small number of spill registers, and more than one of them has 5204 group needs, then by starting in the middle, we may end up 5205 allocating the first one in such a way that we are not left with 5206 sufficient groups to handle the rest. */ 5207 5208 if (noerror || ! force_group) 5209 i = last_spill_reg; 5210 else 5211 i = -1; 5212 5213 for (count = 0; count < n_spills; count++) 5214 { 5215 int class = (int) reload_reg_class[r]; 5216 5217 i = (i + 1) % n_spills; 5218 5219 if ((reload_reg_free_p (spill_regs[i], reload_opnum[r], 5220 reload_when_needed[r]) 5221 || (reload_in[r] 5222 /* We check reload_reg_used to make sure we 5223 don't clobber the return register. */ 5224 && ! TEST_HARD_REG_BIT (reload_reg_used, spill_regs[i]) 5225 && reload_reg_free_for_value_p (spill_regs[i], 5226 reload_opnum[r], 5227 reload_when_needed[r], 5228 reload_in[r], 5229 reload_out[r], r))) 5230 && TEST_HARD_REG_BIT (reg_class_contents[class], spill_regs[i]) 5231 && HARD_REGNO_MODE_OK (spill_regs[i], reload_mode[r]) 5232 /* Look first for regs to share, then for unshared. But 5233 don't share regs used for inherited reloads; they are 5234 the ones we want to preserve. */ 5235 && (pass 5236 || (TEST_HARD_REG_BIT (reload_reg_used_at_all, 5237 spill_regs[i]) 5238 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, 5239 spill_regs[i])))) 5240 { 5241 int nr = HARD_REGNO_NREGS (spill_regs[i], reload_mode[r]); 5242 /* Avoid the problem where spilling a GENERAL_OR_FP_REG 5243 (on 68000) got us two FP regs. If NR is 1, 5244 we would reject both of them. */ 5245 if (force_group) 5246 nr = CLASS_MAX_NREGS (reload_reg_class[r], reload_mode[r]); 5247 /* If we need only one reg, we have already won. */ 5248 if (nr == 1) 5249 { 5250 /* But reject a single reg if we demand a group. */ 5251 if (force_group) 5252 continue; 5253 break; 5254 } 5255 /* Otherwise check that as many consecutive regs as we need 5256 are available here. 5257 Also, don't use for a group registers that are 5258 needed for nongroups. */ 5259 if (! TEST_HARD_REG_BIT (counted_for_nongroups, spill_regs[i])) 5260 while (nr > 1) 5261 { 5262 regno = spill_regs[i] + nr - 1; 5263 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) 5264 && spill_reg_order[regno] >= 0 5265 && reload_reg_free_p (regno, reload_opnum[r], 5266 reload_when_needed[r]) 5267 && ! TEST_HARD_REG_BIT (counted_for_nongroups, 5268 regno))) 5269 break; 5270 nr--; 5271 } 5272 if (nr == 1) 5273 break; 5274 } 5275 } 5276 5277 /* If we found something on pass 1, omit pass 2. */ 5278 if (count < n_spills) 5279 break; 5280 } 5281 5282 /* We should have found a spill register by now. */ 5283 if (count == n_spills) 5284 { 5285 if (noerror) 5286 return 0; 5287 goto failure; 5288 } 5289 5290 /* I is the index in SPILL_REG_RTX of the reload register we are to 5291 allocate. Get an rtx for it and find its register number. */ 5292 5293 new = spill_reg_rtx[i]; 5294 5295 if (new == 0 || GET_MODE (new) != reload_mode[r]) 5296 spill_reg_rtx[i] = new 5297 = gen_rtx_REG (reload_mode[r], spill_regs[i]); 5298 5299 regno = true_regnum (new); 5300 5301 /* Detect when the reload reg can't hold the reload mode. 5302 This used to be one `if', but Sequent compiler can't handle that. */ 5303 if (HARD_REGNO_MODE_OK (regno, reload_mode[r])) 5304 { 5305 enum machine_mode test_mode = VOIDmode; 5306 if (reload_in[r]) 5307 test_mode = GET_MODE (reload_in[r]); 5308 /* If reload_in[r] has VOIDmode, it means we will load it 5309 in whatever mode the reload reg has: to wit, reload_mode[r]. 5310 We have already tested that for validity. */ 5311 /* Aside from that, we need to test that the expressions 5312 to reload from or into have modes which are valid for this 5313 reload register. Otherwise the reload insns would be invalid. */ 5314 if (! (reload_in[r] != 0 && test_mode != VOIDmode 5315 && ! HARD_REGNO_MODE_OK (regno, test_mode))) 5316 if (! (reload_out[r] != 0 5317 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (reload_out[r])))) 5318 { 5319 /* The reg is OK. */ 5320 last_spill_reg = i; 5321 5322 /* Mark as in use for this insn the reload regs we use 5323 for this. */ 5324 mark_reload_reg_in_use (spill_regs[i], reload_opnum[r], 5325 reload_when_needed[r], reload_mode[r]); 5326 5327 reload_reg_rtx[r] = new; 5328 reload_spill_index[r] = spill_regs[i]; 5329 return 1; 5330 } 5331 } 5332 5333 /* The reg is not OK. */ 5334 if (noerror) 5335 return 0; 5336 5337 failure: 5338 if (asm_noperands (PATTERN (insn)) < 0) 5339 /* It's the compiler's fault. */ 5340 fatal_insn ("Could not find a spill register", insn); 5341 5342 /* It's the user's fault; the operand's mode and constraint 5343 don't match. Disable this reload so we don't crash in final. */ 5344 error_for_asm (insn, 5345 "`asm' operand constraint incompatible with operand size"); 5346 reload_in[r] = 0; 5347 reload_out[r] = 0; 5348 reload_reg_rtx[r] = 0; 5349 reload_optional[r] = 1; 5350 reload_secondary_p[r] = 1; 5351 5352 return 1; 5353} 5354 5355/* Assign hard reg targets for the pseudo-registers we must reload 5356 into hard regs for this insn. 5357 Also output the instructions to copy them in and out of the hard regs. 5358 5359 For machines with register classes, we are responsible for 5360 finding a reload reg in the proper class. */ 5361 5362static void 5363choose_reload_regs (insn, avoid_return_reg) 5364 rtx insn; 5365 rtx avoid_return_reg; 5366{ 5367 register int i, j; 5368 int max_group_size = 1; 5369 enum reg_class group_class = NO_REGS; 5370 int inheritance; 5371 5372 rtx save_reload_reg_rtx[MAX_RELOADS]; 5373 char save_reload_inherited[MAX_RELOADS]; 5374 rtx save_reload_inheritance_insn[MAX_RELOADS]; 5375 rtx save_reload_override_in[MAX_RELOADS]; 5376 int save_reload_spill_index[MAX_RELOADS]; 5377 HARD_REG_SET save_reload_reg_used; 5378 HARD_REG_SET save_reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; 5379 HARD_REG_SET save_reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; 5380 HARD_REG_SET save_reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; 5381 HARD_REG_SET save_reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; 5382 HARD_REG_SET save_reload_reg_used_in_input[MAX_RECOG_OPERANDS]; 5383 HARD_REG_SET save_reload_reg_used_in_output[MAX_RECOG_OPERANDS]; 5384 HARD_REG_SET save_reload_reg_used_in_op_addr; 5385 HARD_REG_SET save_reload_reg_used_in_op_addr_reload; 5386 HARD_REG_SET save_reload_reg_used_in_insn; 5387 HARD_REG_SET save_reload_reg_used_in_other_addr; 5388 HARD_REG_SET save_reload_reg_used_at_all; 5389 5390 bzero (reload_inherited, MAX_RELOADS); 5391 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx)); 5392 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx)); 5393 5394 CLEAR_HARD_REG_SET (reload_reg_used); 5395 CLEAR_HARD_REG_SET (reload_reg_used_at_all); 5396 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); 5397 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); 5398 CLEAR_HARD_REG_SET (reload_reg_used_in_insn); 5399 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); 5400 5401 for (i = 0; i < reload_n_operands; i++) 5402 { 5403 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); 5404 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); 5405 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); 5406 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); 5407 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); 5408 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); 5409 } 5410 5411 /* Don't bother with avoiding the return reg 5412 if we have no mandatory reload that could use it. */ 5413 if (SMALL_REGISTER_CLASSES && avoid_return_reg) 5414 { 5415 int do_avoid = 0; 5416 int regno = REGNO (avoid_return_reg); 5417 int nregs 5418 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); 5419 int r; 5420 5421 for (r = regno; r < regno + nregs; r++) 5422 if (spill_reg_order[r] >= 0) 5423 for (j = 0; j < n_reloads; j++) 5424 if (!reload_optional[j] && reload_reg_rtx[j] == 0 5425 && (reload_in[j] != 0 || reload_out[j] != 0 5426 || reload_secondary_p[j]) 5427 && 5428 TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[j]], r)) 5429 do_avoid = 1; 5430 if (!do_avoid) 5431 avoid_return_reg = 0; 5432 } 5433 5434#if 0 /* Not needed, now that we can always retry without inheritance. */ 5435 /* See if we have more mandatory reloads than spill regs. 5436 If so, then we cannot risk optimizations that could prevent 5437 reloads from sharing one spill register. 5438 5439 Since we will try finding a better register than reload_reg_rtx 5440 unless it is equal to reload_in or reload_out, count such reloads. */ 5441 5442 { 5443 int tem = SMALL_REGISTER_CLASSES? (avoid_return_reg != 0): 0; 5444 for (j = 0; j < n_reloads; j++) 5445 if (! reload_optional[j] 5446 && (reload_in[j] != 0 || reload_out[j] != 0 || reload_secondary_p[j]) 5447 && (reload_reg_rtx[j] == 0 5448 || (! rtx_equal_p (reload_reg_rtx[j], reload_in[j]) 5449 && ! rtx_equal_p (reload_reg_rtx[j], reload_out[j])))) 5450 tem++; 5451 if (tem > n_spills) 5452 must_reuse = 1; 5453 } 5454#endif 5455 5456 /* Don't use the subroutine call return reg for a reload 5457 if we are supposed to avoid it. */ 5458 if (SMALL_REGISTER_CLASSES && avoid_return_reg) 5459 { 5460 int regno = REGNO (avoid_return_reg); 5461 int nregs 5462 = HARD_REGNO_NREGS (regno, GET_MODE (avoid_return_reg)); 5463 int r; 5464 5465 for (r = regno; r < regno + nregs; r++) 5466 if (spill_reg_order[r] >= 0) 5467 SET_HARD_REG_BIT (reload_reg_used, r); 5468 } 5469 5470 /* In order to be certain of getting the registers we need, 5471 we must sort the reloads into order of increasing register class. 5472 Then our grabbing of reload registers will parallel the process 5473 that provided the reload registers. 5474 5475 Also note whether any of the reloads wants a consecutive group of regs. 5476 If so, record the maximum size of the group desired and what 5477 register class contains all the groups needed by this insn. */ 5478 5479 for (j = 0; j < n_reloads; j++) 5480 { 5481 reload_order[j] = j; 5482 reload_spill_index[j] = -1; 5483 5484 reload_mode[j] 5485 = (reload_inmode[j] == VOIDmode 5486 || (GET_MODE_SIZE (reload_outmode[j]) 5487 > GET_MODE_SIZE (reload_inmode[j]))) 5488 ? reload_outmode[j] : reload_inmode[j]; 5489 5490 reload_nregs[j] = CLASS_MAX_NREGS (reload_reg_class[j], reload_mode[j]); 5491 5492 if (reload_nregs[j] > 1) 5493 { 5494 max_group_size = MAX (reload_nregs[j], max_group_size); 5495 group_class = reg_class_superunion[(int)reload_reg_class[j]][(int)group_class]; 5496 } 5497 5498 /* If we have already decided to use a certain register, 5499 don't use it in another way. */ 5500 if (reload_reg_rtx[j]) 5501 mark_reload_reg_in_use (REGNO (reload_reg_rtx[j]), reload_opnum[j], 5502 reload_when_needed[j], reload_mode[j]); 5503 } 5504 5505 if (n_reloads > 1) 5506 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); 5507 5508 bcopy ((char *) reload_reg_rtx, (char *) save_reload_reg_rtx, 5509 sizeof reload_reg_rtx); 5510 bcopy (reload_inherited, save_reload_inherited, sizeof reload_inherited); 5511 bcopy ((char *) reload_inheritance_insn, 5512 (char *) save_reload_inheritance_insn, 5513 sizeof reload_inheritance_insn); 5514 bcopy ((char *) reload_override_in, (char *) save_reload_override_in, 5515 sizeof reload_override_in); 5516 bcopy ((char *) reload_spill_index, (char *) save_reload_spill_index, 5517 sizeof reload_spill_index); 5518 COPY_HARD_REG_SET (save_reload_reg_used, reload_reg_used); 5519 COPY_HARD_REG_SET (save_reload_reg_used_at_all, reload_reg_used_at_all); 5520 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr, 5521 reload_reg_used_in_op_addr); 5522 5523 COPY_HARD_REG_SET (save_reload_reg_used_in_op_addr_reload, 5524 reload_reg_used_in_op_addr_reload); 5525 5526 COPY_HARD_REG_SET (save_reload_reg_used_in_insn, 5527 reload_reg_used_in_insn); 5528 COPY_HARD_REG_SET (save_reload_reg_used_in_other_addr, 5529 reload_reg_used_in_other_addr); 5530 5531 for (i = 0; i < reload_n_operands; i++) 5532 { 5533 COPY_HARD_REG_SET (save_reload_reg_used_in_output[i], 5534 reload_reg_used_in_output[i]); 5535 COPY_HARD_REG_SET (save_reload_reg_used_in_input[i], 5536 reload_reg_used_in_input[i]); 5537 COPY_HARD_REG_SET (save_reload_reg_used_in_input_addr[i], 5538 reload_reg_used_in_input_addr[i]); 5539 COPY_HARD_REG_SET (save_reload_reg_used_in_inpaddr_addr[i], 5540 reload_reg_used_in_inpaddr_addr[i]); 5541 COPY_HARD_REG_SET (save_reload_reg_used_in_output_addr[i], 5542 reload_reg_used_in_output_addr[i]); 5543 COPY_HARD_REG_SET (save_reload_reg_used_in_outaddr_addr[i], 5544 reload_reg_used_in_outaddr_addr[i]); 5545 } 5546 5547 /* If -O, try first with inheritance, then turning it off. 5548 If not -O, don't do inheritance. 5549 Using inheritance when not optimizing leads to paradoxes 5550 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves 5551 because one side of the comparison might be inherited. */ 5552 5553 for (inheritance = optimize > 0; inheritance >= 0; inheritance--) 5554 { 5555 /* Process the reloads in order of preference just found. 5556 Beyond this point, subregs can be found in reload_reg_rtx. 5557 5558 This used to look for an existing reloaded home for all 5559 of the reloads, and only then perform any new reloads. 5560 But that could lose if the reloads were done out of reg-class order 5561 because a later reload with a looser constraint might have an old 5562 home in a register needed by an earlier reload with a tighter constraint. 5563 5564 To solve this, we make two passes over the reloads, in the order 5565 described above. In the first pass we try to inherit a reload 5566 from a previous insn. If there is a later reload that needs a 5567 class that is a proper subset of the class being processed, we must 5568 also allocate a spill register during the first pass. 5569 5570 Then make a second pass over the reloads to allocate any reloads 5571 that haven't been given registers yet. */ 5572 5573 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); 5574 5575 for (j = 0; j < n_reloads; j++) 5576 { 5577 register int r = reload_order[j]; 5578 5579 /* Ignore reloads that got marked inoperative. */ 5580 if (reload_out[r] == 0 && reload_in[r] == 0 5581 && ! reload_secondary_p[r]) 5582 continue; 5583 5584 /* If find_reloads chose a to use reload_in or reload_out as a reload 5585 register, we don't need to chose one. Otherwise, try even if it 5586 found one since we might save an insn if we find the value lying 5587 around. */ 5588 if (reload_in[r] != 0 && reload_reg_rtx[r] != 0 5589 && (rtx_equal_p (reload_in[r], reload_reg_rtx[r]) 5590 || rtx_equal_p (reload_out[r], reload_reg_rtx[r]))) 5591 continue; 5592 5593#if 0 /* No longer needed for correct operation. 5594 It might give better code, or might not; worth an experiment? */ 5595 /* If this is an optional reload, we can't inherit from earlier insns 5596 until we are sure that any non-optional reloads have been allocated. 5597 The following code takes advantage of the fact that optional reloads 5598 are at the end of reload_order. */ 5599 if (reload_optional[r] != 0) 5600 for (i = 0; i < j; i++) 5601 if ((reload_out[reload_order[i]] != 0 5602 || reload_in[reload_order[i]] != 0 5603 || reload_secondary_p[reload_order[i]]) 5604 && ! reload_optional[reload_order[i]] 5605 && reload_reg_rtx[reload_order[i]] == 0) 5606 allocate_reload_reg (reload_order[i], insn, 0, inheritance); 5607#endif 5608 5609 /* First see if this pseudo is already available as reloaded 5610 for a previous insn. We cannot try to inherit for reloads 5611 that are smaller than the maximum number of registers needed 5612 for groups unless the register we would allocate cannot be used 5613 for the groups. 5614 5615 We could check here to see if this is a secondary reload for 5616 an object that is already in a register of the desired class. 5617 This would avoid the need for the secondary reload register. 5618 But this is complex because we can't easily determine what 5619 objects might want to be loaded via this reload. So let a 5620 register be allocated here. In `emit_reload_insns' we suppress 5621 one of the loads in the case described above. */ 5622 5623 if (inheritance) 5624 { 5625 register int regno = -1; 5626 enum machine_mode mode; 5627 5628 if (reload_in[r] == 0) 5629 ; 5630 else if (GET_CODE (reload_in[r]) == REG) 5631 { 5632 regno = REGNO (reload_in[r]); 5633 mode = GET_MODE (reload_in[r]); 5634 } 5635 else if (GET_CODE (reload_in_reg[r]) == REG) 5636 { 5637 regno = REGNO (reload_in_reg[r]); 5638 mode = GET_MODE (reload_in_reg[r]); 5639 } 5640 else if (GET_CODE (reload_in[r]) == MEM) 5641 { 5642 rtx prev = prev_nonnote_insn (insn), note; 5643 5644 if (prev && GET_CODE (prev) == INSN 5645 && GET_CODE (PATTERN (prev)) == USE 5646 && GET_CODE (XEXP (PATTERN (prev), 0)) == REG 5647 && (REGNO (XEXP (PATTERN (prev), 0)) 5648 >= FIRST_PSEUDO_REGISTER) 5649 && (note = find_reg_note (prev, REG_EQUAL, NULL_RTX)) 5650 && GET_CODE (XEXP (note, 0)) == MEM) 5651 { 5652 rtx addr = XEXP (XEXP (note, 0), 0); 5653 int size_diff 5654 = (GET_MODE_SIZE (GET_MODE (addr)) 5655 - GET_MODE_SIZE (GET_MODE (reload_in[r]))); 5656 if (size_diff >= 0 5657 && rtx_equal_p ((BYTES_BIG_ENDIAN 5658 ? plus_constant (addr, size_diff) 5659 : addr), 5660 XEXP (reload_in[r], 0))) 5661 { 5662 regno = REGNO (XEXP (PATTERN (prev), 0)); 5663 mode = GET_MODE (reload_in[r]); 5664 } 5665 } 5666 } 5667#if 0 5668 /* This won't work, since REGNO can be a pseudo reg number. 5669 Also, it takes much more hair to keep track of all the things 5670 that can invalidate an inherited reload of part of a pseudoreg. */ 5671 else if (GET_CODE (reload_in[r]) == SUBREG 5672 && GET_CODE (SUBREG_REG (reload_in[r])) == REG) 5673 regno = REGNO (SUBREG_REG (reload_in[r])) + SUBREG_WORD (reload_in[r]); 5674#endif 5675 5676 if (regno >= 0 && reg_last_reload_reg[regno] != 0) 5677 { 5678 i = REGNO (reg_last_reload_reg[regno]); 5679 5680 if (reg_reloaded_contents[i] == regno 5681 && TEST_HARD_REG_BIT (reg_reloaded_valid, i) 5682 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])) 5683 >= GET_MODE_SIZE (mode)) 5684 && HARD_REGNO_MODE_OK (i, reload_mode[r]) 5685 && TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], 5686 i) 5687 && (reload_nregs[r] == max_group_size 5688 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], 5689 i)) 5690 && ((reload_reg_free_p (i, reload_opnum[r], 5691 reload_when_needed[r]) 5692 && reload_reg_free_before_p (i, reload_opnum[r], 5693 reload_when_needed[r])) 5694 || reload_reg_free_for_value_p (i, reload_opnum[r], 5695 reload_when_needed[r], 5696 reload_in[r], 5697 reload_out[r], r))) 5698 { 5699 /* If a group is needed, verify that all the subsequent 5700 registers still have their values intact. */ 5701 int nr 5702 = HARD_REGNO_NREGS (i, reload_mode[r]); 5703 int k; 5704 5705 for (k = 1; k < nr; k++) 5706 if (reg_reloaded_contents[i + k] != regno 5707 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) 5708 break; 5709 5710 if (k == nr) 5711 { 5712 int i1; 5713 5714 /* We found a register that contains the 5715 value we need. If this register is the 5716 same as an `earlyclobber' operand of the 5717 current insn, just mark it as a place to 5718 reload from since we can't use it as the 5719 reload register itself. */ 5720 5721 for (i1 = 0; i1 < n_earlyclobbers; i1++) 5722 if (reg_overlap_mentioned_for_reload_p 5723 (reg_last_reload_reg[regno], 5724 reload_earlyclobbers[i1])) 5725 break; 5726 5727 if (i1 != n_earlyclobbers 5728 /* Don't use it if we'd clobber a pseudo reg. */ 5729 || (spill_reg_order[i] < 0 5730 && reload_out[r] 5731 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) 5732 /* Don't really use the inherited spill reg 5733 if we need it wider than we've got it. */ 5734 || (GET_MODE_SIZE (reload_mode[r]) 5735 > GET_MODE_SIZE (mode))) 5736 reload_override_in[r] = reg_last_reload_reg[regno]; 5737 else 5738 { 5739 int k; 5740 /* We can use this as a reload reg. */ 5741 /* Mark the register as in use for this part of 5742 the insn. */ 5743 mark_reload_reg_in_use (i, 5744 reload_opnum[r], 5745 reload_when_needed[r], 5746 reload_mode[r]); 5747 reload_reg_rtx[r] = reg_last_reload_reg[regno]; 5748 reload_inherited[r] = 1; 5749 reload_inheritance_insn[r] 5750 = reg_reloaded_insn[i]; 5751 reload_spill_index[r] = i; 5752 for (k = 0; k < nr; k++) 5753 SET_HARD_REG_BIT (reload_reg_used_for_inherit, 5754 i + k); 5755 } 5756 } 5757 } 5758 } 5759 } 5760 5761 /* Here's another way to see if the value is already lying around. */ 5762 if (inheritance 5763 && reload_in[r] != 0 5764 && ! reload_inherited[r] 5765 && reload_out[r] == 0 5766 && (CONSTANT_P (reload_in[r]) 5767 || GET_CODE (reload_in[r]) == PLUS 5768 || GET_CODE (reload_in[r]) == REG 5769 || GET_CODE (reload_in[r]) == MEM) 5770 && (reload_nregs[r] == max_group_size 5771 || ! reg_classes_intersect_p (reload_reg_class[r], group_class))) 5772 { 5773 register rtx equiv 5774 = find_equiv_reg (reload_in[r], insn, reload_reg_class[r], 5775 -1, NULL_PTR, 0, reload_mode[r]); 5776 int regno; 5777 5778 if (equiv != 0) 5779 { 5780 if (GET_CODE (equiv) == REG) 5781 regno = REGNO (equiv); 5782 else if (GET_CODE (equiv) == SUBREG) 5783 { 5784 /* This must be a SUBREG of a hard register. 5785 Make a new REG since this might be used in an 5786 address and not all machines support SUBREGs 5787 there. */ 5788 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv); 5789 equiv = gen_rtx_REG (reload_mode[r], regno); 5790 } 5791 else 5792 abort (); 5793 } 5794 5795 /* If we found a spill reg, reject it unless it is free 5796 and of the desired class. */ 5797 if (equiv != 0 5798 && ((spill_reg_order[regno] >= 0 5799 && ! (reload_reg_free_before_p (regno, reload_opnum[r], 5800 reload_when_needed[r]) 5801 || reload_reg_free_for_value_p (regno, 5802 reload_opnum[r], 5803 reload_when_needed[r], 5804 reload_in[r], 5805 reload_out[r], r))) 5806 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) reload_reg_class[r]], 5807 regno))) 5808 equiv = 0; 5809 5810 if (equiv != 0 && TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)) 5811 equiv = 0; 5812 5813 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, reload_mode[r])) 5814 equiv = 0; 5815 5816 /* We found a register that contains the value we need. 5817 If this register is the same as an `earlyclobber' operand 5818 of the current insn, just mark it as a place to reload from 5819 since we can't use it as the reload register itself. */ 5820 5821 if (equiv != 0) 5822 for (i = 0; i < n_earlyclobbers; i++) 5823 if (reg_overlap_mentioned_for_reload_p (equiv, 5824 reload_earlyclobbers[i])) 5825 { 5826 reload_override_in[r] = equiv; 5827 equiv = 0; 5828 break; 5829 } 5830 5831 /* If the equiv register we have found is explicitly clobbered 5832 in the current insn, it depends on the reload type if we 5833 can use it, use it for reload_override_in, or not at all. 5834 In particular, we then can't use EQUIV for a 5835 RELOAD_FOR_OUTPUT_ADDRESS reload. */ 5836 5837 if (equiv != 0 && regno_clobbered_p (regno, insn)) 5838 { 5839 switch (reload_when_needed[r]) 5840 { 5841 case RELOAD_FOR_OTHER_ADDRESS: 5842 case RELOAD_FOR_INPADDR_ADDRESS: 5843 case RELOAD_FOR_INPUT_ADDRESS: 5844 case RELOAD_FOR_OPADDR_ADDR: 5845 break; 5846 case RELOAD_OTHER: 5847 case RELOAD_FOR_INPUT: 5848 case RELOAD_FOR_OPERAND_ADDRESS: 5849 reload_override_in[r] = equiv; 5850 /* Fall through. */ 5851 default: 5852 equiv = 0; 5853 break; 5854 } 5855 } 5856 5857 /* If we found an equivalent reg, say no code need be generated 5858 to load it, and use it as our reload reg. */ 5859 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM) 5860 { 5861 int nr = HARD_REGNO_NREGS (regno, reload_mode[r]); 5862 int k; 5863 reload_reg_rtx[r] = equiv; 5864 reload_inherited[r] = 1; 5865 5866 /* If reg_reloaded_valid is not set for this register, 5867 there might be a stale spill_reg_store lying around. 5868 We must clear it, since otherwise emit_reload_insns 5869 might delete the store. */ 5870 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) 5871 spill_reg_store[regno] = NULL_RTX; 5872 /* If any of the hard registers in EQUIV are spill 5873 registers, mark them as in use for this insn. */ 5874 for (k = 0; k < nr; k++) 5875 { 5876 i = spill_reg_order[regno + k]; 5877 if (i >= 0) 5878 { 5879 mark_reload_reg_in_use (regno, reload_opnum[r], 5880 reload_when_needed[r], 5881 reload_mode[r]); 5882 SET_HARD_REG_BIT (reload_reg_used_for_inherit, 5883 regno + k); 5884 } 5885 } 5886 } 5887 } 5888 5889 /* If we found a register to use already, or if this is an optional 5890 reload, we are done. */ 5891 if (reload_reg_rtx[r] != 0 || reload_optional[r] != 0) 5892 continue; 5893 5894#if 0 /* No longer needed for correct operation. Might or might not 5895 give better code on the average. Want to experiment? */ 5896 5897 /* See if there is a later reload that has a class different from our 5898 class that intersects our class or that requires less register 5899 than our reload. If so, we must allocate a register to this 5900 reload now, since that reload might inherit a previous reload 5901 and take the only available register in our class. Don't do this 5902 for optional reloads since they will force all previous reloads 5903 to be allocated. Also don't do this for reloads that have been 5904 turned off. */ 5905 5906 for (i = j + 1; i < n_reloads; i++) 5907 { 5908 int s = reload_order[i]; 5909 5910 if ((reload_in[s] == 0 && reload_out[s] == 0 5911 && ! reload_secondary_p[s]) 5912 || reload_optional[s]) 5913 continue; 5914 5915 if ((reload_reg_class[s] != reload_reg_class[r] 5916 && reg_classes_intersect_p (reload_reg_class[r], 5917 reload_reg_class[s])) 5918 || reload_nregs[s] < reload_nregs[r]) 5919 break; 5920 } 5921 5922 if (i == n_reloads) 5923 continue; 5924 5925 allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance); 5926#endif 5927 } 5928 5929 /* Now allocate reload registers for anything non-optional that 5930 didn't get one yet. */ 5931 for (j = 0; j < n_reloads; j++) 5932 { 5933 register int r = reload_order[j]; 5934 5935 /* Ignore reloads that got marked inoperative. */ 5936 if (reload_out[r] == 0 && reload_in[r] == 0 && ! reload_secondary_p[r]) 5937 continue; 5938 5939 /* Skip reloads that already have a register allocated or are 5940 optional. */ 5941 if (reload_reg_rtx[r] != 0 || reload_optional[r]) 5942 continue; 5943 5944 if (! allocate_reload_reg (r, insn, j == n_reloads - 1, inheritance)) 5945 break; 5946 } 5947 5948 /* If that loop got all the way, we have won. */ 5949 if (j == n_reloads) 5950 break; 5951 5952 fail: 5953 /* Loop around and try without any inheritance. */ 5954 /* First undo everything done by the failed attempt 5955 to allocate with inheritance. */ 5956 bcopy ((char *) save_reload_reg_rtx, (char *) reload_reg_rtx, 5957 sizeof reload_reg_rtx); 5958 bcopy ((char *) save_reload_inherited, (char *) reload_inherited, 5959 sizeof reload_inherited); 5960 bcopy ((char *) save_reload_inheritance_insn, 5961 (char *) reload_inheritance_insn, 5962 sizeof reload_inheritance_insn); 5963 bcopy ((char *) save_reload_override_in, (char *) reload_override_in, 5964 sizeof reload_override_in); 5965 bcopy ((char *) save_reload_spill_index, (char *) reload_spill_index, 5966 sizeof reload_spill_index); 5967 COPY_HARD_REG_SET (reload_reg_used, save_reload_reg_used); 5968 COPY_HARD_REG_SET (reload_reg_used_at_all, save_reload_reg_used_at_all); 5969 COPY_HARD_REG_SET (reload_reg_used_in_op_addr, 5970 save_reload_reg_used_in_op_addr); 5971 COPY_HARD_REG_SET (reload_reg_used_in_op_addr_reload, 5972 save_reload_reg_used_in_op_addr_reload); 5973 COPY_HARD_REG_SET (reload_reg_used_in_insn, 5974 save_reload_reg_used_in_insn); 5975 COPY_HARD_REG_SET (reload_reg_used_in_other_addr, 5976 save_reload_reg_used_in_other_addr); 5977 5978 for (i = 0; i < reload_n_operands; i++) 5979 { 5980 COPY_HARD_REG_SET (reload_reg_used_in_input[i], 5981 save_reload_reg_used_in_input[i]); 5982 COPY_HARD_REG_SET (reload_reg_used_in_output[i], 5983 save_reload_reg_used_in_output[i]); 5984 COPY_HARD_REG_SET (reload_reg_used_in_input_addr[i], 5985 save_reload_reg_used_in_input_addr[i]); 5986 COPY_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i], 5987 save_reload_reg_used_in_inpaddr_addr[i]); 5988 COPY_HARD_REG_SET (reload_reg_used_in_output_addr[i], 5989 save_reload_reg_used_in_output_addr[i]); 5990 COPY_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i], 5991 save_reload_reg_used_in_outaddr_addr[i]); 5992 } 5993 } 5994 5995 /* If we thought we could inherit a reload, because it seemed that 5996 nothing else wanted the same reload register earlier in the insn, 5997 verify that assumption, now that all reloads have been assigned. */ 5998 5999 for (j = 0; j < n_reloads; j++) 6000 { 6001 register int r = reload_order[j]; 6002 6003 if (reload_inherited[r] && reload_reg_rtx[r] != 0 6004 && ! (reload_reg_free_before_p (true_regnum (reload_reg_rtx[r]), 6005 reload_opnum[r], 6006 reload_when_needed[r]) 6007 || reload_reg_free_for_value_p (true_regnum (reload_reg_rtx[r]), 6008 reload_opnum[r], 6009 reload_when_needed[r], 6010 reload_in[r], 6011 reload_out[r], r))) 6012 reload_inherited[r] = 0; 6013 /* If we can inherit a RELOAD_FOR_INPUT, then we do not need its related 6014 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads. 6015 ??? This could be extended to other reload types, but these are 6016 more tricky to handle: 6017 RELOAD_FOR_OTHER_ADDRESS reloads might have been merged, so we 6018 can't eliminate them without a check that *all* references are 6019 now unused due to inheritance. 6020 While RELOAD_FOR_INPADDR_ADDRESS and RELOAD_FOR_OUTADDR_ADDRESS are 6021 not merged, we can't be sure that we have eliminated the use of 6022 that particular reload if we have seen just one 6023 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_OUTPUT_ADDRESS being inherited, 6024 since there might be multiple of the latter two reloads for a single 6025 operand. 6026 RELOAD_FOR_OPADDR_ADDR reloads for different operands are not 6027 merged, but might share the same register by courtesy of 6028 reload_reg_free_for_value_p. reload_reg_used_in_op_addr_reload 6029 does not differentiate by opnum, thus calling clear_reload_reg_in_use 6030 for one of these reloads would mark the register as free even though 6031 another RELOAD_FOR_OPADDR_ADDR reload might still use it. */ 6032 else if (reload_inherited[r] && reload_when_needed[r] == RELOAD_FOR_INPUT) 6033 { 6034 for (i = 0; i < n_reloads; i++) 6035 { 6036 if ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS 6037 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS) 6038 && reload_opnum[i] == reload_opnum[r] 6039 && reload_in[i] && reload_reg_rtx[i]) 6040 { 6041 int regno = true_regnum (reload_reg_rtx[i]); 6042 6043 reload_in[i] = 0; 6044 if (spill_reg_order[regno] >= 0) 6045 clear_reload_reg_in_use (regno, reload_opnum[i], 6046 reload_when_needed[i], 6047 reload_mode[i]); 6048 reload_reg_rtx[i] = 0; 6049 reload_spill_index[i] = -1; 6050 remove_replacements (i); 6051 } 6052 } 6053 } 6054 6055 /* If we found a better place to reload from, 6056 validate it in the same fashion, if it is a reload reg. */ 6057 if (reload_override_in[r] 6058 && (GET_CODE (reload_override_in[r]) == REG 6059 || GET_CODE (reload_override_in[r]) == SUBREG)) 6060 { 6061 int regno = true_regnum (reload_override_in[r]); 6062 if (spill_reg_order[regno] >= 0 6063 && ! reload_reg_free_before_p (regno, reload_opnum[r], 6064 reload_when_needed[r])) 6065 reload_override_in[r] = 0; 6066 } 6067 } 6068 6069 /* Now that reload_override_in is known valid, 6070 actually override reload_in. */ 6071 for (j = 0; j < n_reloads; j++) 6072 if (reload_override_in[j]) 6073 reload_in[j] = reload_override_in[j]; 6074 6075 /* If this reload won't be done because it has been cancelled or is 6076 optional and not inherited, clear reload_reg_rtx so other 6077 routines (such as subst_reloads) don't get confused. */ 6078 for (j = 0; j < n_reloads; j++) 6079 if (reload_reg_rtx[j] != 0 6080 && ((reload_optional[j] && ! reload_inherited[j]) 6081 || (reload_in[j] == 0 && reload_out[j] == 0 6082 && ! reload_secondary_p[j]))) 6083 { 6084 int regno = true_regnum (reload_reg_rtx[j]); 6085 6086 if (spill_reg_order[regno] >= 0) 6087 clear_reload_reg_in_use (regno, reload_opnum[j], 6088 reload_when_needed[j], reload_mode[j]); 6089 reload_reg_rtx[j] = 0; 6090 } 6091 6092 /* Record which pseudos and which spill regs have output reloads. */ 6093 for (j = 0; j < n_reloads; j++) 6094 { 6095 register int r = reload_order[j]; 6096 6097 i = reload_spill_index[r]; 6098 6099 /* I is nonneg if this reload uses a register. 6100 If reload_reg_rtx[r] is 0, this is an optional reload 6101 that we opted to ignore. */ 6102 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG 6103 && reload_reg_rtx[r] != 0) 6104 { 6105 register int nregno = REGNO (reload_out[r]); 6106 int nr = 1; 6107 6108 if (nregno < FIRST_PSEUDO_REGISTER) 6109 nr = HARD_REGNO_NREGS (nregno, reload_mode[r]); 6110 6111 while (--nr >= 0) 6112 reg_has_output_reload[nregno + nr] = 1; 6113 6114 if (i >= 0) 6115 { 6116 nr = HARD_REGNO_NREGS (i, reload_mode[r]); 6117 while (--nr >= 0) 6118 SET_HARD_REG_BIT (reg_is_output_reload, i + nr); 6119 } 6120 6121 if (reload_when_needed[r] != RELOAD_OTHER 6122 && reload_when_needed[r] != RELOAD_FOR_OUTPUT 6123 && reload_when_needed[r] != RELOAD_FOR_INSN) 6124 abort (); 6125 } 6126 } 6127} 6128 6129/* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two 6130 reloads of the same item for fear that we might not have enough reload 6131 registers. However, normally they will get the same reload register 6132 and hence actually need not be loaded twice. 6133 6134 Here we check for the most common case of this phenomenon: when we have 6135 a number of reloads for the same object, each of which were allocated 6136 the same reload_reg_rtx, that reload_reg_rtx is not used for any other 6137 reload, and is not modified in the insn itself. If we find such, 6138 merge all the reloads and set the resulting reload to RELOAD_OTHER. 6139 This will not increase the number of spill registers needed and will 6140 prevent redundant code. */ 6141 6142static void 6143merge_assigned_reloads (insn) 6144 rtx insn; 6145{ 6146 int i, j; 6147 6148 /* Scan all the reloads looking for ones that only load values and 6149 are not already RELOAD_OTHER and ones whose reload_reg_rtx are 6150 assigned and not modified by INSN. */ 6151 6152 for (i = 0; i < n_reloads; i++) 6153 { 6154 int conflicting_input = 0; 6155 int max_input_address_opnum = -1; 6156 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; 6157 6158 if (reload_in[i] == 0 || reload_when_needed[i] == RELOAD_OTHER 6159 || reload_out[i] != 0 || reload_reg_rtx[i] == 0 6160 || reg_set_p (reload_reg_rtx[i], insn)) 6161 continue; 6162 6163 /* Look at all other reloads. Ensure that the only use of this 6164 reload_reg_rtx is in a reload that just loads the same value 6165 as we do. Note that any secondary reloads must be of the identical 6166 class since the values, modes, and result registers are the 6167 same, so we need not do anything with any secondary reloads. */ 6168 6169 for (j = 0; j < n_reloads; j++) 6170 { 6171 if (i == j || reload_reg_rtx[j] == 0 6172 || ! reg_overlap_mentioned_p (reload_reg_rtx[j], 6173 reload_reg_rtx[i])) 6174 continue; 6175 6176 if (reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS 6177 && reload_opnum[j] > max_input_address_opnum) 6178 max_input_address_opnum = reload_opnum[j]; 6179 6180 /* If the reload regs aren't exactly the same (e.g, different modes) 6181 or if the values are different, we can't merge this reload. 6182 But if it is an input reload, we might still merge 6183 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ 6184 6185 if (! rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]) 6186 || reload_out[j] != 0 || reload_in[j] == 0 6187 || ! rtx_equal_p (reload_in[i], reload_in[j])) 6188 { 6189 if (reload_when_needed[j] != RELOAD_FOR_INPUT 6190 || ((reload_when_needed[i] != RELOAD_FOR_INPUT_ADDRESS 6191 || reload_opnum[i] > reload_opnum[j]) 6192 && reload_when_needed[i] != RELOAD_FOR_OTHER_ADDRESS)) 6193 break; 6194 conflicting_input = 1; 6195 if (min_conflicting_input_opnum > reload_opnum[j]) 6196 min_conflicting_input_opnum = reload_opnum[j]; 6197 } 6198 } 6199 6200 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if 6201 we, in fact, found any matching reloads. */ 6202 6203 if (j == n_reloads 6204 && max_input_address_opnum <= min_conflicting_input_opnum) 6205 { 6206 for (j = 0; j < n_reloads; j++) 6207 if (i != j && reload_reg_rtx[j] != 0 6208 && rtx_equal_p (reload_reg_rtx[i], reload_reg_rtx[j]) 6209 && (! conflicting_input 6210 || reload_when_needed[j] == RELOAD_FOR_INPUT_ADDRESS 6211 || reload_when_needed[j] == RELOAD_FOR_OTHER_ADDRESS)) 6212 { 6213 reload_when_needed[i] = RELOAD_OTHER; 6214 reload_in[j] = 0; 6215 reload_spill_index[j] = -1; 6216 transfer_replacements (i, j); 6217 } 6218 6219 /* If this is now RELOAD_OTHER, look for any reloads that load 6220 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS 6221 if they were for inputs, RELOAD_OTHER for outputs. Note that 6222 this test is equivalent to looking for reloads for this operand 6223 number. */ 6224 6225 if (reload_when_needed[i] == RELOAD_OTHER) 6226 for (j = 0; j < n_reloads; j++) 6227 if (reload_in[j] != 0 6228 && reload_when_needed[i] != RELOAD_OTHER 6229 && reg_overlap_mentioned_for_reload_p (reload_in[j], 6230 reload_in[i])) 6231 reload_when_needed[j] 6232 = ((reload_when_needed[i] == RELOAD_FOR_INPUT_ADDRESS 6233 || reload_when_needed[i] == RELOAD_FOR_INPADDR_ADDRESS) 6234 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); 6235 } 6236 } 6237} 6238 6239 6240/* Output insns to reload values in and out of the chosen reload regs. */ 6241 6242static void 6243emit_reload_insns (insn) 6244 rtx insn; 6245{ 6246 register int j; 6247 rtx input_reload_insns[MAX_RECOG_OPERANDS]; 6248 rtx other_input_address_reload_insns = 0; 6249 rtx other_input_reload_insns = 0; 6250 rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; 6251 rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; 6252 rtx output_reload_insns[MAX_RECOG_OPERANDS]; 6253 rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; 6254 rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; 6255 rtx operand_reload_insns = 0; 6256 rtx other_operand_reload_insns = 0; 6257 rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; 6258 rtx following_insn = NEXT_INSN (insn); 6259 rtx before_insn = insn; 6260 int special; 6261 /* Values to be put in spill_reg_store are put here first. */ 6262 rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; 6263 HARD_REG_SET reg_reloaded_died; 6264 6265 CLEAR_HARD_REG_SET (reg_reloaded_died); 6266 6267 for (j = 0; j < reload_n_operands; j++) 6268 input_reload_insns[j] = input_address_reload_insns[j] 6269 = inpaddr_address_reload_insns[j] 6270 = output_reload_insns[j] = output_address_reload_insns[j] 6271 = outaddr_address_reload_insns[j] 6272 = other_output_reload_insns[j] = 0; 6273 6274 /* Now output the instructions to copy the data into and out of the 6275 reload registers. Do these in the order that the reloads were reported, 6276 since reloads of base and index registers precede reloads of operands 6277 and the operands may need the base and index registers reloaded. */ 6278 6279 for (j = 0; j < n_reloads; j++) 6280 { 6281 register rtx old; 6282 rtx oldequiv_reg = 0; 6283 rtx this_reload_insn = 0; 6284 int expect_occurrences = 1; 6285 6286 if (reload_spill_index[j] >= 0) 6287 new_spill_reg_store[reload_spill_index[j]] = 0; 6288 6289 old = reload_in[j]; 6290 if (old != 0 && ! reload_inherited[j] 6291 && ! rtx_equal_p (reload_reg_rtx[j], old) 6292 && reload_reg_rtx[j] != 0) 6293 { 6294 register rtx reloadreg = reload_reg_rtx[j]; 6295 rtx oldequiv = 0; 6296 enum machine_mode mode; 6297 rtx *where; 6298 6299 /* Determine the mode to reload in. 6300 This is very tricky because we have three to choose from. 6301 There is the mode the insn operand wants (reload_inmode[J]). 6302 There is the mode of the reload register RELOADREG. 6303 There is the intrinsic mode of the operand, which we could find 6304 by stripping some SUBREGs. 6305 It turns out that RELOADREG's mode is irrelevant: 6306 we can change that arbitrarily. 6307 6308 Consider (SUBREG:SI foo:QI) as an operand that must be SImode; 6309 then the reload reg may not support QImode moves, so use SImode. 6310 If foo is in memory due to spilling a pseudo reg, this is safe, 6311 because the QImode value is in the least significant part of a 6312 slot big enough for a SImode. If foo is some other sort of 6313 memory reference, then it is impossible to reload this case, 6314 so previous passes had better make sure this never happens. 6315 6316 Then consider a one-word union which has SImode and one of its 6317 members is a float, being fetched as (SUBREG:SF union:SI). 6318 We must fetch that as SFmode because we could be loading into 6319 a float-only register. In this case OLD's mode is correct. 6320 6321 Consider an immediate integer: it has VOIDmode. Here we need 6322 to get a mode from something else. 6323 6324 In some cases, there is a fourth mode, the operand's 6325 containing mode. If the insn specifies a containing mode for 6326 this operand, it overrides all others. 6327 6328 I am not sure whether the algorithm here is always right, 6329 but it does the right things in those cases. */ 6330 6331 mode = GET_MODE (old); 6332 if (mode == VOIDmode) 6333 mode = reload_inmode[j]; 6334 6335#ifdef SECONDARY_INPUT_RELOAD_CLASS 6336 /* If we need a secondary register for this operation, see if 6337 the value is already in a register in that class. Don't 6338 do this if the secondary register will be used as a scratch 6339 register. */ 6340 6341 if (reload_secondary_in_reload[j] >= 0 6342 && reload_secondary_in_icode[j] == CODE_FOR_nothing 6343 && optimize) 6344 oldequiv 6345 = find_equiv_reg (old, insn, 6346 reload_reg_class[reload_secondary_in_reload[j]], 6347 -1, NULL_PTR, 0, mode); 6348#endif 6349 6350 /* If reloading from memory, see if there is a register 6351 that already holds the same value. If so, reload from there. 6352 We can pass 0 as the reload_reg_p argument because 6353 any other reload has either already been emitted, 6354 in which case find_equiv_reg will see the reload-insn, 6355 or has yet to be emitted, in which case it doesn't matter 6356 because we will use this equiv reg right away. */ 6357 6358 if (oldequiv == 0 && optimize 6359 && (GET_CODE (old) == MEM 6360 || (GET_CODE (old) == REG 6361 && REGNO (old) >= FIRST_PSEUDO_REGISTER 6362 && reg_renumber[REGNO (old)] < 0))) 6363 oldequiv = find_equiv_reg (old, insn, ALL_REGS, 6364 -1, NULL_PTR, 0, mode); 6365 6366 if (oldequiv) 6367 { 6368 int regno = true_regnum (oldequiv); 6369 6370 /* If OLDEQUIV is a spill register, don't use it for this 6371 if any other reload needs it at an earlier stage of this insn 6372 or at this stage. */ 6373 if (spill_reg_order[regno] >= 0 6374 && (! reload_reg_free_p (regno, reload_opnum[j], 6375 reload_when_needed[j]) 6376 || ! reload_reg_free_before_p (regno, reload_opnum[j], 6377 reload_when_needed[j]))) 6378 oldequiv = 0; 6379 6380 /* If OLDEQUIV is not a spill register, 6381 don't use it if any other reload wants it. */ 6382 if (spill_reg_order[regno] < 0) 6383 { 6384 int k; 6385 for (k = 0; k < n_reloads; k++) 6386 if (reload_reg_rtx[k] != 0 && k != j 6387 && reg_overlap_mentioned_for_reload_p (reload_reg_rtx[k], 6388 oldequiv)) 6389 { 6390 oldequiv = 0; 6391 break; 6392 } 6393 } 6394 6395 /* If it is no cheaper to copy from OLDEQUIV into the 6396 reload register than it would be to move from memory, 6397 don't use it. Likewise, if we need a secondary register 6398 or memory. */ 6399 6400 if (oldequiv != 0 6401 && ((REGNO_REG_CLASS (regno) != reload_reg_class[j] 6402 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno), 6403 reload_reg_class[j]) 6404 >= MEMORY_MOVE_COST (mode, reload_reg_class[j], 1))) 6405#ifdef SECONDARY_INPUT_RELOAD_CLASS 6406 || (SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j], 6407 mode, oldequiv) 6408 != NO_REGS) 6409#endif 6410#ifdef SECONDARY_MEMORY_NEEDED 6411 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), 6412 reload_reg_class[j], 6413 mode) 6414#endif 6415 )) 6416 oldequiv = 0; 6417 } 6418 6419 if (oldequiv == 0) 6420 oldequiv = old; 6421 else if (GET_CODE (oldequiv) == REG) 6422 oldequiv_reg = oldequiv; 6423 else if (GET_CODE (oldequiv) == SUBREG) 6424 oldequiv_reg = SUBREG_REG (oldequiv); 6425 6426 /* If we are reloading from a register that was recently stored in 6427 with an output-reload, see if we can prove there was 6428 actually no need to store the old value in it. */ 6429 6430 if (optimize && GET_CODE (oldequiv) == REG 6431 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER 6432 && spill_reg_store[REGNO (oldequiv)] 6433 && GET_CODE (old) == REG && dead_or_set_p (insn, old) 6434 /* This is unsafe if operand occurs more than once in current 6435 insn. Perhaps some occurrences weren't reloaded. */ 6436 && count_occurrences (PATTERN (insn), old) == 1) 6437 delete_output_reload (insn, j, spill_reg_store[REGNO (oldequiv)]); 6438 6439 /* Encapsulate both RELOADREG and OLDEQUIV into that mode, 6440 then load RELOADREG from OLDEQUIV. Note that we cannot use 6441 gen_lowpart_common since it can do the wrong thing when 6442 RELOADREG has a multi-word mode. Note that RELOADREG 6443 must always be a REG here. */ 6444 6445 if (GET_MODE (reloadreg) != mode) 6446 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); 6447 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) 6448 oldequiv = SUBREG_REG (oldequiv); 6449 if (GET_MODE (oldequiv) != VOIDmode 6450 && mode != GET_MODE (oldequiv)) 6451 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0); 6452 6453 /* Switch to the right place to emit the reload insns. */ 6454 switch (reload_when_needed[j]) 6455 { 6456 case RELOAD_OTHER: 6457 where = &other_input_reload_insns; 6458 break; 6459 case RELOAD_FOR_INPUT: 6460 where = &input_reload_insns[reload_opnum[j]]; 6461 break; 6462 case RELOAD_FOR_INPUT_ADDRESS: 6463 where = &input_address_reload_insns[reload_opnum[j]]; 6464 break; 6465 case RELOAD_FOR_INPADDR_ADDRESS: 6466 where = &inpaddr_address_reload_insns[reload_opnum[j]]; 6467 break; 6468 case RELOAD_FOR_OUTPUT_ADDRESS: 6469 where = &output_address_reload_insns[reload_opnum[j]]; 6470 break; 6471 case RELOAD_FOR_OUTADDR_ADDRESS: 6472 where = &outaddr_address_reload_insns[reload_opnum[j]]; 6473 break; 6474 case RELOAD_FOR_OPERAND_ADDRESS: 6475 where = &operand_reload_insns; 6476 break; 6477 case RELOAD_FOR_OPADDR_ADDR: 6478 where = &other_operand_reload_insns; 6479 break; 6480 case RELOAD_FOR_OTHER_ADDRESS: 6481 where = &other_input_address_reload_insns; 6482 break; 6483 default: 6484 abort (); 6485 } 6486 6487 push_to_sequence (*where); 6488 special = 0; 6489 6490 /* Auto-increment addresses must be reloaded in a special way. */ 6491 if (GET_CODE (oldequiv) == POST_INC 6492 || GET_CODE (oldequiv) == POST_DEC 6493 || GET_CODE (oldequiv) == PRE_INC 6494 || GET_CODE (oldequiv) == PRE_DEC) 6495 { 6496 /* We are not going to bother supporting the case where a 6497 incremented register can't be copied directly from 6498 OLDEQUIV since this seems highly unlikely. */ 6499 if (reload_secondary_in_reload[j] >= 0) 6500 abort (); 6501 /* Prevent normal processing of this reload. */ 6502 special = 1; 6503 /* Output a special code sequence for this case. */ 6504 inc_for_reload (reloadreg, oldequiv, reload_inc[j]); 6505 } 6506 6507 /* If we are reloading a pseudo-register that was set by the previous 6508 insn, see if we can get rid of that pseudo-register entirely 6509 by redirecting the previous insn into our reload register. */ 6510 6511 else if (optimize && GET_CODE (old) == REG 6512 && REGNO (old) >= FIRST_PSEUDO_REGISTER 6513 && dead_or_set_p (insn, old) 6514 /* This is unsafe if some other reload 6515 uses the same reg first. */ 6516 && reload_reg_free_before_p (REGNO (reloadreg), 6517 reload_opnum[j], 6518 reload_when_needed[j])) 6519 { 6520 rtx temp = PREV_INSN (insn); 6521 while (temp && GET_CODE (temp) == NOTE) 6522 temp = PREV_INSN (temp); 6523 if (temp 6524 && GET_CODE (temp) == INSN 6525 && GET_CODE (PATTERN (temp)) == SET 6526 && SET_DEST (PATTERN (temp)) == old 6527 /* Make sure we can access insn_operand_constraint. */ 6528 && asm_noperands (PATTERN (temp)) < 0 6529 /* This is unsafe if prev insn rejects our reload reg. */ 6530 && constraint_accepts_reg_p (insn_operand_constraint[recog_memoized (temp)][0], 6531 reloadreg) 6532 /* This is unsafe if operand occurs more than once in current 6533 insn. Perhaps some occurrences aren't reloaded. */ 6534 && count_occurrences (PATTERN (insn), old) == 1 6535 /* Don't risk splitting a matching pair of operands. */ 6536 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp)))) 6537 { 6538 /* Store into the reload register instead of the pseudo. */ 6539 SET_DEST (PATTERN (temp)) = reloadreg; 6540 /* If these are the only uses of the pseudo reg, 6541 pretend for GDB it lives in the reload reg we used. */ 6542 if (REG_N_DEATHS (REGNO (old)) == 1 6543 && REG_N_SETS (REGNO (old)) == 1) 6544 { 6545 reg_renumber[REGNO (old)] = REGNO (reload_reg_rtx[j]); 6546 alter_reg (REGNO (old), -1); 6547 } 6548 special = 1; 6549 } 6550 } 6551 6552 /* We can't do that, so output an insn to load RELOADREG. */ 6553 6554 if (! special) 6555 { 6556#ifdef SECONDARY_INPUT_RELOAD_CLASS 6557 rtx second_reload_reg = 0; 6558 enum insn_code icode; 6559 6560 /* If we have a secondary reload, pick up the secondary register 6561 and icode, if any. If OLDEQUIV and OLD are different or 6562 if this is an in-out reload, recompute whether or not we 6563 still need a secondary register and what the icode should 6564 be. If we still need a secondary register and the class or 6565 icode is different, go back to reloading from OLD if using 6566 OLDEQUIV means that we got the wrong type of register. We 6567 cannot have different class or icode due to an in-out reload 6568 because we don't make such reloads when both the input and 6569 output need secondary reload registers. */ 6570 6571 if (reload_secondary_in_reload[j] >= 0) 6572 { 6573 int secondary_reload = reload_secondary_in_reload[j]; 6574 rtx real_oldequiv = oldequiv; 6575 rtx real_old = old; 6576 6577 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM 6578 and similarly for OLD. 6579 See comments in get_secondary_reload in reload.c. */ 6580 if (GET_CODE (oldequiv) == REG 6581 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER 6582 && reg_equiv_mem[REGNO (oldequiv)] != 0) 6583 real_oldequiv = reg_equiv_mem[REGNO (oldequiv)]; 6584 6585 if (GET_CODE (old) == REG 6586 && REGNO (old) >= FIRST_PSEUDO_REGISTER 6587 && reg_equiv_mem[REGNO (old)] != 0) 6588 real_old = reg_equiv_mem[REGNO (old)]; 6589 6590 second_reload_reg = reload_reg_rtx[secondary_reload]; 6591 icode = reload_secondary_in_icode[j]; 6592 6593 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) 6594 || (reload_in[j] != 0 && reload_out[j] != 0)) 6595 { 6596 enum reg_class new_class 6597 = SECONDARY_INPUT_RELOAD_CLASS (reload_reg_class[j], 6598 mode, real_oldequiv); 6599 6600 if (new_class == NO_REGS) 6601 second_reload_reg = 0; 6602 else 6603 { 6604 enum insn_code new_icode; 6605 enum machine_mode new_mode; 6606 6607 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], 6608 REGNO (second_reload_reg))) 6609 oldequiv = old, real_oldequiv = real_old; 6610 else 6611 { 6612 new_icode = reload_in_optab[(int) mode]; 6613 if (new_icode != CODE_FOR_nothing 6614 && ((insn_operand_predicate[(int) new_icode][0] 6615 && ! ((*insn_operand_predicate[(int) new_icode][0]) 6616 (reloadreg, mode))) 6617 || (insn_operand_predicate[(int) new_icode][1] 6618 && ! ((*insn_operand_predicate[(int) new_icode][1]) 6619 (real_oldequiv, mode))))) 6620 new_icode = CODE_FOR_nothing; 6621 6622 if (new_icode == CODE_FOR_nothing) 6623 new_mode = mode; 6624 else 6625 new_mode = insn_operand_mode[(int) new_icode][2]; 6626 6627 if (GET_MODE (second_reload_reg) != new_mode) 6628 { 6629 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), 6630 new_mode)) 6631 oldequiv = old, real_oldequiv = real_old; 6632 else 6633 second_reload_reg 6634 = gen_rtx_REG (new_mode, 6635 REGNO (second_reload_reg)); 6636 } 6637 } 6638 } 6639 } 6640 6641 /* If we still need a secondary reload register, check 6642 to see if it is being used as a scratch or intermediate 6643 register and generate code appropriately. If we need 6644 a scratch register, use REAL_OLDEQUIV since the form of 6645 the insn may depend on the actual address if it is 6646 a MEM. */ 6647 6648 if (second_reload_reg) 6649 { 6650 if (icode != CODE_FOR_nothing) 6651 { 6652 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, 6653 second_reload_reg)); 6654 special = 1; 6655 } 6656 else 6657 { 6658 /* See if we need a scratch register to load the 6659 intermediate register (a tertiary reload). */ 6660 enum insn_code tertiary_icode 6661 = reload_secondary_in_icode[secondary_reload]; 6662 6663 if (tertiary_icode != CODE_FOR_nothing) 6664 { 6665 rtx third_reload_reg 6666 = reload_reg_rtx[reload_secondary_in_reload[secondary_reload]]; 6667 6668 emit_insn ((GEN_FCN (tertiary_icode) 6669 (second_reload_reg, real_oldequiv, 6670 third_reload_reg))); 6671 } 6672 else 6673 gen_reload (second_reload_reg, oldequiv, 6674 reload_opnum[j], 6675 reload_when_needed[j]); 6676 6677 oldequiv = second_reload_reg; 6678 } 6679 } 6680 } 6681#endif 6682 6683 if (! special && ! rtx_equal_p (reloadreg, oldequiv)) 6684 gen_reload (reloadreg, oldequiv, reload_opnum[j], 6685 reload_when_needed[j]); 6686 6687#if defined(SECONDARY_INPUT_RELOAD_CLASS) && defined(PRESERVE_DEATH_INFO_REGNO_P) 6688 /* We may have to make a REG_DEAD note for the secondary reload 6689 register in the insns we just made. Find the last insn that 6690 mentioned the register. */ 6691 if (! special && second_reload_reg 6692 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reload_reg))) 6693 { 6694 rtx prev; 6695 6696 for (prev = get_last_insn (); prev; 6697 prev = PREV_INSN (prev)) 6698 if (GET_RTX_CLASS (GET_CODE (prev) == 'i') 6699 && reg_overlap_mentioned_for_reload_p (second_reload_reg, 6700 PATTERN (prev))) 6701 { 6702 REG_NOTES (prev) = gen_rtx_EXPR_LIST (REG_DEAD, 6703 second_reload_reg, 6704 REG_NOTES (prev)); 6705 break; 6706 } 6707 } 6708#endif 6709 } 6710 6711 this_reload_insn = get_last_insn (); 6712 /* End this sequence. */ 6713 *where = get_insns (); 6714 end_sequence (); 6715 } 6716 6717 /* When inheriting a wider reload, we have a MEM in reload_in[j], 6718 e.g. inheriting a SImode output reload for 6719 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ 6720 if (optimize && reload_inherited[j] && reload_in[j] 6721 && GET_CODE (reload_in[j]) == MEM 6722 && reload_spill_index[j] >= 0 6723 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) 6724 { 6725 expect_occurrences 6726 = count_occurrences (PATTERN (insn), reload_in[j]) == 1 ? 0 : -1; 6727 reload_in[j] 6728 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; 6729 } 6730 /* Add a note saying the input reload reg 6731 dies in this insn, if anyone cares. */ 6732#ifdef PRESERVE_DEATH_INFO_REGNO_P 6733 if (old != 0 6734 && reload_reg_rtx[j] != old 6735 && reload_reg_rtx[j] != 0 6736 && reload_out[j] == 0 6737 && ! reload_inherited[j] 6738 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j]))) 6739 { 6740 register rtx reloadreg = reload_reg_rtx[j]; 6741 6742#if 0 6743 /* We can't abort here because we need to support this for sched.c. 6744 It's not terrible to miss a REG_DEAD note, but we should try 6745 to figure out how to do this correctly. */ 6746 /* The code below is incorrect for address-only reloads. */ 6747 if (reload_when_needed[j] != RELOAD_OTHER 6748 && reload_when_needed[j] != RELOAD_FOR_INPUT) 6749 abort (); 6750#endif 6751 6752 /* Add a death note to this insn, for an input reload. */ 6753 6754 if ((reload_when_needed[j] == RELOAD_OTHER 6755 || reload_when_needed[j] == RELOAD_FOR_INPUT) 6756 && ! dead_or_set_p (insn, reloadreg)) 6757 REG_NOTES (insn) 6758 = gen_rtx_EXPR_LIST (REG_DEAD, 6759 reloadreg, REG_NOTES (insn)); 6760 } 6761 6762 /* When we inherit a reload, the last marked death of the reload reg 6763 may no longer really be a death. */ 6764 if (reload_reg_rtx[j] != 0 6765 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (reload_reg_rtx[j])) 6766 && reload_inherited[j]) 6767 { 6768 /* Handle inheriting an output reload. 6769 Remove the death note from the output reload insn. */ 6770 if (reload_spill_index[j] >= 0 6771 && GET_CODE (reload_in[j]) == REG 6772 && spill_reg_store[reload_spill_index[j]] != 0 6773 && find_regno_note (spill_reg_store[reload_spill_index[j]], 6774 REG_DEAD, REGNO (reload_reg_rtx[j]))) 6775 remove_death (REGNO (reload_reg_rtx[j]), 6776 spill_reg_store[reload_spill_index[j]]); 6777 /* Likewise for input reloads that were inherited. */ 6778 else if (reload_spill_index[j] >= 0 6779 && GET_CODE (reload_in[j]) == REG 6780 && spill_reg_store[reload_spill_index[j]] == 0 6781 && reload_inheritance_insn[j] != 0 6782 && find_regno_note (reload_inheritance_insn[j], REG_DEAD, 6783 REGNO (reload_reg_rtx[j]))) 6784 remove_death (REGNO (reload_reg_rtx[j]), 6785 reload_inheritance_insn[j]); 6786 else 6787 { 6788 rtx prev; 6789 6790 /* We got this register from find_equiv_reg. 6791 Search back for its last death note and get rid of it. 6792 But don't search back too far. 6793 Don't go past a place where this reg is set, 6794 since a death note before that remains valid. */ 6795 for (prev = PREV_INSN (insn); 6796 prev && GET_CODE (prev) != CODE_LABEL; 6797 prev = PREV_INSN (prev)) 6798 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i' 6799 && dead_or_set_p (prev, reload_reg_rtx[j])) 6800 { 6801 if (find_regno_note (prev, REG_DEAD, 6802 REGNO (reload_reg_rtx[j]))) 6803 remove_death (REGNO (reload_reg_rtx[j]), prev); 6804 break; 6805 } 6806 } 6807 } 6808 6809 /* We might have used find_equiv_reg above to choose an alternate 6810 place from which to reload. If so, and it died, we need to remove 6811 that death and move it to one of the insns we just made. */ 6812 6813 if (oldequiv_reg != 0 6814 && PRESERVE_DEATH_INFO_REGNO_P (true_regnum (oldequiv_reg))) 6815 { 6816 rtx prev, prev1; 6817 6818 for (prev = PREV_INSN (insn); prev && GET_CODE (prev) != CODE_LABEL; 6819 prev = PREV_INSN (prev)) 6820 if (GET_RTX_CLASS (GET_CODE (prev)) == 'i' 6821 && dead_or_set_p (prev, oldequiv_reg)) 6822 { 6823 if (find_regno_note (prev, REG_DEAD, REGNO (oldequiv_reg))) 6824 { 6825 for (prev1 = this_reload_insn; 6826 prev1; prev1 = PREV_INSN (prev1)) 6827 if (GET_RTX_CLASS (GET_CODE (prev1) == 'i') 6828 && reg_overlap_mentioned_for_reload_p (oldequiv_reg, 6829 PATTERN (prev1))) 6830 { 6831 REG_NOTES (prev1) = gen_rtx_EXPR_LIST (REG_DEAD, 6832 oldequiv_reg, 6833 REG_NOTES (prev1)); 6834 break; 6835 } 6836 remove_death (REGNO (oldequiv_reg), prev); 6837 } 6838 break; 6839 } 6840 } 6841#endif 6842 6843 /* If we are reloading a register that was recently stored in with an 6844 output-reload, see if we can prove there was 6845 actually no need to store the old value in it. */ 6846 6847 if (optimize && reload_inherited[j] && reload_spill_index[j] >= 0 6848 && reload_in[j] != 0 6849 && GET_CODE (reload_in[j]) == REG 6850#if 0 6851 /* There doesn't seem to be any reason to restrict this to pseudos 6852 and doing so loses in the case where we are copying from a 6853 register of the wrong class. */ 6854 && REGNO (reload_in[j]) >= FIRST_PSEUDO_REGISTER 6855#endif 6856 && spill_reg_store[reload_spill_index[j]] != 0 6857 /* This is unsafe if some other reload uses the same reg first. */ 6858 && reload_reg_free_before_p (reload_spill_index[j], 6859 reload_opnum[j], reload_when_needed[j]) 6860 && dead_or_set_p (insn, reload_in[j]) 6861 /* This is unsafe if operand occurs more than once in current 6862 insn. Perhaps some occurrences weren't reloaded. */ 6863 && (count_occurrences (PATTERN (insn), reload_in[j]) 6864 == expect_occurrences)) 6865 delete_output_reload (insn, j, 6866 spill_reg_store[reload_spill_index[j]]); 6867 6868 /* Input-reloading is done. Now do output-reloading, 6869 storing the value from the reload-register after the main insn 6870 if reload_out[j] is nonzero. 6871 6872 ??? At some point we need to support handling output reloads of 6873 JUMP_INSNs or insns that set cc0. */ 6874 old = reload_out[j]; 6875 if (old != 0 6876 && reload_reg_rtx[j] != old 6877 && reload_reg_rtx[j] != 0) 6878 { 6879 register rtx reloadreg = reload_reg_rtx[j]; 6880#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 6881 register rtx second_reloadreg = 0; 6882#endif 6883 rtx note, p; 6884 enum machine_mode mode; 6885 int special = 0; 6886 6887 /* An output operand that dies right away does need a reload, 6888 but need not be copied from it. Show the new location in the 6889 REG_UNUSED note. */ 6890 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) 6891 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) 6892 { 6893 XEXP (note, 0) = reload_reg_rtx[j]; 6894 continue; 6895 } 6896 /* Likewise for a SUBREG of an operand that dies. */ 6897 else if (GET_CODE (old) == SUBREG 6898 && GET_CODE (SUBREG_REG (old)) == REG 6899 && 0 != (note = find_reg_note (insn, REG_UNUSED, 6900 SUBREG_REG (old)))) 6901 { 6902 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), 6903 reload_reg_rtx[j]); 6904 continue; 6905 } 6906 else if (GET_CODE (old) == SCRATCH) 6907 /* If we aren't optimizing, there won't be a REG_UNUSED note, 6908 but we don't want to make an output reload. */ 6909 continue; 6910 6911#if 0 6912 /* Strip off of OLD any size-increasing SUBREGs such as 6913 (SUBREG:SI foo:QI 0). */ 6914 6915 while (GET_CODE (old) == SUBREG && SUBREG_WORD (old) == 0 6916 && (GET_MODE_SIZE (GET_MODE (old)) 6917 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (old))))) 6918 old = SUBREG_REG (old); 6919#endif 6920 6921 /* If is a JUMP_INSN, we can't support output reloads yet. */ 6922 if (GET_CODE (insn) == JUMP_INSN) 6923 abort (); 6924 6925 if (reload_when_needed[j] == RELOAD_OTHER) 6926 start_sequence (); 6927 else 6928 push_to_sequence (output_reload_insns[reload_opnum[j]]); 6929 6930 /* Determine the mode to reload in. 6931 See comments above (for input reloading). */ 6932 6933 mode = GET_MODE (old); 6934 if (mode == VOIDmode) 6935 { 6936 /* VOIDmode should never happen for an output. */ 6937 if (asm_noperands (PATTERN (insn)) < 0) 6938 /* It's the compiler's fault. */ 6939 fatal_insn ("VOIDmode on an output", insn); 6940 error_for_asm (insn, "output operand is constant in `asm'"); 6941 /* Prevent crash--use something we know is valid. */ 6942 mode = word_mode; 6943 old = gen_rtx_REG (mode, REGNO (reloadreg)); 6944 } 6945 6946 if (GET_MODE (reloadreg) != mode) 6947 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); 6948 6949#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 6950 6951 /* If we need two reload regs, set RELOADREG to the intermediate 6952 one, since it will be stored into OLD. We might need a secondary 6953 register only for an input reload, so check again here. */ 6954 6955 if (reload_secondary_out_reload[j] >= 0) 6956 { 6957 rtx real_old = old; 6958 6959 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER 6960 && reg_equiv_mem[REGNO (old)] != 0) 6961 real_old = reg_equiv_mem[REGNO (old)]; 6962 6963 if((SECONDARY_OUTPUT_RELOAD_CLASS (reload_reg_class[j], 6964 mode, real_old) 6965 != NO_REGS)) 6966 { 6967 second_reloadreg = reloadreg; 6968 reloadreg = reload_reg_rtx[reload_secondary_out_reload[j]]; 6969 6970 /* See if RELOADREG is to be used as a scratch register 6971 or as an intermediate register. */ 6972 if (reload_secondary_out_icode[j] != CODE_FOR_nothing) 6973 { 6974 emit_insn ((GEN_FCN (reload_secondary_out_icode[j]) 6975 (real_old, second_reloadreg, reloadreg))); 6976 special = 1; 6977 } 6978 else 6979 { 6980 /* See if we need both a scratch and intermediate reload 6981 register. */ 6982 6983 int secondary_reload = reload_secondary_out_reload[j]; 6984 enum insn_code tertiary_icode 6985 = reload_secondary_out_icode[secondary_reload]; 6986 6987 if (GET_MODE (reloadreg) != mode) 6988 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); 6989 6990 if (tertiary_icode != CODE_FOR_nothing) 6991 { 6992 rtx third_reloadreg 6993 = reload_reg_rtx[reload_secondary_out_reload[secondary_reload]]; 6994 rtx tem; 6995 6996 /* Copy primary reload reg to secondary reload reg. 6997 (Note that these have been swapped above, then 6998 secondary reload reg to OLD using our insn. */ 6999 7000 /* If REAL_OLD is a paradoxical SUBREG, remove it 7001 and try to put the opposite SUBREG on 7002 RELOADREG. */ 7003 if (GET_CODE (real_old) == SUBREG 7004 && (GET_MODE_SIZE (GET_MODE (real_old)) 7005 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) 7006 && 0 != (tem = gen_lowpart_common 7007 (GET_MODE (SUBREG_REG (real_old)), 7008 reloadreg))) 7009 real_old = SUBREG_REG (real_old), reloadreg = tem; 7010 7011 gen_reload (reloadreg, second_reloadreg, 7012 reload_opnum[j], reload_when_needed[j]); 7013 emit_insn ((GEN_FCN (tertiary_icode) 7014 (real_old, reloadreg, third_reloadreg))); 7015 special = 1; 7016 } 7017 7018 else 7019 /* Copy between the reload regs here and then to 7020 OUT later. */ 7021 7022 gen_reload (reloadreg, second_reloadreg, 7023 reload_opnum[j], reload_when_needed[j]); 7024 } 7025 } 7026 } 7027#endif 7028 7029 /* Output the last reload insn. */ 7030 if (! special) 7031 { 7032 rtx set; 7033 7034 /* Don't output the last reload if OLD is not the dest of 7035 INSN and is in the src and is clobbered by INSN. */ 7036 if (! flag_expensive_optimizations 7037 || GET_CODE (old) != REG 7038 || !(set = single_set (insn)) 7039 || rtx_equal_p (old, SET_DEST (set)) 7040 || !reg_mentioned_p (old, SET_SRC (set)) 7041 || !regno_clobbered_p (REGNO (old), insn)) 7042 gen_reload (old, reloadreg, reload_opnum[j], 7043 reload_when_needed[j]); 7044 } 7045 7046#ifdef PRESERVE_DEATH_INFO_REGNO_P 7047 /* If final will look at death notes for this reg, 7048 put one on the last output-reload insn to use it. Similarly 7049 for any secondary register. */ 7050 if (PRESERVE_DEATH_INFO_REGNO_P (REGNO (reloadreg))) 7051 for (p = get_last_insn (); p; p = PREV_INSN (p)) 7052 if (GET_RTX_CLASS (GET_CODE (p)) == 'i' 7053 && reg_overlap_mentioned_for_reload_p (reloadreg, 7054 PATTERN (p))) 7055 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_DEAD, 7056 reloadreg, REG_NOTES (p)); 7057 7058#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 7059 if (! special && second_reloadreg 7060 && PRESERVE_DEATH_INFO_REGNO_P (REGNO (second_reloadreg))) 7061 for (p = get_last_insn (); p; p = PREV_INSN (p)) 7062 if (GET_RTX_CLASS (GET_CODE (p)) == 'i' 7063 && reg_overlap_mentioned_for_reload_p (second_reloadreg, 7064 PATTERN (p))) 7065 REG_NOTES (p) = gen_rtx_EXPR_LIST (REG_DEAD, 7066 second_reloadreg, 7067 REG_NOTES (p)); 7068#endif 7069#endif 7070 /* Look at all insns we emitted, just to be safe. */ 7071 for (p = get_insns (); p; p = NEXT_INSN (p)) 7072 if (GET_RTX_CLASS (GET_CODE (p)) == 'i') 7073 { 7074 rtx pat = PATTERN (p); 7075 7076 /* If this output reload doesn't come from a spill reg, 7077 clear any memory of reloaded copies of the pseudo reg. 7078 If this output reload comes from a spill reg, 7079 reg_has_output_reload will make this do nothing. */ 7080 note_stores (pat, forget_old_reloads_1); 7081 7082 if (reg_mentioned_p (reload_reg_rtx[j], pat)) 7083 { 7084 if (reload_spill_index[j] < 0 7085 && GET_CODE (pat) == SET 7086 && SET_SRC (pat) == reload_reg_rtx[j]) 7087 { 7088 int src = REGNO (SET_SRC (pat)); 7089 7090 reload_spill_index[j] = src; 7091 SET_HARD_REG_BIT (reg_is_output_reload, src); 7092 if (find_regno_note (insn, REG_DEAD, src)) 7093 SET_HARD_REG_BIT (reg_reloaded_died, src); 7094 } 7095 if (reload_spill_index[j] >= 0) 7096 { 7097 int s = reload_secondary_out_reload[j]; 7098 rtx set = single_set (p); 7099 /* If this reload copies only to the secondary reload 7100 register, the secondary reload does the actual 7101 store. */ 7102 if (s >= 0 && set == NULL_RTX) 7103 ; /* We can't tell what function the secondary reload 7104 has and where the actual store to the pseudo is 7105 made; leave new_spill_reg_store alone. */ 7106 else if (s >= 0 7107 && SET_SRC (set) == reload_reg_rtx[j] 7108 && SET_DEST (set) == reload_reg_rtx[s]) 7109 { 7110 /* Usually the next instruction will be the 7111 secondary reload insn; if we can confirm 7112 that it is, setting new_spill_reg_store to 7113 that insn will allow an extra optimization. */ 7114 rtx s_reg = reload_reg_rtx[s]; 7115 rtx next = NEXT_INSN (p); 7116 reload_out[s] = reload_out[j]; 7117 set = single_set (next); 7118 if (set && SET_SRC (set) == s_reg 7119 && ! new_spill_reg_store[REGNO (s_reg)]) 7120 new_spill_reg_store[REGNO (s_reg)] = next; 7121 } 7122 else 7123 new_spill_reg_store[reload_spill_index[j]] = p; 7124 } 7125 } 7126 } 7127 7128 if (reload_when_needed[j] == RELOAD_OTHER) 7129 { 7130 emit_insns (other_output_reload_insns[reload_opnum[j]]); 7131 other_output_reload_insns[reload_opnum[j]] = get_insns (); 7132 } 7133 else 7134 output_reload_insns[reload_opnum[j]] = get_insns (); 7135 7136 end_sequence (); 7137 } 7138 } 7139 7140 /* Now write all the insns we made for reloads in the order expected by 7141 the allocation functions. Prior to the insn being reloaded, we write 7142 the following reloads: 7143 7144 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. 7145 7146 RELOAD_OTHER reloads. 7147 7148 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed 7149 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the 7150 RELOAD_FOR_INPUT reload for the operand. 7151 7152 RELOAD_FOR_OPADDR_ADDRS reloads. 7153 7154 RELOAD_FOR_OPERAND_ADDRESS reloads. 7155 7156 After the insn being reloaded, we write the following: 7157 7158 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed 7159 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the 7160 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output 7161 reloads for the operand. The RELOAD_OTHER output reloads are 7162 output in descending order by reload number. */ 7163 7164 emit_insns_before (other_input_address_reload_insns, before_insn); 7165 emit_insns_before (other_input_reload_insns, before_insn); 7166 7167 for (j = 0; j < reload_n_operands; j++) 7168 { 7169 emit_insns_before (inpaddr_address_reload_insns[j], before_insn); 7170 emit_insns_before (input_address_reload_insns[j], before_insn); 7171 emit_insns_before (input_reload_insns[j], before_insn); 7172 } 7173 7174 emit_insns_before (other_operand_reload_insns, before_insn); 7175 emit_insns_before (operand_reload_insns, before_insn); 7176 7177 for (j = 0; j < reload_n_operands; j++) 7178 { 7179 emit_insns_before (outaddr_address_reload_insns[j], following_insn); 7180 emit_insns_before (output_address_reload_insns[j], following_insn); 7181 emit_insns_before (output_reload_insns[j], following_insn); 7182 emit_insns_before (other_output_reload_insns[j], following_insn); 7183 } 7184 7185 /* Move death notes from INSN 7186 to output-operand-address and output reload insns. */ 7187#ifdef PRESERVE_DEATH_INFO_REGNO_P 7188 { 7189 rtx insn1; 7190 /* Loop over those insns, last ones first. */ 7191 for (insn1 = PREV_INSN (following_insn); insn1 != insn; 7192 insn1 = PREV_INSN (insn1)) 7193 if (GET_CODE (insn1) == INSN && GET_CODE (PATTERN (insn1)) == SET) 7194 { 7195 rtx source = SET_SRC (PATTERN (insn1)); 7196 rtx dest = SET_DEST (PATTERN (insn1)); 7197 7198 /* The note we will examine next. */ 7199 rtx reg_notes = REG_NOTES (insn); 7200 /* The place that pointed to this note. */ 7201 rtx *prev_reg_note = ®_NOTES (insn); 7202 7203 /* If the note is for something used in the source of this 7204 reload insn, or in the output address, move the note. */ 7205 while (reg_notes) 7206 { 7207 rtx next_reg_notes = XEXP (reg_notes, 1); 7208 if (REG_NOTE_KIND (reg_notes) == REG_DEAD 7209 && GET_CODE (XEXP (reg_notes, 0)) == REG 7210 && ((GET_CODE (dest) != REG 7211 && reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0), 7212 dest)) 7213 || reg_overlap_mentioned_for_reload_p (XEXP (reg_notes, 0), 7214 source))) 7215 { 7216 *prev_reg_note = next_reg_notes; 7217 XEXP (reg_notes, 1) = REG_NOTES (insn1); 7218 REG_NOTES (insn1) = reg_notes; 7219 } 7220 else 7221 prev_reg_note = &XEXP (reg_notes, 1); 7222 7223 reg_notes = next_reg_notes; 7224 } 7225 } 7226 } 7227#endif 7228 7229 /* For all the spill regs newly reloaded in this instruction, 7230 record what they were reloaded from, so subsequent instructions 7231 can inherit the reloads. 7232 7233 Update spill_reg_store for the reloads of this insn. 7234 Copy the elements that were updated in the loop above. */ 7235 7236 for (j = 0; j < n_reloads; j++) 7237 { 7238 register int r = reload_order[j]; 7239 register int i = reload_spill_index[r]; 7240 7241 /* I is nonneg if this reload used a register. 7242 If reload_reg_rtx[r] is 0, this is an optional reload 7243 that we opted to ignore. */ 7244 7245 if (i >= 0 && reload_reg_rtx[r] != 0) 7246 { 7247 int nr 7248 = HARD_REGNO_NREGS (i, GET_MODE (reload_reg_rtx[r])); 7249 int k; 7250 int part_reaches_end = 0; 7251 int all_reaches_end = 1; 7252 7253 /* For a multi register reload, we need to check if all or part 7254 of the value lives to the end. */ 7255 for (k = 0; k < nr; k++) 7256 { 7257 if (reload_reg_reaches_end_p (i + k, reload_opnum[r], 7258 reload_when_needed[r])) 7259 part_reaches_end = 1; 7260 else 7261 all_reaches_end = 0; 7262 } 7263 7264 /* Ignore reloads that don't reach the end of the insn in 7265 entirety. */ 7266 if (all_reaches_end) 7267 { 7268 /* First, clear out memory of what used to be in this spill reg. 7269 If consecutive registers are used, clear them all. */ 7270 7271 for (k = 0; k < nr; k++) 7272 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); 7273 7274 /* Maybe the spill reg contains a copy of reload_out. */ 7275 if (reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG) 7276 { 7277 register int nregno = REGNO (reload_out[r]); 7278 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 7279 : HARD_REGNO_NREGS (nregno, 7280 GET_MODE (reload_reg_rtx[r]))); 7281 7282 spill_reg_store[i] = new_spill_reg_store[i]; 7283 reg_last_reload_reg[nregno] = reload_reg_rtx[r]; 7284 7285 /* If NREGNO is a hard register, it may occupy more than 7286 one register. If it does, say what is in the 7287 rest of the registers assuming that both registers 7288 agree on how many words the object takes. If not, 7289 invalidate the subsequent registers. */ 7290 7291 if (nregno < FIRST_PSEUDO_REGISTER) 7292 for (k = 1; k < nnr; k++) 7293 reg_last_reload_reg[nregno + k] 7294 = (nr == nnr 7295 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k], 7296 REGNO (reload_reg_rtx[r]) + k) 7297 : 0); 7298 7299 /* Now do the inverse operation. */ 7300 for (k = 0; k < nr; k++) 7301 { 7302 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); 7303 reg_reloaded_contents[i + k] 7304 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr 7305 ? nregno 7306 : nregno + k); 7307 reg_reloaded_insn[i + k] = insn; 7308 SET_HARD_REG_BIT (reg_reloaded_valid, i + k); 7309 } 7310 } 7311 7312 /* Maybe the spill reg contains a copy of reload_in. Only do 7313 something if there will not be an output reload for 7314 the register being reloaded. */ 7315 else if (reload_out[r] == 0 7316 && reload_in[r] != 0 7317 && spill_reg_order[i] >= 0 7318 && ((GET_CODE (reload_in[r]) == REG 7319 && ! reg_has_output_reload[REGNO (reload_in[r])]) 7320 || (GET_CODE (reload_in_reg[r]) == REG 7321 && ! reg_has_output_reload[REGNO (reload_in_reg[r])]))) 7322 { 7323 register int nregno; 7324 int nnr; 7325 7326 if (GET_CODE (reload_in[r]) == REG) 7327 nregno = REGNO (reload_in[r]); 7328 else 7329 nregno = REGNO (reload_in_reg[r]); 7330 7331 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 7332 : HARD_REGNO_NREGS (nregno, 7333 GET_MODE (reload_reg_rtx[r]))); 7334 7335 reg_last_reload_reg[nregno] = reload_reg_rtx[r]; 7336 7337 if (nregno < FIRST_PSEUDO_REGISTER) 7338 for (k = 1; k < nnr; k++) 7339 reg_last_reload_reg[nregno + k] 7340 = (nr == nnr 7341 ? gen_rtx_REG (reg_raw_mode[REGNO (reload_reg_rtx[r]) + k], 7342 REGNO (reload_reg_rtx[r]) + k) 7343 : 0); 7344 7345 /* Unless we inherited this reload, show we haven't 7346 recently done a store. */ 7347 if (! reload_inherited[r]) 7348 spill_reg_store[i] = 0; 7349 7350 for (k = 0; k < nr; k++) 7351 { 7352 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); 7353 reg_reloaded_contents[i + k] 7354 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr 7355 ? nregno 7356 : nregno + k); 7357 reg_reloaded_insn[i + k] = insn; 7358 SET_HARD_REG_BIT (reg_reloaded_valid, i + k); 7359 } 7360 } 7361 } 7362 7363 /* However, if part of the reload reaches the end, then we must 7364 invalidate the old info for the part that survives to the end. */ 7365 else if (part_reaches_end) 7366 { 7367 for (k = 0; k < nr; k++) 7368 if (reload_reg_reaches_end_p (i + k, 7369 reload_opnum[r], 7370 reload_when_needed[r])) 7371 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); 7372 } 7373 } 7374 7375 /* The following if-statement was #if 0'd in 1.34 (or before...). 7376 It's reenabled in 1.35 because supposedly nothing else 7377 deals with this problem. */ 7378 7379 /* If a register gets output-reloaded from a non-spill register, 7380 that invalidates any previous reloaded copy of it. 7381 But forget_old_reloads_1 won't get to see it, because 7382 it thinks only about the original insn. So invalidate it here. */ 7383 if (i < 0 && reload_out[r] != 0 && GET_CODE (reload_out[r]) == REG) 7384 { 7385 register int nregno = REGNO (reload_out[r]); 7386 if (nregno >= FIRST_PSEUDO_REGISTER) 7387 reg_last_reload_reg[nregno] = 0; 7388 else 7389 { 7390 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (reload_out[r])); 7391 7392 while (num_regs-- > 0) 7393 reg_last_reload_reg[nregno + num_regs] = 0; 7394 } 7395 } 7396 } 7397 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); 7398} 7399 7400/* Emit code to perform a reload from IN (which may be a reload register) to 7401 OUT (which may also be a reload register). IN or OUT is from operand 7402 OPNUM with reload type TYPE. 7403 7404 Returns first insn emitted. */ 7405 7406rtx 7407gen_reload (out, in, opnum, type) 7408 rtx out; 7409 rtx in; 7410 int opnum; 7411 enum reload_type type; 7412{ 7413 rtx last = get_last_insn (); 7414 rtx tem; 7415 7416 /* If IN is a paradoxical SUBREG, remove it and try to put the 7417 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ 7418 if (GET_CODE (in) == SUBREG 7419 && (GET_MODE_SIZE (GET_MODE (in)) 7420 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) 7421 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) 7422 in = SUBREG_REG (in), out = tem; 7423 else if (GET_CODE (out) == SUBREG 7424 && (GET_MODE_SIZE (GET_MODE (out)) 7425 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) 7426 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) 7427 out = SUBREG_REG (out), in = tem; 7428 7429 /* How to do this reload can get quite tricky. Normally, we are being 7430 asked to reload a simple operand, such as a MEM, a constant, or a pseudo 7431 register that didn't get a hard register. In that case we can just 7432 call emit_move_insn. 7433 7434 We can also be asked to reload a PLUS that adds a register or a MEM to 7435 another register, constant or MEM. This can occur during frame pointer 7436 elimination and while reloading addresses. This case is handled by 7437 trying to emit a single insn to perform the add. If it is not valid, 7438 we use a two insn sequence. 7439 7440 Finally, we could be called to handle an 'o' constraint by putting 7441 an address into a register. In that case, we first try to do this 7442 with a named pattern of "reload_load_address". If no such pattern 7443 exists, we just emit a SET insn and hope for the best (it will normally 7444 be valid on machines that use 'o'). 7445 7446 This entire process is made complex because reload will never 7447 process the insns we generate here and so we must ensure that 7448 they will fit their constraints and also by the fact that parts of 7449 IN might be being reloaded separately and replaced with spill registers. 7450 Because of this, we are, in some sense, just guessing the right approach 7451 here. The one listed above seems to work. 7452 7453 ??? At some point, this whole thing needs to be rethought. */ 7454 7455 if (GET_CODE (in) == PLUS 7456 && (GET_CODE (XEXP (in, 0)) == REG 7457 || GET_CODE (XEXP (in, 0)) == SUBREG 7458 || GET_CODE (XEXP (in, 0)) == MEM) 7459 && (GET_CODE (XEXP (in, 1)) == REG 7460 || GET_CODE (XEXP (in, 1)) == SUBREG 7461 || CONSTANT_P (XEXP (in, 1)) 7462 || GET_CODE (XEXP (in, 1)) == MEM)) 7463 { 7464 /* We need to compute the sum of a register or a MEM and another 7465 register, constant, or MEM, and put it into the reload 7466 register. The best possible way of doing this is if the machine 7467 has a three-operand ADD insn that accepts the required operands. 7468 7469 The simplest approach is to try to generate such an insn and see if it 7470 is recognized and matches its constraints. If so, it can be used. 7471 7472 It might be better not to actually emit the insn unless it is valid, 7473 but we need to pass the insn as an operand to `recog' and 7474 `insn_extract' and it is simpler to emit and then delete the insn if 7475 not valid than to dummy things up. */ 7476 7477 rtx op0, op1, tem, insn; 7478 int code; 7479 7480 op0 = find_replacement (&XEXP (in, 0)); 7481 op1 = find_replacement (&XEXP (in, 1)); 7482 7483 /* Since constraint checking is strict, commutativity won't be 7484 checked, so we need to do that here to avoid spurious failure 7485 if the add instruction is two-address and the second operand 7486 of the add is the same as the reload reg, which is frequently 7487 the case. If the insn would be A = B + A, rearrange it so 7488 it will be A = A + B as constrain_operands expects. */ 7489 7490 if (GET_CODE (XEXP (in, 1)) == REG 7491 && REGNO (out) == REGNO (XEXP (in, 1))) 7492 tem = op0, op0 = op1, op1 = tem; 7493 7494 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) 7495 in = gen_rtx_PLUS (GET_MODE (in), op0, op1); 7496 7497 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); 7498 code = recog_memoized (insn); 7499 7500 if (code >= 0) 7501 { 7502 insn_extract (insn); 7503 /* We want constrain operands to treat this insn strictly in 7504 its validity determination, i.e., the way it would after reload 7505 has completed. */ 7506 if (constrain_operands (code, 1)) 7507 return insn; 7508 } 7509 7510 delete_insns_since (last); 7511 7512 /* If that failed, we must use a conservative two-insn sequence. 7513 use move to copy constant, MEM, or pseudo register to the reload 7514 register since "move" will be able to handle an arbitrary operand, 7515 unlike add which can't, in general. Then add the registers. 7516 7517 If there is another way to do this for a specific machine, a 7518 DEFINE_PEEPHOLE should be specified that recognizes the sequence 7519 we emit below. */ 7520 7521 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG 7522 || (GET_CODE (op1) == REG 7523 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)) 7524 tem = op0, op0 = op1, op1 = tem; 7525 7526 gen_reload (out, op0, opnum, type); 7527 7528 /* If OP0 and OP1 are the same, we can use OUT for OP1. 7529 This fixes a problem on the 32K where the stack pointer cannot 7530 be used as an operand of an add insn. */ 7531 7532 if (rtx_equal_p (op0, op1)) 7533 op1 = out; 7534 7535 insn = emit_insn (gen_add2_insn (out, op1)); 7536 7537 /* If that failed, copy the address register to the reload register. 7538 Then add the constant to the reload register. */ 7539 7540 code = recog_memoized (insn); 7541 7542 if (code >= 0) 7543 { 7544 insn_extract (insn); 7545 /* We want constrain operands to treat this insn strictly in 7546 its validity determination, i.e., the way it would after reload 7547 has completed. */ 7548 if (constrain_operands (code, 1)) 7549 { 7550 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ 7551 REG_NOTES (insn) 7552 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); 7553 return insn; 7554 } 7555 } 7556 7557 delete_insns_since (last); 7558 7559 gen_reload (out, op1, opnum, type); 7560 insn = emit_insn (gen_add2_insn (out, op0)); 7561 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); 7562 } 7563 7564#ifdef SECONDARY_MEMORY_NEEDED 7565 /* If we need a memory location to do the move, do it that way. */ 7566 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER 7567 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER 7568 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)), 7569 REGNO_REG_CLASS (REGNO (out)), 7570 GET_MODE (out))) 7571 { 7572 /* Get the memory to use and rewrite both registers to its mode. */ 7573 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); 7574 7575 if (GET_MODE (loc) != GET_MODE (out)) 7576 out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); 7577 7578 if (GET_MODE (loc) != GET_MODE (in)) 7579 in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); 7580 7581 gen_reload (loc, in, opnum, type); 7582 gen_reload (out, loc, opnum, type); 7583 } 7584#endif 7585 7586 /* If IN is a simple operand, use gen_move_insn. */ 7587 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) 7588 emit_insn (gen_move_insn (out, in)); 7589 7590#ifdef HAVE_reload_load_address 7591 else if (HAVE_reload_load_address) 7592 emit_insn (gen_reload_load_address (out, in)); 7593#endif 7594 7595 /* Otherwise, just write (set OUT IN) and hope for the best. */ 7596 else 7597 emit_insn (gen_rtx_SET (VOIDmode, out, in)); 7598 7599 /* Return the first insn emitted. 7600 We can not just return get_last_insn, because there may have 7601 been multiple instructions emitted. Also note that gen_move_insn may 7602 emit more than one insn itself, so we can not assume that there is one 7603 insn emitted per emit_insn_before call. */ 7604 7605 return last ? NEXT_INSN (last) : get_insns (); 7606} 7607 7608/* Delete a previously made output-reload 7609 whose result we now believe is not needed. 7610 First we double-check. 7611 7612 INSN is the insn now being processed. 7613 OUTPUT_RELOAD_INSN is the insn of the output reload. 7614 J is the reload-number for this insn. */ 7615 7616static void 7617delete_output_reload (insn, j, output_reload_insn) 7618 rtx insn; 7619 int j; 7620 rtx output_reload_insn; 7621{ 7622 register rtx i1; 7623 7624 /* Get the raw pseudo-register referred to. */ 7625 7626 rtx reg = reload_in[j]; 7627 while (GET_CODE (reg) == SUBREG) 7628 reg = SUBREG_REG (reg); 7629 7630 /* If the pseudo-reg we are reloading is no longer referenced 7631 anywhere between the store into it and here, 7632 and no jumps or labels intervene, then the value can get 7633 here through the reload reg alone. 7634 Otherwise, give up--return. */ 7635 for (i1 = NEXT_INSN (output_reload_insn); 7636 i1 != insn; i1 = NEXT_INSN (i1)) 7637 { 7638 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) 7639 return; 7640 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) 7641 && reg_mentioned_p (reg, PATTERN (i1))) 7642 { 7643 /* If this is just a single USE with an REG_EQUAL note in front 7644 of INSN, this is no problem, because this mentions just the 7645 address that we are using here. 7646 But if there is more than one such USE, the insn might use 7647 the operand directly, or another reload might do that. 7648 This is analogous to the count_occurences check in the callers. */ 7649 int num_occurences = 0; 7650 7651 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE 7652 && find_reg_note (i1, REG_EQUAL, NULL_RTX)) 7653 { 7654 num_occurences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; 7655 i1 = NEXT_INSN (i1); 7656 } 7657 if (num_occurences == 1 && i1 == insn) 7658 break; 7659 return; 7660 } 7661 } 7662 7663 /* The caller has already checked that REG dies or is set in INSN. 7664 It has also checked that we are optimizing, and thus some inaccurancies 7665 in the debugging information are acceptable. 7666 So we could just delete output_reload_insn. 7667 But in some cases we can improve the debugging information without 7668 sacrificing optimization - maybe even improving the code: 7669 See if the pseudo reg has been completely replaced 7670 with reload regs. If so, delete the store insn 7671 and forget we had a stack slot for the pseudo. */ 7672 if (reload_out[j] != reload_in[j] 7673 && REG_N_DEATHS (REGNO (reg)) == 1 7674 && REG_BASIC_BLOCK (REGNO (reg)) >= 0 7675 && find_regno_note (insn, REG_DEAD, REGNO (reg))) 7676 { 7677 rtx i2; 7678 7679 /* We know that it was used only between here 7680 and the beginning of the current basic block. 7681 (We also know that the last use before INSN was 7682 the output reload we are thinking of deleting, but never mind that.) 7683 Search that range; see if any ref remains. */ 7684 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) 7685 { 7686 rtx set = single_set (i2); 7687 7688 /* Uses which just store in the pseudo don't count, 7689 since if they are the only uses, they are dead. */ 7690 if (set != 0 && SET_DEST (set) == reg) 7691 continue; 7692 if (GET_CODE (i2) == CODE_LABEL 7693 || GET_CODE (i2) == JUMP_INSN) 7694 break; 7695 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) 7696 && reg_mentioned_p (reg, PATTERN (i2))) 7697 { 7698 /* Some other ref remains; just delete the output reload we 7699 know to be dead. */ 7700 delete_insn (output_reload_insn); 7701 return; 7702 } 7703 } 7704 7705 /* Delete the now-dead stores into this pseudo. */ 7706 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) 7707 { 7708 rtx set = single_set (i2); 7709 7710 if (set != 0 && SET_DEST (set) == reg) 7711 { 7712 /* This might be a basic block head, 7713 thus don't use delete_insn. */ 7714 PUT_CODE (i2, NOTE); 7715 NOTE_SOURCE_FILE (i2) = 0; 7716 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED; 7717 } 7718 if (GET_CODE (i2) == CODE_LABEL 7719 || GET_CODE (i2) == JUMP_INSN) 7720 break; 7721 } 7722 7723 /* For the debugging info, 7724 say the pseudo lives in this reload reg. */ 7725 reg_renumber[REGNO (reg)] = REGNO (reload_reg_rtx[j]); 7726 alter_reg (REGNO (reg), -1); 7727 } 7728 delete_insn (output_reload_insn); 7729 7730} 7731 7732/* Output reload-insns to reload VALUE into RELOADREG. 7733 VALUE is an autoincrement or autodecrement RTX whose operand 7734 is a register or memory location; 7735 so reloading involves incrementing that location. 7736 7737 INC_AMOUNT is the number to increment or decrement by (always positive). 7738 This cannot be deduced from VALUE. */ 7739 7740static void 7741inc_for_reload (reloadreg, value, inc_amount) 7742 rtx reloadreg; 7743 rtx value; 7744 int inc_amount; 7745{ 7746 /* REG or MEM to be copied and incremented. */ 7747 rtx incloc = XEXP (value, 0); 7748 /* Nonzero if increment after copying. */ 7749 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); 7750 rtx last; 7751 rtx inc; 7752 rtx add_insn; 7753 int code; 7754 7755 /* No hard register is equivalent to this register after 7756 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero, 7757 we could inc/dec that register as well (maybe even using it for 7758 the source), but I'm not sure it's worth worrying about. */ 7759 if (GET_CODE (incloc) == REG) 7760 reg_last_reload_reg[REGNO (incloc)] = 0; 7761 7762 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) 7763 inc_amount = - inc_amount; 7764 7765 inc = GEN_INT (inc_amount); 7766 7767 /* If this is post-increment, first copy the location to the reload reg. */ 7768 if (post) 7769 emit_insn (gen_move_insn (reloadreg, incloc)); 7770 7771 /* See if we can directly increment INCLOC. Use a method similar to that 7772 in gen_reload. */ 7773 7774 last = get_last_insn (); 7775 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, 7776 gen_rtx_PLUS (GET_MODE (incloc), 7777 incloc, inc))); 7778 7779 code = recog_memoized (add_insn); 7780 if (code >= 0) 7781 { 7782 insn_extract (add_insn); 7783 if (constrain_operands (code, 1)) 7784 { 7785 /* If this is a pre-increment and we have incremented the value 7786 where it lives, copy the incremented value to RELOADREG to 7787 be used as an address. */ 7788 7789 if (! post) 7790 emit_insn (gen_move_insn (reloadreg, incloc)); 7791 7792 return; 7793 } 7794 } 7795 7796 delete_insns_since (last); 7797 7798 /* If couldn't do the increment directly, must increment in RELOADREG. 7799 The way we do this depends on whether this is pre- or post-increment. 7800 For pre-increment, copy INCLOC to the reload register, increment it 7801 there, then save back. */ 7802 7803 if (! post) 7804 { 7805 emit_insn (gen_move_insn (reloadreg, incloc)); 7806 emit_insn (gen_add2_insn (reloadreg, inc)); 7807 emit_insn (gen_move_insn (incloc, reloadreg)); 7808 } 7809 else 7810 { 7811 /* Postincrement. 7812 Because this might be a jump insn or a compare, and because RELOADREG 7813 may not be available after the insn in an input reload, we must do 7814 the incrementation before the insn being reloaded for. 7815 7816 We have already copied INCLOC to RELOADREG. Increment the copy in 7817 RELOADREG, save that back, then decrement RELOADREG so it has 7818 the original value. */ 7819 7820 emit_insn (gen_add2_insn (reloadreg, inc)); 7821 emit_insn (gen_move_insn (incloc, reloadreg)); 7822 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); 7823 } 7824 7825 return; 7826} 7827 7828/* Return 1 if we are certain that the constraint-string STRING allows 7829 the hard register REG. Return 0 if we can't be sure of this. */ 7830 7831static int 7832constraint_accepts_reg_p (string, reg) 7833 char *string; 7834 rtx reg; 7835{ 7836 int value = 0; 7837 int regno = true_regnum (reg); 7838 int c; 7839 7840 /* Initialize for first alternative. */ 7841 value = 0; 7842 /* Check that each alternative contains `g' or `r'. */ 7843 while (1) 7844 switch (c = *string++) 7845 { 7846 case 0: 7847 /* If an alternative lacks `g' or `r', we lose. */ 7848 return value; 7849 case ',': 7850 /* If an alternative lacks `g' or `r', we lose. */ 7851 if (value == 0) 7852 return 0; 7853 /* Initialize for next alternative. */ 7854 value = 0; 7855 break; 7856 case 'g': 7857 case 'r': 7858 /* Any general reg wins for this alternative. */ 7859 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno)) 7860 value = 1; 7861 break; 7862 default: 7863 /* Any reg in specified class wins for this alternative. */ 7864 { 7865 enum reg_class class = REG_CLASS_FROM_LETTER (c); 7866 7867 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno)) 7868 value = 1; 7869 } 7870 } 7871} 7872 7873/* Return the number of places FIND appears within X, but don't count 7874 an occurrence if some SET_DEST is FIND. */ 7875 7876int 7877count_occurrences (x, find) 7878 register rtx x, find; 7879{ 7880 register int i, j; 7881 register enum rtx_code code; 7882 register char *format_ptr; 7883 int count; 7884 7885 if (x == find) 7886 return 1; 7887 if (x == 0) 7888 return 0; 7889 7890 code = GET_CODE (x); 7891 7892 switch (code) 7893 { 7894 case REG: 7895 case QUEUED: 7896 case CONST_INT: 7897 case CONST_DOUBLE: 7898 case SYMBOL_REF: 7899 case CODE_LABEL: 7900 case PC: 7901 case CC0: 7902 return 0; 7903 7904 case SET: 7905 if (SET_DEST (x) == find) 7906 return count_occurrences (SET_SRC (x), find); 7907 break; 7908 7909 default: 7910 break; 7911 } 7912 7913 format_ptr = GET_RTX_FORMAT (code); 7914 count = 0; 7915 7916 for (i = 0; i < GET_RTX_LENGTH (code); i++) 7917 { 7918 switch (*format_ptr++) 7919 { 7920 case 'e': 7921 count += count_occurrences (XEXP (x, i), find); 7922 break; 7923 7924 case 'E': 7925 if (XVEC (x, i) != NULL) 7926 { 7927 for (j = 0; j < XVECLEN (x, i); j++) 7928 count += count_occurrences (XVECEXP (x, i, j), find); 7929 } 7930 break; 7931 } 7932 } 7933 return count; 7934} 7935 7936/* This array holds values which are equivalent to a hard register 7937 during reload_cse_regs. Each array element is an EXPR_LIST of 7938 values. Each time a hard register is set, we set the corresponding 7939 array element to the value. Each time a hard register is copied 7940 into memory, we add the memory location to the corresponding array 7941 element. We don't store values or memory addresses with side 7942 effects in this array. 7943 7944 If the value is a CONST_INT, then the mode of the containing 7945 EXPR_LIST is the mode in which that CONST_INT was referenced. 7946 7947 We sometimes clobber a specific entry in a list. In that case, we 7948 just set XEXP (list-entry, 0) to 0. */ 7949 7950static rtx *reg_values; 7951 7952/* This is a preallocated REG rtx which we use as a temporary in 7953 reload_cse_invalidate_regno, so that we don't need to allocate a 7954 new one each time through a loop in that function. */ 7955 7956static rtx invalidate_regno_rtx; 7957 7958/* This is a set of registers for which we must remove REG_DEAD notes in 7959 previous insns, because our modifications made them invalid. That can 7960 happen if we introduced the register into the current insn, or we deleted 7961 the current insn which used to set the register. */ 7962 7963static HARD_REG_SET no_longer_dead_regs; 7964 7965/* Invalidate any entries in reg_values which depend on REGNO, 7966 including those for REGNO itself. This is called if REGNO is 7967 changing. If CLOBBER is true, then always forget anything we 7968 currently know about REGNO. MODE is the mode of the assignment to 7969 REGNO, which is used to determine how many hard registers are being 7970 changed. If MODE is VOIDmode, then only REGNO is being changed; 7971 this is used when invalidating call clobbered registers across a 7972 call. */ 7973 7974static void 7975reload_cse_invalidate_regno (regno, mode, clobber) 7976 int regno; 7977 enum machine_mode mode; 7978 int clobber; 7979{ 7980 int endregno; 7981 register int i; 7982 7983 /* Our callers don't always go through true_regnum; we may see a 7984 pseudo-register here from a CLOBBER or the like. We probably 7985 won't ever see a pseudo-register that has a real register number, 7986 for we check anyhow for safety. */ 7987 if (regno >= FIRST_PSEUDO_REGISTER) 7988 regno = reg_renumber[regno]; 7989 if (regno < 0) 7990 return; 7991 7992 if (mode == VOIDmode) 7993 endregno = regno + 1; 7994 else 7995 endregno = regno + HARD_REGNO_NREGS (regno, mode); 7996 7997 if (clobber) 7998 for (i = regno; i < endregno; i++) 7999 reg_values[i] = 0; 8000 8001 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8002 { 8003 rtx x; 8004 8005 for (x = reg_values[i]; x; x = XEXP (x, 1)) 8006 { 8007 if (XEXP (x, 0) != 0 8008 && refers_to_regno_p (regno, endregno, XEXP (x, 0), NULL_PTR)) 8009 { 8010 /* If this is the only entry on the list, clear 8011 reg_values[i]. Otherwise, just clear this entry on 8012 the list. */ 8013 if (XEXP (x, 1) == 0 && x == reg_values[i]) 8014 { 8015 reg_values[i] = 0; 8016 break; 8017 } 8018 XEXP (x, 0) = 0; 8019 } 8020 } 8021 } 8022 8023 /* We must look at earlier registers, in case REGNO is part of a 8024 multi word value but is not the first register. If an earlier 8025 register has a value in a mode which overlaps REGNO, then we must 8026 invalidate that earlier register. Note that we do not need to 8027 check REGNO or later registers (we must not check REGNO itself, 8028 because we would incorrectly conclude that there was a conflict). */ 8029 8030 for (i = 0; i < regno; i++) 8031 { 8032 rtx x; 8033 8034 for (x = reg_values[i]; x; x = XEXP (x, 1)) 8035 { 8036 if (XEXP (x, 0) != 0) 8037 { 8038 PUT_MODE (invalidate_regno_rtx, GET_MODE (x)); 8039 REGNO (invalidate_regno_rtx) = i; 8040 if (refers_to_regno_p (regno, endregno, invalidate_regno_rtx, 8041 NULL_PTR)) 8042 { 8043 reload_cse_invalidate_regno (i, VOIDmode, 1); 8044 break; 8045 } 8046 } 8047 } 8048 } 8049} 8050 8051/* The memory at address MEM_BASE is being changed. 8052 Return whether this change will invalidate VAL. */ 8053 8054static int 8055reload_cse_mem_conflict_p (mem_base, val) 8056 rtx mem_base; 8057 rtx val; 8058{ 8059 enum rtx_code code; 8060 char *fmt; 8061 int i; 8062 8063 code = GET_CODE (val); 8064 switch (code) 8065 { 8066 /* Get rid of a few simple cases quickly. */ 8067 case REG: 8068 case PC: 8069 case CC0: 8070 case SCRATCH: 8071 case CONST: 8072 case CONST_INT: 8073 case CONST_DOUBLE: 8074 case SYMBOL_REF: 8075 case LABEL_REF: 8076 return 0; 8077 8078 case MEM: 8079 if (GET_MODE (mem_base) == BLKmode 8080 || GET_MODE (val) == BLKmode) 8081 return 1; 8082 if (anti_dependence (val, mem_base)) 8083 return 1; 8084 /* The address may contain nested MEMs. */ 8085 break; 8086 8087 default: 8088 break; 8089 } 8090 8091 fmt = GET_RTX_FORMAT (code); 8092 8093 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 8094 { 8095 if (fmt[i] == 'e') 8096 { 8097 if (reload_cse_mem_conflict_p (mem_base, XEXP (val, i))) 8098 return 1; 8099 } 8100 else if (fmt[i] == 'E') 8101 { 8102 int j; 8103 8104 for (j = 0; j < XVECLEN (val, i); j++) 8105 if (reload_cse_mem_conflict_p (mem_base, XVECEXP (val, i, j))) 8106 return 1; 8107 } 8108 } 8109 8110 return 0; 8111} 8112 8113/* Invalidate any entries in reg_values which are changed because of a 8114 store to MEM_RTX. If this is called because of a non-const call 8115 instruction, MEM_RTX is (mem:BLK const0_rtx). */ 8116 8117static void 8118reload_cse_invalidate_mem (mem_rtx) 8119 rtx mem_rtx; 8120{ 8121 register int i; 8122 8123 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8124 { 8125 rtx x; 8126 8127 for (x = reg_values[i]; x; x = XEXP (x, 1)) 8128 { 8129 if (XEXP (x, 0) != 0 8130 && reload_cse_mem_conflict_p (mem_rtx, XEXP (x, 0))) 8131 { 8132 /* If this is the only entry on the list, clear 8133 reg_values[i]. Otherwise, just clear this entry on 8134 the list. */ 8135 if (XEXP (x, 1) == 0 && x == reg_values[i]) 8136 { 8137 reg_values[i] = 0; 8138 break; 8139 } 8140 XEXP (x, 0) = 0; 8141 } 8142 } 8143 } 8144} 8145 8146/* Invalidate DEST, which is being assigned to or clobbered. The 8147 second parameter exists so that this function can be passed to 8148 note_stores; it is ignored. */ 8149 8150static void 8151reload_cse_invalidate_rtx (dest, ignore) 8152 rtx dest; 8153 rtx ignore ATTRIBUTE_UNUSED; 8154{ 8155 while (GET_CODE (dest) == STRICT_LOW_PART 8156 || GET_CODE (dest) == SIGN_EXTRACT 8157 || GET_CODE (dest) == ZERO_EXTRACT 8158 || GET_CODE (dest) == SUBREG) 8159 dest = XEXP (dest, 0); 8160 8161 if (GET_CODE (dest) == REG) 8162 reload_cse_invalidate_regno (REGNO (dest), GET_MODE (dest), 1); 8163 else if (GET_CODE (dest) == MEM) 8164 reload_cse_invalidate_mem (dest); 8165} 8166 8167/* Possibly delete death notes on the insns before INSN if modifying INSN 8168 extended the lifespan of the registers. */ 8169 8170static void 8171reload_cse_delete_death_notes (insn) 8172 rtx insn; 8173{ 8174 int dreg; 8175 8176 for (dreg = 0; dreg < FIRST_PSEUDO_REGISTER; dreg++) 8177 { 8178 rtx trial; 8179 8180 if (! TEST_HARD_REG_BIT (no_longer_dead_regs, dreg)) 8181 continue; 8182 8183 for (trial = prev_nonnote_insn (insn); 8184 (trial 8185 && GET_CODE (trial) != CODE_LABEL 8186 && GET_CODE (trial) != BARRIER); 8187 trial = prev_nonnote_insn (trial)) 8188 { 8189 if (find_regno_note (trial, REG_DEAD, dreg)) 8190 { 8191 remove_death (dreg, trial); 8192 break; 8193 } 8194 } 8195 } 8196} 8197 8198/* Record that the current insn uses hard reg REGNO in mode MODE. This 8199 will be used in reload_cse_delete_death_notes to delete prior REG_DEAD 8200 notes for this register. */ 8201 8202static void 8203reload_cse_no_longer_dead (regno, mode) 8204 int regno; 8205 enum machine_mode mode; 8206{ 8207 int nregs = HARD_REGNO_NREGS (regno, mode); 8208 while (nregs-- > 0) 8209 { 8210 SET_HARD_REG_BIT (no_longer_dead_regs, regno); 8211 regno++; 8212 } 8213} 8214 8215 8216/* Do a very simple CSE pass over the hard registers. 8217 8218 This function detects no-op moves where we happened to assign two 8219 different pseudo-registers to the same hard register, and then 8220 copied one to the other. Reload will generate a useless 8221 instruction copying a register to itself. 8222 8223 This function also detects cases where we load a value from memory 8224 into two different registers, and (if memory is more expensive than 8225 registers) changes it to simply copy the first register into the 8226 second register. 8227 8228 Another optimization is performed that scans the operands of each 8229 instruction to see whether the value is already available in a 8230 hard register. It then replaces the operand with the hard register 8231 if possible, much like an optional reload would. */ 8232 8233void 8234reload_cse_regs (first) 8235 rtx first; 8236{ 8237 char *firstobj; 8238 rtx callmem; 8239 register int i; 8240 rtx insn; 8241 8242 init_alias_analysis (); 8243 8244 reg_values = (rtx *) alloca (FIRST_PSEUDO_REGISTER * sizeof (rtx)); 8245 bzero ((char *)reg_values, FIRST_PSEUDO_REGISTER * sizeof (rtx)); 8246 8247 /* Create our EXPR_LIST structures on reload_obstack, so that we can 8248 free them when we are done. */ 8249 push_obstacks (&reload_obstack, &reload_obstack); 8250 firstobj = (char *) obstack_alloc (&reload_obstack, 0); 8251 8252 /* We pass this to reload_cse_invalidate_mem to invalidate all of 8253 memory for a non-const call instruction. */ 8254 callmem = gen_rtx_MEM (BLKmode, const0_rtx); 8255 8256 /* This is used in reload_cse_invalidate_regno to avoid consing a 8257 new REG in a loop in that function. */ 8258 invalidate_regno_rtx = gen_rtx_REG (VOIDmode, 0); 8259 8260 for (insn = first; insn; insn = NEXT_INSN (insn)) 8261 { 8262 rtx body; 8263 8264 if (GET_CODE (insn) == CODE_LABEL) 8265 { 8266 /* Forget all the register values at a code label. We don't 8267 try to do anything clever around jumps. */ 8268 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8269 reg_values[i] = 0; 8270 8271 continue; 8272 } 8273 8274#ifdef NON_SAVING_SETJMP 8275 if (NON_SAVING_SETJMP && GET_CODE (insn) == NOTE 8276 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP) 8277 { 8278 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8279 reg_values[i] = 0; 8280 8281 continue; 8282 } 8283#endif 8284 8285 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i') 8286 continue; 8287 8288 CLEAR_HARD_REG_SET (no_longer_dead_regs); 8289 8290 /* If this is a call instruction, forget anything stored in a 8291 call clobbered register, or, if this is not a const call, in 8292 memory. */ 8293 if (GET_CODE (insn) == CALL_INSN) 8294 { 8295 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8296 if (call_used_regs[i]) 8297 reload_cse_invalidate_regno (i, VOIDmode, 1); 8298 8299 if (! CONST_CALL_P (insn)) 8300 reload_cse_invalidate_mem (callmem); 8301 } 8302 8303 body = PATTERN (insn); 8304 if (GET_CODE (body) == SET) 8305 { 8306 int count = 0; 8307 if (reload_cse_noop_set_p (body, insn)) 8308 { 8309 PUT_CODE (insn, NOTE); 8310 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 8311 NOTE_SOURCE_FILE (insn) = 0; 8312 reload_cse_delete_death_notes (insn); 8313 8314 /* We're done with this insn. */ 8315 continue; 8316 } 8317 8318 /* It's not a no-op, but we can try to simplify it. */ 8319 CLEAR_HARD_REG_SET (no_longer_dead_regs); 8320 count += reload_cse_simplify_set (body, insn); 8321 8322 if (count > 0 && apply_change_group ()) 8323 reload_cse_delete_death_notes (insn); 8324 else if (reload_cse_simplify_operands (insn)) 8325 reload_cse_delete_death_notes (insn); 8326 8327 reload_cse_record_set (body, body); 8328 } 8329 else if (GET_CODE (body) == PARALLEL) 8330 { 8331 int count = 0; 8332 8333 /* If every action in a PARALLEL is a noop, we can delete 8334 the entire PARALLEL. */ 8335 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 8336 if ((GET_CODE (XVECEXP (body, 0, i)) != SET 8337 || ! reload_cse_noop_set_p (XVECEXP (body, 0, i), insn)) 8338 && GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) 8339 break; 8340 if (i < 0) 8341 { 8342 PUT_CODE (insn, NOTE); 8343 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 8344 NOTE_SOURCE_FILE (insn) = 0; 8345 reload_cse_delete_death_notes (insn); 8346 8347 /* We're done with this insn. */ 8348 continue; 8349 } 8350 8351 /* It's not a no-op, but we can try to simplify it. */ 8352 CLEAR_HARD_REG_SET (no_longer_dead_regs); 8353 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 8354 if (GET_CODE (XVECEXP (body, 0, i)) == SET) 8355 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); 8356 8357 if (count > 0 && apply_change_group ()) 8358 reload_cse_delete_death_notes (insn); 8359 else if (reload_cse_simplify_operands (insn)) 8360 reload_cse_delete_death_notes (insn); 8361 8362 /* Look through the PARALLEL and record the values being 8363 set, if possible. Also handle any CLOBBERs. */ 8364 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 8365 { 8366 rtx x = XVECEXP (body, 0, i); 8367 8368 if (GET_CODE (x) == SET) 8369 reload_cse_record_set (x, body); 8370 else 8371 note_stores (x, reload_cse_invalidate_rtx); 8372 } 8373 } 8374 else 8375 note_stores (body, reload_cse_invalidate_rtx); 8376 8377#ifdef AUTO_INC_DEC 8378 /* Clobber any registers which appear in REG_INC notes. We 8379 could keep track of the changes to their values, but it is 8380 unlikely to help. */ 8381 { 8382 rtx x; 8383 8384 for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) 8385 if (REG_NOTE_KIND (x) == REG_INC) 8386 reload_cse_invalidate_rtx (XEXP (x, 0), NULL_RTX); 8387 } 8388#endif 8389 8390 /* Look for any CLOBBERs in CALL_INSN_FUNCTION_USAGE, but only 8391 after we have processed the insn. */ 8392 if (GET_CODE (insn) == CALL_INSN) 8393 { 8394 rtx x; 8395 8396 for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1)) 8397 if (GET_CODE (XEXP (x, 0)) == CLOBBER) 8398 reload_cse_invalidate_rtx (XEXP (XEXP (x, 0), 0), NULL_RTX); 8399 } 8400 } 8401 8402 /* Free all the temporary structures we created, and go back to the 8403 regular obstacks. */ 8404 obstack_free (&reload_obstack, firstobj); 8405 pop_obstacks (); 8406} 8407 8408/* Return whether the values known for REGNO are equal to VAL. MODE 8409 is the mode of the object that VAL is being copied to; this matters 8410 if VAL is a CONST_INT. */ 8411 8412static int 8413reload_cse_regno_equal_p (regno, val, mode) 8414 int regno; 8415 rtx val; 8416 enum machine_mode mode; 8417{ 8418 rtx x; 8419 8420 if (val == 0) 8421 return 0; 8422 8423 for (x = reg_values[regno]; x; x = XEXP (x, 1)) 8424 if (XEXP (x, 0) != 0 8425 && rtx_equal_p (XEXP (x, 0), val) 8426 && (! flag_float_store || GET_CODE (XEXP (x, 0)) != MEM 8427 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT) 8428 && (GET_CODE (val) != CONST_INT 8429 || mode == GET_MODE (x) 8430 || (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x)) 8431 /* On a big endian machine if the value spans more than 8432 one register then this register holds the high part of 8433 it and we can't use it. 8434 8435 ??? We should also compare with the high part of the 8436 value. */ 8437 && !(WORDS_BIG_ENDIAN 8438 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1) 8439 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode), 8440 GET_MODE_BITSIZE (GET_MODE (x)))))) 8441 return 1; 8442 8443 return 0; 8444} 8445 8446/* See whether a single set is a noop. SET is the set instruction we 8447 are should check, and INSN is the instruction from which it came. */ 8448 8449static int 8450reload_cse_noop_set_p (set, insn) 8451 rtx set; 8452 rtx insn; 8453{ 8454 rtx src, dest; 8455 enum machine_mode dest_mode; 8456 int dreg, sreg; 8457 int ret; 8458 8459 src = SET_SRC (set); 8460 dest = SET_DEST (set); 8461 dest_mode = GET_MODE (dest); 8462 8463 if (side_effects_p (src)) 8464 return 0; 8465 8466 dreg = true_regnum (dest); 8467 sreg = true_regnum (src); 8468 8469 /* Check for setting a register to itself. In this case, we don't 8470 have to worry about REG_DEAD notes. */ 8471 if (dreg >= 0 && dreg == sreg) 8472 return 1; 8473 8474 ret = 0; 8475 if (dreg >= 0) 8476 { 8477 /* Check for setting a register to itself. */ 8478 if (dreg == sreg) 8479 ret = 1; 8480 8481 /* Check for setting a register to a value which we already know 8482 is in the register. */ 8483 else if (reload_cse_regno_equal_p (dreg, src, dest_mode)) 8484 ret = 1; 8485 8486 /* Check for setting a register DREG to another register SREG 8487 where SREG is equal to a value which is already in DREG. */ 8488 else if (sreg >= 0) 8489 { 8490 rtx x; 8491 8492 for (x = reg_values[sreg]; x; x = XEXP (x, 1)) 8493 { 8494 rtx tmp; 8495 8496 if (XEXP (x, 0) == 0) 8497 continue; 8498 8499 if (dest_mode == GET_MODE (x)) 8500 tmp = XEXP (x, 0); 8501 else if (GET_MODE_BITSIZE (dest_mode) 8502 < GET_MODE_BITSIZE (GET_MODE (x))) 8503 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0)); 8504 else 8505 continue; 8506 8507 if (tmp 8508 && reload_cse_regno_equal_p (dreg, tmp, dest_mode)) 8509 { 8510 ret = 1; 8511 break; 8512 } 8513 } 8514 } 8515 } 8516 else if (GET_CODE (dest) == MEM) 8517 { 8518 /* Check for storing a register to memory when we know that the 8519 register is equivalent to the memory location. */ 8520 if (sreg >= 0 8521 && reload_cse_regno_equal_p (sreg, dest, dest_mode) 8522 && ! side_effects_p (dest)) 8523 ret = 1; 8524 } 8525 8526 /* If we can delete this SET, then we need to look for an earlier 8527 REG_DEAD note on DREG, and remove it if it exists. */ 8528 if (ret && dreg >= 0) 8529 { 8530 if (! find_regno_note (insn, REG_UNUSED, dreg)) 8531 reload_cse_no_longer_dead (dreg, dest_mode); 8532 } 8533 8534 return ret; 8535} 8536 8537/* Try to simplify a single SET instruction. SET is the set pattern. 8538 INSN is the instruction it came from. 8539 This function only handles one case: if we set a register to a value 8540 which is not a register, we try to find that value in some other register 8541 and change the set into a register copy. */ 8542 8543static int 8544reload_cse_simplify_set (set, insn) 8545 rtx set; 8546 rtx insn; 8547{ 8548 int dreg; 8549 rtx src; 8550 enum machine_mode dest_mode; 8551 enum reg_class dclass; 8552 register int i; 8553 8554 dreg = true_regnum (SET_DEST (set)); 8555 if (dreg < 0) 8556 return 0; 8557 8558 src = SET_SRC (set); 8559 if (side_effects_p (src) || true_regnum (src) >= 0) 8560 return 0; 8561 8562 dclass = REGNO_REG_CLASS (dreg); 8563 8564 /* If memory loads are cheaper than register copies, don't change them. */ 8565 if (GET_CODE (src) == MEM 8566 && MEMORY_MOVE_COST (GET_MODE (src), dclass, 1) < 2) 8567 return 0; 8568 8569 /* If the constant is cheaper than a register, don't change it. */ 8570 if (CONSTANT_P (src) 8571 && rtx_cost (src, SET) < 2) 8572 return 0; 8573 8574 dest_mode = GET_MODE (SET_DEST (set)); 8575 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 8576 { 8577 if (i != dreg 8578 && REGISTER_MOVE_COST (REGNO_REG_CLASS (i), dclass) == 2 8579 && reload_cse_regno_equal_p (i, src, dest_mode)) 8580 { 8581 int validated; 8582 8583 /* Pop back to the real obstacks while changing the insn. */ 8584 pop_obstacks (); 8585 8586 validated = validate_change (insn, &SET_SRC (set), 8587 gen_rtx_REG (dest_mode, i), 1); 8588 8589 /* Go back to the obstack we are using for temporary 8590 storage. */ 8591 push_obstacks (&reload_obstack, &reload_obstack); 8592 8593 if (validated && ! find_regno_note (insn, REG_UNUSED, i)) 8594 { 8595 reload_cse_no_longer_dead (i, dest_mode); 8596 return 1; 8597 } 8598 } 8599 } 8600 return 0; 8601} 8602 8603/* Try to replace operands in INSN with equivalent values that are already 8604 in registers. This can be viewed as optional reloading. 8605 8606 For each non-register operand in the insn, see if any hard regs are 8607 known to be equivalent to that operand. Record the alternatives which 8608 can accept these hard registers. Among all alternatives, select the 8609 ones which are better or equal to the one currently matching, where 8610 "better" is in terms of '?' and '!' constraints. Among the remaining 8611 alternatives, select the one which replaces most operands with 8612 hard registers. */ 8613 8614static int 8615reload_cse_simplify_operands (insn) 8616 rtx insn; 8617{ 8618#ifdef REGISTER_CONSTRAINTS 8619 int insn_code_number, n_operands, n_alternatives; 8620 int i,j; 8621 8622 char *constraints[MAX_RECOG_OPERANDS]; 8623 8624 /* Vector recording how bad an alternative is. */ 8625 int *alternative_reject; 8626 /* Vector recording how many registers can be introduced by choosing 8627 this alternative. */ 8628 int *alternative_nregs; 8629 /* Array of vectors recording, for each operand and each alternative, 8630 which hard register to substitute, or -1 if the operand should be 8631 left as it is. */ 8632 int *op_alt_regno[MAX_RECOG_OPERANDS]; 8633 /* Array of alternatives, sorted in order of decreasing desirability. */ 8634 int *alternative_order; 8635 rtx reg = gen_rtx_REG (VOIDmode, -1); 8636 8637 /* Find out some information about this insn. */ 8638 insn_code_number = recog_memoized (insn); 8639 /* We don't modify asm instructions. */ 8640 if (insn_code_number < 0) 8641 return 0; 8642 8643 n_operands = insn_n_operands[insn_code_number]; 8644 n_alternatives = insn_n_alternatives[insn_code_number]; 8645 8646 if (n_alternatives == 0 || n_operands == 0) 8647 return 0; 8648 insn_extract (insn); 8649 8650 /* Figure out which alternative currently matches. */ 8651 if (! constrain_operands (insn_code_number, 1)) 8652 fatal_insn_not_found (insn); 8653 8654 alternative_reject = (int *) alloca (n_alternatives * sizeof (int)); 8655 alternative_nregs = (int *) alloca (n_alternatives * sizeof (int)); 8656 alternative_order = (int *) alloca (n_alternatives * sizeof (int)); 8657 bzero ((char *)alternative_reject, n_alternatives * sizeof (int)); 8658 bzero ((char *)alternative_nregs, n_alternatives * sizeof (int)); 8659 8660 for (i = 0; i < n_operands; i++) 8661 { 8662 enum machine_mode mode; 8663 int regno; 8664 char *p; 8665 8666 op_alt_regno[i] = (int *) alloca (n_alternatives * sizeof (int)); 8667 for (j = 0; j < n_alternatives; j++) 8668 op_alt_regno[i][j] = -1; 8669 8670 p = constraints[i] = insn_operand_constraint[insn_code_number][i]; 8671 mode = insn_operand_mode[insn_code_number][i]; 8672 8673 /* Add the reject values for each alternative given by the constraints 8674 for this operand. */ 8675 j = 0; 8676 while (*p != '\0') 8677 { 8678 char c = *p++; 8679 if (c == ',') 8680 j++; 8681 else if (c == '?') 8682 alternative_reject[j] += 3; 8683 else if (c == '!') 8684 alternative_reject[j] += 300; 8685 } 8686 8687 /* We won't change operands which are already registers. We 8688 also don't want to modify output operands. */ 8689 regno = true_regnum (recog_operand[i]); 8690 if (regno >= 0 8691 || constraints[i][0] == '=' 8692 || constraints[i][0] == '+') 8693 continue; 8694 8695 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 8696 { 8697 int class = (int) NO_REGS; 8698 8699 if (! reload_cse_regno_equal_p (regno, recog_operand[i], mode)) 8700 continue; 8701 8702 REGNO (reg) = regno; 8703 PUT_MODE (reg, mode); 8704 8705 /* We found a register equal to this operand. Now look for all 8706 alternatives that can accept this register and have not been 8707 assigned a register they can use yet. */ 8708 j = 0; 8709 p = constraints[i]; 8710 for (;;) 8711 { 8712 char c = *p++; 8713 8714 switch (c) 8715 { 8716 case '=': case '+': case '?': 8717 case '#': case '&': case '!': 8718 case '*': case '%': 8719 case '0': case '1': case '2': case '3': case '4': 8720 case 'm': case '<': case '>': case 'V': case 'o': 8721 case 'E': case 'F': case 'G': case 'H': 8722 case 's': case 'i': case 'n': 8723 case 'I': case 'J': case 'K': case 'L': 8724 case 'M': case 'N': case 'O': case 'P': 8725#ifdef EXTRA_CONSTRAINT 8726 case 'Q': case 'R': case 'S': case 'T': case 'U': 8727#endif 8728 case 'p': case 'X': 8729 /* These don't say anything we care about. */ 8730 break; 8731 8732 case 'g': case 'r': 8733 class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; 8734 break; 8735 8736 default: 8737 class 8738 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (c)]; 8739 break; 8740 8741 case ',': case '\0': 8742 /* See if REGNO fits this alternative, and set it up as the 8743 replacement register if we don't have one for this 8744 alternative yet and the operand being replaced is not 8745 a cheap CONST_INT. */ 8746 if (op_alt_regno[i][j] == -1 8747 && reg_fits_class_p (reg, class, 0, mode) 8748 && (GET_CODE (recog_operand[i]) != CONST_INT 8749 || rtx_cost (recog_operand[i], SET) > rtx_cost (reg, SET))) 8750 { 8751 alternative_nregs[j]++; 8752 op_alt_regno[i][j] = regno; 8753 } 8754 j++; 8755 break; 8756 } 8757 8758 if (c == '\0') 8759 break; 8760 } 8761 } 8762 } 8763 8764 /* Record all alternatives which are better or equal to the currently 8765 matching one in the alternative_order array. */ 8766 for (i = j = 0; i < n_alternatives; i++) 8767 if (alternative_reject[i] <= alternative_reject[which_alternative]) 8768 alternative_order[j++] = i; 8769 n_alternatives = j; 8770 8771 /* Sort it. Given a small number of alternatives, a dumb algorithm 8772 won't hurt too much. */ 8773 for (i = 0; i < n_alternatives - 1; i++) 8774 { 8775 int best = i; 8776 int best_reject = alternative_reject[alternative_order[i]]; 8777 int best_nregs = alternative_nregs[alternative_order[i]]; 8778 int tmp; 8779 8780 for (j = i + 1; j < n_alternatives; j++) 8781 { 8782 int this_reject = alternative_reject[alternative_order[j]]; 8783 int this_nregs = alternative_nregs[alternative_order[j]]; 8784 8785 if (this_reject < best_reject 8786 || (this_reject == best_reject && this_nregs < best_nregs)) 8787 { 8788 best = j; 8789 best_reject = this_reject; 8790 best_nregs = this_nregs; 8791 } 8792 } 8793 8794 tmp = alternative_order[best]; 8795 alternative_order[best] = alternative_order[i]; 8796 alternative_order[i] = tmp; 8797 } 8798 8799 /* Substitute the operands as determined by op_alt_regno for the best 8800 alternative. */ 8801 j = alternative_order[0]; 8802 CLEAR_HARD_REG_SET (no_longer_dead_regs); 8803 8804 /* Pop back to the real obstacks while changing the insn. */ 8805 pop_obstacks (); 8806 8807 for (i = 0; i < n_operands; i++) 8808 { 8809 enum machine_mode mode = insn_operand_mode[insn_code_number][i]; 8810 if (op_alt_regno[i][j] == -1) 8811 continue; 8812 8813 reload_cse_no_longer_dead (op_alt_regno[i][j], mode); 8814 validate_change (insn, recog_operand_loc[i], 8815 gen_rtx_REG (mode, op_alt_regno[i][j]), 1); 8816 } 8817 8818 for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) 8819 { 8820 int op = recog_dup_num[i]; 8821 enum machine_mode mode = insn_operand_mode[insn_code_number][op]; 8822 8823 if (op_alt_regno[op][j] == -1) 8824 continue; 8825 8826 reload_cse_no_longer_dead (op_alt_regno[op][j], mode); 8827 validate_change (insn, recog_dup_loc[i], 8828 gen_rtx_REG (mode, op_alt_regno[op][j]), 1); 8829 } 8830 8831 /* Go back to the obstack we are using for temporary 8832 storage. */ 8833 push_obstacks (&reload_obstack, &reload_obstack); 8834 8835 return apply_change_group (); 8836#else 8837 return 0; 8838#endif 8839} 8840 8841/* These two variables are used to pass information from 8842 reload_cse_record_set to reload_cse_check_clobber. */ 8843 8844static int reload_cse_check_clobbered; 8845static rtx reload_cse_check_src; 8846 8847/* See if DEST overlaps with RELOAD_CSE_CHECK_SRC. If it does, set 8848 RELOAD_CSE_CHECK_CLOBBERED. This is called via note_stores. The 8849 second argument, which is passed by note_stores, is ignored. */ 8850 8851static void 8852reload_cse_check_clobber (dest, ignore) 8853 rtx dest; 8854 rtx ignore ATTRIBUTE_UNUSED; 8855{ 8856 if (reg_overlap_mentioned_p (dest, reload_cse_check_src)) 8857 reload_cse_check_clobbered = 1; 8858} 8859 8860/* Record the result of a SET instruction. SET is the set pattern. 8861 BODY is the pattern of the insn that it came from. */ 8862 8863static void 8864reload_cse_record_set (set, body) 8865 rtx set; 8866 rtx body; 8867{ 8868 rtx dest, src, x; 8869 int dreg, sreg; 8870 enum machine_mode dest_mode; 8871 8872 dest = SET_DEST (set); 8873 src = SET_SRC (set); 8874 dreg = true_regnum (dest); 8875 sreg = true_regnum (src); 8876 dest_mode = GET_MODE (dest); 8877 8878 /* Some machines don't define AUTO_INC_DEC, but they still use push 8879 instructions. We need to catch that case here in order to 8880 invalidate the stack pointer correctly. Note that invalidating 8881 the stack pointer is different from invalidating DEST. */ 8882 x = dest; 8883 while (GET_CODE (x) == SUBREG 8884 || GET_CODE (x) == ZERO_EXTRACT 8885 || GET_CODE (x) == SIGN_EXTRACT 8886 || GET_CODE (x) == STRICT_LOW_PART) 8887 x = XEXP (x, 0); 8888 if (push_operand (x, GET_MODE (x))) 8889 { 8890 reload_cse_invalidate_rtx (stack_pointer_rtx, NULL_RTX); 8891 reload_cse_invalidate_rtx (dest, NULL_RTX); 8892 return; 8893 } 8894 8895 /* We can only handle an assignment to a register, or a store of a 8896 register to a memory location. For other cases, we just clobber 8897 the destination. We also have to just clobber if there are side 8898 effects in SRC or DEST. */ 8899 if ((dreg < 0 && GET_CODE (dest) != MEM) 8900 || side_effects_p (src) 8901 || side_effects_p (dest)) 8902 { 8903 reload_cse_invalidate_rtx (dest, NULL_RTX); 8904 return; 8905 } 8906 8907#ifdef HAVE_cc0 8908 /* We don't try to handle values involving CC, because it's a pain 8909 to keep track of when they have to be invalidated. */ 8910 if (reg_mentioned_p (cc0_rtx, src) 8911 || reg_mentioned_p (cc0_rtx, dest)) 8912 { 8913 reload_cse_invalidate_rtx (dest, NULL_RTX); 8914 return; 8915 } 8916#endif 8917 8918 /* If BODY is a PARALLEL, then we need to see whether the source of 8919 SET is clobbered by some other instruction in the PARALLEL. */ 8920 if (GET_CODE (body) == PARALLEL) 8921 { 8922 int i; 8923 8924 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 8925 { 8926 rtx x; 8927 8928 x = XVECEXP (body, 0, i); 8929 if (x == set) 8930 continue; 8931 8932 reload_cse_check_clobbered = 0; 8933 reload_cse_check_src = src; 8934 note_stores (x, reload_cse_check_clobber); 8935 if (reload_cse_check_clobbered) 8936 { 8937 reload_cse_invalidate_rtx (dest, NULL_RTX); 8938 return; 8939 } 8940 } 8941 } 8942 8943 if (dreg >= 0) 8944 { 8945 int i; 8946 8947 /* This is an assignment to a register. Update the value we 8948 have stored for the register. */ 8949 if (sreg >= 0) 8950 { 8951 rtx x; 8952 8953 /* This is a copy from one register to another. Any values 8954 which were valid for SREG are now valid for DREG. If the 8955 mode changes, we use gen_lowpart_common to extract only 8956 the part of the value that is copied. */ 8957 reg_values[dreg] = 0; 8958 for (x = reg_values[sreg]; x; x = XEXP (x, 1)) 8959 { 8960 rtx tmp; 8961 8962 if (XEXP (x, 0) == 0) 8963 continue; 8964 if (dest_mode == GET_MODE (XEXP (x, 0))) 8965 tmp = XEXP (x, 0); 8966 else if (GET_MODE_BITSIZE (dest_mode) 8967 > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))) 8968 continue; 8969 else 8970 tmp = gen_lowpart_common (dest_mode, XEXP (x, 0)); 8971 if (tmp) 8972 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, tmp, 8973 reg_values[dreg]); 8974 } 8975 } 8976 else 8977 reg_values[dreg] = gen_rtx_EXPR_LIST (dest_mode, src, NULL_RTX); 8978 8979 /* We've changed DREG, so invalidate any values held by other 8980 registers that depend upon it. */ 8981 reload_cse_invalidate_regno (dreg, dest_mode, 0); 8982 8983 /* If this assignment changes more than one hard register, 8984 forget anything we know about the others. */ 8985 for (i = 1; i < HARD_REGNO_NREGS (dreg, dest_mode); i++) 8986 reg_values[dreg + i] = 0; 8987 } 8988 else if (GET_CODE (dest) == MEM) 8989 { 8990 /* Invalidate conflicting memory locations. */ 8991 reload_cse_invalidate_mem (dest); 8992 8993 /* If we're storing a register to memory, add DEST to the list 8994 in REG_VALUES. */ 8995 if (sreg >= 0 && ! side_effects_p (dest)) 8996 reg_values[sreg] = gen_rtx_EXPR_LIST (dest_mode, dest, 8997 reg_values[sreg]); 8998 } 8999 else 9000 { 9001 /* We should have bailed out earlier. */ 9002 abort (); 9003 } 9004} 9005