reload1.c revision 117395
155682Smarkm/* Reload pseudo regs into hard regs for insns that require hard regs. 2233294Sstas Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 3233294Sstas 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. 4233294Sstas 555682SmarkmThis file is part of GCC. 6233294Sstas 7233294SstasGCC is free software; you can redistribute it and/or modify it under 8233294Sstasthe terms of the GNU General Public License as published by the Free 955682SmarkmSoftware Foundation; either version 2, or (at your option) any later 10233294Sstasversion. 11233294Sstas 1255682SmarkmGCC is distributed in the hope that it will be useful, but WITHOUT ANY 13233294SstasWARRANTY; without even the implied warranty of MERCHANTABILITY or 14233294SstasFITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15233294Sstasfor more details. 1655682Smarkm 17233294SstasYou should have received a copy of the GNU General Public License 18233294Sstasalong with GCC; see the file COPYING. If not, write to the Free 19233294SstasSoftware Foundation, 59 Temple Place - Suite 330, Boston, MA 2055682Smarkm02111-1307, USA. */ 21233294Sstas 22233294Sstas#include "config.h" 23233294Sstas#include "system.h" 24233294Sstas 25233294Sstas#include "machmode.h" 26233294Sstas#include "hard-reg-set.h" 27233294Sstas#include "rtl.h" 28233294Sstas#include "tm_p.h" 29233294Sstas#include "obstack.h" 30233294Sstas#include "insn-config.h" 31233294Sstas#include "flags.h" 3255682Smarkm#include "function.h" 3355682Smarkm#include "expr.h" 3455682Smarkm#include "optabs.h" 3555682Smarkm#include "regs.h" 3655682Smarkm#include "basic-block.h" 3755682Smarkm#include "reload.h" 3855682Smarkm#include "recog.h" 3955682Smarkm#include "output.h" 40178825Sdfr#include "cselib.h" 4155682Smarkm#include "real.h" 4290926Snectar#include "toplev.h" 4372445Sassar#include "except.h" 4455682Smarkm#include "tree.h" 4555682Smarkm 46233294Sstas/* This file contains the reload pass of the compiler, which is 47233294Sstas run after register allocation has been done. It checks that 48233294Sstas each insn is valid (operands required to be in registers really 49233294Sstas are in registers of the proper class) and fixes up invalid ones 5055682Smarkm by copying values temporarily into registers for the insns 51233294Sstas that need them. 52233294Sstas 5372445Sassar The results of register allocation are described by the vector 54233294Sstas reg_renumber; the insns still contain pseudo regs, but reg_renumber 5555682Smarkm can be used to find which hard reg, if any, a pseudo reg is in. 5655682Smarkm 5755682Smarkm The technique we always use is to free up a few hard regs that are 5855682Smarkm called ``reload regs'', and for each place where a pseudo reg 5955682Smarkm must be in a hard reg, copy it temporarily into one of the reload regs. 60233294Sstas 6155682Smarkm Reload regs are allocated locally for every instruction that needs 6255682Smarkm reloads. When there are pseudos which are allocated to a register that 6355682Smarkm has been chosen as a reload reg, such pseudos must be ``spilled''. 6455682Smarkm This means that they go to other hard regs, or to stack slots if no other 6555682Smarkm available hard regs can be found. Spilling can invalidate more 6655682Smarkm insns, requiring additional need for reloads, so we must keep checking 6755682Smarkm until the process stabilizes. 6855682Smarkm 6955682Smarkm For machines with different classes of registers, we must keep track 7055682Smarkm of the register class needed for each reload, and make sure that 7155682Smarkm we allocate enough reload registers of each class. 7255682Smarkm 7355682Smarkm The file reload.c contains the code that checks one insn for 7455682Smarkm validity and reports the reloads that it needs. This file 7555682Smarkm is in charge of scanning the entire rtl code, accumulating the 7655682Smarkm reload needs, spilling, assigning reload registers to use for 7755682Smarkm fixing up each insn, and generating the new insns to copy values 78233294Sstas into the reload registers. */ 79233294Sstas 80178825Sdfr#ifndef REGISTER_MOVE_COST 8155682Smarkm#define REGISTER_MOVE_COST(m, x, y) 2 8255682Smarkm#endif 8355682Smarkm 8455682Smarkm#ifndef LOCAL_REGNO 8578527Sassar#define LOCAL_REGNO(REGNO) 0 8655682Smarkm#endif 8755682Smarkm 8855682Smarkm/* During reload_as_needed, element N contains a REG rtx for the hard reg 8955682Smarkm into which reg N has been reloaded (perhaps for a previous insn). */ 9055682Smarkmstatic rtx *reg_last_reload_reg; 9155682Smarkm 9255682Smarkm/* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn 93233294Sstas for an output reload that stores into reg N. */ 9455682Smarkmstatic char *reg_has_output_reload; 95233294Sstas 96178825Sdfr/* Indicates which hard regs are reload-registers for an output reload 9755682Smarkm in the current insn. */ 9855682Smarkmstatic HARD_REG_SET reg_is_output_reload; 9990926Snectar 10090926Snectar/* Element N is the constant value to which pseudo reg N is equivalent, 101233294Sstas or zero if pseudo reg N is not equivalent to a constant. 10255682Smarkm find_reloads looks at this in order to replace pseudo reg N 10355682Smarkm with the constant it stands for. */ 10455682Smarkmrtx *reg_equiv_constant; 10555682Smarkm 10655682Smarkm/* Element N is a memory location to which pseudo reg N is equivalent, 10755682Smarkm prior to any register elimination (such as frame pointer to stack 108233294Sstas pointer). Depending on whether or not it is a valid address, this value 109178825Sdfr is transferred to either reg_equiv_address or reg_equiv_mem. */ 110178825Sdfrrtx *reg_equiv_memory_loc; 11155682Smarkm 11255682Smarkm/* Element N is the address of stack slot to which pseudo reg N is equivalent. 11355682Smarkm This is used when the address is not valid as a memory address 11455682Smarkm (because its displacement is too big for the machine.) */ 115178825Sdfrrtx *reg_equiv_address; 116178825Sdfr 117178825Sdfr/* Element N is the memory slot to which pseudo reg N is equivalent, 118233294Sstas or zero if pseudo reg N is not equivalent to a memory slot. */ 119233294Sstasrtx *reg_equiv_mem; 120233294Sstas 12155682Smarkm/* Widest width in which each pseudo reg is referred to (via subreg). */ 12255682Smarkmstatic unsigned int *reg_max_ref_width; 12372445Sassar 12455682Smarkm/* Element N is the list of insns that initialized reg N from its equivalent 12572445Sassar constant or memory slot. */ 12672445Sassarstatic rtx *reg_equiv_init; 12755682Smarkm 128233294Sstas/* Vector to remember old contents of reg_renumber before spilling. */ 129233294Sstasstatic short *reg_old_renumber; 13055682Smarkm 131233294Sstas/* During reload_as_needed, element N contains the last pseudo regno reloaded 13255682Smarkm into hard register N. If that pseudo reg occupied more than one register, 133233294Sstas reg_reloaded_contents points to that pseudo for each spill register in 13455682Smarkm use; all of these must remain set for an inheritance to occur. */ 135233294Sstasstatic int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; 13655682Smarkm 137233294Sstas/* During reload_as_needed, element N contains the insn for which 138233294Sstas hard register N was last used. Its contents are significant only 139233294Sstas when reg_reloaded_valid is set for this register. */ 14055682Smarkmstatic rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; 14155682Smarkm 142233294Sstas/* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */ 14355682Smarkmstatic HARD_REG_SET reg_reloaded_valid; 14455682Smarkm/* Indicate if the register was dead at the end of the reload. 145233294Sstas This is only valid if reg_reloaded_contents is set and valid. */ 14655682Smarkmstatic HARD_REG_SET reg_reloaded_dead; 14755682Smarkm 14855682Smarkm/* Number of spill-regs so far; number of valid elements of spill_regs. */ 14955682Smarkmstatic int n_spills; 15055682Smarkm 15155682Smarkm/* In parallel with spill_regs, contains REG rtx's for those regs. 15255682Smarkm Holds the last rtx used for any given reg, or 0 if it has never 153178825Sdfr been used for spilling yet. This rtx is reused, provided it has 15455682Smarkm the proper mode. */ 15555682Smarkmstatic rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; 156233294Sstas 15772445Sassar/* In parallel with spill_regs, contains nonzero for a spill reg 15855682Smarkm that was stored after the last time it was used. 15972445Sassar The precise value is the insn generated to do the store. */ 16072445Sassarstatic rtx spill_reg_store[FIRST_PSEUDO_REGISTER]; 16172445Sassar 16272445Sassar/* This is the register that was stored with spill_reg_store. This is a 16372445Sassar copy of reload_out / reload_out_reg when the value was stored; if 16472445Sassar reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ 16572445Sassarstatic rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; 16672445Sassar 16772445Sassar/* This table is the inverse mapping of spill_regs: 16872445Sassar indexed by hard reg number, 16972445Sassar it contains the position of that reg in spill_regs, 17072445Sassar or -1 for something that is not in spill_regs. 171233294Sstas 17272445Sassar ?!? This is no longer accurate. */ 17355682Smarkmstatic short spill_reg_order[FIRST_PSEUDO_REGISTER]; 17455682Smarkm 175233294Sstas/* This reg set indicates registers that can't be used as spill registers for 17672445Sassar the currently processed insn. These are the hard registers which are live 17772445Sassar during the insn, but not allocated to pseudos, as well as fixed 17872445Sassar registers. */ 17972445Sassarstatic HARD_REG_SET bad_spill_regs; 18072445Sassar 18172445Sassar/* These are the hard registers that can't be used as spill register for any 18272445Sassar insn. This includes registers used for user variables and registers that 18372445Sassar we can't eliminate. A register that appears in this set also can't be used 18472445Sassar to retry register allocation. */ 18590926Snectarstatic HARD_REG_SET bad_spill_regs_global; 18655682Smarkm 18790926Snectar/* Describes order of use of registers for reloading 188233294Sstas of spilled pseudo-registers. `n_spills' is the number of 18955682Smarkm elements that are actually valid; new ones are added at the end. 19055682Smarkm 19155682Smarkm Both spill_regs and spill_reg_order are used on two occasions: 192233294Sstas once during find_reload_regs, where they keep track of the spill registers 193178825Sdfr for a single insn, but also during reload_as_needed where they show all 19455682Smarkm the registers ever used by reload. For the latter case, the information 19555682Smarkm is calculated during finish_spills. */ 196178825Sdfrstatic short spill_regs[FIRST_PSEUDO_REGISTER]; 197178825Sdfr 198233294Sstas/* This vector of reg sets indicates, for each pseudo, which hard registers 19955682Smarkm may not be used for retrying global allocation because the register was 20055682Smarkm formerly spilled from one of them. If we allowed reallocating a pseudo to 20155682Smarkm a register that it was already allocated to, reload might not 20255682Smarkm terminate. */ 20355682Smarkmstatic HARD_REG_SET *pseudo_previous_regs; 20455682Smarkm 20555682Smarkm/* This vector of reg sets indicates, for each pseudo, which hard 20655682Smarkm registers may not be used for retrying global allocation because they 20755682Smarkm are used as spill registers during one of the insns in which the 208233294Sstas pseudo is live. */ 20955682Smarkmstatic HARD_REG_SET *pseudo_forbidden_regs; 21055682Smarkm 21155682Smarkm/* All hard regs that have been used as spill registers for any insn are 212178825Sdfr marked in this set. */ 213178825Sdfrstatic HARD_REG_SET used_spill_regs; 214178825Sdfr 215178825Sdfr/* Index of last register assigned as a spill register. We allocate in 216178825Sdfr a round-robin fashion. */ 217178825Sdfrstatic int last_spill_reg; 21855682Smarkm 21955682Smarkm/* Nonzero if indirect addressing is supported on the machine; this means 22055682Smarkm that spilling (REG n) does not require reloading it into a register in 22155682Smarkm order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The 22255682Smarkm value indicates the level of indirect addressing supported, e.g., two 223178825Sdfr means that (MEM (MEM (REG n))) is also valid if (REG n) does not get 22455682Smarkm a hard register. */ 22572445Sassarstatic char spill_indirect_levels; 226233294Sstas 22772445Sassar/* Nonzero if indirect addressing is supported when the innermost MEM is 22872445Sassar of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to 22972445Sassar which these are valid is the same as spill_indirect_levels, above. */ 230233294Sstaschar indirect_symref_ok; 23155682Smarkm 23272445Sassar/* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */ 23355682Smarkmchar double_reg_address_ok; 23455682Smarkm 23572445Sassar/* Record the stack slot for each spilled hard register. */ 23655682Smarkmstatic rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; 23755682Smarkm 23855682Smarkm/* Width allocated so far for that stack slot. */ 239233294Sstasstatic unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; 24055682Smarkm 24155682Smarkm/* Record which pseudos needed to be spilled. */ 242233294Sstasstatic regset_head spilled_pseudos; 243233294Sstas 244233294Sstas/* Used for communication between order_regs_for_reload and count_pseudo. 245178825Sdfr Used to avoid counting one pseudo twice. */ 246178825Sdfrstatic regset_head pseudos_counted; 247178825Sdfr 24855682Smarkm/* First uid used by insns created by reload in this function. 24955682Smarkm Used in find_equiv_reg. */ 25055682Smarkmint reload_first_uid; 251178825Sdfr 252178825Sdfr/* Flag set by local-alloc or global-alloc if anything is live in 253178825Sdfr a call-clobbered reg across calls. */ 25455682Smarkmint caller_save_needed; 25555682Smarkm 25655682Smarkm/* Set to 1 while reload_as_needed is operating. 25755682Smarkm Required by some machines to handle any generated moves differently. */ 25855682Smarkmint reload_in_progress = 0; 259178825Sdfr 260178825Sdfr/* These arrays record the insn_code of insns that may be needed to 261178825Sdfr perform input and output reloads of special objects. They provide a 262178825Sdfr place to pass a scratch register. */ 263178825Sdfrenum insn_code reload_in_optab[NUM_MACHINE_MODES]; 264233294Sstasenum insn_code reload_out_optab[NUM_MACHINE_MODES]; 265178825Sdfr 266178825Sdfr/* This obstack is used for allocation of rtl during register elimination. 267233294Sstas The allocated storage can be freed once find_reloads has processed the 268178825Sdfr insn. */ 26955682Smarkmstruct obstack reload_obstack; 270178825Sdfr 27155682Smarkm/* Points to the beginning of the reload_obstack. All insn_chain structures 27255682Smarkm are allocated first. */ 27355682Smarkmchar *reload_startobj; 27455682Smarkm 27555682Smarkm/* The point after all insn_chain structures. Used to quickly deallocate 276233294Sstas memory allocated in copy_reloads during calculate_needs_all_insns. */ 277233294Sstaschar *reload_firstobj; 278233294Sstas 279233294Sstas/* This points before all local rtl generated by register elimination. 28055682Smarkm Used to quickly free all memory after processing one insn. */ 28155682Smarkmstatic char *reload_insn_firstobj; 282 283/* List of insn_chain instructions, one for every insn that reload needs to 284 examine. */ 285struct insn_chain *reload_insn_chain; 286 287#ifdef TREE_CODE 288extern tree current_function_decl; 289#else 290extern union tree_node *current_function_decl; 291#endif 292 293/* List of all insns needing reloads. */ 294static struct insn_chain *insns_need_reload; 295 296/* This structure is used to record information about register eliminations. 297 Each array entry describes one possible way of eliminating a register 298 in favor of another. If there is more than one way of eliminating a 299 particular register, the most preferred should be specified first. */ 300 301struct elim_table 302{ 303 int from; /* Register number to be eliminated. */ 304 int to; /* Register number used as replacement. */ 305 int initial_offset; /* Initial difference between values. */ 306 int can_eliminate; /* Non-zero if this elimination can be done. */ 307 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over 308 insns made by reload. */ 309 int offset; /* Current offset between the two regs. */ 310 int previous_offset; /* Offset at end of previous insn. */ 311 int ref_outside_mem; /* "to" has been referenced outside a MEM. */ 312 rtx from_rtx; /* REG rtx for the register to be eliminated. 313 We cannot simply compare the number since 314 we might then spuriously replace a hard 315 register corresponding to a pseudo 316 assigned to the reg to be eliminated. */ 317 rtx to_rtx; /* REG rtx for the replacement. */ 318}; 319 320static struct elim_table *reg_eliminate = 0; 321 322/* This is an intermediate structure to initialize the table. It has 323 exactly the members provided by ELIMINABLE_REGS. */ 324static const struct elim_table_1 325{ 326 const int from; 327 const int to; 328} reg_eliminate_1[] = 329 330/* If a set of eliminable registers was specified, define the table from it. 331 Otherwise, default to the normal case of the frame pointer being 332 replaced by the stack pointer. */ 333 334#ifdef ELIMINABLE_REGS 335 ELIMINABLE_REGS; 336#else 337 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}; 338#endif 339 340#define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) 341 342/* Record the number of pending eliminations that have an offset not equal 343 to their initial offset. If nonzero, we use a new copy of each 344 replacement result in any insns encountered. */ 345int num_not_at_initial_offset; 346 347/* Count the number of registers that we may be able to eliminate. */ 348static int num_eliminable; 349/* And the number of registers that are equivalent to a constant that 350 can be eliminated to frame_pointer / arg_pointer + constant. */ 351static int num_eliminable_invariants; 352 353/* For each label, we record the offset of each elimination. If we reach 354 a label by more than one path and an offset differs, we cannot do the 355 elimination. This information is indexed by the difference of the 356 number of the label and the first label number. We can't offset the 357 pointer itself as this can cause problems on machines with segmented 358 memory. The first table is an array of flags that records whether we 359 have yet encountered a label and the second table is an array of arrays, 360 one entry in the latter array for each elimination. */ 361 362static int first_label_num; 363static char *offsets_known_at; 364static int (*offsets_at)[NUM_ELIMINABLE_REGS]; 365 366/* Number of labels in the current function. */ 367 368static int num_labels; 369 370static void replace_pseudos_in_call_usage PARAMS ((rtx *, 371 enum machine_mode, 372 rtx)); 373static void maybe_fix_stack_asms PARAMS ((void)); 374static void copy_reloads PARAMS ((struct insn_chain *)); 375static void calculate_needs_all_insns PARAMS ((int)); 376static int find_reg PARAMS ((struct insn_chain *, int)); 377static void find_reload_regs PARAMS ((struct insn_chain *)); 378static void select_reload_regs PARAMS ((void)); 379static void delete_caller_save_insns PARAMS ((void)); 380 381static void spill_failure PARAMS ((rtx, enum reg_class)); 382static void count_spilled_pseudo PARAMS ((int, int, int)); 383static void delete_dead_insn PARAMS ((rtx)); 384static void alter_reg PARAMS ((int, int)); 385static void set_label_offsets PARAMS ((rtx, rtx, int)); 386static void check_eliminable_occurrences PARAMS ((rtx)); 387static void elimination_effects PARAMS ((rtx, enum machine_mode)); 388static int eliminate_regs_in_insn PARAMS ((rtx, int)); 389static void update_eliminable_offsets PARAMS ((void)); 390static void mark_not_eliminable PARAMS ((rtx, rtx, void *)); 391static void set_initial_elim_offsets PARAMS ((void)); 392static void verify_initial_elim_offsets PARAMS ((void)); 393static void set_initial_label_offsets PARAMS ((void)); 394static void set_offsets_for_label PARAMS ((rtx)); 395static void init_elim_table PARAMS ((void)); 396static void update_eliminables PARAMS ((HARD_REG_SET *)); 397static void spill_hard_reg PARAMS ((unsigned int, int)); 398static int finish_spills PARAMS ((int)); 399static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *)); 400static void scan_paradoxical_subregs PARAMS ((rtx)); 401static void count_pseudo PARAMS ((int)); 402static void order_regs_for_reload PARAMS ((struct insn_chain *)); 403static void reload_as_needed PARAMS ((int)); 404static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *)); 405static int reload_reg_class_lower PARAMS ((const PTR, const PTR)); 406static void mark_reload_reg_in_use PARAMS ((unsigned int, int, 407 enum reload_type, 408 enum machine_mode)); 409static void clear_reload_reg_in_use PARAMS ((unsigned int, int, 410 enum reload_type, 411 enum machine_mode)); 412static int reload_reg_free_p PARAMS ((unsigned int, int, 413 enum reload_type)); 414static int reload_reg_free_for_value_p PARAMS ((int, int, int, 415 enum reload_type, 416 rtx, rtx, int, int)); 417static int free_for_value_p PARAMS ((int, enum machine_mode, int, 418 enum reload_type, rtx, rtx, 419 int, int)); 420static int reload_reg_reaches_end_p PARAMS ((unsigned int, int, 421 enum reload_type)); 422static int allocate_reload_reg PARAMS ((struct insn_chain *, int, 423 int)); 424static int conflicts_with_override PARAMS ((rtx)); 425static void failed_reload PARAMS ((rtx, int)); 426static int set_reload_reg PARAMS ((int, int)); 427static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *)); 428static void choose_reload_regs PARAMS ((struct insn_chain *)); 429static void merge_assigned_reloads PARAMS ((rtx)); 430static void emit_input_reload_insns PARAMS ((struct insn_chain *, 431 struct reload *, rtx, int)); 432static void emit_output_reload_insns PARAMS ((struct insn_chain *, 433 struct reload *, int)); 434static void do_input_reload PARAMS ((struct insn_chain *, 435 struct reload *, int)); 436static void do_output_reload PARAMS ((struct insn_chain *, 437 struct reload *, int)); 438static void emit_reload_insns PARAMS ((struct insn_chain *)); 439static void delete_output_reload PARAMS ((rtx, int, int)); 440static void delete_address_reloads PARAMS ((rtx, rtx)); 441static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx)); 442static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int)); 443static void reload_cse_regs_1 PARAMS ((rtx)); 444static int reload_cse_noop_set_p PARAMS ((rtx)); 445static int reload_cse_simplify_set PARAMS ((rtx, rtx)); 446static int reload_cse_simplify_operands PARAMS ((rtx, rtx)); 447static void reload_combine PARAMS ((void)); 448static void reload_combine_note_use PARAMS ((rtx *, rtx)); 449static void reload_combine_note_store PARAMS ((rtx, rtx, void *)); 450static void reload_cse_move2add PARAMS ((rtx)); 451static void move2add_note_store PARAMS ((rtx, rtx, void *)); 452#ifdef AUTO_INC_DEC 453static void add_auto_inc_notes PARAMS ((rtx, rtx)); 454#endif 455static void copy_eh_notes PARAMS ((rtx, rtx)); 456static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode, 457 HOST_WIDE_INT)); 458static void failed_reload PARAMS ((rtx, int)); 459static int set_reload_reg PARAMS ((int, int)); 460static void reload_cse_simplify PARAMS ((rtx, rtx)); 461void fixup_abnormal_edges PARAMS ((void)); 462extern void dump_needs PARAMS ((struct insn_chain *)); 463 464/* Initialize the reload pass once per compilation. */ 465 466void 467init_reload () 468{ 469 int i; 470 471 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. 472 Set spill_indirect_levels to the number of levels such addressing is 473 permitted, zero if it is not permitted at all. */ 474 475 rtx tem 476 = gen_rtx_MEM (Pmode, 477 gen_rtx_PLUS (Pmode, 478 gen_rtx_REG (Pmode, 479 LAST_VIRTUAL_REGISTER + 1), 480 GEN_INT (4))); 481 spill_indirect_levels = 0; 482 483 while (memory_address_p (QImode, tem)) 484 { 485 spill_indirect_levels++; 486 tem = gen_rtx_MEM (Pmode, tem); 487 } 488 489 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ 490 491 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); 492 indirect_symref_ok = memory_address_p (QImode, tem); 493 494 /* See if reg+reg is a valid (and offsettable) address. */ 495 496 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 497 { 498 tem = gen_rtx_PLUS (Pmode, 499 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), 500 gen_rtx_REG (Pmode, i)); 501 502 /* This way, we make sure that reg+reg is an offsettable address. */ 503 tem = plus_constant (tem, 4); 504 505 if (memory_address_p (QImode, tem)) 506 { 507 double_reg_address_ok = 1; 508 break; 509 } 510 } 511 512 /* Initialize obstack for our rtl allocation. */ 513 gcc_obstack_init (&reload_obstack); 514 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0); 515 516 INIT_REG_SET (&spilled_pseudos); 517 INIT_REG_SET (&pseudos_counted); 518} 519 520/* List of insn chains that are currently unused. */ 521static struct insn_chain *unused_insn_chains = 0; 522 523/* Allocate an empty insn_chain structure. */ 524struct insn_chain * 525new_insn_chain () 526{ 527 struct insn_chain *c; 528 529 if (unused_insn_chains == 0) 530 { 531 c = (struct insn_chain *) 532 obstack_alloc (&reload_obstack, sizeof (struct insn_chain)); 533 INIT_REG_SET (&c->live_throughout); 534 INIT_REG_SET (&c->dead_or_set); 535 } 536 else 537 { 538 c = unused_insn_chains; 539 unused_insn_chains = c->next; 540 } 541 c->is_caller_save_insn = 0; 542 c->need_operand_change = 0; 543 c->need_reload = 0; 544 c->need_elim = 0; 545 return c; 546} 547 548/* Small utility function to set all regs in hard reg set TO which are 549 allocated to pseudos in regset FROM. */ 550 551void 552compute_use_by_pseudos (to, from) 553 HARD_REG_SET *to; 554 regset from; 555{ 556 unsigned int regno; 557 558 EXECUTE_IF_SET_IN_REG_SET 559 (from, FIRST_PSEUDO_REGISTER, regno, 560 { 561 int r = reg_renumber[regno]; 562 int nregs; 563 564 if (r < 0) 565 { 566 /* reload_combine uses the information from 567 BASIC_BLOCK->global_live_at_start, which might still 568 contain registers that have not actually been allocated 569 since they have an equivalence. */ 570 if (! reload_completed) 571 abort (); 572 } 573 else 574 { 575 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno)); 576 while (nregs-- > 0) 577 SET_HARD_REG_BIT (*to, r + nregs); 578 } 579 }); 580} 581 582/* Replace all pseudos found in LOC with their corresponding 583 equivalences. */ 584 585static void 586replace_pseudos_in_call_usage (loc, mem_mode, usage) 587 rtx *loc; 588 enum machine_mode mem_mode; 589 rtx usage; 590{ 591 rtx x = *loc; 592 enum rtx_code code; 593 const char *fmt; 594 int i, j; 595 596 if (! x) 597 return; 598 599 code = GET_CODE (x); 600 if (code == REG) 601 { 602 unsigned int regno = REGNO (x); 603 604 if (regno < FIRST_PSEUDO_REGISTER) 605 return; 606 607 x = eliminate_regs (x, mem_mode, usage); 608 if (x != *loc) 609 { 610 *loc = x; 611 replace_pseudos_in_call_usage (loc, mem_mode, usage); 612 return; 613 } 614 615 if (reg_equiv_constant[regno]) 616 *loc = reg_equiv_constant[regno]; 617 else if (reg_equiv_mem[regno]) 618 *loc = reg_equiv_mem[regno]; 619 else if (reg_equiv_address[regno]) 620 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]); 621 else if (GET_CODE (regno_reg_rtx[regno]) != REG 622 || REGNO (regno_reg_rtx[regno]) != regno) 623 *loc = regno_reg_rtx[regno]; 624 else 625 abort (); 626 627 return; 628 } 629 else if (code == MEM) 630 { 631 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage); 632 return; 633 } 634 635 /* Process each of our operands recursively. */ 636 fmt = GET_RTX_FORMAT (code); 637 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 638 if (*fmt == 'e') 639 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage); 640 else if (*fmt == 'E') 641 for (j = 0; j < XVECLEN (x, i); j++) 642 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage); 643} 644 645 646/* Global variables used by reload and its subroutines. */ 647 648/* Set during calculate_needs if an insn needs register elimination. */ 649static int something_needs_elimination; 650/* Set during calculate_needs if an insn needs an operand changed. */ 651int something_needs_operands_changed; 652 653/* Nonzero means we couldn't get enough spill regs. */ 654static int failure; 655 656/* Main entry point for the reload pass. 657 658 FIRST is the first insn of the function being compiled. 659 660 GLOBAL nonzero means we were called from global_alloc 661 and should attempt to reallocate any pseudoregs that we 662 displace from hard regs we will use for reloads. 663 If GLOBAL is zero, we do not have enough information to do that, 664 so any pseudo reg that is spilled must go to the stack. 665 666 Return value is nonzero if reload failed 667 and we must not do any more for this function. */ 668 669int 670reload (first, global) 671 rtx first; 672 int global; 673{ 674 int i; 675 rtx insn; 676 struct elim_table *ep; 677 basic_block bb; 678 679 /* Make sure even insns with volatile mem refs are recognizable. */ 680 init_recog (); 681 682 failure = 0; 683 684 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); 685 686 /* Make sure that the last insn in the chain 687 is not something that needs reloading. */ 688 emit_note (NULL, NOTE_INSN_DELETED); 689 690 /* Enable find_equiv_reg to distinguish insns made by reload. */ 691 reload_first_uid = get_max_uid (); 692 693#ifdef SECONDARY_MEMORY_NEEDED 694 /* Initialize the secondary memory table. */ 695 clear_secondary_mem (); 696#endif 697 698 /* We don't have a stack slot for any spill reg yet. */ 699 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot); 700 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width); 701 702 /* Initialize the save area information for caller-save, in case some 703 are needed. */ 704 init_save_areas (); 705 706 /* Compute which hard registers are now in use 707 as homes for pseudo registers. 708 This is done here rather than (eg) in global_alloc 709 because this point is reached even if not optimizing. */ 710 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 711 mark_home_live (i); 712 713 /* A function that receives a nonlocal goto must save all call-saved 714 registers. */ 715 if (current_function_has_nonlocal_label) 716 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 717 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i)) 718 regs_ever_live[i] = 1; 719 720 /* Find all the pseudo registers that didn't get hard regs 721 but do have known equivalent constants or memory slots. 722 These include parameters (known equivalent to parameter slots) 723 and cse'd or loop-moved constant memory addresses. 724 725 Record constant equivalents in reg_equiv_constant 726 so they will be substituted by find_reloads. 727 Record memory equivalents in reg_mem_equiv so they can 728 be substituted eventually by altering the REG-rtx's. */ 729 730 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx)); 731 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx)); 732 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx)); 733 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx)); 734 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int)); 735 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short)); 736 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); 737 pseudo_forbidden_regs 738 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET)); 739 pseudo_previous_regs 740 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET)); 741 742 CLEAR_HARD_REG_SET (bad_spill_regs_global); 743 744 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to. 745 Also find all paradoxical subregs and find largest such for each pseudo. 746 On machines with small register classes, record hard registers that 747 are used for user variables. These can never be used for spills. 748 Also look for a "constant" REG_SETJMP. This means that all 749 caller-saved registers must be marked live. */ 750 751 num_eliminable_invariants = 0; 752 for (insn = first; insn; insn = NEXT_INSN (insn)) 753 { 754 rtx set = single_set (insn); 755 756 /* We may introduce USEs that we want to remove at the end, so 757 we'll mark them with QImode. Make sure there are no 758 previously-marked insns left by say regmove. */ 759 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE 760 && GET_MODE (insn) != VOIDmode) 761 PUT_MODE (insn, VOIDmode); 762 763 if (GET_CODE (insn) == CALL_INSN 764 && find_reg_note (insn, REG_SETJMP, NULL)) 765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 766 if (! call_used_regs[i]) 767 regs_ever_live[i] = 1; 768 769 if (set != 0 && GET_CODE (SET_DEST (set)) == REG) 770 { 771 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); 772 if (note 773#ifdef LEGITIMATE_PIC_OPERAND_P 774 && (! function_invariant_p (XEXP (note, 0)) 775 || ! flag_pic 776 /* A function invariant is often CONSTANT_P but may 777 include a register. We promise to only pass 778 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ 779 || (CONSTANT_P (XEXP (note, 0)) 780 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))) 781#endif 782 ) 783 { 784 rtx x = XEXP (note, 0); 785 i = REGNO (SET_DEST (set)); 786 if (i > LAST_VIRTUAL_REGISTER) 787 { 788 /* It can happen that a REG_EQUIV note contains a MEM 789 that is not a legitimate memory operand. As later 790 stages of reload assume that all addresses found 791 in the reg_equiv_* arrays were originally legitimate, 792 we ignore such REG_EQUIV notes. */ 793 if (memory_operand (x, VOIDmode)) 794 { 795 /* Always unshare the equivalence, so we can 796 substitute into this insn without touching the 797 equivalence. */ 798 reg_equiv_memory_loc[i] = copy_rtx (x); 799 } 800 else if (function_invariant_p (x)) 801 { 802 if (GET_CODE (x) == PLUS) 803 { 804 /* This is PLUS of frame pointer and a constant, 805 and might be shared. Unshare it. */ 806 reg_equiv_constant[i] = copy_rtx (x); 807 num_eliminable_invariants++; 808 } 809 else if (x == frame_pointer_rtx 810 || x == arg_pointer_rtx) 811 { 812 reg_equiv_constant[i] = x; 813 num_eliminable_invariants++; 814 } 815 else if (LEGITIMATE_CONSTANT_P (x)) 816 reg_equiv_constant[i] = x; 817 else 818 { 819 reg_equiv_memory_loc[i] 820 = force_const_mem (GET_MODE (SET_DEST (set)), x); 821 if (!reg_equiv_memory_loc[i]) 822 continue; 823 } 824 } 825 else 826 continue; 827 828 /* If this register is being made equivalent to a MEM 829 and the MEM is not SET_SRC, the equivalencing insn 830 is one with the MEM as a SET_DEST and it occurs later. 831 So don't mark this insn now. */ 832 if (GET_CODE (x) != MEM 833 || rtx_equal_p (SET_SRC (set), x)) 834 reg_equiv_init[i] 835 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]); 836 } 837 } 838 } 839 840 /* If this insn is setting a MEM from a register equivalent to it, 841 this is the equivalencing insn. */ 842 else if (set && GET_CODE (SET_DEST (set)) == MEM 843 && GET_CODE (SET_SRC (set)) == REG 844 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] 845 && rtx_equal_p (SET_DEST (set), 846 reg_equiv_memory_loc[REGNO (SET_SRC (set))])) 847 reg_equiv_init[REGNO (SET_SRC (set))] 848 = gen_rtx_INSN_LIST (VOIDmode, insn, 849 reg_equiv_init[REGNO (SET_SRC (set))]); 850 851 if (INSN_P (insn)) 852 scan_paradoxical_subregs (PATTERN (insn)); 853 } 854 855 init_elim_table (); 856 857 first_label_num = get_first_label_num (); 858 num_labels = max_label_num () - first_label_num; 859 860 /* Allocate the tables used to store offset information at labels. */ 861 /* We used to use alloca here, but the size of what it would try to 862 allocate would occasionally cause it to exceed the stack limit and 863 cause a core dump. */ 864 offsets_known_at = xmalloc (num_labels); 865 offsets_at 866 = (int (*)[NUM_ELIMINABLE_REGS]) 867 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int)); 868 869 /* Alter each pseudo-reg rtx to contain its hard reg number. 870 Assign stack slots to the pseudos that lack hard regs or equivalents. 871 Do not touch virtual registers. */ 872 873 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) 874 alter_reg (i, -1); 875 876 /* If we have some registers we think can be eliminated, scan all insns to 877 see if there is an insn that sets one of these registers to something 878 other than itself plus a constant. If so, the register cannot be 879 eliminated. Doing this scan here eliminates an extra pass through the 880 main reload loop in the most common case where register elimination 881 cannot be done. */ 882 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) 883 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN 884 || GET_CODE (insn) == CALL_INSN) 885 note_stores (PATTERN (insn), mark_not_eliminable, NULL); 886 887 maybe_fix_stack_asms (); 888 889 insns_need_reload = 0; 890 something_needs_elimination = 0; 891 892 /* Initialize to -1, which means take the first spill register. */ 893 last_spill_reg = -1; 894 895 /* Spill any hard regs that we know we can't eliminate. */ 896 CLEAR_HARD_REG_SET (used_spill_regs); 897 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 898 if (! ep->can_eliminate) 899 spill_hard_reg (ep->from, 1); 900 901#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 902 if (frame_pointer_needed) 903 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); 904#endif 905 finish_spills (global); 906 907 /* From now on, we may need to generate moves differently. We may also 908 allow modifications of insns which cause them to not be recognized. 909 Any such modifications will be cleaned up during reload itself. */ 910 reload_in_progress = 1; 911 912 /* This loop scans the entire function each go-round 913 and repeats until one repetition spills no additional hard regs. */ 914 for (;;) 915 { 916 int something_changed; 917 int did_spill; 918 919 HOST_WIDE_INT starting_frame_size; 920 921 /* Round size of stack frame to stack_alignment_needed. This must be done 922 here because the stack size may be a part of the offset computation 923 for register elimination, and there might have been new stack slots 924 created in the last iteration of this loop. */ 925 if (cfun->stack_alignment_needed) 926 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed); 927 928 starting_frame_size = get_frame_size (); 929 930 set_initial_elim_offsets (); 931 set_initial_label_offsets (); 932 933 /* For each pseudo register that has an equivalent location defined, 934 try to eliminate any eliminable registers (such as the frame pointer) 935 assuming initial offsets for the replacement register, which 936 is the normal case. 937 938 If the resulting location is directly addressable, substitute 939 the MEM we just got directly for the old REG. 940 941 If it is not addressable but is a constant or the sum of a hard reg 942 and constant, it is probably not addressable because the constant is 943 out of range, in that case record the address; we will generate 944 hairy code to compute the address in a register each time it is 945 needed. Similarly if it is a hard register, but one that is not 946 valid as an address register. 947 948 If the location is not addressable, but does not have one of the 949 above forms, assign a stack slot. We have to do this to avoid the 950 potential of producing lots of reloads if, e.g., a location involves 951 a pseudo that didn't get a hard register and has an equivalent memory 952 location that also involves a pseudo that didn't get a hard register. 953 954 Perhaps at some point we will improve reload_when_needed handling 955 so this problem goes away. But that's very hairy. */ 956 957 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 958 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i]) 959 { 960 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX); 961 962 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]), 963 XEXP (x, 0))) 964 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0; 965 else if (CONSTANT_P (XEXP (x, 0)) 966 || (GET_CODE (XEXP (x, 0)) == REG 967 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) 968 || (GET_CODE (XEXP (x, 0)) == PLUS 969 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG 970 && (REGNO (XEXP (XEXP (x, 0), 0)) 971 < FIRST_PSEUDO_REGISTER) 972 && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) 973 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0; 974 else 975 { 976 /* Make a new stack slot. Then indicate that something 977 changed so we go back and recompute offsets for 978 eliminable registers because the allocation of memory 979 below might change some offset. reg_equiv_{mem,address} 980 will be set up for this pseudo on the next pass around 981 the loop. */ 982 reg_equiv_memory_loc[i] = 0; 983 reg_equiv_init[i] = 0; 984 alter_reg (i, -1); 985 } 986 } 987 988 if (caller_save_needed) 989 setup_save_areas (); 990 991 /* If we allocated another stack slot, redo elimination bookkeeping. */ 992 if (starting_frame_size != get_frame_size ()) 993 continue; 994 995 if (caller_save_needed) 996 { 997 save_call_clobbered_regs (); 998 /* That might have allocated new insn_chain structures. */ 999 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0); 1000 } 1001 1002 calculate_needs_all_insns (global); 1003 1004 CLEAR_REG_SET (&spilled_pseudos); 1005 did_spill = 0; 1006 1007 something_changed = 0; 1008 1009 /* If we allocated any new memory locations, make another pass 1010 since it might have changed elimination offsets. */ 1011 if (starting_frame_size != get_frame_size ()) 1012 something_changed = 1; 1013 1014 { 1015 HARD_REG_SET to_spill; 1016 CLEAR_HARD_REG_SET (to_spill); 1017 update_eliminables (&to_spill); 1018 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1019 if (TEST_HARD_REG_BIT (to_spill, i)) 1020 { 1021 spill_hard_reg (i, 1); 1022 did_spill = 1; 1023 1024 /* Regardless of the state of spills, if we previously had 1025 a register that we thought we could eliminate, but now can 1026 not eliminate, we must run another pass. 1027 1028 Consider pseudos which have an entry in reg_equiv_* which 1029 reference an eliminable register. We must make another pass 1030 to update reg_equiv_* so that we do not substitute in the 1031 old value from when we thought the elimination could be 1032 performed. */ 1033 something_changed = 1; 1034 } 1035 } 1036 1037 select_reload_regs (); 1038 if (failure) 1039 goto failed; 1040 1041 if (insns_need_reload != 0 || did_spill) 1042 something_changed |= finish_spills (global); 1043 1044 if (! something_changed) 1045 break; 1046 1047 if (caller_save_needed) 1048 delete_caller_save_insns (); 1049 1050 obstack_free (&reload_obstack, reload_firstobj); 1051 } 1052 1053 /* If global-alloc was run, notify it of any register eliminations we have 1054 done. */ 1055 if (global) 1056 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 1057 if (ep->can_eliminate) 1058 mark_elimination (ep->from, ep->to); 1059 1060 /* If a pseudo has no hard reg, delete the insns that made the equivalence. 1061 If that insn didn't set the register (i.e., it copied the register to 1062 memory), just delete that insn instead of the equivalencing insn plus 1063 anything now dead. If we call delete_dead_insn on that insn, we may 1064 delete the insn that actually sets the register if the register dies 1065 there and that is incorrect. */ 1066 1067 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 1068 { 1069 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0) 1070 { 1071 rtx list; 1072 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1)) 1073 { 1074 rtx equiv_insn = XEXP (list, 0); 1075 1076 /* If we already deleted the insn or if it may trap, we can't 1077 delete it. The latter case shouldn't happen, but can 1078 if an insn has a variable address, gets a REG_EH_REGION 1079 note added to it, and then gets converted into an load 1080 from a constant address. */ 1081 if (GET_CODE (equiv_insn) == NOTE 1082 || can_throw_internal (equiv_insn)) 1083 ; 1084 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) 1085 delete_dead_insn (equiv_insn); 1086 else 1087 { 1088 PUT_CODE (equiv_insn, NOTE); 1089 NOTE_SOURCE_FILE (equiv_insn) = 0; 1090 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED; 1091 } 1092 } 1093 } 1094 } 1095 1096 /* Use the reload registers where necessary 1097 by generating move instructions to move the must-be-register 1098 values into or out of the reload registers. */ 1099 1100 if (insns_need_reload != 0 || something_needs_elimination 1101 || something_needs_operands_changed) 1102 { 1103 HOST_WIDE_INT old_frame_size = get_frame_size (); 1104 1105 reload_as_needed (global); 1106 1107 if (old_frame_size != get_frame_size ()) 1108 abort (); 1109 1110 if (num_eliminable) 1111 verify_initial_elim_offsets (); 1112 } 1113 1114 /* If we were able to eliminate the frame pointer, show that it is no 1115 longer live at the start of any basic block. If it ls live by 1116 virtue of being in a pseudo, that pseudo will be marked live 1117 and hence the frame pointer will be known to be live via that 1118 pseudo. */ 1119 1120 if (! frame_pointer_needed) 1121 FOR_EACH_BB (bb) 1122 CLEAR_REGNO_REG_SET (bb->global_live_at_start, 1123 HARD_FRAME_POINTER_REGNUM); 1124 1125 /* Come here (with failure set nonzero) if we can't get enough spill regs 1126 and we decide not to abort about it. */ 1127 failed: 1128 1129 CLEAR_REG_SET (&spilled_pseudos); 1130 reload_in_progress = 0; 1131 1132 /* Now eliminate all pseudo regs by modifying them into 1133 their equivalent memory references. 1134 The REG-rtx's for the pseudos are modified in place, 1135 so all insns that used to refer to them now refer to memory. 1136 1137 For a reg that has a reg_equiv_address, all those insns 1138 were changed by reloading so that no insns refer to it any longer; 1139 but the DECL_RTL of a variable decl may refer to it, 1140 and if so this causes the debugging info to mention the variable. */ 1141 1142 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 1143 { 1144 rtx addr = 0; 1145 1146 if (reg_equiv_mem[i]) 1147 addr = XEXP (reg_equiv_mem[i], 0); 1148 1149 if (reg_equiv_address[i]) 1150 addr = reg_equiv_address[i]; 1151 1152 if (addr) 1153 { 1154 if (reg_renumber[i] < 0) 1155 { 1156 rtx reg = regno_reg_rtx[i]; 1157 1158 REG_USERVAR_P (reg) = 0; 1159 PUT_CODE (reg, MEM); 1160 XEXP (reg, 0) = addr; 1161 if (reg_equiv_memory_loc[i]) 1162 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]); 1163 else 1164 { 1165 RTX_UNCHANGING_P (reg) = MEM_IN_STRUCT_P (reg) 1166 = MEM_SCALAR_P (reg) = 0; 1167 MEM_ATTRS (reg) = 0; 1168 } 1169 } 1170 else if (reg_equiv_mem[i]) 1171 XEXP (reg_equiv_mem[i], 0) = addr; 1172 } 1173 } 1174 1175 /* We must set reload_completed now since the cleanup_subreg_operands call 1176 below will re-recognize each insn and reload may have generated insns 1177 which are only valid during and after reload. */ 1178 reload_completed = 1; 1179 1180 /* Make a pass over all the insns and delete all USEs which we inserted 1181 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED 1182 notes. Delete all CLOBBER insns, except those that refer to the return 1183 value and the special mem:BLK CLOBBERs added to prevent the scheduler 1184 from misarranging variable-array code, and simplify (subreg (reg)) 1185 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they 1186 are no longer useful or accurate. Strip and regenerate REG_INC notes 1187 that may have been moved around. */ 1188 1189 for (insn = first; insn; insn = NEXT_INSN (insn)) 1190 if (INSN_P (insn)) 1191 { 1192 rtx *pnote; 1193 1194 if (GET_CODE (insn) == CALL_INSN) 1195 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn), 1196 VOIDmode, 1197 CALL_INSN_FUNCTION_USAGE (insn)); 1198 1199 if ((GET_CODE (PATTERN (insn)) == USE 1200 /* We mark with QImode USEs introduced by reload itself. */ 1201 && (GET_MODE (insn) == QImode 1202 || find_reg_note (insn, REG_EQUAL, NULL_RTX))) 1203 || (GET_CODE (PATTERN (insn)) == CLOBBER 1204 && (GET_CODE (XEXP (PATTERN (insn), 0)) != MEM 1205 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode 1206 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH 1207 && XEXP (XEXP (PATTERN (insn), 0), 0) 1208 != stack_pointer_rtx)) 1209 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG 1210 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) 1211 { 1212 delete_insn (insn); 1213 continue; 1214 } 1215 1216 pnote = ®_NOTES (insn); 1217 while (*pnote != 0) 1218 { 1219 if (REG_NOTE_KIND (*pnote) == REG_DEAD 1220 || REG_NOTE_KIND (*pnote) == REG_UNUSED 1221 || REG_NOTE_KIND (*pnote) == REG_INC 1222 || REG_NOTE_KIND (*pnote) == REG_RETVAL 1223 || REG_NOTE_KIND (*pnote) == REG_LIBCALL) 1224 *pnote = XEXP (*pnote, 1); 1225 else 1226 pnote = &XEXP (*pnote, 1); 1227 } 1228 1229#ifdef AUTO_INC_DEC 1230 add_auto_inc_notes (insn, PATTERN (insn)); 1231#endif 1232 1233 /* And simplify (subreg (reg)) if it appears as an operand. */ 1234 cleanup_subreg_operands (insn); 1235 } 1236 1237 /* If we are doing stack checking, give a warning if this function's 1238 frame size is larger than we expect. */ 1239 if (flag_stack_check && ! STACK_CHECK_BUILTIN) 1240 { 1241 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; 1242 static int verbose_warned = 0; 1243 1244 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1245 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i]) 1246 size += UNITS_PER_WORD; 1247 1248 if (size > STACK_CHECK_MAX_FRAME_SIZE) 1249 { 1250 warning ("frame size too large for reliable stack checking"); 1251 if (! verbose_warned) 1252 { 1253 warning ("try reducing the number of local variables"); 1254 verbose_warned = 1; 1255 } 1256 } 1257 } 1258 1259 /* Indicate that we no longer have known memory locations or constants. */ 1260 if (reg_equiv_constant) 1261 free (reg_equiv_constant); 1262 reg_equiv_constant = 0; 1263 if (reg_equiv_memory_loc) 1264 free (reg_equiv_memory_loc); 1265 reg_equiv_memory_loc = 0; 1266 1267 if (offsets_known_at) 1268 free (offsets_known_at); 1269 if (offsets_at) 1270 free (offsets_at); 1271 1272 free (reg_equiv_mem); 1273 free (reg_equiv_init); 1274 free (reg_equiv_address); 1275 free (reg_max_ref_width); 1276 free (reg_old_renumber); 1277 free (pseudo_previous_regs); 1278 free (pseudo_forbidden_regs); 1279 1280 CLEAR_HARD_REG_SET (used_spill_regs); 1281 for (i = 0; i < n_spills; i++) 1282 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); 1283 1284 /* Free all the insn_chain structures at once. */ 1285 obstack_free (&reload_obstack, reload_startobj); 1286 unused_insn_chains = 0; 1287 fixup_abnormal_edges (); 1288 1289 /* Replacing pseudos with their memory equivalents might have 1290 created shared rtx. Subsequent passes would get confused 1291 by this, so unshare everything here. */ 1292 unshare_all_rtl_again (first); 1293 1294 return failure; 1295} 1296 1297/* Yet another special case. Unfortunately, reg-stack forces people to 1298 write incorrect clobbers in asm statements. These clobbers must not 1299 cause the register to appear in bad_spill_regs, otherwise we'll call 1300 fatal_insn later. We clear the corresponding regnos in the live 1301 register sets to avoid this. 1302 The whole thing is rather sick, I'm afraid. */ 1303 1304static void 1305maybe_fix_stack_asms () 1306{ 1307#ifdef STACK_REGS 1308 const char *constraints[MAX_RECOG_OPERANDS]; 1309 enum machine_mode operand_mode[MAX_RECOG_OPERANDS]; 1310 struct insn_chain *chain; 1311 1312 for (chain = reload_insn_chain; chain != 0; chain = chain->next) 1313 { 1314 int i, noperands; 1315 HARD_REG_SET clobbered, allowed; 1316 rtx pat; 1317 1318 if (! INSN_P (chain->insn) 1319 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) 1320 continue; 1321 pat = PATTERN (chain->insn); 1322 if (GET_CODE (pat) != PARALLEL) 1323 continue; 1324 1325 CLEAR_HARD_REG_SET (clobbered); 1326 CLEAR_HARD_REG_SET (allowed); 1327 1328 /* First, make a mask of all stack regs that are clobbered. */ 1329 for (i = 0; i < XVECLEN (pat, 0); i++) 1330 { 1331 rtx t = XVECEXP (pat, 0, i); 1332 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) 1333 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); 1334 } 1335 1336 /* Get the operand values and constraints out of the insn. */ 1337 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, 1338 constraints, operand_mode); 1339 1340 /* For every operand, see what registers are allowed. */ 1341 for (i = 0; i < noperands; i++) 1342 { 1343 const char *p = constraints[i]; 1344 /* For every alternative, we compute the class of registers allowed 1345 for reloading in CLS, and merge its contents into the reg set 1346 ALLOWED. */ 1347 int cls = (int) NO_REGS; 1348 1349 for (;;) 1350 { 1351 char c = *p++; 1352 1353 if (c == '\0' || c == ',' || c == '#') 1354 { 1355 /* End of one alternative - mark the regs in the current 1356 class, and reset the class. */ 1357 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]); 1358 cls = NO_REGS; 1359 if (c == '#') 1360 do { 1361 c = *p++; 1362 } while (c != '\0' && c != ','); 1363 if (c == '\0') 1364 break; 1365 continue; 1366 } 1367 1368 switch (c) 1369 { 1370 case '=': case '+': case '*': case '%': case '?': case '!': 1371 case '0': case '1': case '2': case '3': case '4': case 'm': 1372 case '<': case '>': case 'V': case 'o': case '&': case 'E': 1373 case 'F': case 's': case 'i': case 'n': case 'X': case 'I': 1374 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': 1375 case 'P': 1376 break; 1377 1378 case 'p': 1379 cls = (int) reg_class_subunion[cls] 1380 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1381 break; 1382 1383 case 'g': 1384 case 'r': 1385 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; 1386 break; 1387 1388 default: 1389 if (EXTRA_ADDRESS_CONSTRAINT (c)) 1390 cls = (int) reg_class_subunion[cls] 1391 [(int) MODE_BASE_REG_CLASS (VOIDmode)]; 1392 else 1393 cls = (int) reg_class_subunion[cls] 1394 [(int) REG_CLASS_FROM_LETTER (c)]; 1395 } 1396 } 1397 } 1398 /* Those of the registers which are clobbered, but allowed by the 1399 constraints, must be usable as reload registers. So clear them 1400 out of the life information. */ 1401 AND_HARD_REG_SET (allowed, clobbered); 1402 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1403 if (TEST_HARD_REG_BIT (allowed, i)) 1404 { 1405 CLEAR_REGNO_REG_SET (&chain->live_throughout, i); 1406 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); 1407 } 1408 } 1409 1410#endif 1411} 1412 1413/* Copy the global variables n_reloads and rld into the corresponding elts 1414 of CHAIN. */ 1415static void 1416copy_reloads (chain) 1417 struct insn_chain *chain; 1418{ 1419 chain->n_reloads = n_reloads; 1420 chain->rld 1421 = (struct reload *) obstack_alloc (&reload_obstack, 1422 n_reloads * sizeof (struct reload)); 1423 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); 1424 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); 1425} 1426 1427/* Walk the chain of insns, and determine for each whether it needs reloads 1428 and/or eliminations. Build the corresponding insns_need_reload list, and 1429 set something_needs_elimination as appropriate. */ 1430static void 1431calculate_needs_all_insns (global) 1432 int global; 1433{ 1434 struct insn_chain **pprev_reload = &insns_need_reload; 1435 struct insn_chain *chain, *next = 0; 1436 1437 something_needs_elimination = 0; 1438 1439 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0); 1440 for (chain = reload_insn_chain; chain != 0; chain = next) 1441 { 1442 rtx insn = chain->insn; 1443 1444 next = chain->next; 1445 1446 /* Clear out the shortcuts. */ 1447 chain->n_reloads = 0; 1448 chain->need_elim = 0; 1449 chain->need_reload = 0; 1450 chain->need_operand_change = 0; 1451 1452 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might 1453 include REG_LABEL), we need to see what effects this has on the 1454 known offsets at labels. */ 1455 1456 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN 1457 || (INSN_P (insn) && REG_NOTES (insn) != 0)) 1458 set_label_offsets (insn, insn, 0); 1459 1460 if (INSN_P (insn)) 1461 { 1462 rtx old_body = PATTERN (insn); 1463 int old_code = INSN_CODE (insn); 1464 rtx old_notes = REG_NOTES (insn); 1465 int did_elimination = 0; 1466 int operands_changed = 0; 1467 rtx set = single_set (insn); 1468 1469 /* Skip insns that only set an equivalence. */ 1470 if (set && GET_CODE (SET_DEST (set)) == REG 1471 && reg_renumber[REGNO (SET_DEST (set))] < 0 1472 && reg_equiv_constant[REGNO (SET_DEST (set))]) 1473 continue; 1474 1475 /* If needed, eliminate any eliminable registers. */ 1476 if (num_eliminable || num_eliminable_invariants) 1477 did_elimination = eliminate_regs_in_insn (insn, 0); 1478 1479 /* Analyze the instruction. */ 1480 operands_changed = find_reloads (insn, 0, spill_indirect_levels, 1481 global, spill_reg_order); 1482 1483 /* If a no-op set needs more than one reload, this is likely 1484 to be something that needs input address reloads. We 1485 can't get rid of this cleanly later, and it is of no use 1486 anyway, so discard it now. 1487 We only do this when expensive_optimizations is enabled, 1488 since this complements reload inheritance / output 1489 reload deletion, and it can make debugging harder. */ 1490 if (flag_expensive_optimizations && n_reloads > 1) 1491 { 1492 rtx set = single_set (insn); 1493 if (set 1494 && SET_SRC (set) == SET_DEST (set) 1495 && GET_CODE (SET_SRC (set)) == REG 1496 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) 1497 { 1498 delete_insn (insn); 1499 /* Delete it from the reload chain. */ 1500 if (chain->prev) 1501 chain->prev->next = next; 1502 else 1503 reload_insn_chain = next; 1504 if (next) 1505 next->prev = chain->prev; 1506 chain->next = unused_insn_chains; 1507 unused_insn_chains = chain; 1508 continue; 1509 } 1510 } 1511 if (num_eliminable) 1512 update_eliminable_offsets (); 1513 1514 /* Remember for later shortcuts which insns had any reloads or 1515 register eliminations. */ 1516 chain->need_elim = did_elimination; 1517 chain->need_reload = n_reloads > 0; 1518 chain->need_operand_change = operands_changed; 1519 1520 /* Discard any register replacements done. */ 1521 if (did_elimination) 1522 { 1523 obstack_free (&reload_obstack, reload_insn_firstobj); 1524 PATTERN (insn) = old_body; 1525 INSN_CODE (insn) = old_code; 1526 REG_NOTES (insn) = old_notes; 1527 something_needs_elimination = 1; 1528 } 1529 1530 something_needs_operands_changed |= operands_changed; 1531 1532 if (n_reloads != 0) 1533 { 1534 copy_reloads (chain); 1535 *pprev_reload = chain; 1536 pprev_reload = &chain->next_need_reload; 1537 } 1538 } 1539 } 1540 *pprev_reload = 0; 1541} 1542 1543/* Comparison function for qsort to decide which of two reloads 1544 should be handled first. *P1 and *P2 are the reload numbers. */ 1545 1546static int 1547reload_reg_class_lower (r1p, r2p) 1548 const PTR r1p; 1549 const PTR r2p; 1550{ 1551 int r1 = *(const short *) r1p, r2 = *(const short *) r2p; 1552 int t; 1553 1554 /* Consider required reloads before optional ones. */ 1555 t = rld[r1].optional - rld[r2].optional; 1556 if (t != 0) 1557 return t; 1558 1559 /* Count all solitary classes before non-solitary ones. */ 1560 t = ((reg_class_size[(int) rld[r2].class] == 1) 1561 - (reg_class_size[(int) rld[r1].class] == 1)); 1562 if (t != 0) 1563 return t; 1564 1565 /* Aside from solitaires, consider all multi-reg groups first. */ 1566 t = rld[r2].nregs - rld[r1].nregs; 1567 if (t != 0) 1568 return t; 1569 1570 /* Consider reloads in order of increasing reg-class number. */ 1571 t = (int) rld[r1].class - (int) rld[r2].class; 1572 if (t != 0) 1573 return t; 1574 1575 /* If reloads are equally urgent, sort by reload number, 1576 so that the results of qsort leave nothing to chance. */ 1577 return r1 - r2; 1578} 1579 1580/* The cost of spilling each hard reg. */ 1581static int spill_cost[FIRST_PSEUDO_REGISTER]; 1582 1583/* When spilling multiple hard registers, we use SPILL_COST for the first 1584 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST 1585 only the first hard reg for a multi-reg pseudo. */ 1586static int spill_add_cost[FIRST_PSEUDO_REGISTER]; 1587 1588/* Update the spill cost arrays, considering that pseudo REG is live. */ 1589 1590static void 1591count_pseudo (reg) 1592 int reg; 1593{ 1594 int freq = REG_FREQ (reg); 1595 int r = reg_renumber[reg]; 1596 int nregs; 1597 1598 if (REGNO_REG_SET_P (&pseudos_counted, reg) 1599 || REGNO_REG_SET_P (&spilled_pseudos, reg)) 1600 return; 1601 1602 SET_REGNO_REG_SET (&pseudos_counted, reg); 1603 1604 if (r < 0) 1605 abort (); 1606 1607 spill_add_cost[r] += freq; 1608 1609 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); 1610 while (nregs-- > 0) 1611 spill_cost[r + nregs] += freq; 1612} 1613 1614/* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the 1615 contents of BAD_SPILL_REGS for the insn described by CHAIN. */ 1616 1617static void 1618order_regs_for_reload (chain) 1619 struct insn_chain *chain; 1620{ 1621 int i; 1622 HARD_REG_SET used_by_pseudos; 1623 HARD_REG_SET used_by_pseudos2; 1624 1625 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set); 1626 1627 memset (spill_cost, 0, sizeof spill_cost); 1628 memset (spill_add_cost, 0, sizeof spill_add_cost); 1629 1630 /* Count number of uses of each hard reg by pseudo regs allocated to it 1631 and then order them by decreasing use. First exclude hard registers 1632 that are live in or across this insn. */ 1633 1634 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); 1635 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); 1636 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos); 1637 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2); 1638 1639 /* Now find out which pseudos are allocated to it, and update 1640 hard_reg_n_uses. */ 1641 CLEAR_REG_SET (&pseudos_counted); 1642 1643 EXECUTE_IF_SET_IN_REG_SET 1644 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, 1645 { 1646 count_pseudo (i); 1647 }); 1648 EXECUTE_IF_SET_IN_REG_SET 1649 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, 1650 { 1651 count_pseudo (i); 1652 }); 1653 CLEAR_REG_SET (&pseudos_counted); 1654} 1655 1656/* Vector of reload-numbers showing the order in which the reloads should 1657 be processed. */ 1658static short reload_order[MAX_RELOADS]; 1659 1660/* This is used to keep track of the spill regs used in one insn. */ 1661static HARD_REG_SET used_spill_regs_local; 1662 1663/* We decided to spill hard register SPILLED, which has a size of 1664 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, 1665 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will 1666 update SPILL_COST/SPILL_ADD_COST. */ 1667 1668static void 1669count_spilled_pseudo (spilled, spilled_nregs, reg) 1670 int spilled, spilled_nregs, reg; 1671{ 1672 int r = reg_renumber[reg]; 1673 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg)); 1674 1675 if (REGNO_REG_SET_P (&spilled_pseudos, reg) 1676 || spilled + spilled_nregs <= r || r + nregs <= spilled) 1677 return; 1678 1679 SET_REGNO_REG_SET (&spilled_pseudos, reg); 1680 1681 spill_add_cost[r] -= REG_FREQ (reg); 1682 while (nregs-- > 0) 1683 spill_cost[r + nregs] -= REG_FREQ (reg); 1684} 1685 1686/* Find reload register to use for reload number ORDER. */ 1687 1688static int 1689find_reg (chain, order) 1690 struct insn_chain *chain; 1691 int order; 1692{ 1693 int rnum = reload_order[order]; 1694 struct reload *rl = rld + rnum; 1695 int best_cost = INT_MAX; 1696 int best_reg = -1; 1697 unsigned int i, j; 1698 int k; 1699 HARD_REG_SET not_usable; 1700 HARD_REG_SET used_by_other_reload; 1701 1702 COPY_HARD_REG_SET (not_usable, bad_spill_regs); 1703 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global); 1704 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]); 1705 1706 CLEAR_HARD_REG_SET (used_by_other_reload); 1707 for (k = 0; k < order; k++) 1708 { 1709 int other = reload_order[k]; 1710 1711 if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) 1712 for (j = 0; j < rld[other].nregs; j++) 1713 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); 1714 } 1715 1716 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1717 { 1718 unsigned int regno = i; 1719 1720 if (! TEST_HARD_REG_BIT (not_usable, regno) 1721 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) 1722 && HARD_REGNO_MODE_OK (regno, rl->mode)) 1723 { 1724 int this_cost = spill_cost[regno]; 1725 int ok = 1; 1726 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode); 1727 1728 for (j = 1; j < this_nregs; j++) 1729 { 1730 this_cost += spill_add_cost[regno + j]; 1731 if ((TEST_HARD_REG_BIT (not_usable, regno + j)) 1732 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) 1733 ok = 0; 1734 } 1735 if (! ok) 1736 continue; 1737 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno) 1738 this_cost--; 1739 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno) 1740 this_cost--; 1741 if (this_cost < best_cost 1742 /* Among registers with equal cost, prefer caller-saved ones, or 1743 use REG_ALLOC_ORDER if it is defined. */ 1744 || (this_cost == best_cost 1745#ifdef REG_ALLOC_ORDER 1746 && (inv_reg_alloc_order[regno] 1747 < inv_reg_alloc_order[best_reg]) 1748#else 1749 && call_used_regs[regno] 1750 && ! call_used_regs[best_reg] 1751#endif 1752 )) 1753 { 1754 best_reg = regno; 1755 best_cost = this_cost; 1756 } 1757 } 1758 } 1759 if (best_reg == -1) 1760 return 0; 1761 1762 if (rtl_dump_file) 1763 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum); 1764 1765 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode); 1766 rl->regno = best_reg; 1767 1768 EXECUTE_IF_SET_IN_REG_SET 1769 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, 1770 { 1771 count_spilled_pseudo (best_reg, rl->nregs, j); 1772 }); 1773 1774 EXECUTE_IF_SET_IN_REG_SET 1775 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, 1776 { 1777 count_spilled_pseudo (best_reg, rl->nregs, j); 1778 }); 1779 1780 for (i = 0; i < rl->nregs; i++) 1781 { 1782 if (spill_cost[best_reg + i] != 0 1783 || spill_add_cost[best_reg + i] != 0) 1784 abort (); 1785 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); 1786 } 1787 return 1; 1788} 1789 1790/* Find more reload regs to satisfy the remaining need of an insn, which 1791 is given by CHAIN. 1792 Do it by ascending class number, since otherwise a reg 1793 might be spilled for a big class and might fail to count 1794 for a smaller class even though it belongs to that class. */ 1795 1796static void 1797find_reload_regs (chain) 1798 struct insn_chain *chain; 1799{ 1800 int i; 1801 1802 /* In order to be certain of getting the registers we need, 1803 we must sort the reloads into order of increasing register class. 1804 Then our grabbing of reload registers will parallel the process 1805 that provided the reload registers. */ 1806 for (i = 0; i < chain->n_reloads; i++) 1807 { 1808 /* Show whether this reload already has a hard reg. */ 1809 if (chain->rld[i].reg_rtx) 1810 { 1811 int regno = REGNO (chain->rld[i].reg_rtx); 1812 chain->rld[i].regno = regno; 1813 chain->rld[i].nregs 1814 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx)); 1815 } 1816 else 1817 chain->rld[i].regno = -1; 1818 reload_order[i] = i; 1819 } 1820 1821 n_reloads = chain->n_reloads; 1822 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); 1823 1824 CLEAR_HARD_REG_SET (used_spill_regs_local); 1825 1826 if (rtl_dump_file) 1827 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); 1828 1829 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); 1830 1831 /* Compute the order of preference for hard registers to spill. */ 1832 1833 order_regs_for_reload (chain); 1834 1835 for (i = 0; i < n_reloads; i++) 1836 { 1837 int r = reload_order[i]; 1838 1839 /* Ignore reloads that got marked inoperative. */ 1840 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) 1841 && ! rld[r].optional 1842 && rld[r].regno == -1) 1843 if (! find_reg (chain, i)) 1844 { 1845 spill_failure (chain->insn, rld[r].class); 1846 failure = 1; 1847 return; 1848 } 1849 } 1850 1851 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local); 1852 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local); 1853 1854 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); 1855} 1856 1857static void 1858select_reload_regs () 1859{ 1860 struct insn_chain *chain; 1861 1862 /* Try to satisfy the needs for each insn. */ 1863 for (chain = insns_need_reload; chain != 0; 1864 chain = chain->next_need_reload) 1865 find_reload_regs (chain); 1866} 1867 1868/* Delete all insns that were inserted by emit_caller_save_insns during 1869 this iteration. */ 1870static void 1871delete_caller_save_insns () 1872{ 1873 struct insn_chain *c = reload_insn_chain; 1874 1875 while (c != 0) 1876 { 1877 while (c != 0 && c->is_caller_save_insn) 1878 { 1879 struct insn_chain *next = c->next; 1880 rtx insn = c->insn; 1881 1882 if (c == reload_insn_chain) 1883 reload_insn_chain = next; 1884 delete_insn (insn); 1885 1886 if (next) 1887 next->prev = c->prev; 1888 if (c->prev) 1889 c->prev->next = next; 1890 c->next = unused_insn_chains; 1891 unused_insn_chains = c; 1892 c = next; 1893 } 1894 if (c != 0) 1895 c = c->next; 1896 } 1897} 1898 1899/* Handle the failure to find a register to spill. 1900 INSN should be one of the insns which needed this particular spill reg. */ 1901 1902static void 1903spill_failure (insn, class) 1904 rtx insn; 1905 enum reg_class class; 1906{ 1907 static const char *const reg_class_names[] = REG_CLASS_NAMES; 1908 if (asm_noperands (PATTERN (insn)) >= 0) 1909 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'", 1910 reg_class_names[class]); 1911 else 1912 { 1913 error ("unable to find a register to spill in class `%s'", 1914 reg_class_names[class]); 1915 fatal_insn ("this is the insn:", insn); 1916 } 1917} 1918 1919/* Delete an unneeded INSN and any previous insns who sole purpose is loading 1920 data that is dead in INSN. */ 1921 1922static void 1923delete_dead_insn (insn) 1924 rtx insn; 1925{ 1926 rtx prev = prev_real_insn (insn); 1927 rtx prev_dest; 1928 1929 /* If the previous insn sets a register that dies in our insn, delete it 1930 too. */ 1931 if (prev && GET_CODE (PATTERN (prev)) == SET 1932 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG) 1933 && reg_mentioned_p (prev_dest, PATTERN (insn)) 1934 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) 1935 && ! side_effects_p (SET_SRC (PATTERN (prev)))) 1936 delete_dead_insn (prev); 1937 1938 PUT_CODE (insn, NOTE); 1939 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED; 1940 NOTE_SOURCE_FILE (insn) = 0; 1941} 1942 1943/* Modify the home of pseudo-reg I. 1944 The new home is present in reg_renumber[I]. 1945 1946 FROM_REG may be the hard reg that the pseudo-reg is being spilled from; 1947 or it may be -1, meaning there is none or it is not relevant. 1948 This is used so that all pseudos spilled from a given hard reg 1949 can share one stack slot. */ 1950 1951static void 1952alter_reg (i, from_reg) 1953 int i; 1954 int from_reg; 1955{ 1956 /* When outputting an inline function, this can happen 1957 for a reg that isn't actually used. */ 1958 if (regno_reg_rtx[i] == 0) 1959 return; 1960 1961 /* If the reg got changed to a MEM at rtl-generation time, 1962 ignore it. */ 1963 if (GET_CODE (regno_reg_rtx[i]) != REG) 1964 return; 1965 1966 /* Modify the reg-rtx to contain the new hard reg 1967 number or else to contain its pseudo reg number. */ 1968 REGNO (regno_reg_rtx[i]) 1969 = reg_renumber[i] >= 0 ? reg_renumber[i] : i; 1970 1971 /* If we have a pseudo that is needed but has no hard reg or equivalent, 1972 allocate a stack slot for it. */ 1973 1974 if (reg_renumber[i] < 0 1975 && REG_N_REFS (i) > 0 1976 && reg_equiv_constant[i] == 0 1977 && reg_equiv_memory_loc[i] == 0) 1978 { 1979 rtx x; 1980 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i); 1981 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]); 1982 int adjust = 0; 1983 1984 /* Each pseudo reg has an inherent size which comes from its own mode, 1985 and a total size which provides room for paradoxical subregs 1986 which refer to the pseudo reg in wider modes. 1987 1988 We can use a slot already allocated if it provides both 1989 enough inherent space and enough total space. 1990 Otherwise, we allocate a new slot, making sure that it has no less 1991 inherent space, and no less total space, then the previous slot. */ 1992 if (from_reg == -1) 1993 { 1994 /* No known place to spill from => no slot to reuse. */ 1995 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size, 1996 inherent_size == total_size ? 0 : -1); 1997 if (BYTES_BIG_ENDIAN) 1998 /* Cancel the big-endian correction done in assign_stack_local. 1999 Get the address of the beginning of the slot. 2000 This is so we can do a big-endian correction unconditionally 2001 below. */ 2002 adjust = inherent_size - total_size; 2003 2004 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]); 2005 2006 /* Nothing can alias this slot except this pseudo. */ 2007 set_mem_alias_set (x, new_alias_set ()); 2008 } 2009 2010 /* Reuse a stack slot if possible. */ 2011 else if (spill_stack_slot[from_reg] != 0 2012 && spill_stack_slot_width[from_reg] >= total_size 2013 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) 2014 >= inherent_size)) 2015 x = spill_stack_slot[from_reg]; 2016 2017 /* Allocate a bigger slot. */ 2018 else 2019 { 2020 /* Compute maximum size needed, both for inherent size 2021 and for total size. */ 2022 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]); 2023 rtx stack_slot; 2024 2025 if (spill_stack_slot[from_reg]) 2026 { 2027 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg])) 2028 > inherent_size) 2029 mode = GET_MODE (spill_stack_slot[from_reg]); 2030 if (spill_stack_slot_width[from_reg] > total_size) 2031 total_size = spill_stack_slot_width[from_reg]; 2032 } 2033 2034 /* Make a slot with that size. */ 2035 x = assign_stack_local (mode, total_size, 2036 inherent_size == total_size ? 0 : -1); 2037 stack_slot = x; 2038 2039 /* All pseudos mapped to this slot can alias each other. */ 2040 if (spill_stack_slot[from_reg]) 2041 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg])); 2042 else 2043 set_mem_alias_set (x, new_alias_set ()); 2044 2045 if (BYTES_BIG_ENDIAN) 2046 { 2047 /* Cancel the big-endian correction done in assign_stack_local. 2048 Get the address of the beginning of the slot. 2049 This is so we can do a big-endian correction unconditionally 2050 below. */ 2051 adjust = GET_MODE_SIZE (mode) - total_size; 2052 if (adjust) 2053 stack_slot 2054 = adjust_address_nv (x, mode_for_size (total_size 2055 * BITS_PER_UNIT, 2056 MODE_INT, 1), 2057 adjust); 2058 } 2059 2060 spill_stack_slot[from_reg] = stack_slot; 2061 spill_stack_slot_width[from_reg] = total_size; 2062 } 2063 2064 /* On a big endian machine, the "address" of the slot 2065 is the address of the low part that fits its inherent mode. */ 2066 if (BYTES_BIG_ENDIAN && inherent_size < total_size) 2067 adjust += (total_size - inherent_size); 2068 2069 /* If we have any adjustment to make, or if the stack slot is the 2070 wrong mode, make a new stack slot. */ 2071 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); 2072 2073 /* If we have a decl for the original register, set it for the 2074 memory. If this is a shared MEM, make a copy. */ 2075 if (REGNO_DECL (i)) 2076 { 2077 rtx decl = DECL_RTL_IF_SET (REGNO_DECL (i)); 2078 2079 /* We can do this only for the DECLs home pseudo, not for 2080 any copies of it, since otherwise when the stack slot 2081 is reused, nonoverlapping_memrefs_p might think they 2082 cannot overlap. */ 2083 if (decl && GET_CODE (decl) == REG && REGNO (decl) == (unsigned) i) 2084 { 2085 if (from_reg != -1 && spill_stack_slot[from_reg] == x) 2086 x = copy_rtx (x); 2087 2088 set_mem_expr (x, REGNO_DECL (i)); 2089 } 2090 } 2091 2092 /* Save the stack slot for later. */ 2093 reg_equiv_memory_loc[i] = x; 2094 } 2095} 2096 2097/* Mark the slots in regs_ever_live for the hard regs 2098 used by pseudo-reg number REGNO. */ 2099 2100void 2101mark_home_live (regno) 2102 int regno; 2103{ 2104 int i, lim; 2105 2106 i = reg_renumber[regno]; 2107 if (i < 0) 2108 return; 2109 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno)); 2110 while (i < lim) 2111 regs_ever_live[i++] = 1; 2112} 2113 2114/* This function handles the tracking of elimination offsets around branches. 2115 2116 X is a piece of RTL being scanned. 2117 2118 INSN is the insn that it came from, if any. 2119 2120 INITIAL_P is nonzero if we are to set the offset to be the initial 2121 offset and zero if we are setting the offset of the label to be the 2122 current offset. */ 2123 2124static void 2125set_label_offsets (x, insn, initial_p) 2126 rtx x; 2127 rtx insn; 2128 int initial_p; 2129{ 2130 enum rtx_code code = GET_CODE (x); 2131 rtx tem; 2132 unsigned int i; 2133 struct elim_table *p; 2134 2135 switch (code) 2136 { 2137 case LABEL_REF: 2138 if (LABEL_REF_NONLOCAL_P (x)) 2139 return; 2140 2141 x = XEXP (x, 0); 2142 2143 /* ... fall through ... */ 2144 2145 case CODE_LABEL: 2146 /* If we know nothing about this label, set the desired offsets. Note 2147 that this sets the offset at a label to be the offset before a label 2148 if we don't know anything about the label. This is not correct for 2149 the label after a BARRIER, but is the best guess we can make. If 2150 we guessed wrong, we will suppress an elimination that might have 2151 been possible had we been able to guess correctly. */ 2152 2153 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num]) 2154 { 2155 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2156 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] 2157 = (initial_p ? reg_eliminate[i].initial_offset 2158 : reg_eliminate[i].offset); 2159 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1; 2160 } 2161 2162 /* Otherwise, if this is the definition of a label and it is 2163 preceded by a BARRIER, set our offsets to the known offset of 2164 that label. */ 2165 2166 else if (x == insn 2167 && (tem = prev_nonnote_insn (insn)) != 0 2168 && GET_CODE (tem) == BARRIER) 2169 set_offsets_for_label (insn); 2170 else 2171 /* If neither of the above cases is true, compare each offset 2172 with those previously recorded and suppress any eliminations 2173 where the offsets disagree. */ 2174 2175 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2176 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] 2177 != (initial_p ? reg_eliminate[i].initial_offset 2178 : reg_eliminate[i].offset)) 2179 reg_eliminate[i].can_eliminate = 0; 2180 2181 return; 2182 2183 case JUMP_INSN: 2184 set_label_offsets (PATTERN (insn), insn, initial_p); 2185 2186 /* ... fall through ... */ 2187 2188 case INSN: 2189 case CALL_INSN: 2190 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly 2191 and hence must have all eliminations at their initial offsets. */ 2192 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) 2193 if (REG_NOTE_KIND (tem) == REG_LABEL) 2194 set_label_offsets (XEXP (tem, 0), insn, 1); 2195 return; 2196 2197 case PARALLEL: 2198 case ADDR_VEC: 2199 case ADDR_DIFF_VEC: 2200 /* Each of the labels in the parallel or address vector must be 2201 at their initial offsets. We want the first field for PARALLEL 2202 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ 2203 2204 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) 2205 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), 2206 insn, initial_p); 2207 return; 2208 2209 case SET: 2210 /* We only care about setting PC. If the source is not RETURN, 2211 IF_THEN_ELSE, or a label, disable any eliminations not at 2212 their initial offsets. Similarly if any arm of the IF_THEN_ELSE 2213 isn't one of those possibilities. For branches to a label, 2214 call ourselves recursively. 2215 2216 Note that this can disable elimination unnecessarily when we have 2217 a non-local goto since it will look like a non-constant jump to 2218 someplace in the current function. This isn't a significant 2219 problem since such jumps will normally be when all elimination 2220 pairs are back to their initial offsets. */ 2221 2222 if (SET_DEST (x) != pc_rtx) 2223 return; 2224 2225 switch (GET_CODE (SET_SRC (x))) 2226 { 2227 case PC: 2228 case RETURN: 2229 return; 2230 2231 case LABEL_REF: 2232 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p); 2233 return; 2234 2235 case IF_THEN_ELSE: 2236 tem = XEXP (SET_SRC (x), 1); 2237 if (GET_CODE (tem) == LABEL_REF) 2238 set_label_offsets (XEXP (tem, 0), insn, initial_p); 2239 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) 2240 break; 2241 2242 tem = XEXP (SET_SRC (x), 2); 2243 if (GET_CODE (tem) == LABEL_REF) 2244 set_label_offsets (XEXP (tem, 0), insn, initial_p); 2245 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) 2246 break; 2247 return; 2248 2249 default: 2250 break; 2251 } 2252 2253 /* If we reach here, all eliminations must be at their initial 2254 offset because we are doing a jump to a variable address. */ 2255 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) 2256 if (p->offset != p->initial_offset) 2257 p->can_eliminate = 0; 2258 break; 2259 2260 default: 2261 break; 2262 } 2263} 2264 2265/* Scan X and replace any eliminable registers (such as fp) with a 2266 replacement (such as sp), plus an offset. 2267 2268 MEM_MODE is the mode of an enclosing MEM. We need this to know how 2269 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a 2270 MEM, we are allowed to replace a sum of a register and the constant zero 2271 with the register, which we cannot do outside a MEM. In addition, we need 2272 to record the fact that a register is referenced outside a MEM. 2273 2274 If INSN is an insn, it is the insn containing X. If we replace a REG 2275 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a 2276 CLOBBER of the pseudo after INSN so find_equiv_regs will know that 2277 the REG is being modified. 2278 2279 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). 2280 That's used when we eliminate in expressions stored in notes. 2281 This means, do not set ref_outside_mem even if the reference 2282 is outside of MEMs. 2283 2284 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had 2285 replacements done assuming all offsets are at their initial values. If 2286 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we 2287 encounter, return the actual location so that find_reloads will do 2288 the proper thing. */ 2289 2290rtx 2291eliminate_regs (x, mem_mode, insn) 2292 rtx x; 2293 enum machine_mode mem_mode; 2294 rtx insn; 2295{ 2296 enum rtx_code code = GET_CODE (x); 2297 struct elim_table *ep; 2298 int regno; 2299 rtx new; 2300 int i, j; 2301 const char *fmt; 2302 int copied = 0; 2303 2304 if (! current_function_decl) 2305 return x; 2306 2307 switch (code) 2308 { 2309 case CONST_INT: 2310 case CONST_DOUBLE: 2311 case CONST_VECTOR: 2312 case CONST: 2313 case SYMBOL_REF: 2314 case CODE_LABEL: 2315 case PC: 2316 case CC0: 2317 case ASM_INPUT: 2318 case ADDR_VEC: 2319 case ADDR_DIFF_VEC: 2320 case RETURN: 2321 return x; 2322 2323 case ADDRESSOF: 2324 /* This is only for the benefit of the debugging backends, which call 2325 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are 2326 removed after CSE. */ 2327 new = eliminate_regs (XEXP (x, 0), 0, insn); 2328 if (GET_CODE (new) == MEM) 2329 return XEXP (new, 0); 2330 return x; 2331 2332 case REG: 2333 regno = REGNO (x); 2334 2335 /* First handle the case where we encounter a bare register that 2336 is eliminable. Replace it with a PLUS. */ 2337 if (regno < FIRST_PSEUDO_REGISTER) 2338 { 2339 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2340 ep++) 2341 if (ep->from_rtx == x && ep->can_eliminate) 2342 return plus_constant (ep->to_rtx, ep->previous_offset); 2343 2344 } 2345 else if (reg_renumber && reg_renumber[regno] < 0 2346 && reg_equiv_constant && reg_equiv_constant[regno] 2347 && ! CONSTANT_P (reg_equiv_constant[regno])) 2348 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]), 2349 mem_mode, insn); 2350 return x; 2351 2352 /* You might think handling MINUS in a manner similar to PLUS is a 2353 good idea. It is not. It has been tried multiple times and every 2354 time the change has had to have been reverted. 2355 2356 Other parts of reload know a PLUS is special (gen_reload for example) 2357 and require special code to handle code a reloaded PLUS operand. 2358 2359 Also consider backends where the flags register is clobbered by a 2360 MINUS, but we can emit a PLUS that does not clobber flags (ia32, 2361 lea instruction comes to mind). If we try to reload a MINUS, we 2362 may kill the flags register that was holding a useful value. 2363 2364 So, please before trying to handle MINUS, consider reload as a 2365 whole instead of this little section as well as the backend issues. */ 2366 case PLUS: 2367 /* If this is the sum of an eliminable register and a constant, rework 2368 the sum. */ 2369 if (GET_CODE (XEXP (x, 0)) == REG 2370 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 2371 && CONSTANT_P (XEXP (x, 1))) 2372 { 2373 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2374 ep++) 2375 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) 2376 { 2377 /* The only time we want to replace a PLUS with a REG (this 2378 occurs when the constant operand of the PLUS is the negative 2379 of the offset) is when we are inside a MEM. We won't want 2380 to do so at other times because that would change the 2381 structure of the insn in a way that reload can't handle. 2382 We special-case the commonest situation in 2383 eliminate_regs_in_insn, so just replace a PLUS with a 2384 PLUS here, unless inside a MEM. */ 2385 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT 2386 && INTVAL (XEXP (x, 1)) == - ep->previous_offset) 2387 return ep->to_rtx; 2388 else 2389 return gen_rtx_PLUS (Pmode, ep->to_rtx, 2390 plus_constant (XEXP (x, 1), 2391 ep->previous_offset)); 2392 } 2393 2394 /* If the register is not eliminable, we are done since the other 2395 operand is a constant. */ 2396 return x; 2397 } 2398 2399 /* If this is part of an address, we want to bring any constant to the 2400 outermost PLUS. We will do this by doing register replacement in 2401 our operands and seeing if a constant shows up in one of them. 2402 2403 Note that there is no risk of modifying the structure of the insn, 2404 since we only get called for its operands, thus we are either 2405 modifying the address inside a MEM, or something like an address 2406 operand of a load-address insn. */ 2407 2408 { 2409 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2410 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn); 2411 2412 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) 2413 { 2414 /* If one side is a PLUS and the other side is a pseudo that 2415 didn't get a hard register but has a reg_equiv_constant, 2416 we must replace the constant here since it may no longer 2417 be in the position of any operand. */ 2418 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG 2419 && REGNO (new1) >= FIRST_PSEUDO_REGISTER 2420 && reg_renumber[REGNO (new1)] < 0 2421 && reg_equiv_constant != 0 2422 && reg_equiv_constant[REGNO (new1)] != 0) 2423 new1 = reg_equiv_constant[REGNO (new1)]; 2424 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG 2425 && REGNO (new0) >= FIRST_PSEUDO_REGISTER 2426 && reg_renumber[REGNO (new0)] < 0 2427 && reg_equiv_constant[REGNO (new0)] != 0) 2428 new0 = reg_equiv_constant[REGNO (new0)]; 2429 2430 new = form_sum (new0, new1); 2431 2432 /* As above, if we are not inside a MEM we do not want to 2433 turn a PLUS into something else. We might try to do so here 2434 for an addition of 0 if we aren't optimizing. */ 2435 if (! mem_mode && GET_CODE (new) != PLUS) 2436 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx); 2437 else 2438 return new; 2439 } 2440 } 2441 return x; 2442 2443 case MULT: 2444 /* If this is the product of an eliminable register and a 2445 constant, apply the distribute law and move the constant out 2446 so that we have (plus (mult ..) ..). This is needed in order 2447 to keep load-address insns valid. This case is pathological. 2448 We ignore the possibility of overflow here. */ 2449 if (GET_CODE (XEXP (x, 0)) == REG 2450 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 2451 && GET_CODE (XEXP (x, 1)) == CONST_INT) 2452 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2453 ep++) 2454 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) 2455 { 2456 if (! mem_mode 2457 /* Refs inside notes don't count for this purpose. */ 2458 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST 2459 || GET_CODE (insn) == INSN_LIST))) 2460 ep->ref_outside_mem = 1; 2461 2462 return 2463 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), 2464 ep->previous_offset * INTVAL (XEXP (x, 1))); 2465 } 2466 2467 /* ... fall through ... */ 2468 2469 case CALL: 2470 case COMPARE: 2471 /* See comments before PLUS about handling MINUS. */ 2472 case MINUS: 2473 case DIV: case UDIV: 2474 case MOD: case UMOD: 2475 case AND: case IOR: case XOR: 2476 case ROTATERT: case ROTATE: 2477 case ASHIFTRT: case LSHIFTRT: case ASHIFT: 2478 case NE: case EQ: 2479 case GE: case GT: case GEU: case GTU: 2480 case LE: case LT: case LEU: case LTU: 2481 { 2482 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2483 rtx new1 2484 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0; 2485 2486 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) 2487 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); 2488 } 2489 return x; 2490 2491 case EXPR_LIST: 2492 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ 2493 if (XEXP (x, 0)) 2494 { 2495 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2496 if (new != XEXP (x, 0)) 2497 { 2498 /* If this is a REG_DEAD note, it is not valid anymore. 2499 Using the eliminated version could result in creating a 2500 REG_DEAD note for the stack or frame pointer. */ 2501 if (GET_MODE (x) == REG_DEAD) 2502 return (XEXP (x, 1) 2503 ? eliminate_regs (XEXP (x, 1), mem_mode, insn) 2504 : NULL_RTX); 2505 2506 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1)); 2507 } 2508 } 2509 2510 /* ... fall through ... */ 2511 2512 case INSN_LIST: 2513 /* Now do eliminations in the rest of the chain. If this was 2514 an EXPR_LIST, this might result in allocating more memory than is 2515 strictly needed, but it simplifies the code. */ 2516 if (XEXP (x, 1)) 2517 { 2518 new = eliminate_regs (XEXP (x, 1), mem_mode, insn); 2519 if (new != XEXP (x, 1)) 2520 return 2521 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new); 2522 } 2523 return x; 2524 2525 case PRE_INC: 2526 case POST_INC: 2527 case PRE_DEC: 2528 case POST_DEC: 2529 case STRICT_LOW_PART: 2530 case NEG: case NOT: 2531 case SIGN_EXTEND: case ZERO_EXTEND: 2532 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: 2533 case FLOAT: case FIX: 2534 case UNSIGNED_FIX: case UNSIGNED_FLOAT: 2535 case ABS: 2536 case SQRT: 2537 case FFS: 2538 new = eliminate_regs (XEXP (x, 0), mem_mode, insn); 2539 if (new != XEXP (x, 0)) 2540 return gen_rtx_fmt_e (code, GET_MODE (x), new); 2541 return x; 2542 2543 case SUBREG: 2544 /* Similar to above processing, but preserve SUBREG_BYTE. 2545 Convert (subreg (mem)) to (mem) if not paradoxical. 2546 Also, if we have a non-paradoxical (subreg (pseudo)) and the 2547 pseudo didn't get a hard reg, we must replace this with the 2548 eliminated version of the memory location because push_reloads 2549 may do the replacement in certain circumstances. */ 2550 if (GET_CODE (SUBREG_REG (x)) == REG 2551 && (GET_MODE_SIZE (GET_MODE (x)) 2552 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 2553 && reg_equiv_memory_loc != 0 2554 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) 2555 { 2556 new = SUBREG_REG (x); 2557 } 2558 else 2559 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn); 2560 2561 if (new != SUBREG_REG (x)) 2562 { 2563 int x_size = GET_MODE_SIZE (GET_MODE (x)); 2564 int new_size = GET_MODE_SIZE (GET_MODE (new)); 2565 2566 if (GET_CODE (new) == MEM 2567 && ((x_size < new_size 2568#ifdef WORD_REGISTER_OPERATIONS 2569 /* On these machines, combine can create rtl of the form 2570 (set (subreg:m1 (reg:m2 R) 0) ...) 2571 where m1 < m2, and expects something interesting to 2572 happen to the entire word. Moreover, it will use the 2573 (reg:m2 R) later, expecting all bits to be preserved. 2574 So if the number of words is the same, preserve the 2575 subreg so that push_reloads can see it. */ 2576 && ! ((x_size - 1) / UNITS_PER_WORD 2577 == (new_size -1 ) / UNITS_PER_WORD) 2578#endif 2579 ) 2580 || x_size == new_size) 2581 ) 2582 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x)); 2583 else 2584 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x)); 2585 } 2586 2587 return x; 2588 2589 case MEM: 2590 /* This is only for the benefit of the debugging backends, which call 2591 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are 2592 removed after CSE. */ 2593 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) 2594 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn); 2595 2596 /* Our only special processing is to pass the mode of the MEM to our 2597 recursive call and copy the flags. While we are here, handle this 2598 case more efficiently. */ 2599 return 2600 replace_equiv_address_nv (x, 2601 eliminate_regs (XEXP (x, 0), 2602 GET_MODE (x), insn)); 2603 2604 case USE: 2605 /* Handle insn_list USE that a call to a pure function may generate. */ 2606 new = eliminate_regs (XEXP (x, 0), 0, insn); 2607 if (new != XEXP (x, 0)) 2608 return gen_rtx_USE (GET_MODE (x), new); 2609 return x; 2610 2611 case CLOBBER: 2612 case ASM_OPERANDS: 2613 case SET: 2614 abort (); 2615 2616 default: 2617 break; 2618 } 2619 2620 /* Process each of our operands recursively. If any have changed, make a 2621 copy of the rtx. */ 2622 fmt = GET_RTX_FORMAT (code); 2623 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 2624 { 2625 if (*fmt == 'e') 2626 { 2627 new = eliminate_regs (XEXP (x, i), mem_mode, insn); 2628 if (new != XEXP (x, i) && ! copied) 2629 { 2630 rtx new_x = rtx_alloc (code); 2631 memcpy (new_x, x, 2632 (sizeof (*new_x) - sizeof (new_x->fld) 2633 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code))); 2634 x = new_x; 2635 copied = 1; 2636 } 2637 XEXP (x, i) = new; 2638 } 2639 else if (*fmt == 'E') 2640 { 2641 int copied_vec = 0; 2642 for (j = 0; j < XVECLEN (x, i); j++) 2643 { 2644 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn); 2645 if (new != XVECEXP (x, i, j) && ! copied_vec) 2646 { 2647 rtvec new_v = gen_rtvec_v (XVECLEN (x, i), 2648 XVEC (x, i)->elem); 2649 if (! copied) 2650 { 2651 rtx new_x = rtx_alloc (code); 2652 memcpy (new_x, x, 2653 (sizeof (*new_x) - sizeof (new_x->fld) 2654 + (sizeof (new_x->fld[0]) 2655 * GET_RTX_LENGTH (code)))); 2656 x = new_x; 2657 copied = 1; 2658 } 2659 XVEC (x, i) = new_v; 2660 copied_vec = 1; 2661 } 2662 XVECEXP (x, i, j) = new; 2663 } 2664 } 2665 } 2666 2667 return x; 2668} 2669 2670/* Scan rtx X for modifications of elimination target registers. Update 2671 the table of eliminables to reflect the changed state. MEM_MODE is 2672 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ 2673 2674static void 2675elimination_effects (x, mem_mode) 2676 rtx x; 2677 enum machine_mode mem_mode; 2678 2679{ 2680 enum rtx_code code = GET_CODE (x); 2681 struct elim_table *ep; 2682 int regno; 2683 int i, j; 2684 const char *fmt; 2685 2686 switch (code) 2687 { 2688 case CONST_INT: 2689 case CONST_DOUBLE: 2690 case CONST_VECTOR: 2691 case CONST: 2692 case SYMBOL_REF: 2693 case CODE_LABEL: 2694 case PC: 2695 case CC0: 2696 case ASM_INPUT: 2697 case ADDR_VEC: 2698 case ADDR_DIFF_VEC: 2699 case RETURN: 2700 return; 2701 2702 case ADDRESSOF: 2703 abort (); 2704 2705 case REG: 2706 regno = REGNO (x); 2707 2708 /* First handle the case where we encounter a bare register that 2709 is eliminable. Replace it with a PLUS. */ 2710 if (regno < FIRST_PSEUDO_REGISTER) 2711 { 2712 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2713 ep++) 2714 if (ep->from_rtx == x && ep->can_eliminate) 2715 { 2716 if (! mem_mode) 2717 ep->ref_outside_mem = 1; 2718 return; 2719 } 2720 2721 } 2722 else if (reg_renumber[regno] < 0 && reg_equiv_constant 2723 && reg_equiv_constant[regno] 2724 && ! function_invariant_p (reg_equiv_constant[regno])) 2725 elimination_effects (reg_equiv_constant[regno], mem_mode); 2726 return; 2727 2728 case PRE_INC: 2729 case POST_INC: 2730 case PRE_DEC: 2731 case POST_DEC: 2732 case POST_MODIFY: 2733 case PRE_MODIFY: 2734 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2735 if (ep->to_rtx == XEXP (x, 0)) 2736 { 2737 int size = GET_MODE_SIZE (mem_mode); 2738 2739 /* If more bytes than MEM_MODE are pushed, account for them. */ 2740#ifdef PUSH_ROUNDING 2741 if (ep->to_rtx == stack_pointer_rtx) 2742 size = PUSH_ROUNDING (size); 2743#endif 2744 if (code == PRE_DEC || code == POST_DEC) 2745 ep->offset += size; 2746 else if (code == PRE_INC || code == POST_INC) 2747 ep->offset -= size; 2748 else if ((code == PRE_MODIFY || code == POST_MODIFY) 2749 && GET_CODE (XEXP (x, 1)) == PLUS 2750 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) 2751 && CONSTANT_P (XEXP (XEXP (x, 1), 1))) 2752 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); 2753 } 2754 2755 /* These two aren't unary operators. */ 2756 if (code == POST_MODIFY || code == PRE_MODIFY) 2757 break; 2758 2759 /* Fall through to generic unary operation case. */ 2760 case STRICT_LOW_PART: 2761 case NEG: case NOT: 2762 case SIGN_EXTEND: case ZERO_EXTEND: 2763 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: 2764 case FLOAT: case FIX: 2765 case UNSIGNED_FIX: case UNSIGNED_FLOAT: 2766 case ABS: 2767 case SQRT: 2768 case FFS: 2769 elimination_effects (XEXP (x, 0), mem_mode); 2770 return; 2771 2772 case SUBREG: 2773 if (GET_CODE (SUBREG_REG (x)) == REG 2774 && (GET_MODE_SIZE (GET_MODE (x)) 2775 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 2776 && reg_equiv_memory_loc != 0 2777 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0) 2778 return; 2779 2780 elimination_effects (SUBREG_REG (x), mem_mode); 2781 return; 2782 2783 case USE: 2784 /* If using a register that is the source of an eliminate we still 2785 think can be performed, note it cannot be performed since we don't 2786 know how this register is used. */ 2787 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2788 if (ep->from_rtx == XEXP (x, 0)) 2789 ep->can_eliminate = 0; 2790 2791 elimination_effects (XEXP (x, 0), mem_mode); 2792 return; 2793 2794 case CLOBBER: 2795 /* If clobbering a register that is the replacement register for an 2796 elimination we still think can be performed, note that it cannot 2797 be performed. Otherwise, we need not be concerned about it. */ 2798 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2799 if (ep->to_rtx == XEXP (x, 0)) 2800 ep->can_eliminate = 0; 2801 2802 elimination_effects (XEXP (x, 0), mem_mode); 2803 return; 2804 2805 case SET: 2806 /* Check for setting a register that we know about. */ 2807 if (GET_CODE (SET_DEST (x)) == REG) 2808 { 2809 /* See if this is setting the replacement register for an 2810 elimination. 2811 2812 If DEST is the hard frame pointer, we do nothing because we 2813 assume that all assignments to the frame pointer are for 2814 non-local gotos and are being done at a time when they are valid 2815 and do not disturb anything else. Some machines want to 2816 eliminate a fake argument pointer (or even a fake frame pointer) 2817 with either the real frame or the stack pointer. Assignments to 2818 the hard frame pointer must not prevent this elimination. */ 2819 2820 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2821 ep++) 2822 if (ep->to_rtx == SET_DEST (x) 2823 && SET_DEST (x) != hard_frame_pointer_rtx) 2824 { 2825 /* If it is being incremented, adjust the offset. Otherwise, 2826 this elimination can't be done. */ 2827 rtx src = SET_SRC (x); 2828 2829 if (GET_CODE (src) == PLUS 2830 && XEXP (src, 0) == SET_DEST (x) 2831 && GET_CODE (XEXP (src, 1)) == CONST_INT) 2832 ep->offset -= INTVAL (XEXP (src, 1)); 2833 else 2834 ep->can_eliminate = 0; 2835 } 2836 } 2837 2838 elimination_effects (SET_DEST (x), 0); 2839 elimination_effects (SET_SRC (x), 0); 2840 return; 2841 2842 case MEM: 2843 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF) 2844 abort (); 2845 2846 /* Our only special processing is to pass the mode of the MEM to our 2847 recursive call. */ 2848 elimination_effects (XEXP (x, 0), GET_MODE (x)); 2849 return; 2850 2851 default: 2852 break; 2853 } 2854 2855 fmt = GET_RTX_FORMAT (code); 2856 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 2857 { 2858 if (*fmt == 'e') 2859 elimination_effects (XEXP (x, i), mem_mode); 2860 else if (*fmt == 'E') 2861 for (j = 0; j < XVECLEN (x, i); j++) 2862 elimination_effects (XVECEXP (x, i, j), mem_mode); 2863 } 2864} 2865 2866/* Descend through rtx X and verify that no references to eliminable registers 2867 remain. If any do remain, mark the involved register as not 2868 eliminable. */ 2869 2870static void 2871check_eliminable_occurrences (x) 2872 rtx x; 2873{ 2874 const char *fmt; 2875 int i; 2876 enum rtx_code code; 2877 2878 if (x == 0) 2879 return; 2880 2881 code = GET_CODE (x); 2882 2883 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) 2884 { 2885 struct elim_table *ep; 2886 2887 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2888 if (ep->from_rtx == x && ep->can_eliminate) 2889 ep->can_eliminate = 0; 2890 return; 2891 } 2892 2893 fmt = GET_RTX_FORMAT (code); 2894 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 2895 { 2896 if (*fmt == 'e') 2897 check_eliminable_occurrences (XEXP (x, i)); 2898 else if (*fmt == 'E') 2899 { 2900 int j; 2901 for (j = 0; j < XVECLEN (x, i); j++) 2902 check_eliminable_occurrences (XVECEXP (x, i, j)); 2903 } 2904 } 2905} 2906 2907/* Scan INSN and eliminate all eliminable registers in it. 2908 2909 If REPLACE is nonzero, do the replacement destructively. Also 2910 delete the insn as dead it if it is setting an eliminable register. 2911 2912 If REPLACE is zero, do all our allocations in reload_obstack. 2913 2914 If no eliminations were done and this insn doesn't require any elimination 2915 processing (these are not identical conditions: it might be updating sp, 2916 but not referencing fp; this needs to be seen during reload_as_needed so 2917 that the offset between fp and sp can be taken into consideration), zero 2918 is returned. Otherwise, 1 is returned. */ 2919 2920static int 2921eliminate_regs_in_insn (insn, replace) 2922 rtx insn; 2923 int replace; 2924{ 2925 int icode = recog_memoized (insn); 2926 rtx old_body = PATTERN (insn); 2927 int insn_is_asm = asm_noperands (old_body) >= 0; 2928 rtx old_set = single_set (insn); 2929 rtx new_body; 2930 int val = 0; 2931 int i, any_changes; 2932 rtx substed_operand[MAX_RECOG_OPERANDS]; 2933 rtx orig_operand[MAX_RECOG_OPERANDS]; 2934 struct elim_table *ep; 2935 2936 if (! insn_is_asm && icode < 0) 2937 { 2938 if (GET_CODE (PATTERN (insn)) == USE 2939 || GET_CODE (PATTERN (insn)) == CLOBBER 2940 || GET_CODE (PATTERN (insn)) == ADDR_VEC 2941 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC 2942 || GET_CODE (PATTERN (insn)) == ASM_INPUT) 2943 return 0; 2944 abort (); 2945 } 2946 2947 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG 2948 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) 2949 { 2950 /* Check for setting an eliminable register. */ 2951 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 2952 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) 2953 { 2954#if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM 2955 /* If this is setting the frame pointer register to the 2956 hardware frame pointer register and this is an elimination 2957 that will be done (tested above), this insn is really 2958 adjusting the frame pointer downward to compensate for 2959 the adjustment done before a nonlocal goto. */ 2960 if (ep->from == FRAME_POINTER_REGNUM 2961 && ep->to == HARD_FRAME_POINTER_REGNUM) 2962 { 2963 rtx base = SET_SRC (old_set); 2964 rtx base_insn = insn; 2965 int offset = 0; 2966 2967 while (base != ep->to_rtx) 2968 { 2969 rtx prev_insn, prev_set; 2970 2971 if (GET_CODE (base) == PLUS 2972 && GET_CODE (XEXP (base, 1)) == CONST_INT) 2973 { 2974 offset += INTVAL (XEXP (base, 1)); 2975 base = XEXP (base, 0); 2976 } 2977 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0 2978 && (prev_set = single_set (prev_insn)) != 0 2979 && rtx_equal_p (SET_DEST (prev_set), base)) 2980 { 2981 base = SET_SRC (prev_set); 2982 base_insn = prev_insn; 2983 } 2984 else 2985 break; 2986 } 2987 2988 if (base == ep->to_rtx) 2989 { 2990 rtx src 2991 = plus_constant (ep->to_rtx, offset - ep->offset); 2992 2993 new_body = old_body; 2994 if (! replace) 2995 { 2996 new_body = copy_insn (old_body); 2997 if (REG_NOTES (insn)) 2998 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); 2999 } 3000 PATTERN (insn) = new_body; 3001 old_set = single_set (insn); 3002 3003 /* First see if this insn remains valid when we 3004 make the change. If not, keep the INSN_CODE 3005 the same and let reload fit it up. */ 3006 validate_change (insn, &SET_SRC (old_set), src, 1); 3007 validate_change (insn, &SET_DEST (old_set), 3008 ep->to_rtx, 1); 3009 if (! apply_change_group ()) 3010 { 3011 SET_SRC (old_set) = src; 3012 SET_DEST (old_set) = ep->to_rtx; 3013 } 3014 3015 val = 1; 3016 goto done; 3017 } 3018 } 3019#endif 3020 3021 /* In this case this insn isn't serving a useful purpose. We 3022 will delete it in reload_as_needed once we know that this 3023 elimination is, in fact, being done. 3024 3025 If REPLACE isn't set, we can't delete this insn, but needn't 3026 process it since it won't be used unless something changes. */ 3027 if (replace) 3028 { 3029 delete_dead_insn (insn); 3030 return 1; 3031 } 3032 val = 1; 3033 goto done; 3034 } 3035 } 3036 3037 /* We allow one special case which happens to work on all machines we 3038 currently support: a single set with the source being a PLUS of an 3039 eliminable register and a constant. */ 3040 if (old_set 3041 && GET_CODE (SET_DEST (old_set)) == REG 3042 && GET_CODE (SET_SRC (old_set)) == PLUS 3043 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG 3044 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT 3045 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER) 3046 { 3047 rtx reg = XEXP (SET_SRC (old_set), 0); 3048 int offset = INTVAL (XEXP (SET_SRC (old_set), 1)); 3049 3050 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3051 if (ep->from_rtx == reg && ep->can_eliminate) 3052 { 3053 offset += ep->offset; 3054 3055 if (offset == 0) 3056 { 3057 int num_clobbers; 3058 /* We assume here that if we need a PARALLEL with 3059 CLOBBERs for this assignment, we can do with the 3060 MATCH_SCRATCHes that add_clobbers allocates. 3061 There's not much we can do if that doesn't work. */ 3062 PATTERN (insn) = gen_rtx_SET (VOIDmode, 3063 SET_DEST (old_set), 3064 ep->to_rtx); 3065 num_clobbers = 0; 3066 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers); 3067 if (num_clobbers) 3068 { 3069 rtvec vec = rtvec_alloc (num_clobbers + 1); 3070 3071 vec->elem[0] = PATTERN (insn); 3072 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec); 3073 add_clobbers (PATTERN (insn), INSN_CODE (insn)); 3074 } 3075 if (INSN_CODE (insn) < 0) 3076 abort (); 3077 } 3078 else 3079 { 3080 new_body = old_body; 3081 if (! replace) 3082 { 3083 new_body = copy_insn (old_body); 3084 if (REG_NOTES (insn)) 3085 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); 3086 } 3087 PATTERN (insn) = new_body; 3088 old_set = single_set (insn); 3089 3090 XEXP (SET_SRC (old_set), 0) = ep->to_rtx; 3091 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset); 3092 } 3093 val = 1; 3094 /* This can't have an effect on elimination offsets, so skip right 3095 to the end. */ 3096 goto done; 3097 } 3098 } 3099 3100 /* Determine the effects of this insn on elimination offsets. */ 3101 elimination_effects (old_body, 0); 3102 3103 /* Eliminate all eliminable registers occurring in operands that 3104 can be handled by reload. */ 3105 extract_insn (insn); 3106 any_changes = 0; 3107 for (i = 0; i < recog_data.n_operands; i++) 3108 { 3109 orig_operand[i] = recog_data.operand[i]; 3110 substed_operand[i] = recog_data.operand[i]; 3111 3112 /* For an asm statement, every operand is eliminable. */ 3113 if (insn_is_asm || insn_data[icode].operand[i].eliminable) 3114 { 3115 /* Check for setting a register that we know about. */ 3116 if (recog_data.operand_type[i] != OP_IN 3117 && GET_CODE (orig_operand[i]) == REG) 3118 { 3119 /* If we are assigning to a register that can be eliminated, it 3120 must be as part of a PARALLEL, since the code above handles 3121 single SETs. We must indicate that we can no longer 3122 eliminate this reg. */ 3123 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3124 ep++) 3125 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate) 3126 ep->can_eliminate = 0; 3127 } 3128 3129 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0, 3130 replace ? insn : NULL_RTX); 3131 if (substed_operand[i] != orig_operand[i]) 3132 val = any_changes = 1; 3133 /* Terminate the search in check_eliminable_occurrences at 3134 this point. */ 3135 *recog_data.operand_loc[i] = 0; 3136 3137 /* If an output operand changed from a REG to a MEM and INSN is an 3138 insn, write a CLOBBER insn. */ 3139 if (recog_data.operand_type[i] != OP_IN 3140 && GET_CODE (orig_operand[i]) == REG 3141 && GET_CODE (substed_operand[i]) == MEM 3142 && replace) 3143 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]), 3144 insn); 3145 } 3146 } 3147 3148 for (i = 0; i < recog_data.n_dups; i++) 3149 *recog_data.dup_loc[i] 3150 = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; 3151 3152 /* If any eliminable remain, they aren't eliminable anymore. */ 3153 check_eliminable_occurrences (old_body); 3154 3155 /* Substitute the operands; the new values are in the substed_operand 3156 array. */ 3157 for (i = 0; i < recog_data.n_operands; i++) 3158 *recog_data.operand_loc[i] = substed_operand[i]; 3159 for (i = 0; i < recog_data.n_dups; i++) 3160 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; 3161 3162 /* If we are replacing a body that was a (set X (plus Y Z)), try to 3163 re-recognize the insn. We do this in case we had a simple addition 3164 but now can do this as a load-address. This saves an insn in this 3165 common case. 3166 If re-recognition fails, the old insn code number will still be used, 3167 and some register operands may have changed into PLUS expressions. 3168 These will be handled by find_reloads by loading them into a register 3169 again. */ 3170 3171 if (val) 3172 { 3173 /* If we aren't replacing things permanently and we changed something, 3174 make another copy to ensure that all the RTL is new. Otherwise 3175 things can go wrong if find_reload swaps commutative operands 3176 and one is inside RTL that has been copied while the other is not. */ 3177 new_body = old_body; 3178 if (! replace) 3179 { 3180 new_body = copy_insn (old_body); 3181 if (REG_NOTES (insn)) 3182 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); 3183 } 3184 PATTERN (insn) = new_body; 3185 3186 /* If we had a move insn but now we don't, rerecognize it. This will 3187 cause spurious re-recognition if the old move had a PARALLEL since 3188 the new one still will, but we can't call single_set without 3189 having put NEW_BODY into the insn and the re-recognition won't 3190 hurt in this rare case. */ 3191 /* ??? Why this huge if statement - why don't we just rerecognize the 3192 thing always? */ 3193 if (! insn_is_asm 3194 && old_set != 0 3195 && ((GET_CODE (SET_SRC (old_set)) == REG 3196 && (GET_CODE (new_body) != SET 3197 || GET_CODE (SET_SRC (new_body)) != REG)) 3198 /* If this was a load from or store to memory, compare 3199 the MEM in recog_data.operand to the one in the insn. 3200 If they are not equal, then rerecognize the insn. */ 3201 || (old_set != 0 3202 && ((GET_CODE (SET_SRC (old_set)) == MEM 3203 && SET_SRC (old_set) != recog_data.operand[1]) 3204 || (GET_CODE (SET_DEST (old_set)) == MEM 3205 && SET_DEST (old_set) != recog_data.operand[0]))) 3206 /* If this was an add insn before, rerecognize. */ 3207 || GET_CODE (SET_SRC (old_set)) == PLUS)) 3208 { 3209 int new_icode = recog (PATTERN (insn), insn, 0); 3210 if (new_icode < 0) 3211 INSN_CODE (insn) = icode; 3212 } 3213 } 3214 3215 /* Restore the old body. If there were any changes to it, we made a copy 3216 of it while the changes were still in place, so we'll correctly return 3217 a modified insn below. */ 3218 if (! replace) 3219 { 3220 /* Restore the old body. */ 3221 for (i = 0; i < recog_data.n_operands; i++) 3222 *recog_data.operand_loc[i] = orig_operand[i]; 3223 for (i = 0; i < recog_data.n_dups; i++) 3224 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; 3225 } 3226 3227 /* Update all elimination pairs to reflect the status after the current 3228 insn. The changes we make were determined by the earlier call to 3229 elimination_effects. 3230 3231 We also detect cases where register elimination cannot be done, 3232 namely, if a register would be both changed and referenced outside a MEM 3233 in the resulting insn since such an insn is often undefined and, even if 3234 not, we cannot know what meaning will be given to it. Note that it is 3235 valid to have a register used in an address in an insn that changes it 3236 (presumably with a pre- or post-increment or decrement). 3237 3238 If anything changes, return nonzero. */ 3239 3240 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3241 { 3242 if (ep->previous_offset != ep->offset && ep->ref_outside_mem) 3243 ep->can_eliminate = 0; 3244 3245 ep->ref_outside_mem = 0; 3246 3247 if (ep->previous_offset != ep->offset) 3248 val = 1; 3249 } 3250 3251 done: 3252 /* If we changed something, perform elimination in REG_NOTES. This is 3253 needed even when REPLACE is zero because a REG_DEAD note might refer 3254 to a register that we eliminate and could cause a different number 3255 of spill registers to be needed in the final reload pass than in 3256 the pre-passes. */ 3257 if (val && REG_NOTES (insn) != 0) 3258 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn)); 3259 3260 return val; 3261} 3262 3263/* Loop through all elimination pairs. 3264 Recalculate the number not at initial offset. 3265 3266 Compute the maximum offset (minimum offset if the stack does not 3267 grow downward) for each elimination pair. */ 3268 3269static void 3270update_eliminable_offsets () 3271{ 3272 struct elim_table *ep; 3273 3274 num_not_at_initial_offset = 0; 3275 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3276 { 3277 ep->previous_offset = ep->offset; 3278 if (ep->can_eliminate && ep->offset != ep->initial_offset) 3279 num_not_at_initial_offset++; 3280 } 3281} 3282 3283/* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register 3284 replacement we currently believe is valid, mark it as not eliminable if X 3285 modifies DEST in any way other than by adding a constant integer to it. 3286 3287 If DEST is the frame pointer, we do nothing because we assume that 3288 all assignments to the hard frame pointer are nonlocal gotos and are being 3289 done at a time when they are valid and do not disturb anything else. 3290 Some machines want to eliminate a fake argument pointer with either the 3291 frame or stack pointer. Assignments to the hard frame pointer must not 3292 prevent this elimination. 3293 3294 Called via note_stores from reload before starting its passes to scan 3295 the insns of the function. */ 3296 3297static void 3298mark_not_eliminable (dest, x, data) 3299 rtx dest; 3300 rtx x; 3301 void *data ATTRIBUTE_UNUSED; 3302{ 3303 unsigned int i; 3304 3305 /* A SUBREG of a hard register here is just changing its mode. We should 3306 not see a SUBREG of an eliminable hard register, but check just in 3307 case. */ 3308 if (GET_CODE (dest) == SUBREG) 3309 dest = SUBREG_REG (dest); 3310 3311 if (dest == hard_frame_pointer_rtx) 3312 return; 3313 3314 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 3315 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx 3316 && (GET_CODE (x) != SET 3317 || GET_CODE (SET_SRC (x)) != PLUS 3318 || XEXP (SET_SRC (x), 0) != dest 3319 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT)) 3320 { 3321 reg_eliminate[i].can_eliminate_previous 3322 = reg_eliminate[i].can_eliminate = 0; 3323 num_eliminable--; 3324 } 3325} 3326 3327/* Verify that the initial elimination offsets did not change since the 3328 last call to set_initial_elim_offsets. This is used to catch cases 3329 where something illegal happened during reload_as_needed that could 3330 cause incorrect code to be generated if we did not check for it. */ 3331 3332static void 3333verify_initial_elim_offsets () 3334{ 3335 int t; 3336 3337#ifdef ELIMINABLE_REGS 3338 struct elim_table *ep; 3339 3340 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3341 { 3342 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); 3343 if (t != ep->initial_offset) 3344 abort (); 3345 } 3346#else 3347 INITIAL_FRAME_POINTER_OFFSET (t); 3348 if (t != reg_eliminate[0].initial_offset) 3349 abort (); 3350#endif 3351} 3352 3353/* Reset all offsets on eliminable registers to their initial values. */ 3354 3355static void 3356set_initial_elim_offsets () 3357{ 3358 struct elim_table *ep = reg_eliminate; 3359 3360#ifdef ELIMINABLE_REGS 3361 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3362 { 3363 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); 3364 ep->previous_offset = ep->offset = ep->initial_offset; 3365 } 3366#else 3367 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset); 3368 ep->previous_offset = ep->offset = ep->initial_offset; 3369#endif 3370 3371 num_not_at_initial_offset = 0; 3372} 3373 3374/* Initialize the known label offsets. 3375 Set a known offset for each forced label to be at the initial offset 3376 of each elimination. We do this because we assume that all 3377 computed jumps occur from a location where each elimination is 3378 at its initial offset. 3379 For all other labels, show that we don't know the offsets. */ 3380 3381static void 3382set_initial_label_offsets () 3383{ 3384 rtx x; 3385 memset (offsets_known_at, 0, num_labels); 3386 3387 for (x = forced_labels; x; x = XEXP (x, 1)) 3388 if (XEXP (x, 0)) 3389 set_label_offsets (XEXP (x, 0), NULL_RTX, 1); 3390} 3391 3392/* Set all elimination offsets to the known values for the code label given 3393 by INSN. */ 3394 3395static void 3396set_offsets_for_label (insn) 3397 rtx insn; 3398{ 3399 unsigned int i; 3400 int label_nr = CODE_LABEL_NUMBER (insn); 3401 struct elim_table *ep; 3402 3403 num_not_at_initial_offset = 0; 3404 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) 3405 { 3406 ep->offset = ep->previous_offset 3407 = offsets_at[label_nr - first_label_num][i]; 3408 if (ep->can_eliminate && ep->offset != ep->initial_offset) 3409 num_not_at_initial_offset++; 3410 } 3411} 3412 3413/* See if anything that happened changes which eliminations are valid. 3414 For example, on the SPARC, whether or not the frame pointer can 3415 be eliminated can depend on what registers have been used. We need 3416 not check some conditions again (such as flag_omit_frame_pointer) 3417 since they can't have changed. */ 3418 3419static void 3420update_eliminables (pset) 3421 HARD_REG_SET *pset; 3422{ 3423 int previous_frame_pointer_needed = frame_pointer_needed; 3424 struct elim_table *ep; 3425 3426 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3427 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED) 3428#ifdef ELIMINABLE_REGS 3429 || ! CAN_ELIMINATE (ep->from, ep->to) 3430#endif 3431 ) 3432 ep->can_eliminate = 0; 3433 3434 /* Look for the case where we have discovered that we can't replace 3435 register A with register B and that means that we will now be 3436 trying to replace register A with register C. This means we can 3437 no longer replace register C with register B and we need to disable 3438 such an elimination, if it exists. This occurs often with A == ap, 3439 B == sp, and C == fp. */ 3440 3441 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3442 { 3443 struct elim_table *op; 3444 int new_to = -1; 3445 3446 if (! ep->can_eliminate && ep->can_eliminate_previous) 3447 { 3448 /* Find the current elimination for ep->from, if there is a 3449 new one. */ 3450 for (op = reg_eliminate; 3451 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) 3452 if (op->from == ep->from && op->can_eliminate) 3453 { 3454 new_to = op->to; 3455 break; 3456 } 3457 3458 /* See if there is an elimination of NEW_TO -> EP->TO. If so, 3459 disable it. */ 3460 for (op = reg_eliminate; 3461 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) 3462 if (op->from == new_to && op->to == ep->to) 3463 op->can_eliminate = 0; 3464 } 3465 } 3466 3467 /* See if any registers that we thought we could eliminate the previous 3468 time are no longer eliminable. If so, something has changed and we 3469 must spill the register. Also, recompute the number of eliminable 3470 registers and see if the frame pointer is needed; it is if there is 3471 no elimination of the frame pointer that we can perform. */ 3472 3473 frame_pointer_needed = 1; 3474 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3475 { 3476 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM 3477 && ep->to != HARD_FRAME_POINTER_REGNUM) 3478 frame_pointer_needed = 0; 3479 3480 if (! ep->can_eliminate && ep->can_eliminate_previous) 3481 { 3482 ep->can_eliminate_previous = 0; 3483 SET_HARD_REG_BIT (*pset, ep->from); 3484 num_eliminable--; 3485 } 3486 } 3487 3488 /* If we didn't need a frame pointer last time, but we do now, spill 3489 the hard frame pointer. */ 3490 if (frame_pointer_needed && ! previous_frame_pointer_needed) 3491 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); 3492} 3493 3494/* Initialize the table of registers to eliminate. */ 3495 3496static void 3497init_elim_table () 3498{ 3499 struct elim_table *ep; 3500#ifdef ELIMINABLE_REGS 3501 const struct elim_table_1 *ep1; 3502#endif 3503 3504 if (!reg_eliminate) 3505 reg_eliminate = (struct elim_table *) 3506 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS); 3507 3508 /* Does this function require a frame pointer? */ 3509 3510 frame_pointer_needed = (! flag_omit_frame_pointer 3511#ifdef EXIT_IGNORE_STACK 3512 /* ?? If EXIT_IGNORE_STACK is set, we will not save 3513 and restore sp for alloca. So we can't eliminate 3514 the frame pointer in that case. At some point, 3515 we should improve this by emitting the 3516 sp-adjusting insns for this case. */ 3517 || (current_function_calls_alloca 3518 && EXIT_IGNORE_STACK) 3519#endif 3520 || FRAME_POINTER_REQUIRED); 3521 3522 num_eliminable = 0; 3523 3524#ifdef ELIMINABLE_REGS 3525 for (ep = reg_eliminate, ep1 = reg_eliminate_1; 3526 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) 3527 { 3528 ep->from = ep1->from; 3529 ep->to = ep1->to; 3530 ep->can_eliminate = ep->can_eliminate_previous 3531 = (CAN_ELIMINATE (ep->from, ep->to) 3532 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed)); 3533 } 3534#else 3535 reg_eliminate[0].from = reg_eliminate_1[0].from; 3536 reg_eliminate[0].to = reg_eliminate_1[0].to; 3537 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous 3538 = ! frame_pointer_needed; 3539#endif 3540 3541 /* Count the number of eliminable registers and build the FROM and TO 3542 REG rtx's. Note that code in gen_rtx will cause, e.g., 3543 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. 3544 We depend on this. */ 3545 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3546 { 3547 num_eliminable += ep->can_eliminate; 3548 ep->from_rtx = gen_rtx_REG (Pmode, ep->from); 3549 ep->to_rtx = gen_rtx_REG (Pmode, ep->to); 3550 } 3551} 3552 3553/* Kick all pseudos out of hard register REGNO. 3554 3555 If CANT_ELIMINATE is nonzero, it means that we are doing this spill 3556 because we found we can't eliminate some register. In the case, no pseudos 3557 are allowed to be in the register, even if they are only in a block that 3558 doesn't require spill registers, unlike the case when we are spilling this 3559 hard reg to produce another spill register. 3560 3561 Return nonzero if any pseudos needed to be kicked out. */ 3562 3563static void 3564spill_hard_reg (regno, cant_eliminate) 3565 unsigned int regno; 3566 int cant_eliminate; 3567{ 3568 int i; 3569 3570 if (cant_eliminate) 3571 { 3572 SET_HARD_REG_BIT (bad_spill_regs_global, regno); 3573 regs_ever_live[regno] = 1; 3574 } 3575 3576 /* Spill every pseudo reg that was allocated to this reg 3577 or to something that overlaps this reg. */ 3578 3579 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3580 if (reg_renumber[i] >= 0 3581 && (unsigned int) reg_renumber[i] <= regno 3582 && ((unsigned int) reg_renumber[i] 3583 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i], 3584 PSEUDO_REGNO_MODE (i)) 3585 > regno)) 3586 SET_REGNO_REG_SET (&spilled_pseudos, i); 3587} 3588 3589/* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET 3590 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */ 3591 3592static void 3593ior_hard_reg_set (set1, set2) 3594 HARD_REG_SET *set1, *set2; 3595{ 3596 IOR_HARD_REG_SET (*set1, *set2); 3597} 3598 3599/* After find_reload_regs has been run for all insn that need reloads, 3600 and/or spill_hard_regs was called, this function is used to actually 3601 spill pseudo registers and try to reallocate them. It also sets up the 3602 spill_regs array for use by choose_reload_regs. */ 3603 3604static int 3605finish_spills (global) 3606 int global; 3607{ 3608 struct insn_chain *chain; 3609 int something_changed = 0; 3610 int i; 3611 3612 /* Build the spill_regs array for the function. */ 3613 /* If there are some registers still to eliminate and one of the spill regs 3614 wasn't ever used before, additional stack space may have to be 3615 allocated to store this register. Thus, we may have changed the offset 3616 between the stack and frame pointers, so mark that something has changed. 3617 3618 One might think that we need only set VAL to 1 if this is a call-used 3619 register. However, the set of registers that must be saved by the 3620 prologue is not identical to the call-used set. For example, the 3621 register used by the call insn for the return PC is a call-used register, 3622 but must be saved by the prologue. */ 3623 3624 n_spills = 0; 3625 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3626 if (TEST_HARD_REG_BIT (used_spill_regs, i)) 3627 { 3628 spill_reg_order[i] = n_spills; 3629 spill_regs[n_spills++] = i; 3630 if (num_eliminable && ! regs_ever_live[i]) 3631 something_changed = 1; 3632 regs_ever_live[i] = 1; 3633 } 3634 else 3635 spill_reg_order[i] = -1; 3636 3637 EXECUTE_IF_SET_IN_REG_SET 3638 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, 3639 { 3640 /* Record the current hard register the pseudo is allocated to in 3641 pseudo_previous_regs so we avoid reallocating it to the same 3642 hard reg in a later pass. */ 3643 if (reg_renumber[i] < 0) 3644 abort (); 3645 3646 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); 3647 /* Mark it as no longer having a hard register home. */ 3648 reg_renumber[i] = -1; 3649 /* We will need to scan everything again. */ 3650 something_changed = 1; 3651 }); 3652 3653 /* Retry global register allocation if possible. */ 3654 if (global) 3655 { 3656 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); 3657 /* For every insn that needs reloads, set the registers used as spill 3658 regs in pseudo_forbidden_regs for every pseudo live across the 3659 insn. */ 3660 for (chain = insns_need_reload; chain; chain = chain->next_need_reload) 3661 { 3662 EXECUTE_IF_SET_IN_REG_SET 3663 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, 3664 { 3665 ior_hard_reg_set (pseudo_forbidden_regs + i, 3666 &chain->used_spill_regs); 3667 }); 3668 EXECUTE_IF_SET_IN_REG_SET 3669 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, 3670 { 3671 ior_hard_reg_set (pseudo_forbidden_regs + i, 3672 &chain->used_spill_regs); 3673 }); 3674 } 3675 3676 /* Retry allocating the spilled pseudos. For each reg, merge the 3677 various reg sets that indicate which hard regs can't be used, 3678 and call retry_global_alloc. 3679 We change spill_pseudos here to only contain pseudos that did not 3680 get a new hard register. */ 3681 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3682 if (reg_old_renumber[i] != reg_renumber[i]) 3683 { 3684 HARD_REG_SET forbidden; 3685 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global); 3686 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]); 3687 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]); 3688 retry_global_alloc (i, forbidden); 3689 if (reg_renumber[i] >= 0) 3690 CLEAR_REGNO_REG_SET (&spilled_pseudos, i); 3691 } 3692 } 3693 3694 /* Fix up the register information in the insn chain. 3695 This involves deleting those of the spilled pseudos which did not get 3696 a new hard register home from the live_{before,after} sets. */ 3697 for (chain = reload_insn_chain; chain; chain = chain->next) 3698 { 3699 HARD_REG_SET used_by_pseudos; 3700 HARD_REG_SET used_by_pseudos2; 3701 3702 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); 3703 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); 3704 3705 /* Mark any unallocated hard regs as available for spills. That 3706 makes inheritance work somewhat better. */ 3707 if (chain->need_reload) 3708 { 3709 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); 3710 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); 3711 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2); 3712 3713 /* Save the old value for the sanity test below. */ 3714 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs); 3715 3716 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); 3717 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); 3718 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos); 3719 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs); 3720 3721 /* Make sure we only enlarge the set. */ 3722 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok); 3723 abort (); 3724 ok:; 3725 } 3726 } 3727 3728 /* Let alter_reg modify the reg rtx's for the modified pseudos. */ 3729 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 3730 { 3731 int regno = reg_renumber[i]; 3732 if (reg_old_renumber[i] == regno) 3733 continue; 3734 3735 alter_reg (i, reg_old_renumber[i]); 3736 reg_old_renumber[i] = regno; 3737 if (rtl_dump_file) 3738 { 3739 if (regno == -1) 3740 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i); 3741 else 3742 fprintf (rtl_dump_file, " Register %d now in %d.\n\n", 3743 i, reg_renumber[i]); 3744 } 3745 } 3746 3747 return something_changed; 3748} 3749 3750/* Find all paradoxical subregs within X and update reg_max_ref_width. 3751 Also mark any hard registers used to store user variables as 3752 forbidden from being used for spill registers. */ 3753 3754static void 3755scan_paradoxical_subregs (x) 3756 rtx x; 3757{ 3758 int i; 3759 const char *fmt; 3760 enum rtx_code code = GET_CODE (x); 3761 3762 switch (code) 3763 { 3764 case REG: 3765#if 0 3766 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER 3767 && REG_USERVAR_P (x)) 3768 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x)); 3769#endif 3770 return; 3771 3772 case CONST_INT: 3773 case CONST: 3774 case SYMBOL_REF: 3775 case LABEL_REF: 3776 case CONST_DOUBLE: 3777 case CONST_VECTOR: /* shouldn't happen, but just in case. */ 3778 case CC0: 3779 case PC: 3780 case USE: 3781 case CLOBBER: 3782 return; 3783 3784 case SUBREG: 3785 if (GET_CODE (SUBREG_REG (x)) == REG 3786 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))) 3787 reg_max_ref_width[REGNO (SUBREG_REG (x))] 3788 = GET_MODE_SIZE (GET_MODE (x)); 3789 return; 3790 3791 default: 3792 break; 3793 } 3794 3795 fmt = GET_RTX_FORMAT (code); 3796 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3797 { 3798 if (fmt[i] == 'e') 3799 scan_paradoxical_subregs (XEXP (x, i)); 3800 else if (fmt[i] == 'E') 3801 { 3802 int j; 3803 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3804 scan_paradoxical_subregs (XVECEXP (x, i, j)); 3805 } 3806 } 3807} 3808 3809/* Reload pseudo-registers into hard regs around each insn as needed. 3810 Additional register load insns are output before the insn that needs it 3811 and perhaps store insns after insns that modify the reloaded pseudo reg. 3812 3813 reg_last_reload_reg and reg_reloaded_contents keep track of 3814 which registers are already available in reload registers. 3815 We update these for the reloads that we perform, 3816 as the insns are scanned. */ 3817 3818static void 3819reload_as_needed (live_known) 3820 int live_known; 3821{ 3822 struct insn_chain *chain; 3823#if defined (AUTO_INC_DEC) 3824 int i; 3825#endif 3826 rtx x; 3827 3828 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx); 3829 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store); 3830 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx)); 3831 reg_has_output_reload = (char *) xmalloc (max_regno); 3832 CLEAR_HARD_REG_SET (reg_reloaded_valid); 3833 3834 set_initial_elim_offsets (); 3835 3836 for (chain = reload_insn_chain; chain; chain = chain->next) 3837 { 3838 rtx prev; 3839 rtx insn = chain->insn; 3840 rtx old_next = NEXT_INSN (insn); 3841 3842 /* If we pass a label, copy the offsets from the label information 3843 into the current offsets of each elimination. */ 3844 if (GET_CODE (insn) == CODE_LABEL) 3845 set_offsets_for_label (insn); 3846 3847 else if (INSN_P (insn)) 3848 { 3849 rtx oldpat = copy_rtx (PATTERN (insn)); 3850 3851 /* If this is a USE and CLOBBER of a MEM, ensure that any 3852 references to eliminable registers have been removed. */ 3853 3854 if ((GET_CODE (PATTERN (insn)) == USE 3855 || GET_CODE (PATTERN (insn)) == CLOBBER) 3856 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM) 3857 XEXP (XEXP (PATTERN (insn), 0), 0) 3858 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), 3859 GET_MODE (XEXP (PATTERN (insn), 0)), 3860 NULL_RTX); 3861 3862 /* If we need to do register elimination processing, do so. 3863 This might delete the insn, in which case we are done. */ 3864 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) 3865 { 3866 eliminate_regs_in_insn (insn, 1); 3867 if (GET_CODE (insn) == NOTE) 3868 { 3869 update_eliminable_offsets (); 3870 continue; 3871 } 3872 } 3873 3874 /* If need_elim is nonzero but need_reload is zero, one might think 3875 that we could simply set n_reloads to 0. However, find_reloads 3876 could have done some manipulation of the insn (such as swapping 3877 commutative operands), and these manipulations are lost during 3878 the first pass for every insn that needs register elimination. 3879 So the actions of find_reloads must be redone here. */ 3880 3881 if (! chain->need_elim && ! chain->need_reload 3882 && ! chain->need_operand_change) 3883 n_reloads = 0; 3884 /* First find the pseudo regs that must be reloaded for this insn. 3885 This info is returned in the tables reload_... (see reload.h). 3886 Also modify the body of INSN by substituting RELOAD 3887 rtx's for those pseudo regs. */ 3888 else 3889 { 3890 memset (reg_has_output_reload, 0, max_regno); 3891 CLEAR_HARD_REG_SET (reg_is_output_reload); 3892 3893 find_reloads (insn, 1, spill_indirect_levels, live_known, 3894 spill_reg_order); 3895 } 3896 3897 if (n_reloads > 0) 3898 { 3899 rtx next = NEXT_INSN (insn); 3900 rtx p; 3901 3902 prev = PREV_INSN (insn); 3903 3904 /* Now compute which reload regs to reload them into. Perhaps 3905 reusing reload regs from previous insns, or else output 3906 load insns to reload them. Maybe output store insns too. 3907 Record the choices of reload reg in reload_reg_rtx. */ 3908 choose_reload_regs (chain); 3909 3910 /* Merge any reloads that we didn't combine for fear of 3911 increasing the number of spill registers needed but now 3912 discover can be safely merged. */ 3913 if (SMALL_REGISTER_CLASSES) 3914 merge_assigned_reloads (insn); 3915 3916 /* Generate the insns to reload operands into or out of 3917 their reload regs. */ 3918 emit_reload_insns (chain); 3919 3920 /* Substitute the chosen reload regs from reload_reg_rtx 3921 into the insn's body (or perhaps into the bodies of other 3922 load and store insn that we just made for reloading 3923 and that we moved the structure into). */ 3924 subst_reloads (insn); 3925 3926 /* If this was an ASM, make sure that all the reload insns 3927 we have generated are valid. If not, give an error 3928 and delete them. */ 3929 3930 if (asm_noperands (PATTERN (insn)) >= 0) 3931 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p)) 3932 if (p != insn && INSN_P (p) 3933 && GET_CODE (PATTERN (p)) != USE 3934 && (recog_memoized (p) < 0 3935 || (extract_insn (p), ! constrain_operands (1)))) 3936 { 3937 error_for_asm (insn, 3938 "`asm' operand requires impossible reload"); 3939 delete_insn (p); 3940 } 3941 } 3942 3943 if (num_eliminable && chain->need_elim) 3944 update_eliminable_offsets (); 3945 3946 /* Any previously reloaded spilled pseudo reg, stored in this insn, 3947 is no longer validly lying around to save a future reload. 3948 Note that this does not detect pseudos that were reloaded 3949 for this insn in order to be stored in 3950 (obeying register constraints). That is correct; such reload 3951 registers ARE still valid. */ 3952 note_stores (oldpat, forget_old_reloads_1, NULL); 3953 3954 /* There may have been CLOBBER insns placed after INSN. So scan 3955 between INSN and NEXT and use them to forget old reloads. */ 3956 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) 3957 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER) 3958 note_stores (PATTERN (x), forget_old_reloads_1, NULL); 3959 3960#ifdef AUTO_INC_DEC 3961 /* Likewise for regs altered by auto-increment in this insn. 3962 REG_INC notes have been changed by reloading: 3963 find_reloads_address_1 records substitutions for them, 3964 which have been performed by subst_reloads above. */ 3965 for (i = n_reloads - 1; i >= 0; i--) 3966 { 3967 rtx in_reg = rld[i].in_reg; 3968 if (in_reg) 3969 { 3970 enum rtx_code code = GET_CODE (in_reg); 3971 /* PRE_INC / PRE_DEC will have the reload register ending up 3972 with the same value as the stack slot, but that doesn't 3973 hold true for POST_INC / POST_DEC. Either we have to 3974 convert the memory access to a true POST_INC / POST_DEC, 3975 or we can't use the reload register for inheritance. */ 3976 if ((code == POST_INC || code == POST_DEC) 3977 && TEST_HARD_REG_BIT (reg_reloaded_valid, 3978 REGNO (rld[i].reg_rtx)) 3979 /* Make sure it is the inc/dec pseudo, and not 3980 some other (e.g. output operand) pseudo. */ 3981 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] 3982 == REGNO (XEXP (in_reg, 0)))) 3983 3984 { 3985 rtx reload_reg = rld[i].reg_rtx; 3986 enum machine_mode mode = GET_MODE (reload_reg); 3987 int n = 0; 3988 rtx p; 3989 3990 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) 3991 { 3992 /* We really want to ignore REG_INC notes here, so 3993 use PATTERN (p) as argument to reg_set_p . */ 3994 if (reg_set_p (reload_reg, PATTERN (p))) 3995 break; 3996 n = count_occurrences (PATTERN (p), reload_reg, 0); 3997 if (! n) 3998 continue; 3999 if (n == 1) 4000 { 4001 n = validate_replace_rtx (reload_reg, 4002 gen_rtx (code, mode, 4003 reload_reg), 4004 p); 4005 4006 /* We must also verify that the constraints 4007 are met after the replacement. */ 4008 extract_insn (p); 4009 if (n) 4010 n = constrain_operands (1); 4011 else 4012 break; 4013 4014 /* If the constraints were not met, then 4015 undo the replacement. */ 4016 if (!n) 4017 { 4018 validate_replace_rtx (gen_rtx (code, mode, 4019 reload_reg), 4020 reload_reg, p); 4021 break; 4022 } 4023 4024 } 4025 break; 4026 } 4027 if (n == 1) 4028 { 4029 REG_NOTES (p) 4030 = gen_rtx_EXPR_LIST (REG_INC, reload_reg, 4031 REG_NOTES (p)); 4032 /* Mark this as having an output reload so that the 4033 REG_INC processing code below won't invalidate 4034 the reload for inheritance. */ 4035 SET_HARD_REG_BIT (reg_is_output_reload, 4036 REGNO (reload_reg)); 4037 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; 4038 } 4039 else 4040 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, 4041 NULL); 4042 } 4043 else if ((code == PRE_INC || code == PRE_DEC) 4044 && TEST_HARD_REG_BIT (reg_reloaded_valid, 4045 REGNO (rld[i].reg_rtx)) 4046 /* Make sure it is the inc/dec pseudo, and not 4047 some other (e.g. output operand) pseudo. */ 4048 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)] 4049 == REGNO (XEXP (in_reg, 0)))) 4050 { 4051 SET_HARD_REG_BIT (reg_is_output_reload, 4052 REGNO (rld[i].reg_rtx)); 4053 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1; 4054 } 4055 } 4056 } 4057 /* If a pseudo that got a hard register is auto-incremented, 4058 we must purge records of copying it into pseudos without 4059 hard registers. */ 4060 for (x = REG_NOTES (insn); x; x = XEXP (x, 1)) 4061 if (REG_NOTE_KIND (x) == REG_INC) 4062 { 4063 /* See if this pseudo reg was reloaded in this insn. 4064 If so, its last-reload info is still valid 4065 because it is based on this insn's reload. */ 4066 for (i = 0; i < n_reloads; i++) 4067 if (rld[i].out == XEXP (x, 0)) 4068 break; 4069 4070 if (i == n_reloads) 4071 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); 4072 } 4073#endif 4074 } 4075 /* A reload reg's contents are unknown after a label. */ 4076 if (GET_CODE (insn) == CODE_LABEL) 4077 CLEAR_HARD_REG_SET (reg_reloaded_valid); 4078 4079 /* Don't assume a reload reg is still good after a call insn 4080 if it is a call-used reg. */ 4081 else if (GET_CODE (insn) == CALL_INSN) 4082 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set); 4083 } 4084 4085 /* Clean up. */ 4086 free (reg_last_reload_reg); 4087 free (reg_has_output_reload); 4088} 4089 4090/* Discard all record of any value reloaded from X, 4091 or reloaded in X from someplace else; 4092 unless X is an output reload reg of the current insn. 4093 4094 X may be a hard reg (the reload reg) 4095 or it may be a pseudo reg that was reloaded from. */ 4096 4097static void 4098forget_old_reloads_1 (x, ignored, data) 4099 rtx x; 4100 rtx ignored ATTRIBUTE_UNUSED; 4101 void *data ATTRIBUTE_UNUSED; 4102{ 4103 unsigned int regno; 4104 unsigned int nr; 4105 4106 /* note_stores does give us subregs of hard regs, 4107 subreg_regno_offset will abort if it is not a hard reg. */ 4108 while (GET_CODE (x) == SUBREG) 4109 { 4110 /* We ignore the subreg offset when calculating the regno, 4111 because we are using the entire underlying hard register 4112 below. */ 4113 x = SUBREG_REG (x); 4114 } 4115 4116 if (GET_CODE (x) != REG) 4117 return; 4118 4119 regno = REGNO (x); 4120 4121 if (regno >= FIRST_PSEUDO_REGISTER) 4122 nr = 1; 4123 else 4124 { 4125 unsigned int i; 4126 4127 nr = HARD_REGNO_NREGS (regno, GET_MODE (x)); 4128 /* Storing into a spilled-reg invalidates its contents. 4129 This can happen if a block-local pseudo is allocated to that reg 4130 and it wasn't spilled because this block's total need is 0. 4131 Then some insn might have an optional reload and use this reg. */ 4132 for (i = 0; i < nr; i++) 4133 /* But don't do this if the reg actually serves as an output 4134 reload reg in the current instruction. */ 4135 if (n_reloads == 0 4136 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) 4137 { 4138 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); 4139 spill_reg_store[regno + i] = 0; 4140 } 4141 } 4142 4143 /* Since value of X has changed, 4144 forget any value previously copied from it. */ 4145 4146 while (nr-- > 0) 4147 /* But don't forget a copy if this is the output reload 4148 that establishes the copy's validity. */ 4149 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0) 4150 reg_last_reload_reg[regno + nr] = 0; 4151} 4152 4153/* The following HARD_REG_SETs indicate when each hard register is 4154 used for a reload of various parts of the current insn. */ 4155 4156/* If reg is unavailable for all reloads. */ 4157static HARD_REG_SET reload_reg_unavailable; 4158/* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ 4159static HARD_REG_SET reload_reg_used; 4160/* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ 4161static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; 4162/* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ 4163static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; 4164/* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ 4165static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; 4166/* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ 4167static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; 4168/* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ 4169static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; 4170/* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ 4171static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; 4172/* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ 4173static HARD_REG_SET reload_reg_used_in_op_addr; 4174/* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ 4175static HARD_REG_SET reload_reg_used_in_op_addr_reload; 4176/* If reg is in use for a RELOAD_FOR_INSN reload. */ 4177static HARD_REG_SET reload_reg_used_in_insn; 4178/* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ 4179static HARD_REG_SET reload_reg_used_in_other_addr; 4180 4181/* If reg is in use as a reload reg for any sort of reload. */ 4182static HARD_REG_SET reload_reg_used_at_all; 4183 4184/* If reg is use as an inherited reload. We just mark the first register 4185 in the group. */ 4186static HARD_REG_SET reload_reg_used_for_inherit; 4187 4188/* Records which hard regs are used in any way, either as explicit use or 4189 by being allocated to a pseudo during any point of the current insn. */ 4190static HARD_REG_SET reg_used_in_insn; 4191 4192/* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and 4193 TYPE. MODE is used to indicate how many consecutive regs are 4194 actually used. */ 4195 4196static void 4197mark_reload_reg_in_use (regno, opnum, type, mode) 4198 unsigned int regno; 4199 int opnum; 4200 enum reload_type type; 4201 enum machine_mode mode; 4202{ 4203 unsigned int nregs = HARD_REGNO_NREGS (regno, mode); 4204 unsigned int i; 4205 4206 for (i = regno; i < nregs + regno; i++) 4207 { 4208 switch (type) 4209 { 4210 case RELOAD_OTHER: 4211 SET_HARD_REG_BIT (reload_reg_used, i); 4212 break; 4213 4214 case RELOAD_FOR_INPUT_ADDRESS: 4215 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i); 4216 break; 4217 4218 case RELOAD_FOR_INPADDR_ADDRESS: 4219 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i); 4220 break; 4221 4222 case RELOAD_FOR_OUTPUT_ADDRESS: 4223 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i); 4224 break; 4225 4226 case RELOAD_FOR_OUTADDR_ADDRESS: 4227 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i); 4228 break; 4229 4230 case RELOAD_FOR_OPERAND_ADDRESS: 4231 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i); 4232 break; 4233 4234 case RELOAD_FOR_OPADDR_ADDR: 4235 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i); 4236 break; 4237 4238 case RELOAD_FOR_OTHER_ADDRESS: 4239 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i); 4240 break; 4241 4242 case RELOAD_FOR_INPUT: 4243 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i); 4244 break; 4245 4246 case RELOAD_FOR_OUTPUT: 4247 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i); 4248 break; 4249 4250 case RELOAD_FOR_INSN: 4251 SET_HARD_REG_BIT (reload_reg_used_in_insn, i); 4252 break; 4253 } 4254 4255 SET_HARD_REG_BIT (reload_reg_used_at_all, i); 4256 } 4257} 4258 4259/* Similarly, but show REGNO is no longer in use for a reload. */ 4260 4261static void 4262clear_reload_reg_in_use (regno, opnum, type, mode) 4263 unsigned int regno; 4264 int opnum; 4265 enum reload_type type; 4266 enum machine_mode mode; 4267{ 4268 unsigned int nregs = HARD_REGNO_NREGS (regno, mode); 4269 unsigned int start_regno, end_regno, r; 4270 int i; 4271 /* A complication is that for some reload types, inheritance might 4272 allow multiple reloads of the same types to share a reload register. 4273 We set check_opnum if we have to check only reloads with the same 4274 operand number, and check_any if we have to check all reloads. */ 4275 int check_opnum = 0; 4276 int check_any = 0; 4277 HARD_REG_SET *used_in_set; 4278 4279 switch (type) 4280 { 4281 case RELOAD_OTHER: 4282 used_in_set = &reload_reg_used; 4283 break; 4284 4285 case RELOAD_FOR_INPUT_ADDRESS: 4286 used_in_set = &reload_reg_used_in_input_addr[opnum]; 4287 break; 4288 4289 case RELOAD_FOR_INPADDR_ADDRESS: 4290 check_opnum = 1; 4291 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; 4292 break; 4293 4294 case RELOAD_FOR_OUTPUT_ADDRESS: 4295 used_in_set = &reload_reg_used_in_output_addr[opnum]; 4296 break; 4297 4298 case RELOAD_FOR_OUTADDR_ADDRESS: 4299 check_opnum = 1; 4300 used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; 4301 break; 4302 4303 case RELOAD_FOR_OPERAND_ADDRESS: 4304 used_in_set = &reload_reg_used_in_op_addr; 4305 break; 4306 4307 case RELOAD_FOR_OPADDR_ADDR: 4308 check_any = 1; 4309 used_in_set = &reload_reg_used_in_op_addr_reload; 4310 break; 4311 4312 case RELOAD_FOR_OTHER_ADDRESS: 4313 used_in_set = &reload_reg_used_in_other_addr; 4314 check_any = 1; 4315 break; 4316 4317 case RELOAD_FOR_INPUT: 4318 used_in_set = &reload_reg_used_in_input[opnum]; 4319 break; 4320 4321 case RELOAD_FOR_OUTPUT: 4322 used_in_set = &reload_reg_used_in_output[opnum]; 4323 break; 4324 4325 case RELOAD_FOR_INSN: 4326 used_in_set = &reload_reg_used_in_insn; 4327 break; 4328 default: 4329 abort (); 4330 } 4331 /* We resolve conflicts with remaining reloads of the same type by 4332 excluding the intervals of reload registers by them from the 4333 interval of freed reload registers. Since we only keep track of 4334 one set of interval bounds, we might have to exclude somewhat 4335 more than what would be necessary if we used a HARD_REG_SET here. 4336 But this should only happen very infrequently, so there should 4337 be no reason to worry about it. */ 4338 4339 start_regno = regno; 4340 end_regno = regno + nregs; 4341 if (check_opnum || check_any) 4342 { 4343 for (i = n_reloads - 1; i >= 0; i--) 4344 { 4345 if (rld[i].when_needed == type 4346 && (check_any || rld[i].opnum == opnum) 4347 && rld[i].reg_rtx) 4348 { 4349 unsigned int conflict_start = true_regnum (rld[i].reg_rtx); 4350 unsigned int conflict_end 4351 = (conflict_start 4352 + HARD_REGNO_NREGS (conflict_start, rld[i].mode)); 4353 4354 /* If there is an overlap with the first to-be-freed register, 4355 adjust the interval start. */ 4356 if (conflict_start <= start_regno && conflict_end > start_regno) 4357 start_regno = conflict_end; 4358 /* Otherwise, if there is a conflict with one of the other 4359 to-be-freed registers, adjust the interval end. */ 4360 if (conflict_start > start_regno && conflict_start < end_regno) 4361 end_regno = conflict_start; 4362 } 4363 } 4364 } 4365 4366 for (r = start_regno; r < end_regno; r++) 4367 CLEAR_HARD_REG_BIT (*used_in_set, r); 4368} 4369 4370/* 1 if reg REGNO is free as a reload reg for a reload of the sort 4371 specified by OPNUM and TYPE. */ 4372 4373static int 4374reload_reg_free_p (regno, opnum, type) 4375 unsigned int regno; 4376 int opnum; 4377 enum reload_type type; 4378{ 4379 int i; 4380 4381 /* In use for a RELOAD_OTHER means it's not available for anything. */ 4382 if (TEST_HARD_REG_BIT (reload_reg_used, regno) 4383 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) 4384 return 0; 4385 4386 switch (type) 4387 { 4388 case RELOAD_OTHER: 4389 /* In use for anything means we can't use it for RELOAD_OTHER. */ 4390 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) 4391 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4392 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 4393 return 0; 4394 4395 for (i = 0; i < reload_n_operands; i++) 4396 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4397 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4398 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4399 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4400 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) 4401 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4402 return 0; 4403 4404 return 1; 4405 4406 case RELOAD_FOR_INPUT: 4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4408 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) 4409 return 0; 4410 4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 4412 return 0; 4413 4414 /* If it is used for some other input, can't use it. */ 4415 for (i = 0; i < reload_n_operands; i++) 4416 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4417 return 0; 4418 4419 /* If it is used in a later operand's address, can't use it. */ 4420 for (i = opnum + 1; i < reload_n_operands; i++) 4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4422 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 4423 return 0; 4424 4425 return 1; 4426 4427 case RELOAD_FOR_INPUT_ADDRESS: 4428 /* Can't use a register if it is used for an input address for this 4429 operand or used as an input in an earlier one. */ 4430 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) 4431 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 4432 return 0; 4433 4434 for (i = 0; i < opnum; i++) 4435 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4436 return 0; 4437 4438 return 1; 4439 4440 case RELOAD_FOR_INPADDR_ADDRESS: 4441 /* Can't use a register if it is used for an input address 4442 for this operand or used as an input in an earlier 4443 one. */ 4444 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 4445 return 0; 4446 4447 for (i = 0; i < opnum; i++) 4448 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4449 return 0; 4450 4451 return 1; 4452 4453 case RELOAD_FOR_OUTPUT_ADDRESS: 4454 /* Can't use a register if it is used for an output address for this 4455 operand or used as an output in this or a later operand. Note 4456 that multiple output operands are emitted in reverse order, so 4457 the conflicting ones are those with lower indices. */ 4458 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) 4459 return 0; 4460 4461 for (i = 0; i <= opnum; i++) 4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4463 return 0; 4464 4465 return 1; 4466 4467 case RELOAD_FOR_OUTADDR_ADDRESS: 4468 /* Can't use a register if it is used for an output address 4469 for this operand or used as an output in this or a 4470 later operand. Note that multiple output operands are 4471 emitted in reverse order, so the conflicting ones are 4472 those with lower indices. */ 4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) 4474 return 0; 4475 4476 for (i = 0; i <= opnum; i++) 4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4478 return 0; 4479 4480 return 1; 4481 4482 case RELOAD_FOR_OPERAND_ADDRESS: 4483 for (i = 0; i < reload_n_operands; i++) 4484 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4485 return 0; 4486 4487 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4488 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 4489 4490 case RELOAD_FOR_OPADDR_ADDR: 4491 for (i = 0; i < reload_n_operands; i++) 4492 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4493 return 0; 4494 4495 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); 4496 4497 case RELOAD_FOR_OUTPUT: 4498 /* This cannot share a register with RELOAD_FOR_INSN reloads, other 4499 outputs, or an operand address for this or an earlier output. 4500 Note that multiple output operands are emitted in reverse order, 4501 so the conflicting ones are those with higher indices. */ 4502 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 4503 return 0; 4504 4505 for (i = 0; i < reload_n_operands; i++) 4506 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4507 return 0; 4508 4509 for (i = opnum; i < reload_n_operands; i++) 4510 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4511 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) 4512 return 0; 4513 4514 return 1; 4515 4516 case RELOAD_FOR_INSN: 4517 for (i = 0; i < reload_n_operands; i++) 4518 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) 4519 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4520 return 0; 4521 4522 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4523 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 4524 4525 case RELOAD_FOR_OTHER_ADDRESS: 4526 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); 4527 } 4528 abort (); 4529} 4530 4531/* Return 1 if the value in reload reg REGNO, as used by a reload 4532 needed for the part of the insn specified by OPNUM and TYPE, 4533 is still available in REGNO at the end of the insn. 4534 4535 We can assume that the reload reg was already tested for availability 4536 at the time it is needed, and we should not check this again, 4537 in case the reg has already been marked in use. */ 4538 4539static int 4540reload_reg_reaches_end_p (regno, opnum, type) 4541 unsigned int regno; 4542 int opnum; 4543 enum reload_type type; 4544{ 4545 int i; 4546 4547 switch (type) 4548 { 4549 case RELOAD_OTHER: 4550 /* Since a RELOAD_OTHER reload claims the reg for the entire insn, 4551 its value must reach the end. */ 4552 return 1; 4553 4554 /* If this use is for part of the insn, 4555 its value reaches if no subsequent part uses the same register. 4556 Just like the above function, don't try to do this with lots 4557 of fallthroughs. */ 4558 4559 case RELOAD_FOR_OTHER_ADDRESS: 4560 /* Here we check for everything else, since these don't conflict 4561 with anything else and everything comes later. */ 4562 4563 for (i = 0; i < reload_n_operands; i++) 4564 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4565 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4566 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) 4567 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4568 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4569 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4570 return 0; 4571 4572 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4573 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4574 && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); 4575 4576 case RELOAD_FOR_INPUT_ADDRESS: 4577 case RELOAD_FOR_INPADDR_ADDRESS: 4578 /* Similar, except that we check only for this and subsequent inputs 4579 and the address of only subsequent inputs and we do not need 4580 to check for RELOAD_OTHER objects since they are known not to 4581 conflict. */ 4582 4583 for (i = opnum; i < reload_n_operands; i++) 4584 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4585 return 0; 4586 4587 for (i = opnum + 1; i < reload_n_operands; i++) 4588 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4589 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 4590 return 0; 4591 4592 for (i = 0; i < reload_n_operands; i++) 4593 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4594 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4595 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4596 return 0; 4597 4598 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 4599 return 0; 4600 4601 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4602 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4603 && !TEST_HARD_REG_BIT (reload_reg_used, regno)); 4604 4605 case RELOAD_FOR_INPUT: 4606 /* Similar to input address, except we start at the next operand for 4607 both input and input address and we do not check for 4608 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these 4609 would conflict. */ 4610 4611 for (i = opnum + 1; i < reload_n_operands; i++) 4612 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 4613 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 4614 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 4615 return 0; 4616 4617 /* ... fall through ... */ 4618 4619 case RELOAD_FOR_OPERAND_ADDRESS: 4620 /* Check outputs and their addresses. */ 4621 4622 for (i = 0; i < reload_n_operands; i++) 4623 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4624 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4625 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4626 return 0; 4627 4628 return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); 4629 4630 case RELOAD_FOR_OPADDR_ADDR: 4631 for (i = 0; i < reload_n_operands; i++) 4632 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4633 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 4634 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 4635 return 0; 4636 4637 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 4638 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 4639 && !TEST_HARD_REG_BIT (reload_reg_used, regno)); 4640 4641 case RELOAD_FOR_INSN: 4642 /* These conflict with other outputs with RELOAD_OTHER. So 4643 we need only check for output addresses. */ 4644 4645 opnum = reload_n_operands; 4646 4647 /* ... fall through ... */ 4648 4649 case RELOAD_FOR_OUTPUT: 4650 case RELOAD_FOR_OUTPUT_ADDRESS: 4651 case RELOAD_FOR_OUTADDR_ADDRESS: 4652 /* We already know these can't conflict with a later output. So the 4653 only thing to check are later output addresses. 4654 Note that multiple output operands are emitted in reverse order, 4655 so the conflicting ones are those with lower indices. */ 4656 for (i = 0; i < opnum; i++) 4657 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 4658 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) 4659 return 0; 4660 4661 return 1; 4662 } 4663 4664 abort (); 4665} 4666 4667/* Return 1 if the reloads denoted by R1 and R2 cannot share a register. 4668 Return 0 otherwise. 4669 4670 This function uses the same algorithm as reload_reg_free_p above. */ 4671 4672int 4673reloads_conflict (r1, r2) 4674 int r1, r2; 4675{ 4676 enum reload_type r1_type = rld[r1].when_needed; 4677 enum reload_type r2_type = rld[r2].when_needed; 4678 int r1_opnum = rld[r1].opnum; 4679 int r2_opnum = rld[r2].opnum; 4680 4681 /* RELOAD_OTHER conflicts with everything. */ 4682 if (r2_type == RELOAD_OTHER) 4683 return 1; 4684 4685 /* Otherwise, check conflicts differently for each type. */ 4686 4687 switch (r1_type) 4688 { 4689 case RELOAD_FOR_INPUT: 4690 return (r2_type == RELOAD_FOR_INSN 4691 || r2_type == RELOAD_FOR_OPERAND_ADDRESS 4692 || r2_type == RELOAD_FOR_OPADDR_ADDR 4693 || r2_type == RELOAD_FOR_INPUT 4694 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS 4695 || r2_type == RELOAD_FOR_INPADDR_ADDRESS) 4696 && r2_opnum > r1_opnum)); 4697 4698 case RELOAD_FOR_INPUT_ADDRESS: 4699 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) 4700 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); 4701 4702 case RELOAD_FOR_INPADDR_ADDRESS: 4703 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) 4704 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); 4705 4706 case RELOAD_FOR_OUTPUT_ADDRESS: 4707 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) 4708 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); 4709 4710 case RELOAD_FOR_OUTADDR_ADDRESS: 4711 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) 4712 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); 4713 4714 case RELOAD_FOR_OPERAND_ADDRESS: 4715 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN 4716 || r2_type == RELOAD_FOR_OPERAND_ADDRESS); 4717 4718 case RELOAD_FOR_OPADDR_ADDR: 4719 return (r2_type == RELOAD_FOR_INPUT 4720 || r2_type == RELOAD_FOR_OPADDR_ADDR); 4721 4722 case RELOAD_FOR_OUTPUT: 4723 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT 4724 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS 4725 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) 4726 && r2_opnum >= r1_opnum)); 4727 4728 case RELOAD_FOR_INSN: 4729 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT 4730 || r2_type == RELOAD_FOR_INSN 4731 || r2_type == RELOAD_FOR_OPERAND_ADDRESS); 4732 4733 case RELOAD_FOR_OTHER_ADDRESS: 4734 return r2_type == RELOAD_FOR_OTHER_ADDRESS; 4735 4736 case RELOAD_OTHER: 4737 return 1; 4738 4739 default: 4740 abort (); 4741 } 4742} 4743 4744/* Indexed by reload number, 1 if incoming value 4745 inherited from previous insns. */ 4746char reload_inherited[MAX_RELOADS]; 4747 4748/* For an inherited reload, this is the insn the reload was inherited from, 4749 if we know it. Otherwise, this is 0. */ 4750rtx reload_inheritance_insn[MAX_RELOADS]; 4751 4752/* If nonzero, this is a place to get the value of the reload, 4753 rather than using reload_in. */ 4754rtx reload_override_in[MAX_RELOADS]; 4755 4756/* For each reload, the hard register number of the register used, 4757 or -1 if we did not need a register for this reload. */ 4758int reload_spill_index[MAX_RELOADS]; 4759 4760/* Subroutine of free_for_value_p, used to check a single register. 4761 START_REGNO is the starting regno of the full reload register 4762 (possibly comprising multiple hard registers) that we are considering. */ 4763 4764static int 4765reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out, 4766 reloadnum, ignore_address_reloads) 4767 int start_regno, regno; 4768 int opnum; 4769 enum reload_type type; 4770 rtx value, out; 4771 int reloadnum; 4772 int ignore_address_reloads; 4773{ 4774 int time1; 4775 /* Set if we see an input reload that must not share its reload register 4776 with any new earlyclobber, but might otherwise share the reload 4777 register with an output or input-output reload. */ 4778 int check_earlyclobber = 0; 4779 int i; 4780 int copy = 0; 4781 4782 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) 4783 return 0; 4784 4785 if (out == const0_rtx) 4786 { 4787 copy = 1; 4788 out = NULL_RTX; 4789 } 4790 4791 /* We use some pseudo 'time' value to check if the lifetimes of the 4792 new register use would overlap with the one of a previous reload 4793 that is not read-only or uses a different value. 4794 The 'time' used doesn't have to be linear in any shape or form, just 4795 monotonic. 4796 Some reload types use different 'buckets' for each operand. 4797 So there are MAX_RECOG_OPERANDS different time values for each 4798 such reload type. 4799 We compute TIME1 as the time when the register for the prospective 4800 new reload ceases to be live, and TIME2 for each existing 4801 reload as the time when that the reload register of that reload 4802 becomes live. 4803 Where there is little to be gained by exact lifetime calculations, 4804 we just make conservative assumptions, i.e. a longer lifetime; 4805 this is done in the 'default:' cases. */ 4806 switch (type) 4807 { 4808 case RELOAD_FOR_OTHER_ADDRESS: 4809 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ 4810 time1 = copy ? 0 : 1; 4811 break; 4812 case RELOAD_OTHER: 4813 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; 4814 break; 4815 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, 4816 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , 4817 respectively, to the time values for these, we get distinct time 4818 values. To get distinct time values for each operand, we have to 4819 multiply opnum by at least three. We round that up to four because 4820 multiply by four is often cheaper. */ 4821 case RELOAD_FOR_INPADDR_ADDRESS: 4822 time1 = opnum * 4 + 2; 4823 break; 4824 case RELOAD_FOR_INPUT_ADDRESS: 4825 time1 = opnum * 4 + 3; 4826 break; 4827 case RELOAD_FOR_INPUT: 4828 /* All RELOAD_FOR_INPUT reloads remain live till the instruction 4829 executes (inclusive). */ 4830 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; 4831 break; 4832 case RELOAD_FOR_OPADDR_ADDR: 4833 /* opnum * 4 + 4 4834 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ 4835 time1 = MAX_RECOG_OPERANDS * 4 + 1; 4836 break; 4837 case RELOAD_FOR_OPERAND_ADDRESS: 4838 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn 4839 is executed. */ 4840 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; 4841 break; 4842 case RELOAD_FOR_OUTADDR_ADDRESS: 4843 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; 4844 break; 4845 case RELOAD_FOR_OUTPUT_ADDRESS: 4846 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; 4847 break; 4848 default: 4849 time1 = MAX_RECOG_OPERANDS * 5 + 5; 4850 } 4851 4852 for (i = 0; i < n_reloads; i++) 4853 { 4854 rtx reg = rld[i].reg_rtx; 4855 if (reg && GET_CODE (reg) == REG 4856 && ((unsigned) regno - true_regnum (reg) 4857 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned) 1) 4858 && i != reloadnum) 4859 { 4860 rtx other_input = rld[i].in; 4861 4862 /* If the other reload loads the same input value, that 4863 will not cause a conflict only if it's loading it into 4864 the same register. */ 4865 if (true_regnum (reg) != start_regno) 4866 other_input = NULL_RTX; 4867 if (! other_input || ! rtx_equal_p (other_input, value) 4868 || rld[i].out || out) 4869 { 4870 int time2; 4871 switch (rld[i].when_needed) 4872 { 4873 case RELOAD_FOR_OTHER_ADDRESS: 4874 time2 = 0; 4875 break; 4876 case RELOAD_FOR_INPADDR_ADDRESS: 4877 /* find_reloads makes sure that a 4878 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used 4879 by at most one - the first - 4880 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the 4881 address reload is inherited, the address address reload 4882 goes away, so we can ignore this conflict. */ 4883 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 4884 && ignore_address_reloads 4885 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. 4886 Then the address address is still needed to store 4887 back the new address. */ 4888 && ! rld[reloadnum].out) 4889 continue; 4890 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its 4891 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS 4892 reloads go away. */ 4893 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum 4894 && ignore_address_reloads 4895 /* Unless we are reloading an auto_inc expression. */ 4896 && ! rld[reloadnum].out) 4897 continue; 4898 time2 = rld[i].opnum * 4 + 2; 4899 break; 4900 case RELOAD_FOR_INPUT_ADDRESS: 4901 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum 4902 && ignore_address_reloads 4903 && ! rld[reloadnum].out) 4904 continue; 4905 time2 = rld[i].opnum * 4 + 3; 4906 break; 4907 case RELOAD_FOR_INPUT: 4908 time2 = rld[i].opnum * 4 + 4; 4909 check_earlyclobber = 1; 4910 break; 4911 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 4912 == MAX_RECOG_OPERAND * 4 */ 4913 case RELOAD_FOR_OPADDR_ADDR: 4914 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 4915 && ignore_address_reloads 4916 && ! rld[reloadnum].out) 4917 continue; 4918 time2 = MAX_RECOG_OPERANDS * 4 + 1; 4919 break; 4920 case RELOAD_FOR_OPERAND_ADDRESS: 4921 time2 = MAX_RECOG_OPERANDS * 4 + 2; 4922 check_earlyclobber = 1; 4923 break; 4924 case RELOAD_FOR_INSN: 4925 time2 = MAX_RECOG_OPERANDS * 4 + 3; 4926 break; 4927 case RELOAD_FOR_OUTPUT: 4928 /* All RELOAD_FOR_OUTPUT reloads become live just after the 4929 instruction is executed. */ 4930 time2 = MAX_RECOG_OPERANDS * 4 + 4; 4931 break; 4932 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with 4933 the RELOAD_FOR_OUTPUT reloads, so assign it the same time 4934 value. */ 4935 case RELOAD_FOR_OUTADDR_ADDRESS: 4936 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 4937 && ignore_address_reloads 4938 && ! rld[reloadnum].out) 4939 continue; 4940 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; 4941 break; 4942 case RELOAD_FOR_OUTPUT_ADDRESS: 4943 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; 4944 break; 4945 case RELOAD_OTHER: 4946 /* If there is no conflict in the input part, handle this 4947 like an output reload. */ 4948 if (! rld[i].in || rtx_equal_p (other_input, value)) 4949 { 4950 time2 = MAX_RECOG_OPERANDS * 4 + 4; 4951 /* Earlyclobbered outputs must conflict with inputs. */ 4952 if (earlyclobber_operand_p (rld[i].out)) 4953 time2 = MAX_RECOG_OPERANDS * 4 + 3; 4954 4955 break; 4956 } 4957 time2 = 1; 4958 /* RELOAD_OTHER might be live beyond instruction execution, 4959 but this is not obvious when we set time2 = 1. So check 4960 here if there might be a problem with the new reload 4961 clobbering the register used by the RELOAD_OTHER. */ 4962 if (out) 4963 return 0; 4964 break; 4965 default: 4966 return 0; 4967 } 4968 if ((time1 >= time2 4969 && (! rld[i].in || rld[i].out 4970 || ! rtx_equal_p (other_input, value))) 4971 || (out && rld[reloadnum].out_reg 4972 && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) 4973 return 0; 4974 } 4975 } 4976 } 4977 4978 /* Earlyclobbered outputs must conflict with inputs. */ 4979 if (check_earlyclobber && out && earlyclobber_operand_p (out)) 4980 return 0; 4981 4982 return 1; 4983} 4984 4985/* Return 1 if the value in reload reg REGNO, as used by a reload 4986 needed for the part of the insn specified by OPNUM and TYPE, 4987 may be used to load VALUE into it. 4988 4989 MODE is the mode in which the register is used, this is needed to 4990 determine how many hard regs to test. 4991 4992 Other read-only reloads with the same value do not conflict 4993 unless OUT is nonzero and these other reloads have to live while 4994 output reloads live. 4995 If OUT is CONST0_RTX, this is a special case: it means that the 4996 test should not be for using register REGNO as reload register, but 4997 for copying from register REGNO into the reload register. 4998 4999 RELOADNUM is the number of the reload we want to load this value for; 5000 a reload does not conflict with itself. 5001 5002 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with 5003 reloads that load an address for the very reload we are considering. 5004 5005 The caller has to make sure that there is no conflict with the return 5006 register. */ 5007 5008static int 5009free_for_value_p (regno, mode, opnum, type, value, out, reloadnum, 5010 ignore_address_reloads) 5011 int regno; 5012 enum machine_mode mode; 5013 int opnum; 5014 enum reload_type type; 5015 rtx value, out; 5016 int reloadnum; 5017 int ignore_address_reloads; 5018{ 5019 int nregs = HARD_REGNO_NREGS (regno, mode); 5020 while (nregs-- > 0) 5021 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, 5022 value, out, reloadnum, 5023 ignore_address_reloads)) 5024 return 0; 5025 return 1; 5026} 5027 5028/* Determine whether the reload reg X overlaps any rtx'es used for 5029 overriding inheritance. Return nonzero if so. */ 5030 5031static int 5032conflicts_with_override (x) 5033 rtx x; 5034{ 5035 int i; 5036 for (i = 0; i < n_reloads; i++) 5037 if (reload_override_in[i] 5038 && reg_overlap_mentioned_p (x, reload_override_in[i])) 5039 return 1; 5040 return 0; 5041} 5042 5043/* Give an error message saying we failed to find a reload for INSN, 5044 and clear out reload R. */ 5045static void 5046failed_reload (insn, r) 5047 rtx insn; 5048 int r; 5049{ 5050 if (asm_noperands (PATTERN (insn)) < 0) 5051 /* It's the compiler's fault. */ 5052 fatal_insn ("could not find a spill register", insn); 5053 5054 /* It's the user's fault; the operand's mode and constraint 5055 don't match. Disable this reload so we don't crash in final. */ 5056 error_for_asm (insn, 5057 "`asm' operand constraint incompatible with operand size"); 5058 rld[r].in = 0; 5059 rld[r].out = 0; 5060 rld[r].reg_rtx = 0; 5061 rld[r].optional = 1; 5062 rld[r].secondary_p = 1; 5063} 5064 5065/* I is the index in SPILL_REG_RTX of the reload register we are to allocate 5066 for reload R. If it's valid, get an rtx for it. Return nonzero if 5067 successful. */ 5068static int 5069set_reload_reg (i, r) 5070 int i, r; 5071{ 5072 int regno; 5073 rtx reg = spill_reg_rtx[i]; 5074 5075 if (reg == 0 || GET_MODE (reg) != rld[r].mode) 5076 spill_reg_rtx[i] = reg 5077 = gen_rtx_REG (rld[r].mode, spill_regs[i]); 5078 5079 regno = true_regnum (reg); 5080 5081 /* Detect when the reload reg can't hold the reload mode. 5082 This used to be one `if', but Sequent compiler can't handle that. */ 5083 if (HARD_REGNO_MODE_OK (regno, rld[r].mode)) 5084 { 5085 enum machine_mode test_mode = VOIDmode; 5086 if (rld[r].in) 5087 test_mode = GET_MODE (rld[r].in); 5088 /* If rld[r].in has VOIDmode, it means we will load it 5089 in whatever mode the reload reg has: to wit, rld[r].mode. 5090 We have already tested that for validity. */ 5091 /* Aside from that, we need to test that the expressions 5092 to reload from or into have modes which are valid for this 5093 reload register. Otherwise the reload insns would be invalid. */ 5094 if (! (rld[r].in != 0 && test_mode != VOIDmode 5095 && ! HARD_REGNO_MODE_OK (regno, test_mode))) 5096 if (! (rld[r].out != 0 5097 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out)))) 5098 { 5099 /* The reg is OK. */ 5100 last_spill_reg = i; 5101 5102 /* Mark as in use for this insn the reload regs we use 5103 for this. */ 5104 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, 5105 rld[r].when_needed, rld[r].mode); 5106 5107 rld[r].reg_rtx = reg; 5108 reload_spill_index[r] = spill_regs[i]; 5109 return 1; 5110 } 5111 } 5112 return 0; 5113} 5114 5115/* Find a spill register to use as a reload register for reload R. 5116 LAST_RELOAD is nonzero if this is the last reload for the insn being 5117 processed. 5118 5119 Set rld[R].reg_rtx to the register allocated. 5120 5121 We return 1 if successful, or 0 if we couldn't find a spill reg and 5122 we didn't change anything. */ 5123 5124static int 5125allocate_reload_reg (chain, r, last_reload) 5126 struct insn_chain *chain ATTRIBUTE_UNUSED; 5127 int r; 5128 int last_reload; 5129{ 5130 int i, pass, count; 5131 5132 /* If we put this reload ahead, thinking it is a group, 5133 then insist on finding a group. Otherwise we can grab a 5134 reg that some other reload needs. 5135 (That can happen when we have a 68000 DATA_OR_FP_REG 5136 which is a group of data regs or one fp reg.) 5137 We need not be so restrictive if there are no more reloads 5138 for this insn. 5139 5140 ??? Really it would be nicer to have smarter handling 5141 for that kind of reg class, where a problem like this is normal. 5142 Perhaps those classes should be avoided for reloading 5143 by use of more alternatives. */ 5144 5145 int force_group = rld[r].nregs > 1 && ! last_reload; 5146 5147 /* If we want a single register and haven't yet found one, 5148 take any reg in the right class and not in use. 5149 If we want a consecutive group, here is where we look for it. 5150 5151 We use two passes so we can first look for reload regs to 5152 reuse, which are already in use for other reloads in this insn, 5153 and only then use additional registers. 5154 I think that maximizing reuse is needed to make sure we don't 5155 run out of reload regs. Suppose we have three reloads, and 5156 reloads A and B can share regs. These need two regs. 5157 Suppose A and B are given different regs. 5158 That leaves none for C. */ 5159 for (pass = 0; pass < 2; pass++) 5160 { 5161 /* I is the index in spill_regs. 5162 We advance it round-robin between insns to use all spill regs 5163 equally, so that inherited reloads have a chance 5164 of leapfrogging each other. */ 5165 5166 i = last_spill_reg; 5167 5168 for (count = 0; count < n_spills; count++) 5169 { 5170 int class = (int) rld[r].class; 5171 int regnum; 5172 5173 i++; 5174 if (i >= n_spills) 5175 i -= n_spills; 5176 regnum = spill_regs[i]; 5177 5178 if ((reload_reg_free_p (regnum, rld[r].opnum, 5179 rld[r].when_needed) 5180 || (rld[r].in 5181 /* We check reload_reg_used to make sure we 5182 don't clobber the return register. */ 5183 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) 5184 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, 5185 rld[r].when_needed, rld[r].in, 5186 rld[r].out, r, 1))) 5187 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum) 5188 && HARD_REGNO_MODE_OK (regnum, rld[r].mode) 5189 /* Look first for regs to share, then for unshared. But 5190 don't share regs used for inherited reloads; they are 5191 the ones we want to preserve. */ 5192 && (pass 5193 || (TEST_HARD_REG_BIT (reload_reg_used_at_all, 5194 regnum) 5195 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, 5196 regnum)))) 5197 { 5198 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode); 5199 /* Avoid the problem where spilling a GENERAL_OR_FP_REG 5200 (on 68000) got us two FP regs. If NR is 1, 5201 we would reject both of them. */ 5202 if (force_group) 5203 nr = rld[r].nregs; 5204 /* If we need only one reg, we have already won. */ 5205 if (nr == 1) 5206 { 5207 /* But reject a single reg if we demand a group. */ 5208 if (force_group) 5209 continue; 5210 break; 5211 } 5212 /* Otherwise check that as many consecutive regs as we need 5213 are available here. */ 5214 while (nr > 1) 5215 { 5216 int regno = regnum + nr - 1; 5217 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno) 5218 && spill_reg_order[regno] >= 0 5219 && reload_reg_free_p (regno, rld[r].opnum, 5220 rld[r].when_needed))) 5221 break; 5222 nr--; 5223 } 5224 if (nr == 1) 5225 break; 5226 } 5227 } 5228 5229 /* If we found something on pass 1, omit pass 2. */ 5230 if (count < n_spills) 5231 break; 5232 } 5233 5234 /* We should have found a spill register by now. */ 5235 if (count >= n_spills) 5236 return 0; 5237 5238 /* I is the index in SPILL_REG_RTX of the reload register we are to 5239 allocate. Get an rtx for it and find its register number. */ 5240 5241 return set_reload_reg (i, r); 5242} 5243 5244/* Initialize all the tables needed to allocate reload registers. 5245 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX 5246 is the array we use to restore the reg_rtx field for every reload. */ 5247 5248static void 5249choose_reload_regs_init (chain, save_reload_reg_rtx) 5250 struct insn_chain *chain; 5251 rtx *save_reload_reg_rtx; 5252{ 5253 int i; 5254 5255 for (i = 0; i < n_reloads; i++) 5256 rld[i].reg_rtx = save_reload_reg_rtx[i]; 5257 5258 memset (reload_inherited, 0, MAX_RELOADS); 5259 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); 5260 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); 5261 5262 CLEAR_HARD_REG_SET (reload_reg_used); 5263 CLEAR_HARD_REG_SET (reload_reg_used_at_all); 5264 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); 5265 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); 5266 CLEAR_HARD_REG_SET (reload_reg_used_in_insn); 5267 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); 5268 5269 CLEAR_HARD_REG_SET (reg_used_in_insn); 5270 { 5271 HARD_REG_SET tmp; 5272 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); 5273 IOR_HARD_REG_SET (reg_used_in_insn, tmp); 5274 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); 5275 IOR_HARD_REG_SET (reg_used_in_insn, tmp); 5276 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); 5277 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); 5278 } 5279 5280 for (i = 0; i < reload_n_operands; i++) 5281 { 5282 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); 5283 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); 5284 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); 5285 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); 5286 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); 5287 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); 5288 } 5289 5290 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs); 5291 5292 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); 5293 5294 for (i = 0; i < n_reloads; i++) 5295 /* If we have already decided to use a certain register, 5296 don't use it in another way. */ 5297 if (rld[i].reg_rtx) 5298 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, 5299 rld[i].when_needed, rld[i].mode); 5300} 5301 5302/* Assign hard reg targets for the pseudo-registers we must reload 5303 into hard regs for this insn. 5304 Also output the instructions to copy them in and out of the hard regs. 5305 5306 For machines with register classes, we are responsible for 5307 finding a reload reg in the proper class. */ 5308 5309static void 5310choose_reload_regs (chain) 5311 struct insn_chain *chain; 5312{ 5313 rtx insn = chain->insn; 5314 int i, j; 5315 unsigned int max_group_size = 1; 5316 enum reg_class group_class = NO_REGS; 5317 int pass, win, inheritance; 5318 5319 rtx save_reload_reg_rtx[MAX_RELOADS]; 5320 5321 /* In order to be certain of getting the registers we need, 5322 we must sort the reloads into order of increasing register class. 5323 Then our grabbing of reload registers will parallel the process 5324 that provided the reload registers. 5325 5326 Also note whether any of the reloads wants a consecutive group of regs. 5327 If so, record the maximum size of the group desired and what 5328 register class contains all the groups needed by this insn. */ 5329 5330 for (j = 0; j < n_reloads; j++) 5331 { 5332 reload_order[j] = j; 5333 reload_spill_index[j] = -1; 5334 5335 if (rld[j].nregs > 1) 5336 { 5337 max_group_size = MAX (rld[j].nregs, max_group_size); 5338 group_class 5339 = reg_class_superunion[(int) rld[j].class][(int) group_class]; 5340 } 5341 5342 save_reload_reg_rtx[j] = rld[j].reg_rtx; 5343 } 5344 5345 if (n_reloads > 1) 5346 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); 5347 5348 /* If -O, try first with inheritance, then turning it off. 5349 If not -O, don't do inheritance. 5350 Using inheritance when not optimizing leads to paradoxes 5351 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves 5352 because one side of the comparison might be inherited. */ 5353 win = 0; 5354 for (inheritance = optimize > 0; inheritance >= 0; inheritance--) 5355 { 5356 choose_reload_regs_init (chain, save_reload_reg_rtx); 5357 5358 /* Process the reloads in order of preference just found. 5359 Beyond this point, subregs can be found in reload_reg_rtx. 5360 5361 This used to look for an existing reloaded home for all of the 5362 reloads, and only then perform any new reloads. But that could lose 5363 if the reloads were done out of reg-class order because a later 5364 reload with a looser constraint might have an old home in a register 5365 needed by an earlier reload with a tighter constraint. 5366 5367 To solve this, we make two passes over the reloads, in the order 5368 described above. In the first pass we try to inherit a reload 5369 from a previous insn. If there is a later reload that needs a 5370 class that is a proper subset of the class being processed, we must 5371 also allocate a spill register during the first pass. 5372 5373 Then make a second pass over the reloads to allocate any reloads 5374 that haven't been given registers yet. */ 5375 5376 for (j = 0; j < n_reloads; j++) 5377 { 5378 int r = reload_order[j]; 5379 rtx search_equiv = NULL_RTX; 5380 5381 /* Ignore reloads that got marked inoperative. */ 5382 if (rld[r].out == 0 && rld[r].in == 0 5383 && ! rld[r].secondary_p) 5384 continue; 5385 5386 /* If find_reloads chose to use reload_in or reload_out as a reload 5387 register, we don't need to chose one. Otherwise, try even if it 5388 found one since we might save an insn if we find the value lying 5389 around. 5390 Try also when reload_in is a pseudo without a hard reg. */ 5391 if (rld[r].in != 0 && rld[r].reg_rtx != 0 5392 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) 5393 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) 5394 && GET_CODE (rld[r].in) != MEM 5395 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) 5396 continue; 5397 5398#if 0 /* No longer needed for correct operation. 5399 It might give better code, or might not; worth an experiment? */ 5400 /* If this is an optional reload, we can't inherit from earlier insns 5401 until we are sure that any non-optional reloads have been allocated. 5402 The following code takes advantage of the fact that optional reloads 5403 are at the end of reload_order. */ 5404 if (rld[r].optional != 0) 5405 for (i = 0; i < j; i++) 5406 if ((rld[reload_order[i]].out != 0 5407 || rld[reload_order[i]].in != 0 5408 || rld[reload_order[i]].secondary_p) 5409 && ! rld[reload_order[i]].optional 5410 && rld[reload_order[i]].reg_rtx == 0) 5411 allocate_reload_reg (chain, reload_order[i], 0); 5412#endif 5413 5414 /* First see if this pseudo is already available as reloaded 5415 for a previous insn. We cannot try to inherit for reloads 5416 that are smaller than the maximum number of registers needed 5417 for groups unless the register we would allocate cannot be used 5418 for the groups. 5419 5420 We could check here to see if this is a secondary reload for 5421 an object that is already in a register of the desired class. 5422 This would avoid the need for the secondary reload register. 5423 But this is complex because we can't easily determine what 5424 objects might want to be loaded via this reload. So let a 5425 register be allocated here. In `emit_reload_insns' we suppress 5426 one of the loads in the case described above. */ 5427 5428 if (inheritance) 5429 { 5430 int byte = 0; 5431 int regno = -1; 5432 enum machine_mode mode = VOIDmode; 5433 5434 if (rld[r].in == 0) 5435 ; 5436 else if (GET_CODE (rld[r].in) == REG) 5437 { 5438 regno = REGNO (rld[r].in); 5439 mode = GET_MODE (rld[r].in); 5440 } 5441 else if (GET_CODE (rld[r].in_reg) == REG) 5442 { 5443 regno = REGNO (rld[r].in_reg); 5444 mode = GET_MODE (rld[r].in_reg); 5445 } 5446 else if (GET_CODE (rld[r].in_reg) == SUBREG 5447 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG) 5448 { 5449 byte = SUBREG_BYTE (rld[r].in_reg); 5450 regno = REGNO (SUBREG_REG (rld[r].in_reg)); 5451 if (regno < FIRST_PSEUDO_REGISTER) 5452 regno = subreg_regno (rld[r].in_reg); 5453 mode = GET_MODE (rld[r].in_reg); 5454 } 5455#ifdef AUTO_INC_DEC 5456 else if ((GET_CODE (rld[r].in_reg) == PRE_INC 5457 || GET_CODE (rld[r].in_reg) == PRE_DEC 5458 || GET_CODE (rld[r].in_reg) == POST_INC 5459 || GET_CODE (rld[r].in_reg) == POST_DEC) 5460 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG) 5461 { 5462 regno = REGNO (XEXP (rld[r].in_reg, 0)); 5463 mode = GET_MODE (XEXP (rld[r].in_reg, 0)); 5464 rld[r].out = rld[r].in; 5465 } 5466#endif 5467#if 0 5468 /* This won't work, since REGNO can be a pseudo reg number. 5469 Also, it takes much more hair to keep track of all the things 5470 that can invalidate an inherited reload of part of a pseudoreg. */ 5471 else if (GET_CODE (rld[r].in) == SUBREG 5472 && GET_CODE (SUBREG_REG (rld[r].in)) == REG) 5473 regno = subreg_regno (rld[r].in); 5474#endif 5475 5476 if (regno >= 0 && reg_last_reload_reg[regno] != 0) 5477 { 5478 enum reg_class class = rld[r].class, last_class; 5479 rtx last_reg = reg_last_reload_reg[regno]; 5480 enum machine_mode need_mode; 5481 5482 i = REGNO (last_reg); 5483 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); 5484 last_class = REGNO_REG_CLASS (i); 5485 5486 if (byte == 0) 5487 need_mode = mode; 5488 else 5489 need_mode 5490 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte, 5491 GET_MODE_CLASS (mode)); 5492 5493 if ( 5494#ifdef CANNOT_CHANGE_MODE_CLASS 5495 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg), 5496 need_mode) 5497 && 5498#endif 5499 (GET_MODE_SIZE (GET_MODE (last_reg)) 5500 >= GET_MODE_SIZE (need_mode)) 5501#ifdef CANNOT_CHANGE_MODE_CLASS 5502 ) 5503#endif 5504 && reg_reloaded_contents[i] == regno 5505 && TEST_HARD_REG_BIT (reg_reloaded_valid, i) 5506 && HARD_REGNO_MODE_OK (i, rld[r].mode) 5507 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i) 5508 /* Even if we can't use this register as a reload 5509 register, we might use it for reload_override_in, 5510 if copying it to the desired class is cheap 5511 enough. */ 5512 || ((REGISTER_MOVE_COST (mode, last_class, class) 5513 < MEMORY_MOVE_COST (mode, class, 1)) 5514#ifdef SECONDARY_INPUT_RELOAD_CLASS 5515 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode, 5516 last_reg) 5517 == NO_REGS) 5518#endif 5519#ifdef SECONDARY_MEMORY_NEEDED 5520 && ! SECONDARY_MEMORY_NEEDED (last_class, class, 5521 mode) 5522#endif 5523 )) 5524 5525 && (rld[r].nregs == max_group_size 5526 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], 5527 i)) 5528 && free_for_value_p (i, rld[r].mode, rld[r].opnum, 5529 rld[r].when_needed, rld[r].in, 5530 const0_rtx, r, 1)) 5531 { 5532 /* If a group is needed, verify that all the subsequent 5533 registers still have their values intact. */ 5534 int nr = HARD_REGNO_NREGS (i, rld[r].mode); 5535 int k; 5536 5537 for (k = 1; k < nr; k++) 5538 if (reg_reloaded_contents[i + k] != regno 5539 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) 5540 break; 5541 5542 if (k == nr) 5543 { 5544 int i1; 5545 int bad_for_class; 5546 5547 last_reg = (GET_MODE (last_reg) == mode 5548 ? last_reg : gen_rtx_REG (mode, i)); 5549 5550 bad_for_class = 0; 5551 for (k = 0; k < nr; k++) 5552 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], 5553 i+k); 5554 5555 /* We found a register that contains the 5556 value we need. If this register is the 5557 same as an `earlyclobber' operand of the 5558 current insn, just mark it as a place to 5559 reload from since we can't use it as the 5560 reload register itself. */ 5561 5562 for (i1 = 0; i1 < n_earlyclobbers; i1++) 5563 if (reg_overlap_mentioned_for_reload_p 5564 (reg_last_reload_reg[regno], 5565 reload_earlyclobbers[i1])) 5566 break; 5567 5568 if (i1 != n_earlyclobbers 5569 || ! (free_for_value_p (i, rld[r].mode, 5570 rld[r].opnum, 5571 rld[r].when_needed, rld[r].in, 5572 rld[r].out, r, 1)) 5573 /* Don't use it if we'd clobber a pseudo reg. */ 5574 || (TEST_HARD_REG_BIT (reg_used_in_insn, i) 5575 && rld[r].out 5576 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) 5577 /* Don't clobber the frame pointer. */ 5578 || (i == HARD_FRAME_POINTER_REGNUM 5579 && frame_pointer_needed 5580 && rld[r].out) 5581 /* Don't really use the inherited spill reg 5582 if we need it wider than we've got it. */ 5583 || (GET_MODE_SIZE (rld[r].mode) 5584 > GET_MODE_SIZE (mode)) 5585 || bad_for_class 5586 5587 /* If find_reloads chose reload_out as reload 5588 register, stay with it - that leaves the 5589 inherited register for subsequent reloads. */ 5590 || (rld[r].out && rld[r].reg_rtx 5591 && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) 5592 { 5593 if (! rld[r].optional) 5594 { 5595 reload_override_in[r] = last_reg; 5596 reload_inheritance_insn[r] 5597 = reg_reloaded_insn[i]; 5598 } 5599 } 5600 else 5601 { 5602 int k; 5603 /* We can use this as a reload reg. */ 5604 /* Mark the register as in use for this part of 5605 the insn. */ 5606 mark_reload_reg_in_use (i, 5607 rld[r].opnum, 5608 rld[r].when_needed, 5609 rld[r].mode); 5610 rld[r].reg_rtx = last_reg; 5611 reload_inherited[r] = 1; 5612 reload_inheritance_insn[r] 5613 = reg_reloaded_insn[i]; 5614 reload_spill_index[r] = i; 5615 for (k = 0; k < nr; k++) 5616 SET_HARD_REG_BIT (reload_reg_used_for_inherit, 5617 i + k); 5618 } 5619 } 5620 } 5621 } 5622 } 5623 5624 /* Here's another way to see if the value is already lying around. */ 5625 if (inheritance 5626 && rld[r].in != 0 5627 && ! reload_inherited[r] 5628 && rld[r].out == 0 5629 && (CONSTANT_P (rld[r].in) 5630 || GET_CODE (rld[r].in) == PLUS 5631 || GET_CODE (rld[r].in) == REG 5632 || GET_CODE (rld[r].in) == MEM) 5633 && (rld[r].nregs == max_group_size 5634 || ! reg_classes_intersect_p (rld[r].class, group_class))) 5635 search_equiv = rld[r].in; 5636 /* If this is an output reload from a simple move insn, look 5637 if an equivalence for the input is available. */ 5638 else if (inheritance && rld[r].in == 0 && rld[r].out != 0) 5639 { 5640 rtx set = single_set (insn); 5641 5642 if (set 5643 && rtx_equal_p (rld[r].out, SET_DEST (set)) 5644 && CONSTANT_P (SET_SRC (set))) 5645 search_equiv = SET_SRC (set); 5646 } 5647 5648 if (search_equiv) 5649 { 5650 rtx equiv 5651 = find_equiv_reg (search_equiv, insn, rld[r].class, 5652 -1, NULL, 0, rld[r].mode); 5653 int regno = 0; 5654 5655 if (equiv != 0) 5656 { 5657 if (GET_CODE (equiv) == REG) 5658 regno = REGNO (equiv); 5659 else if (GET_CODE (equiv) == SUBREG) 5660 { 5661 /* This must be a SUBREG of a hard register. 5662 Make a new REG since this might be used in an 5663 address and not all machines support SUBREGs 5664 there. */ 5665 regno = subreg_regno (equiv); 5666 equiv = gen_rtx_REG (rld[r].mode, regno); 5667 } 5668 else 5669 abort (); 5670 } 5671 5672 /* If we found a spill reg, reject it unless it is free 5673 and of the desired class. */ 5674 if (equiv != 0 5675 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno) 5676 && ! free_for_value_p (regno, rld[r].mode, 5677 rld[r].opnum, rld[r].when_needed, 5678 rld[r].in, rld[r].out, r, 1)) 5679 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class], 5680 regno))) 5681 equiv = 0; 5682 5683 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode)) 5684 equiv = 0; 5685 5686 /* We found a register that contains the value we need. 5687 If this register is the same as an `earlyclobber' operand 5688 of the current insn, just mark it as a place to reload from 5689 since we can't use it as the reload register itself. */ 5690 5691 if (equiv != 0) 5692 for (i = 0; i < n_earlyclobbers; i++) 5693 if (reg_overlap_mentioned_for_reload_p (equiv, 5694 reload_earlyclobbers[i])) 5695 { 5696 if (! rld[r].optional) 5697 reload_override_in[r] = equiv; 5698 equiv = 0; 5699 break; 5700 } 5701 5702 /* If the equiv register we have found is explicitly clobbered 5703 in the current insn, it depends on the reload type if we 5704 can use it, use it for reload_override_in, or not at all. 5705 In particular, we then can't use EQUIV for a 5706 RELOAD_FOR_OUTPUT_ADDRESS reload. */ 5707 5708 if (equiv != 0) 5709 { 5710 if (regno_clobbered_p (regno, insn, rld[r].mode, 0)) 5711 switch (rld[r].when_needed) 5712 { 5713 case RELOAD_FOR_OTHER_ADDRESS: 5714 case RELOAD_FOR_INPADDR_ADDRESS: 5715 case RELOAD_FOR_INPUT_ADDRESS: 5716 case RELOAD_FOR_OPADDR_ADDR: 5717 break; 5718 case RELOAD_OTHER: 5719 case RELOAD_FOR_INPUT: 5720 case RELOAD_FOR_OPERAND_ADDRESS: 5721 if (! rld[r].optional) 5722 reload_override_in[r] = equiv; 5723 /* Fall through. */ 5724 default: 5725 equiv = 0; 5726 break; 5727 } 5728 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) 5729 switch (rld[r].when_needed) 5730 { 5731 case RELOAD_FOR_OTHER_ADDRESS: 5732 case RELOAD_FOR_INPADDR_ADDRESS: 5733 case RELOAD_FOR_INPUT_ADDRESS: 5734 case RELOAD_FOR_OPADDR_ADDR: 5735 case RELOAD_FOR_OPERAND_ADDRESS: 5736 case RELOAD_FOR_INPUT: 5737 break; 5738 case RELOAD_OTHER: 5739 if (! rld[r].optional) 5740 reload_override_in[r] = equiv; 5741 /* Fall through. */ 5742 default: 5743 equiv = 0; 5744 break; 5745 } 5746 } 5747 5748 /* If we found an equivalent reg, say no code need be generated 5749 to load it, and use it as our reload reg. */ 5750 if (equiv != 0 5751 && (regno != HARD_FRAME_POINTER_REGNUM 5752 || !frame_pointer_needed)) 5753 { 5754 int nr = HARD_REGNO_NREGS (regno, rld[r].mode); 5755 int k; 5756 rld[r].reg_rtx = equiv; 5757 reload_inherited[r] = 1; 5758 5759 /* If reg_reloaded_valid is not set for this register, 5760 there might be a stale spill_reg_store lying around. 5761 We must clear it, since otherwise emit_reload_insns 5762 might delete the store. */ 5763 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) 5764 spill_reg_store[regno] = NULL_RTX; 5765 /* If any of the hard registers in EQUIV are spill 5766 registers, mark them as in use for this insn. */ 5767 for (k = 0; k < nr; k++) 5768 { 5769 i = spill_reg_order[regno + k]; 5770 if (i >= 0) 5771 { 5772 mark_reload_reg_in_use (regno, rld[r].opnum, 5773 rld[r].when_needed, 5774 rld[r].mode); 5775 SET_HARD_REG_BIT (reload_reg_used_for_inherit, 5776 regno + k); 5777 } 5778 } 5779 } 5780 } 5781 5782 /* If we found a register to use already, or if this is an optional 5783 reload, we are done. */ 5784 if (rld[r].reg_rtx != 0 || rld[r].optional != 0) 5785 continue; 5786 5787#if 0 5788 /* No longer needed for correct operation. Might or might 5789 not give better code on the average. Want to experiment? */ 5790 5791 /* See if there is a later reload that has a class different from our 5792 class that intersects our class or that requires less register 5793 than our reload. If so, we must allocate a register to this 5794 reload now, since that reload might inherit a previous reload 5795 and take the only available register in our class. Don't do this 5796 for optional reloads since they will force all previous reloads 5797 to be allocated. Also don't do this for reloads that have been 5798 turned off. */ 5799 5800 for (i = j + 1; i < n_reloads; i++) 5801 { 5802 int s = reload_order[i]; 5803 5804 if ((rld[s].in == 0 && rld[s].out == 0 5805 && ! rld[s].secondary_p) 5806 || rld[s].optional) 5807 continue; 5808 5809 if ((rld[s].class != rld[r].class 5810 && reg_classes_intersect_p (rld[r].class, 5811 rld[s].class)) 5812 || rld[s].nregs < rld[r].nregs) 5813 break; 5814 } 5815 5816 if (i == n_reloads) 5817 continue; 5818 5819 allocate_reload_reg (chain, r, j == n_reloads - 1); 5820#endif 5821 } 5822 5823 /* Now allocate reload registers for anything non-optional that 5824 didn't get one yet. */ 5825 for (j = 0; j < n_reloads; j++) 5826 { 5827 int r = reload_order[j]; 5828 5829 /* Ignore reloads that got marked inoperative. */ 5830 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) 5831 continue; 5832 5833 /* Skip reloads that already have a register allocated or are 5834 optional. */ 5835 if (rld[r].reg_rtx != 0 || rld[r].optional) 5836 continue; 5837 5838 if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) 5839 break; 5840 } 5841 5842 /* If that loop got all the way, we have won. */ 5843 if (j == n_reloads) 5844 { 5845 win = 1; 5846 break; 5847 } 5848 5849 /* Loop around and try without any inheritance. */ 5850 } 5851 5852 if (! win) 5853 { 5854 /* First undo everything done by the failed attempt 5855 to allocate with inheritance. */ 5856 choose_reload_regs_init (chain, save_reload_reg_rtx); 5857 5858 /* Some sanity tests to verify that the reloads found in the first 5859 pass are identical to the ones we have now. */ 5860 if (chain->n_reloads != n_reloads) 5861 abort (); 5862 5863 for (i = 0; i < n_reloads; i++) 5864 { 5865 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) 5866 continue; 5867 if (chain->rld[i].when_needed != rld[i].when_needed) 5868 abort (); 5869 for (j = 0; j < n_spills; j++) 5870 if (spill_regs[j] == chain->rld[i].regno) 5871 if (! set_reload_reg (j, i)) 5872 failed_reload (chain->insn, i); 5873 } 5874 } 5875 5876 /* If we thought we could inherit a reload, because it seemed that 5877 nothing else wanted the same reload register earlier in the insn, 5878 verify that assumption, now that all reloads have been assigned. 5879 Likewise for reloads where reload_override_in has been set. */ 5880 5881 /* If doing expensive optimizations, do one preliminary pass that doesn't 5882 cancel any inheritance, but removes reloads that have been needed only 5883 for reloads that we know can be inherited. */ 5884 for (pass = flag_expensive_optimizations; pass >= 0; pass--) 5885 { 5886 for (j = 0; j < n_reloads; j++) 5887 { 5888 int r = reload_order[j]; 5889 rtx check_reg; 5890 if (reload_inherited[r] && rld[r].reg_rtx) 5891 check_reg = rld[r].reg_rtx; 5892 else if (reload_override_in[r] 5893 && (GET_CODE (reload_override_in[r]) == REG 5894 || GET_CODE (reload_override_in[r]) == SUBREG)) 5895 check_reg = reload_override_in[r]; 5896 else 5897 continue; 5898 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, 5899 rld[r].opnum, rld[r].when_needed, rld[r].in, 5900 (reload_inherited[r] 5901 ? rld[r].out : const0_rtx), 5902 r, 1)) 5903 { 5904 if (pass) 5905 continue; 5906 reload_inherited[r] = 0; 5907 reload_override_in[r] = 0; 5908 } 5909 /* If we can inherit a RELOAD_FOR_INPUT, or can use a 5910 reload_override_in, then we do not need its related 5911 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; 5912 likewise for other reload types. 5913 We handle this by removing a reload when its only replacement 5914 is mentioned in reload_in of the reload we are going to inherit. 5915 A special case are auto_inc expressions; even if the input is 5916 inherited, we still need the address for the output. We can 5917 recognize them because they have RELOAD_OUT set to RELOAD_IN. 5918 If we succeeded removing some reload and we are doing a preliminary 5919 pass just to remove such reloads, make another pass, since the 5920 removal of one reload might allow us to inherit another one. */ 5921 else if (rld[r].in 5922 && rld[r].out != rld[r].in 5923 && remove_address_replacements (rld[r].in) && pass) 5924 pass = 2; 5925 } 5926 } 5927 5928 /* Now that reload_override_in is known valid, 5929 actually override reload_in. */ 5930 for (j = 0; j < n_reloads; j++) 5931 if (reload_override_in[j]) 5932 rld[j].in = reload_override_in[j]; 5933 5934 /* If this reload won't be done because it has been cancelled or is 5935 optional and not inherited, clear reload_reg_rtx so other 5936 routines (such as subst_reloads) don't get confused. */ 5937 for (j = 0; j < n_reloads; j++) 5938 if (rld[j].reg_rtx != 0 5939 && ((rld[j].optional && ! reload_inherited[j]) 5940 || (rld[j].in == 0 && rld[j].out == 0 5941 && ! rld[j].secondary_p))) 5942 { 5943 int regno = true_regnum (rld[j].reg_rtx); 5944 5945 if (spill_reg_order[regno] >= 0) 5946 clear_reload_reg_in_use (regno, rld[j].opnum, 5947 rld[j].when_needed, rld[j].mode); 5948 rld[j].reg_rtx = 0; 5949 reload_spill_index[j] = -1; 5950 } 5951 5952 /* Record which pseudos and which spill regs have output reloads. */ 5953 for (j = 0; j < n_reloads; j++) 5954 { 5955 int r = reload_order[j]; 5956 5957 i = reload_spill_index[r]; 5958 5959 /* I is nonneg if this reload uses a register. 5960 If rld[r].reg_rtx is 0, this is an optional reload 5961 that we opted to ignore. */ 5962 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG 5963 && rld[r].reg_rtx != 0) 5964 { 5965 int nregno = REGNO (rld[r].out_reg); 5966 int nr = 1; 5967 5968 if (nregno < FIRST_PSEUDO_REGISTER) 5969 nr = HARD_REGNO_NREGS (nregno, rld[r].mode); 5970 5971 while (--nr >= 0) 5972 reg_has_output_reload[nregno + nr] = 1; 5973 5974 if (i >= 0) 5975 { 5976 nr = HARD_REGNO_NREGS (i, rld[r].mode); 5977 while (--nr >= 0) 5978 SET_HARD_REG_BIT (reg_is_output_reload, i + nr); 5979 } 5980 5981 if (rld[r].when_needed != RELOAD_OTHER 5982 && rld[r].when_needed != RELOAD_FOR_OUTPUT 5983 && rld[r].when_needed != RELOAD_FOR_INSN) 5984 abort (); 5985 } 5986 } 5987} 5988 5989/* Deallocate the reload register for reload R. This is called from 5990 remove_address_replacements. */ 5991 5992void 5993deallocate_reload_reg (r) 5994 int r; 5995{ 5996 int regno; 5997 5998 if (! rld[r].reg_rtx) 5999 return; 6000 regno = true_regnum (rld[r].reg_rtx); 6001 rld[r].reg_rtx = 0; 6002 if (spill_reg_order[regno] >= 0) 6003 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, 6004 rld[r].mode); 6005 reload_spill_index[r] = -1; 6006} 6007 6008/* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two 6009 reloads of the same item for fear that we might not have enough reload 6010 registers. However, normally they will get the same reload register 6011 and hence actually need not be loaded twice. 6012 6013 Here we check for the most common case of this phenomenon: when we have 6014 a number of reloads for the same object, each of which were allocated 6015 the same reload_reg_rtx, that reload_reg_rtx is not used for any other 6016 reload, and is not modified in the insn itself. If we find such, 6017 merge all the reloads and set the resulting reload to RELOAD_OTHER. 6018 This will not increase the number of spill registers needed and will 6019 prevent redundant code. */ 6020 6021static void 6022merge_assigned_reloads (insn) 6023 rtx insn; 6024{ 6025 int i, j; 6026 6027 /* Scan all the reloads looking for ones that only load values and 6028 are not already RELOAD_OTHER and ones whose reload_reg_rtx are 6029 assigned and not modified by INSN. */ 6030 6031 for (i = 0; i < n_reloads; i++) 6032 { 6033 int conflicting_input = 0; 6034 int max_input_address_opnum = -1; 6035 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS; 6036 6037 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER 6038 || rld[i].out != 0 || rld[i].reg_rtx == 0 6039 || reg_set_p (rld[i].reg_rtx, insn)) 6040 continue; 6041 6042 /* Look at all other reloads. Ensure that the only use of this 6043 reload_reg_rtx is in a reload that just loads the same value 6044 as we do. Note that any secondary reloads must be of the identical 6045 class since the values, modes, and result registers are the 6046 same, so we need not do anything with any secondary reloads. */ 6047 6048 for (j = 0; j < n_reloads; j++) 6049 { 6050 if (i == j || rld[j].reg_rtx == 0 6051 || ! reg_overlap_mentioned_p (rld[j].reg_rtx, 6052 rld[i].reg_rtx)) 6053 continue; 6054 6055 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS 6056 && rld[j].opnum > max_input_address_opnum) 6057 max_input_address_opnum = rld[j].opnum; 6058 6059 /* If the reload regs aren't exactly the same (e.g, different modes) 6060 or if the values are different, we can't merge this reload. 6061 But if it is an input reload, we might still merge 6062 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */ 6063 6064 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) 6065 || rld[j].out != 0 || rld[j].in == 0 6066 || ! rtx_equal_p (rld[i].in, rld[j].in)) 6067 { 6068 if (rld[j].when_needed != RELOAD_FOR_INPUT 6069 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS 6070 || rld[i].opnum > rld[j].opnum) 6071 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS)) 6072 break; 6073 conflicting_input = 1; 6074 if (min_conflicting_input_opnum > rld[j].opnum) 6075 min_conflicting_input_opnum = rld[j].opnum; 6076 } 6077 } 6078 6079 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if 6080 we, in fact, found any matching reloads. */ 6081 6082 if (j == n_reloads 6083 && max_input_address_opnum <= min_conflicting_input_opnum) 6084 { 6085 for (j = 0; j < n_reloads; j++) 6086 if (i != j && rld[j].reg_rtx != 0 6087 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx) 6088 && (! conflicting_input 6089 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS 6090 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS)) 6091 { 6092 rld[i].when_needed = RELOAD_OTHER; 6093 rld[j].in = 0; 6094 reload_spill_index[j] = -1; 6095 transfer_replacements (i, j); 6096 } 6097 6098 /* If this is now RELOAD_OTHER, look for any reloads that load 6099 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS 6100 if they were for inputs, RELOAD_OTHER for outputs. Note that 6101 this test is equivalent to looking for reloads for this operand 6102 number. */ 6103 /* We must take special care when there are two or more reloads to 6104 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the 6105 same value or a part of it; we must not change its type if there 6106 is a conflicting input. */ 6107 6108 if (rld[i].when_needed == RELOAD_OTHER) 6109 for (j = 0; j < n_reloads; j++) 6110 if (rld[j].in != 0 6111 && rld[j].when_needed != RELOAD_OTHER 6112 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS 6113 && (! conflicting_input 6114 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS 6115 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) 6116 && reg_overlap_mentioned_for_reload_p (rld[j].in, 6117 rld[i].in)) 6118 { 6119 int k; 6120 6121 rld[j].when_needed 6122 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS 6123 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS) 6124 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER); 6125 6126 /* Check to see if we accidentally converted two reloads 6127 that use the same reload register with different inputs 6128 to the same type. If so, the resulting code won't work, 6129 so abort. */ 6130 if (rld[j].reg_rtx) 6131 for (k = 0; k < j; k++) 6132 if (rld[k].in != 0 && rld[k].reg_rtx != 0 6133 && rld[k].when_needed == rld[j].when_needed 6134 && rtx_equal_p (rld[k].reg_rtx, rld[j].reg_rtx) 6135 && ! rtx_equal_p (rld[k].in, rld[j].in)) 6136 abort (); 6137 } 6138 } 6139 } 6140} 6141 6142/* These arrays are filled by emit_reload_insns and its subroutines. */ 6143static rtx input_reload_insns[MAX_RECOG_OPERANDS]; 6144static rtx other_input_address_reload_insns = 0; 6145static rtx other_input_reload_insns = 0; 6146static rtx input_address_reload_insns[MAX_RECOG_OPERANDS]; 6147static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; 6148static rtx output_reload_insns[MAX_RECOG_OPERANDS]; 6149static rtx output_address_reload_insns[MAX_RECOG_OPERANDS]; 6150static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; 6151static rtx operand_reload_insns = 0; 6152static rtx other_operand_reload_insns = 0; 6153static rtx other_output_reload_insns[MAX_RECOG_OPERANDS]; 6154 6155/* Values to be put in spill_reg_store are put here first. */ 6156static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER]; 6157static HARD_REG_SET reg_reloaded_died; 6158 6159/* Generate insns to perform reload RL, which is for the insn in CHAIN and 6160 has the number J. OLD contains the value to be used as input. */ 6161 6162static void 6163emit_input_reload_insns (chain, rl, old, j) 6164 struct insn_chain *chain; 6165 struct reload *rl; 6166 rtx old; 6167 int j; 6168{ 6169 rtx insn = chain->insn; 6170 rtx reloadreg = rl->reg_rtx; 6171 rtx oldequiv_reg = 0; 6172 rtx oldequiv = 0; 6173 int special = 0; 6174 enum machine_mode mode; 6175 rtx *where; 6176 6177 /* Determine the mode to reload in. 6178 This is very tricky because we have three to choose from. 6179 There is the mode the insn operand wants (rl->inmode). 6180 There is the mode of the reload register RELOADREG. 6181 There is the intrinsic mode of the operand, which we could find 6182 by stripping some SUBREGs. 6183 It turns out that RELOADREG's mode is irrelevant: 6184 we can change that arbitrarily. 6185 6186 Consider (SUBREG:SI foo:QI) as an operand that must be SImode; 6187 then the reload reg may not support QImode moves, so use SImode. 6188 If foo is in memory due to spilling a pseudo reg, this is safe, 6189 because the QImode value is in the least significant part of a 6190 slot big enough for a SImode. If foo is some other sort of 6191 memory reference, then it is impossible to reload this case, 6192 so previous passes had better make sure this never happens. 6193 6194 Then consider a one-word union which has SImode and one of its 6195 members is a float, being fetched as (SUBREG:SF union:SI). 6196 We must fetch that as SFmode because we could be loading into 6197 a float-only register. In this case OLD's mode is correct. 6198 6199 Consider an immediate integer: it has VOIDmode. Here we need 6200 to get a mode from something else. 6201 6202 In some cases, there is a fourth mode, the operand's 6203 containing mode. If the insn specifies a containing mode for 6204 this operand, it overrides all others. 6205 6206 I am not sure whether the algorithm here is always right, 6207 but it does the right things in those cases. */ 6208 6209 mode = GET_MODE (old); 6210 if (mode == VOIDmode) 6211 mode = rl->inmode; 6212 6213#ifdef SECONDARY_INPUT_RELOAD_CLASS 6214 /* If we need a secondary register for this operation, see if 6215 the value is already in a register in that class. Don't 6216 do this if the secondary register will be used as a scratch 6217 register. */ 6218 6219 if (rl->secondary_in_reload >= 0 6220 && rl->secondary_in_icode == CODE_FOR_nothing 6221 && optimize) 6222 oldequiv 6223 = find_equiv_reg (old, insn, 6224 rld[rl->secondary_in_reload].class, 6225 -1, NULL, 0, mode); 6226#endif 6227 6228 /* If reloading from memory, see if there is a register 6229 that already holds the same value. If so, reload from there. 6230 We can pass 0 as the reload_reg_p argument because 6231 any other reload has either already been emitted, 6232 in which case find_equiv_reg will see the reload-insn, 6233 or has yet to be emitted, in which case it doesn't matter 6234 because we will use this equiv reg right away. */ 6235 6236 if (oldequiv == 0 && optimize 6237 && (GET_CODE (old) == MEM 6238 || (GET_CODE (old) == REG 6239 && REGNO (old) >= FIRST_PSEUDO_REGISTER 6240 && reg_renumber[REGNO (old)] < 0))) 6241 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode); 6242 6243 if (oldequiv) 6244 { 6245 unsigned int regno = true_regnum (oldequiv); 6246 6247 /* Don't use OLDEQUIV if any other reload changes it at an 6248 earlier stage of this insn or at this stage. */ 6249 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed, 6250 rl->in, const0_rtx, j, 0)) 6251 oldequiv = 0; 6252 6253 /* If it is no cheaper to copy from OLDEQUIV into the 6254 reload register than it would be to move from memory, 6255 don't use it. Likewise, if we need a secondary register 6256 or memory. */ 6257 6258 if (oldequiv != 0 6259 && ((REGNO_REG_CLASS (regno) != rl->class 6260 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno), 6261 rl->class) 6262 >= MEMORY_MOVE_COST (mode, rl->class, 1))) 6263#ifdef SECONDARY_INPUT_RELOAD_CLASS 6264 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class, 6265 mode, oldequiv) 6266 != NO_REGS) 6267#endif 6268#ifdef SECONDARY_MEMORY_NEEDED 6269 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno), 6270 rl->class, 6271 mode) 6272#endif 6273 )) 6274 oldequiv = 0; 6275 } 6276 6277 /* delete_output_reload is only invoked properly if old contains 6278 the original pseudo register. Since this is replaced with a 6279 hard reg when RELOAD_OVERRIDE_IN is set, see if we can 6280 find the pseudo in RELOAD_IN_REG. */ 6281 if (oldequiv == 0 6282 && reload_override_in[j] 6283 && GET_CODE (rl->in_reg) == REG) 6284 { 6285 oldequiv = old; 6286 old = rl->in_reg; 6287 } 6288 if (oldequiv == 0) 6289 oldequiv = old; 6290 else if (GET_CODE (oldequiv) == REG) 6291 oldequiv_reg = oldequiv; 6292 else if (GET_CODE (oldequiv) == SUBREG) 6293 oldequiv_reg = SUBREG_REG (oldequiv); 6294 6295 /* If we are reloading from a register that was recently stored in 6296 with an output-reload, see if we can prove there was 6297 actually no need to store the old value in it. */ 6298 6299 if (optimize && GET_CODE (oldequiv) == REG 6300 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER 6301 && spill_reg_store[REGNO (oldequiv)] 6302 && GET_CODE (old) == REG 6303 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) 6304 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], 6305 rl->out_reg))) 6306 delete_output_reload (insn, j, REGNO (oldequiv)); 6307 6308 /* Encapsulate both RELOADREG and OLDEQUIV into that mode, 6309 then load RELOADREG from OLDEQUIV. Note that we cannot use 6310 gen_lowpart_common since it can do the wrong thing when 6311 RELOADREG has a multi-word mode. Note that RELOADREG 6312 must always be a REG here. */ 6313 6314 if (GET_MODE (reloadreg) != mode) 6315 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); 6316 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) 6317 oldequiv = SUBREG_REG (oldequiv); 6318 if (GET_MODE (oldequiv) != VOIDmode 6319 && mode != GET_MODE (oldequiv)) 6320 oldequiv = gen_lowpart_SUBREG (mode, oldequiv); 6321 6322 /* Switch to the right place to emit the reload insns. */ 6323 switch (rl->when_needed) 6324 { 6325 case RELOAD_OTHER: 6326 where = &other_input_reload_insns; 6327 break; 6328 case RELOAD_FOR_INPUT: 6329 where = &input_reload_insns[rl->opnum]; 6330 break; 6331 case RELOAD_FOR_INPUT_ADDRESS: 6332 where = &input_address_reload_insns[rl->opnum]; 6333 break; 6334 case RELOAD_FOR_INPADDR_ADDRESS: 6335 where = &inpaddr_address_reload_insns[rl->opnum]; 6336 break; 6337 case RELOAD_FOR_OUTPUT_ADDRESS: 6338 where = &output_address_reload_insns[rl->opnum]; 6339 break; 6340 case RELOAD_FOR_OUTADDR_ADDRESS: 6341 where = &outaddr_address_reload_insns[rl->opnum]; 6342 break; 6343 case RELOAD_FOR_OPERAND_ADDRESS: 6344 where = &operand_reload_insns; 6345 break; 6346 case RELOAD_FOR_OPADDR_ADDR: 6347 where = &other_operand_reload_insns; 6348 break; 6349 case RELOAD_FOR_OTHER_ADDRESS: 6350 where = &other_input_address_reload_insns; 6351 break; 6352 default: 6353 abort (); 6354 } 6355 6356 push_to_sequence (*where); 6357 6358 /* Auto-increment addresses must be reloaded in a special way. */ 6359 if (rl->out && ! rl->out_reg) 6360 { 6361 /* We are not going to bother supporting the case where a 6362 incremented register can't be copied directly from 6363 OLDEQUIV since this seems highly unlikely. */ 6364 if (rl->secondary_in_reload >= 0) 6365 abort (); 6366 6367 if (reload_inherited[j]) 6368 oldequiv = reloadreg; 6369 6370 old = XEXP (rl->in_reg, 0); 6371 6372 if (optimize && GET_CODE (oldequiv) == REG 6373 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER 6374 && spill_reg_store[REGNO (oldequiv)] 6375 && GET_CODE (old) == REG 6376 && (dead_or_set_p (insn, 6377 spill_reg_stored_to[REGNO (oldequiv)]) 6378 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], 6379 old))) 6380 delete_output_reload (insn, j, REGNO (oldequiv)); 6381 6382 /* Prevent normal processing of this reload. */ 6383 special = 1; 6384 /* Output a special code sequence for this case. */ 6385 new_spill_reg_store[REGNO (reloadreg)] 6386 = inc_for_reload (reloadreg, oldequiv, rl->out, 6387 rl->inc); 6388 } 6389 6390 /* If we are reloading a pseudo-register that was set by the previous 6391 insn, see if we can get rid of that pseudo-register entirely 6392 by redirecting the previous insn into our reload register. */ 6393 6394 else if (optimize && GET_CODE (old) == REG 6395 && REGNO (old) >= FIRST_PSEUDO_REGISTER 6396 && dead_or_set_p (insn, old) 6397 /* This is unsafe if some other reload 6398 uses the same reg first. */ 6399 && ! conflicts_with_override (reloadreg) 6400 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, 6401 rl->when_needed, old, rl->out, j, 0)) 6402 { 6403 rtx temp = PREV_INSN (insn); 6404 while (temp && GET_CODE (temp) == NOTE) 6405 temp = PREV_INSN (temp); 6406 if (temp 6407 && GET_CODE (temp) == INSN 6408 && GET_CODE (PATTERN (temp)) == SET 6409 && SET_DEST (PATTERN (temp)) == old 6410 /* Make sure we can access insn_operand_constraint. */ 6411 && asm_noperands (PATTERN (temp)) < 0 6412 /* This is unsafe if operand occurs more than once in current 6413 insn. Perhaps some occurrences aren't reloaded. */ 6414 && count_occurrences (PATTERN (insn), old, 0) == 1) 6415 { 6416 rtx old = SET_DEST (PATTERN (temp)); 6417 /* Store into the reload register instead of the pseudo. */ 6418 SET_DEST (PATTERN (temp)) = reloadreg; 6419 6420 /* Verify that resulting insn is valid. */ 6421 extract_insn (temp); 6422 if (constrain_operands (1)) 6423 { 6424 /* If the previous insn is an output reload, the source is 6425 a reload register, and its spill_reg_store entry will 6426 contain the previous destination. This is now 6427 invalid. */ 6428 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG 6429 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) 6430 { 6431 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; 6432 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; 6433 } 6434 6435 /* If these are the only uses of the pseudo reg, 6436 pretend for GDB it lives in the reload reg we used. */ 6437 if (REG_N_DEATHS (REGNO (old)) == 1 6438 && REG_N_SETS (REGNO (old)) == 1) 6439 { 6440 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx); 6441 alter_reg (REGNO (old), -1); 6442 } 6443 special = 1; 6444 } 6445 else 6446 { 6447 SET_DEST (PATTERN (temp)) = old; 6448 } 6449 } 6450 } 6451 6452 /* We can't do that, so output an insn to load RELOADREG. */ 6453 6454#ifdef SECONDARY_INPUT_RELOAD_CLASS 6455 /* If we have a secondary reload, pick up the secondary register 6456 and icode, if any. If OLDEQUIV and OLD are different or 6457 if this is an in-out reload, recompute whether or not we 6458 still need a secondary register and what the icode should 6459 be. If we still need a secondary register and the class or 6460 icode is different, go back to reloading from OLD if using 6461 OLDEQUIV means that we got the wrong type of register. We 6462 cannot have different class or icode due to an in-out reload 6463 because we don't make such reloads when both the input and 6464 output need secondary reload registers. */ 6465 6466 if (! special && rl->secondary_in_reload >= 0) 6467 { 6468 rtx second_reload_reg = 0; 6469 int secondary_reload = rl->secondary_in_reload; 6470 rtx real_oldequiv = oldequiv; 6471 rtx real_old = old; 6472 rtx tmp; 6473 enum insn_code icode; 6474 6475 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM 6476 and similarly for OLD. 6477 See comments in get_secondary_reload in reload.c. */ 6478 /* If it is a pseudo that cannot be replaced with its 6479 equivalent MEM, we must fall back to reload_in, which 6480 will have all the necessary substitutions registered. 6481 Likewise for a pseudo that can't be replaced with its 6482 equivalent constant. 6483 6484 Take extra care for subregs of such pseudos. Note that 6485 we cannot use reg_equiv_mem in this case because it is 6486 not in the right mode. */ 6487 6488 tmp = oldequiv; 6489 if (GET_CODE (tmp) == SUBREG) 6490 tmp = SUBREG_REG (tmp); 6491 if (GET_CODE (tmp) == REG 6492 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER 6493 && (reg_equiv_memory_loc[REGNO (tmp)] != 0 6494 || reg_equiv_constant[REGNO (tmp)] != 0)) 6495 { 6496 if (! reg_equiv_mem[REGNO (tmp)] 6497 || num_not_at_initial_offset 6498 || GET_CODE (oldequiv) == SUBREG) 6499 real_oldequiv = rl->in; 6500 else 6501 real_oldequiv = reg_equiv_mem[REGNO (tmp)]; 6502 } 6503 6504 tmp = old; 6505 if (GET_CODE (tmp) == SUBREG) 6506 tmp = SUBREG_REG (tmp); 6507 if (GET_CODE (tmp) == REG 6508 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER 6509 && (reg_equiv_memory_loc[REGNO (tmp)] != 0 6510 || reg_equiv_constant[REGNO (tmp)] != 0)) 6511 { 6512 if (! reg_equiv_mem[REGNO (tmp)] 6513 || num_not_at_initial_offset 6514 || GET_CODE (old) == SUBREG) 6515 real_old = rl->in; 6516 else 6517 real_old = reg_equiv_mem[REGNO (tmp)]; 6518 } 6519 6520 second_reload_reg = rld[secondary_reload].reg_rtx; 6521 icode = rl->secondary_in_icode; 6522 6523 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) 6524 || (rl->in != 0 && rl->out != 0)) 6525 { 6526 enum reg_class new_class 6527 = SECONDARY_INPUT_RELOAD_CLASS (rl->class, 6528 mode, real_oldequiv); 6529 6530 if (new_class == NO_REGS) 6531 second_reload_reg = 0; 6532 else 6533 { 6534 enum insn_code new_icode; 6535 enum machine_mode new_mode; 6536 6537 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], 6538 REGNO (second_reload_reg))) 6539 oldequiv = old, real_oldequiv = real_old; 6540 else 6541 { 6542 new_icode = reload_in_optab[(int) mode]; 6543 if (new_icode != CODE_FOR_nothing 6544 && ((insn_data[(int) new_icode].operand[0].predicate 6545 && ! ((*insn_data[(int) new_icode].operand[0].predicate) 6546 (reloadreg, mode))) 6547 || (insn_data[(int) new_icode].operand[1].predicate 6548 && ! ((*insn_data[(int) new_icode].operand[1].predicate) 6549 (real_oldequiv, mode))))) 6550 new_icode = CODE_FOR_nothing; 6551 6552 if (new_icode == CODE_FOR_nothing) 6553 new_mode = mode; 6554 else 6555 new_mode = insn_data[(int) new_icode].operand[2].mode; 6556 6557 if (GET_MODE (second_reload_reg) != new_mode) 6558 { 6559 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg), 6560 new_mode)) 6561 oldequiv = old, real_oldequiv = real_old; 6562 else 6563 second_reload_reg 6564 = gen_rtx_REG (new_mode, 6565 REGNO (second_reload_reg)); 6566 } 6567 } 6568 } 6569 } 6570 6571 /* If we still need a secondary reload register, check 6572 to see if it is being used as a scratch or intermediate 6573 register and generate code appropriately. If we need 6574 a scratch register, use REAL_OLDEQUIV since the form of 6575 the insn may depend on the actual address if it is 6576 a MEM. */ 6577 6578 if (second_reload_reg) 6579 { 6580 if (icode != CODE_FOR_nothing) 6581 { 6582 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, 6583 second_reload_reg)); 6584 special = 1; 6585 } 6586 else 6587 { 6588 /* See if we need a scratch register to load the 6589 intermediate register (a tertiary reload). */ 6590 enum insn_code tertiary_icode 6591 = rld[secondary_reload].secondary_in_icode; 6592 6593 if (tertiary_icode != CODE_FOR_nothing) 6594 { 6595 rtx third_reload_reg 6596 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx; 6597 6598 emit_insn ((GEN_FCN (tertiary_icode) 6599 (second_reload_reg, real_oldequiv, 6600 third_reload_reg))); 6601 } 6602 else 6603 gen_reload (second_reload_reg, real_oldequiv, 6604 rl->opnum, 6605 rl->when_needed); 6606 6607 oldequiv = second_reload_reg; 6608 } 6609 } 6610 } 6611#endif 6612 6613 if (! special && ! rtx_equal_p (reloadreg, oldequiv)) 6614 { 6615 rtx real_oldequiv = oldequiv; 6616 6617 if ((GET_CODE (oldequiv) == REG 6618 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER 6619 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0 6620 || reg_equiv_constant[REGNO (oldequiv)] != 0)) 6621 || (GET_CODE (oldequiv) == SUBREG 6622 && GET_CODE (SUBREG_REG (oldequiv)) == REG 6623 && (REGNO (SUBREG_REG (oldequiv)) 6624 >= FIRST_PSEUDO_REGISTER) 6625 && ((reg_equiv_memory_loc 6626 [REGNO (SUBREG_REG (oldequiv))] != 0) 6627 || (reg_equiv_constant 6628 [REGNO (SUBREG_REG (oldequiv))] != 0))) 6629 || (CONSTANT_P (oldequiv) 6630 && (PREFERRED_RELOAD_CLASS (oldequiv, 6631 REGNO_REG_CLASS (REGNO (reloadreg))) 6632 == NO_REGS))) 6633 real_oldequiv = rl->in; 6634 gen_reload (reloadreg, real_oldequiv, rl->opnum, 6635 rl->when_needed); 6636 } 6637 6638 if (flag_non_call_exceptions) 6639 copy_eh_notes (insn, get_insns ()); 6640 6641 /* End this sequence. */ 6642 *where = get_insns (); 6643 end_sequence (); 6644 6645 /* Update reload_override_in so that delete_address_reloads_1 6646 can see the actual register usage. */ 6647 if (oldequiv_reg) 6648 reload_override_in[j] = oldequiv; 6649} 6650 6651/* Generate insns to for the output reload RL, which is for the insn described 6652 by CHAIN and has the number J. */ 6653static void 6654emit_output_reload_insns (chain, rl, j) 6655 struct insn_chain *chain; 6656 struct reload *rl; 6657 int j; 6658{ 6659 rtx reloadreg = rl->reg_rtx; 6660 rtx insn = chain->insn; 6661 int special = 0; 6662 rtx old = rl->out; 6663 enum machine_mode mode = GET_MODE (old); 6664 rtx p; 6665 6666 if (rl->when_needed == RELOAD_OTHER) 6667 start_sequence (); 6668 else 6669 push_to_sequence (output_reload_insns[rl->opnum]); 6670 6671 /* Determine the mode to reload in. 6672 See comments above (for input reloading). */ 6673 6674 if (mode == VOIDmode) 6675 { 6676 /* VOIDmode should never happen for an output. */ 6677 if (asm_noperands (PATTERN (insn)) < 0) 6678 /* It's the compiler's fault. */ 6679 fatal_insn ("VOIDmode on an output", insn); 6680 error_for_asm (insn, "output operand is constant in `asm'"); 6681 /* Prevent crash--use something we know is valid. */ 6682 mode = word_mode; 6683 old = gen_rtx_REG (mode, REGNO (reloadreg)); 6684 } 6685 6686 if (GET_MODE (reloadreg) != mode) 6687 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); 6688 6689#ifdef SECONDARY_OUTPUT_RELOAD_CLASS 6690 6691 /* If we need two reload regs, set RELOADREG to the intermediate 6692 one, since it will be stored into OLD. We might need a secondary 6693 register only for an input reload, so check again here. */ 6694 6695 if (rl->secondary_out_reload >= 0) 6696 { 6697 rtx real_old = old; 6698 6699 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER 6700 && reg_equiv_mem[REGNO (old)] != 0) 6701 real_old = reg_equiv_mem[REGNO (old)]; 6702 6703 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class, 6704 mode, real_old) 6705 != NO_REGS)) 6706 { 6707 rtx second_reloadreg = reloadreg; 6708 reloadreg = rld[rl->secondary_out_reload].reg_rtx; 6709 6710 /* See if RELOADREG is to be used as a scratch register 6711 or as an intermediate register. */ 6712 if (rl->secondary_out_icode != CODE_FOR_nothing) 6713 { 6714 emit_insn ((GEN_FCN (rl->secondary_out_icode) 6715 (real_old, second_reloadreg, reloadreg))); 6716 special = 1; 6717 } 6718 else 6719 { 6720 /* See if we need both a scratch and intermediate reload 6721 register. */ 6722 6723 int secondary_reload = rl->secondary_out_reload; 6724 enum insn_code tertiary_icode 6725 = rld[secondary_reload].secondary_out_icode; 6726 6727 if (GET_MODE (reloadreg) != mode) 6728 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg)); 6729 6730 if (tertiary_icode != CODE_FOR_nothing) 6731 { 6732 rtx third_reloadreg 6733 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx; 6734 rtx tem; 6735 6736 /* Copy primary reload reg to secondary reload reg. 6737 (Note that these have been swapped above, then 6738 secondary reload reg to OLD using our insn.) */ 6739 6740 /* If REAL_OLD is a paradoxical SUBREG, remove it 6741 and try to put the opposite SUBREG on 6742 RELOADREG. */ 6743 if (GET_CODE (real_old) == SUBREG 6744 && (GET_MODE_SIZE (GET_MODE (real_old)) 6745 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old)))) 6746 && 0 != (tem = gen_lowpart_common 6747 (GET_MODE (SUBREG_REG (real_old)), 6748 reloadreg))) 6749 real_old = SUBREG_REG (real_old), reloadreg = tem; 6750 6751 gen_reload (reloadreg, second_reloadreg, 6752 rl->opnum, rl->when_needed); 6753 emit_insn ((GEN_FCN (tertiary_icode) 6754 (real_old, reloadreg, third_reloadreg))); 6755 special = 1; 6756 } 6757 6758 else 6759 /* Copy between the reload regs here and then to 6760 OUT later. */ 6761 6762 gen_reload (reloadreg, second_reloadreg, 6763 rl->opnum, rl->when_needed); 6764 } 6765 } 6766 } 6767#endif 6768 6769 /* Output the last reload insn. */ 6770 if (! special) 6771 { 6772 rtx set; 6773 6774 /* Don't output the last reload if OLD is not the dest of 6775 INSN and is in the src and is clobbered by INSN. */ 6776 if (! flag_expensive_optimizations 6777 || GET_CODE (old) != REG 6778 || !(set = single_set (insn)) 6779 || rtx_equal_p (old, SET_DEST (set)) 6780 || !reg_mentioned_p (old, SET_SRC (set)) 6781 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0)) 6782 gen_reload (old, reloadreg, rl->opnum, 6783 rl->when_needed); 6784 } 6785 6786 /* Look at all insns we emitted, just to be safe. */ 6787 for (p = get_insns (); p; p = NEXT_INSN (p)) 6788 if (INSN_P (p)) 6789 { 6790 rtx pat = PATTERN (p); 6791 6792 /* If this output reload doesn't come from a spill reg, 6793 clear any memory of reloaded copies of the pseudo reg. 6794 If this output reload comes from a spill reg, 6795 reg_has_output_reload will make this do nothing. */ 6796 note_stores (pat, forget_old_reloads_1, NULL); 6797 6798 if (reg_mentioned_p (rl->reg_rtx, pat)) 6799 { 6800 rtx set = single_set (insn); 6801 if (reload_spill_index[j] < 0 6802 && set 6803 && SET_SRC (set) == rl->reg_rtx) 6804 { 6805 int src = REGNO (SET_SRC (set)); 6806 6807 reload_spill_index[j] = src; 6808 SET_HARD_REG_BIT (reg_is_output_reload, src); 6809 if (find_regno_note (insn, REG_DEAD, src)) 6810 SET_HARD_REG_BIT (reg_reloaded_died, src); 6811 } 6812 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER) 6813 { 6814 int s = rl->secondary_out_reload; 6815 set = single_set (p); 6816 /* If this reload copies only to the secondary reload 6817 register, the secondary reload does the actual 6818 store. */ 6819 if (s >= 0 && set == NULL_RTX) 6820 /* We can't tell what function the secondary reload 6821 has and where the actual store to the pseudo is 6822 made; leave new_spill_reg_store alone. */ 6823 ; 6824 else if (s >= 0 6825 && SET_SRC (set) == rl->reg_rtx 6826 && SET_DEST (set) == rld[s].reg_rtx) 6827 { 6828 /* Usually the next instruction will be the 6829 secondary reload insn; if we can confirm 6830 that it is, setting new_spill_reg_store to 6831 that insn will allow an extra optimization. */ 6832 rtx s_reg = rld[s].reg_rtx; 6833 rtx next = NEXT_INSN (p); 6834 rld[s].out = rl->out; 6835 rld[s].out_reg = rl->out_reg; 6836 set = single_set (next); 6837 if (set && SET_SRC (set) == s_reg 6838 && ! new_spill_reg_store[REGNO (s_reg)]) 6839 { 6840 SET_HARD_REG_BIT (reg_is_output_reload, 6841 REGNO (s_reg)); 6842 new_spill_reg_store[REGNO (s_reg)] = next; 6843 } 6844 } 6845 else 6846 new_spill_reg_store[REGNO (rl->reg_rtx)] = p; 6847 } 6848 } 6849 } 6850 6851 if (rl->when_needed == RELOAD_OTHER) 6852 { 6853 emit_insn (other_output_reload_insns[rl->opnum]); 6854 other_output_reload_insns[rl->opnum] = get_insns (); 6855 } 6856 else 6857 output_reload_insns[rl->opnum] = get_insns (); 6858 6859 if (flag_non_call_exceptions) 6860 copy_eh_notes (insn, get_insns ()); 6861 6862 end_sequence (); 6863} 6864 6865/* Do input reloading for reload RL, which is for the insn described by CHAIN 6866 and has the number J. */ 6867static void 6868do_input_reload (chain, rl, j) 6869 struct insn_chain *chain; 6870 struct reload *rl; 6871 int j; 6872{ 6873 int expect_occurrences = 1; 6874 rtx insn = chain->insn; 6875 rtx old = (rl->in && GET_CODE (rl->in) == MEM 6876 ? rl->in_reg : rl->in); 6877 6878 if (old != 0 6879 /* AUTO_INC reloads need to be handled even if inherited. We got an 6880 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ 6881 && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) 6882 && ! rtx_equal_p (rl->reg_rtx, old) 6883 && rl->reg_rtx != 0) 6884 emit_input_reload_insns (chain, rld + j, old, j); 6885 6886 /* When inheriting a wider reload, we have a MEM in rl->in, 6887 e.g. inheriting a SImode output reload for 6888 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ 6889 if (optimize && reload_inherited[j] && rl->in 6890 && GET_CODE (rl->in) == MEM 6891 && GET_CODE (rl->in_reg) == MEM 6892 && reload_spill_index[j] >= 0 6893 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) 6894 { 6895 expect_occurrences 6896 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1; 6897 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; 6898 } 6899 6900 /* If we are reloading a register that was recently stored in with an 6901 output-reload, see if we can prove there was 6902 actually no need to store the old value in it. */ 6903 6904 if (optimize 6905 && (reload_inherited[j] || reload_override_in[j]) 6906 && rl->reg_rtx 6907 && GET_CODE (rl->reg_rtx) == REG 6908 && spill_reg_store[REGNO (rl->reg_rtx)] != 0 6909#if 0 6910 /* There doesn't seem to be any reason to restrict this to pseudos 6911 and doing so loses in the case where we are copying from a 6912 register of the wrong class. */ 6913 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)]) 6914 >= FIRST_PSEUDO_REGISTER) 6915#endif 6916 /* The insn might have already some references to stackslots 6917 replaced by MEMs, while reload_out_reg still names the 6918 original pseudo. */ 6919 && (dead_or_set_p (insn, 6920 spill_reg_stored_to[REGNO (rl->reg_rtx)]) 6921 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)], 6922 rl->out_reg))) 6923 delete_output_reload (insn, j, REGNO (rl->reg_rtx)); 6924} 6925 6926/* Do output reloading for reload RL, which is for the insn described by 6927 CHAIN and has the number J. 6928 ??? At some point we need to support handling output reloads of 6929 JUMP_INSNs or insns that set cc0. */ 6930static void 6931do_output_reload (chain, rl, j) 6932 struct insn_chain *chain; 6933 struct reload *rl; 6934 int j; 6935{ 6936 rtx note, old; 6937 rtx insn = chain->insn; 6938 /* If this is an output reload that stores something that is 6939 not loaded in this same reload, see if we can eliminate a previous 6940 store. */ 6941 rtx pseudo = rl->out_reg; 6942 6943 if (pseudo 6944 && optimize 6945 && GET_CODE (pseudo) == REG 6946 && ! rtx_equal_p (rl->in_reg, pseudo) 6947 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER 6948 && reg_last_reload_reg[REGNO (pseudo)]) 6949 { 6950 int pseudo_no = REGNO (pseudo); 6951 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); 6952 6953 /* We don't need to test full validity of last_regno for 6954 inherit here; we only want to know if the store actually 6955 matches the pseudo. */ 6956 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) 6957 && reg_reloaded_contents[last_regno] == pseudo_no 6958 && spill_reg_store[last_regno] 6959 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) 6960 delete_output_reload (insn, j, last_regno); 6961 } 6962 6963 old = rl->out_reg; 6964 if (old == 0 6965 || rl->reg_rtx == old 6966 || rl->reg_rtx == 0) 6967 return; 6968 6969 /* An output operand that dies right away does need a reload, 6970 but need not be copied from it. Show the new location in the 6971 REG_UNUSED note. */ 6972 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH) 6973 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) 6974 { 6975 XEXP (note, 0) = rl->reg_rtx; 6976 return; 6977 } 6978 /* Likewise for a SUBREG of an operand that dies. */ 6979 else if (GET_CODE (old) == SUBREG 6980 && GET_CODE (SUBREG_REG (old)) == REG 6981 && 0 != (note = find_reg_note (insn, REG_UNUSED, 6982 SUBREG_REG (old)))) 6983 { 6984 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), 6985 rl->reg_rtx); 6986 return; 6987 } 6988 else if (GET_CODE (old) == SCRATCH) 6989 /* If we aren't optimizing, there won't be a REG_UNUSED note, 6990 but we don't want to make an output reload. */ 6991 return; 6992 6993 /* If is a JUMP_INSN, we can't support output reloads yet. */ 6994 if (GET_CODE (insn) == JUMP_INSN) 6995 abort (); 6996 6997 emit_output_reload_insns (chain, rld + j, j); 6998} 6999 7000/* Output insns to reload values in and out of the chosen reload regs. */ 7001 7002static void 7003emit_reload_insns (chain) 7004 struct insn_chain *chain; 7005{ 7006 rtx insn = chain->insn; 7007 7008 int j; 7009 7010 CLEAR_HARD_REG_SET (reg_reloaded_died); 7011 7012 for (j = 0; j < reload_n_operands; j++) 7013 input_reload_insns[j] = input_address_reload_insns[j] 7014 = inpaddr_address_reload_insns[j] 7015 = output_reload_insns[j] = output_address_reload_insns[j] 7016 = outaddr_address_reload_insns[j] 7017 = other_output_reload_insns[j] = 0; 7018 other_input_address_reload_insns = 0; 7019 other_input_reload_insns = 0; 7020 operand_reload_insns = 0; 7021 other_operand_reload_insns = 0; 7022 7023 /* Dump reloads into the dump file. */ 7024 if (rtl_dump_file) 7025 { 7026 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); 7027 debug_reload_to_stream (rtl_dump_file); 7028 } 7029 7030 /* Now output the instructions to copy the data into and out of the 7031 reload registers. Do these in the order that the reloads were reported, 7032 since reloads of base and index registers precede reloads of operands 7033 and the operands may need the base and index registers reloaded. */ 7034 7035 for (j = 0; j < n_reloads; j++) 7036 { 7037 if (rld[j].reg_rtx 7038 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER) 7039 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0; 7040 7041 do_input_reload (chain, rld + j, j); 7042 do_output_reload (chain, rld + j, j); 7043 } 7044 7045 /* Now write all the insns we made for reloads in the order expected by 7046 the allocation functions. Prior to the insn being reloaded, we write 7047 the following reloads: 7048 7049 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. 7050 7051 RELOAD_OTHER reloads. 7052 7053 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed 7054 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the 7055 RELOAD_FOR_INPUT reload for the operand. 7056 7057 RELOAD_FOR_OPADDR_ADDRS reloads. 7058 7059 RELOAD_FOR_OPERAND_ADDRESS reloads. 7060 7061 After the insn being reloaded, we write the following: 7062 7063 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed 7064 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the 7065 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output 7066 reloads for the operand. The RELOAD_OTHER output reloads are 7067 output in descending order by reload number. */ 7068 7069 emit_insn_before (other_input_address_reload_insns, insn); 7070 emit_insn_before (other_input_reload_insns, insn); 7071 7072 for (j = 0; j < reload_n_operands; j++) 7073 { 7074 emit_insn_before (inpaddr_address_reload_insns[j], insn); 7075 emit_insn_before (input_address_reload_insns[j], insn); 7076 emit_insn_before (input_reload_insns[j], insn); 7077 } 7078 7079 emit_insn_before (other_operand_reload_insns, insn); 7080 emit_insn_before (operand_reload_insns, insn); 7081 7082 for (j = 0; j < reload_n_operands; j++) 7083 { 7084 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn); 7085 x = emit_insn_after (output_address_reload_insns[j], x); 7086 x = emit_insn_after (output_reload_insns[j], x); 7087 emit_insn_after (other_output_reload_insns[j], x); 7088 } 7089 7090 /* For all the spill regs newly reloaded in this instruction, 7091 record what they were reloaded from, so subsequent instructions 7092 can inherit the reloads. 7093 7094 Update spill_reg_store for the reloads of this insn. 7095 Copy the elements that were updated in the loop above. */ 7096 7097 for (j = 0; j < n_reloads; j++) 7098 { 7099 int r = reload_order[j]; 7100 int i = reload_spill_index[r]; 7101 7102 /* If this is a non-inherited input reload from a pseudo, we must 7103 clear any memory of a previous store to the same pseudo. Only do 7104 something if there will not be an output reload for the pseudo 7105 being reloaded. */ 7106 if (rld[r].in_reg != 0 7107 && ! (reload_inherited[r] || reload_override_in[r])) 7108 { 7109 rtx reg = rld[r].in_reg; 7110 7111 if (GET_CODE (reg) == SUBREG) 7112 reg = SUBREG_REG (reg); 7113 7114 if (GET_CODE (reg) == REG 7115 && REGNO (reg) >= FIRST_PSEUDO_REGISTER 7116 && ! reg_has_output_reload[REGNO (reg)]) 7117 { 7118 int nregno = REGNO (reg); 7119 7120 if (reg_last_reload_reg[nregno]) 7121 { 7122 int last_regno = REGNO (reg_last_reload_reg[nregno]); 7123 7124 if (reg_reloaded_contents[last_regno] == nregno) 7125 spill_reg_store[last_regno] = 0; 7126 } 7127 } 7128 } 7129 7130 /* I is nonneg if this reload used a register. 7131 If rld[r].reg_rtx is 0, this is an optional reload 7132 that we opted to ignore. */ 7133 7134 if (i >= 0 && rld[r].reg_rtx != 0) 7135 { 7136 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx)); 7137 int k; 7138 int part_reaches_end = 0; 7139 int all_reaches_end = 1; 7140 7141 /* For a multi register reload, we need to check if all or part 7142 of the value lives to the end. */ 7143 for (k = 0; k < nr; k++) 7144 { 7145 if (reload_reg_reaches_end_p (i + k, rld[r].opnum, 7146 rld[r].when_needed)) 7147 part_reaches_end = 1; 7148 else 7149 all_reaches_end = 0; 7150 } 7151 7152 /* Ignore reloads that don't reach the end of the insn in 7153 entirety. */ 7154 if (all_reaches_end) 7155 { 7156 /* First, clear out memory of what used to be in this spill reg. 7157 If consecutive registers are used, clear them all. */ 7158 7159 for (k = 0; k < nr; k++) 7160 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); 7161 7162 /* Maybe the spill reg contains a copy of reload_out. */ 7163 if (rld[r].out != 0 7164 && (GET_CODE (rld[r].out) == REG 7165#ifdef AUTO_INC_DEC 7166 || ! rld[r].out_reg 7167#endif 7168 || GET_CODE (rld[r].out_reg) == REG)) 7169 { 7170 rtx out = (GET_CODE (rld[r].out) == REG 7171 ? rld[r].out 7172 : rld[r].out_reg 7173 ? rld[r].out_reg 7174/* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); 7175 int nregno = REGNO (out); 7176 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 7177 : HARD_REGNO_NREGS (nregno, 7178 GET_MODE (rld[r].reg_rtx))); 7179 7180 spill_reg_store[i] = new_spill_reg_store[i]; 7181 spill_reg_stored_to[i] = out; 7182 reg_last_reload_reg[nregno] = rld[r].reg_rtx; 7183 7184 /* If NREGNO is a hard register, it may occupy more than 7185 one register. If it does, say what is in the 7186 rest of the registers assuming that both registers 7187 agree on how many words the object takes. If not, 7188 invalidate the subsequent registers. */ 7189 7190 if (nregno < FIRST_PSEUDO_REGISTER) 7191 for (k = 1; k < nnr; k++) 7192 reg_last_reload_reg[nregno + k] 7193 = (nr == nnr 7194 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] 7195 : 0); 7196 7197 /* Now do the inverse operation. */ 7198 for (k = 0; k < nr; k++) 7199 { 7200 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); 7201 reg_reloaded_contents[i + k] 7202 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr 7203 ? nregno 7204 : nregno + k); 7205 reg_reloaded_insn[i + k] = insn; 7206 SET_HARD_REG_BIT (reg_reloaded_valid, i + k); 7207 } 7208 } 7209 7210 /* Maybe the spill reg contains a copy of reload_in. Only do 7211 something if there will not be an output reload for 7212 the register being reloaded. */ 7213 else if (rld[r].out_reg == 0 7214 && rld[r].in != 0 7215 && ((GET_CODE (rld[r].in) == REG 7216 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER 7217 && ! reg_has_output_reload[REGNO (rld[r].in)]) 7218 || (GET_CODE (rld[r].in_reg) == REG 7219 && ! reg_has_output_reload[REGNO (rld[r].in_reg)])) 7220 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn))) 7221 { 7222 int nregno; 7223 int nnr; 7224 7225 if (GET_CODE (rld[r].in) == REG 7226 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) 7227 nregno = REGNO (rld[r].in); 7228 else if (GET_CODE (rld[r].in_reg) == REG) 7229 nregno = REGNO (rld[r].in_reg); 7230 else 7231 nregno = REGNO (XEXP (rld[r].in_reg, 0)); 7232 7233 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1 7234 : HARD_REGNO_NREGS (nregno, 7235 GET_MODE (rld[r].reg_rtx))); 7236 7237 reg_last_reload_reg[nregno] = rld[r].reg_rtx; 7238 7239 if (nregno < FIRST_PSEUDO_REGISTER) 7240 for (k = 1; k < nnr; k++) 7241 reg_last_reload_reg[nregno + k] 7242 = (nr == nnr 7243 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k] 7244 : 0); 7245 7246 /* Unless we inherited this reload, show we haven't 7247 recently done a store. 7248 Previous stores of inherited auto_inc expressions 7249 also have to be discarded. */ 7250 if (! reload_inherited[r] 7251 || (rld[r].out && ! rld[r].out_reg)) 7252 spill_reg_store[i] = 0; 7253 7254 for (k = 0; k < nr; k++) 7255 { 7256 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k); 7257 reg_reloaded_contents[i + k] 7258 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr 7259 ? nregno 7260 : nregno + k); 7261 reg_reloaded_insn[i + k] = insn; 7262 SET_HARD_REG_BIT (reg_reloaded_valid, i + k); 7263 } 7264 } 7265 } 7266 7267 /* However, if part of the reload reaches the end, then we must 7268 invalidate the old info for the part that survives to the end. */ 7269 else if (part_reaches_end) 7270 { 7271 for (k = 0; k < nr; k++) 7272 if (reload_reg_reaches_end_p (i + k, 7273 rld[r].opnum, 7274 rld[r].when_needed)) 7275 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); 7276 } 7277 } 7278 7279 /* The following if-statement was #if 0'd in 1.34 (or before...). 7280 It's reenabled in 1.35 because supposedly nothing else 7281 deals with this problem. */ 7282 7283 /* If a register gets output-reloaded from a non-spill register, 7284 that invalidates any previous reloaded copy of it. 7285 But forget_old_reloads_1 won't get to see it, because 7286 it thinks only about the original insn. So invalidate it here. */ 7287 if (i < 0 && rld[r].out != 0 7288 && (GET_CODE (rld[r].out) == REG 7289 || (GET_CODE (rld[r].out) == MEM 7290 && GET_CODE (rld[r].out_reg) == REG))) 7291 { 7292 rtx out = (GET_CODE (rld[r].out) == REG 7293 ? rld[r].out : rld[r].out_reg); 7294 int nregno = REGNO (out); 7295 if (nregno >= FIRST_PSEUDO_REGISTER) 7296 { 7297 rtx src_reg, store_insn = NULL_RTX; 7298 7299 reg_last_reload_reg[nregno] = 0; 7300 7301 /* If we can find a hard register that is stored, record 7302 the storing insn so that we may delete this insn with 7303 delete_output_reload. */ 7304 src_reg = rld[r].reg_rtx; 7305 7306 /* If this is an optional reload, try to find the source reg 7307 from an input reload. */ 7308 if (! src_reg) 7309 { 7310 rtx set = single_set (insn); 7311 if (set && SET_DEST (set) == rld[r].out) 7312 { 7313 int k; 7314 7315 src_reg = SET_SRC (set); 7316 store_insn = insn; 7317 for (k = 0; k < n_reloads; k++) 7318 { 7319 if (rld[k].in == src_reg) 7320 { 7321 src_reg = rld[k].reg_rtx; 7322 break; 7323 } 7324 } 7325 } 7326 } 7327 else 7328 store_insn = new_spill_reg_store[REGNO (src_reg)]; 7329 if (src_reg && GET_CODE (src_reg) == REG 7330 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) 7331 { 7332 int src_regno = REGNO (src_reg); 7333 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode); 7334 /* The place where to find a death note varies with 7335 PRESERVE_DEATH_INFO_REGNO_P . The condition is not 7336 necessarily checked exactly in the code that moves 7337 notes, so just check both locations. */ 7338 rtx note = find_regno_note (insn, REG_DEAD, src_regno); 7339 if (! note && store_insn) 7340 note = find_regno_note (store_insn, REG_DEAD, src_regno); 7341 while (nr-- > 0) 7342 { 7343 spill_reg_store[src_regno + nr] = store_insn; 7344 spill_reg_stored_to[src_regno + nr] = out; 7345 reg_reloaded_contents[src_regno + nr] = nregno; 7346 reg_reloaded_insn[src_regno + nr] = store_insn; 7347 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr); 7348 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr); 7349 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr); 7350 if (note) 7351 SET_HARD_REG_BIT (reg_reloaded_died, src_regno); 7352 else 7353 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); 7354 } 7355 reg_last_reload_reg[nregno] = src_reg; 7356 } 7357 } 7358 else 7359 { 7360 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out)); 7361 7362 while (num_regs-- > 0) 7363 reg_last_reload_reg[nregno + num_regs] = 0; 7364 } 7365 } 7366 } 7367 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died); 7368} 7369 7370/* Emit code to perform a reload from IN (which may be a reload register) to 7371 OUT (which may also be a reload register). IN or OUT is from operand 7372 OPNUM with reload type TYPE. 7373 7374 Returns first insn emitted. */ 7375 7376rtx 7377gen_reload (out, in, opnum, type) 7378 rtx out; 7379 rtx in; 7380 int opnum; 7381 enum reload_type type; 7382{ 7383 rtx last = get_last_insn (); 7384 rtx tem; 7385 7386 /* If IN is a paradoxical SUBREG, remove it and try to put the 7387 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ 7388 if (GET_CODE (in) == SUBREG 7389 && (GET_MODE_SIZE (GET_MODE (in)) 7390 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in)))) 7391 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0) 7392 in = SUBREG_REG (in), out = tem; 7393 else if (GET_CODE (out) == SUBREG 7394 && (GET_MODE_SIZE (GET_MODE (out)) 7395 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out)))) 7396 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0) 7397 out = SUBREG_REG (out), in = tem; 7398 7399 /* How to do this reload can get quite tricky. Normally, we are being 7400 asked to reload a simple operand, such as a MEM, a constant, or a pseudo 7401 register that didn't get a hard register. In that case we can just 7402 call emit_move_insn. 7403 7404 We can also be asked to reload a PLUS that adds a register or a MEM to 7405 another register, constant or MEM. This can occur during frame pointer 7406 elimination and while reloading addresses. This case is handled by 7407 trying to emit a single insn to perform the add. If it is not valid, 7408 we use a two insn sequence. 7409 7410 Finally, we could be called to handle an 'o' constraint by putting 7411 an address into a register. In that case, we first try to do this 7412 with a named pattern of "reload_load_address". If no such pattern 7413 exists, we just emit a SET insn and hope for the best (it will normally 7414 be valid on machines that use 'o'). 7415 7416 This entire process is made complex because reload will never 7417 process the insns we generate here and so we must ensure that 7418 they will fit their constraints and also by the fact that parts of 7419 IN might be being reloaded separately and replaced with spill registers. 7420 Because of this, we are, in some sense, just guessing the right approach 7421 here. The one listed above seems to work. 7422 7423 ??? At some point, this whole thing needs to be rethought. */ 7424 7425 if (GET_CODE (in) == PLUS 7426 && (GET_CODE (XEXP (in, 0)) == REG 7427 || GET_CODE (XEXP (in, 0)) == SUBREG 7428 || GET_CODE (XEXP (in, 0)) == MEM) 7429 && (GET_CODE (XEXP (in, 1)) == REG 7430 || GET_CODE (XEXP (in, 1)) == SUBREG 7431 || CONSTANT_P (XEXP (in, 1)) 7432 || GET_CODE (XEXP (in, 1)) == MEM)) 7433 { 7434 /* We need to compute the sum of a register or a MEM and another 7435 register, constant, or MEM, and put it into the reload 7436 register. The best possible way of doing this is if the machine 7437 has a three-operand ADD insn that accepts the required operands. 7438 7439 The simplest approach is to try to generate such an insn and see if it 7440 is recognized and matches its constraints. If so, it can be used. 7441 7442 It might be better not to actually emit the insn unless it is valid, 7443 but we need to pass the insn as an operand to `recog' and 7444 `extract_insn' and it is simpler to emit and then delete the insn if 7445 not valid than to dummy things up. */ 7446 7447 rtx op0, op1, tem, insn; 7448 int code; 7449 7450 op0 = find_replacement (&XEXP (in, 0)); 7451 op1 = find_replacement (&XEXP (in, 1)); 7452 7453 /* Since constraint checking is strict, commutativity won't be 7454 checked, so we need to do that here to avoid spurious failure 7455 if the add instruction is two-address and the second operand 7456 of the add is the same as the reload reg, which is frequently 7457 the case. If the insn would be A = B + A, rearrange it so 7458 it will be A = A + B as constrain_operands expects. */ 7459 7460 if (GET_CODE (XEXP (in, 1)) == REG 7461 && REGNO (out) == REGNO (XEXP (in, 1))) 7462 tem = op0, op0 = op1, op1 = tem; 7463 7464 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) 7465 in = gen_rtx_PLUS (GET_MODE (in), op0, op1); 7466 7467 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in)); 7468 code = recog_memoized (insn); 7469 7470 if (code >= 0) 7471 { 7472 extract_insn (insn); 7473 /* We want constrain operands to treat this insn strictly in 7474 its validity determination, i.e., the way it would after reload 7475 has completed. */ 7476 if (constrain_operands (1)) 7477 return insn; 7478 } 7479 7480 delete_insns_since (last); 7481 7482 /* If that failed, we must use a conservative two-insn sequence. 7483 7484 Use a move to copy one operand into the reload register. Prefer 7485 to reload a constant, MEM or pseudo since the move patterns can 7486 handle an arbitrary operand. If OP1 is not a constant, MEM or 7487 pseudo and OP1 is not a valid operand for an add instruction, then 7488 reload OP1. 7489 7490 After reloading one of the operands into the reload register, add 7491 the reload register to the output register. 7492 7493 If there is another way to do this for a specific machine, a 7494 DEFINE_PEEPHOLE should be specified that recognizes the sequence 7495 we emit below. */ 7496 7497 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code; 7498 7499 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG 7500 || (GET_CODE (op1) == REG 7501 && REGNO (op1) >= FIRST_PSEUDO_REGISTER) 7502 || (code != CODE_FOR_nothing 7503 && ! ((*insn_data[code].operand[2].predicate) 7504 (op1, insn_data[code].operand[2].mode)))) 7505 tem = op0, op0 = op1, op1 = tem; 7506 7507 gen_reload (out, op0, opnum, type); 7508 7509 /* If OP0 and OP1 are the same, we can use OUT for OP1. 7510 This fixes a problem on the 32K where the stack pointer cannot 7511 be used as an operand of an add insn. */ 7512 7513 if (rtx_equal_p (op0, op1)) 7514 op1 = out; 7515 7516 insn = emit_insn (gen_add2_insn (out, op1)); 7517 7518 /* If that failed, copy the address register to the reload register. 7519 Then add the constant to the reload register. */ 7520 7521 code = recog_memoized (insn); 7522 7523 if (code >= 0) 7524 { 7525 extract_insn (insn); 7526 /* We want constrain operands to treat this insn strictly in 7527 its validity determination, i.e., the way it would after reload 7528 has completed. */ 7529 if (constrain_operands (1)) 7530 { 7531 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ 7532 REG_NOTES (insn) 7533 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); 7534 return insn; 7535 } 7536 } 7537 7538 delete_insns_since (last); 7539 7540 gen_reload (out, op1, opnum, type); 7541 insn = emit_insn (gen_add2_insn (out, op0)); 7542 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn)); 7543 } 7544 7545#ifdef SECONDARY_MEMORY_NEEDED 7546 /* If we need a memory location to do the move, do it that way. */ 7547 else if ((GET_CODE (in) == REG || GET_CODE (in) == SUBREG) 7548 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER 7549 && (GET_CODE (out) == REG || GET_CODE (out) == SUBREG) 7550 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER 7551 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)), 7552 REGNO_REG_CLASS (reg_or_subregno (out)), 7553 GET_MODE (out))) 7554 { 7555 /* Get the memory to use and rewrite both registers to its mode. */ 7556 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); 7557 7558 if (GET_MODE (loc) != GET_MODE (out)) 7559 out = gen_rtx_REG (GET_MODE (loc), REGNO (out)); 7560 7561 if (GET_MODE (loc) != GET_MODE (in)) 7562 in = gen_rtx_REG (GET_MODE (loc), REGNO (in)); 7563 7564 gen_reload (loc, in, opnum, type); 7565 gen_reload (out, loc, opnum, type); 7566 } 7567#endif 7568 7569 /* If IN is a simple operand, use gen_move_insn. */ 7570 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG) 7571 emit_insn (gen_move_insn (out, in)); 7572 7573#ifdef HAVE_reload_load_address 7574 else if (HAVE_reload_load_address) 7575 emit_insn (gen_reload_load_address (out, in)); 7576#endif 7577 7578 /* Otherwise, just write (set OUT IN) and hope for the best. */ 7579 else 7580 emit_insn (gen_rtx_SET (VOIDmode, out, in)); 7581 7582 /* Return the first insn emitted. 7583 We can not just return get_last_insn, because there may have 7584 been multiple instructions emitted. Also note that gen_move_insn may 7585 emit more than one insn itself, so we can not assume that there is one 7586 insn emitted per emit_insn_before call. */ 7587 7588 return last ? NEXT_INSN (last) : get_insns (); 7589} 7590 7591/* Delete a previously made output-reload whose result we now believe 7592 is not needed. First we double-check. 7593 7594 INSN is the insn now being processed. 7595 LAST_RELOAD_REG is the hard register number for which we want to delete 7596 the last output reload. 7597 J is the reload-number that originally used REG. The caller has made 7598 certain that reload J doesn't use REG any longer for input. */ 7599 7600static void 7601delete_output_reload (insn, j, last_reload_reg) 7602 rtx insn; 7603 int j; 7604 int last_reload_reg; 7605{ 7606 rtx output_reload_insn = spill_reg_store[last_reload_reg]; 7607 rtx reg = spill_reg_stored_to[last_reload_reg]; 7608 int k; 7609 int n_occurrences; 7610 int n_inherited = 0; 7611 rtx i1; 7612 rtx substed; 7613 7614 /* It is possible that this reload has been only used to set another reload 7615 we eliminated earlier and thus deleted this instruction too. */ 7616 if (INSN_DELETED_P (output_reload_insn)) 7617 return; 7618 7619 /* Get the raw pseudo-register referred to. */ 7620 7621 while (GET_CODE (reg) == SUBREG) 7622 reg = SUBREG_REG (reg); 7623 substed = reg_equiv_memory_loc[REGNO (reg)]; 7624 7625 /* This is unsafe if the operand occurs more often in the current 7626 insn than it is inherited. */ 7627 for (k = n_reloads - 1; k >= 0; k--) 7628 { 7629 rtx reg2 = rld[k].in; 7630 if (! reg2) 7631 continue; 7632 if (GET_CODE (reg2) == MEM || reload_override_in[k]) 7633 reg2 = rld[k].in_reg; 7634#ifdef AUTO_INC_DEC 7635 if (rld[k].out && ! rld[k].out_reg) 7636 reg2 = XEXP (rld[k].in_reg, 0); 7637#endif 7638 while (GET_CODE (reg2) == SUBREG) 7639 reg2 = SUBREG_REG (reg2); 7640 if (rtx_equal_p (reg2, reg)) 7641 { 7642 if (reload_inherited[k] || reload_override_in[k] || k == j) 7643 { 7644 n_inherited++; 7645 reg2 = rld[k].out_reg; 7646 if (! reg2) 7647 continue; 7648 while (GET_CODE (reg2) == SUBREG) 7649 reg2 = XEXP (reg2, 0); 7650 if (rtx_equal_p (reg2, reg)) 7651 n_inherited++; 7652 } 7653 else 7654 return; 7655 } 7656 } 7657 n_occurrences = count_occurrences (PATTERN (insn), reg, 0); 7658 if (substed) 7659 n_occurrences += count_occurrences (PATTERN (insn), 7660 eliminate_regs (substed, 0, 7661 NULL_RTX), 0); 7662 if (n_occurrences > n_inherited) 7663 return; 7664 7665 /* If the pseudo-reg we are reloading is no longer referenced 7666 anywhere between the store into it and here, 7667 and no jumps or labels intervene, then the value can get 7668 here through the reload reg alone. 7669 Otherwise, give up--return. */ 7670 for (i1 = NEXT_INSN (output_reload_insn); 7671 i1 != insn; i1 = NEXT_INSN (i1)) 7672 { 7673 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN) 7674 return; 7675 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN) 7676 && reg_mentioned_p (reg, PATTERN (i1))) 7677 { 7678 /* If this is USE in front of INSN, we only have to check that 7679 there are no more references than accounted for by inheritance. */ 7680 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE) 7681 { 7682 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; 7683 i1 = NEXT_INSN (i1); 7684 } 7685 if (n_occurrences <= n_inherited && i1 == insn) 7686 break; 7687 return; 7688 } 7689 } 7690 7691 /* We will be deleting the insn. Remove the spill reg information. */ 7692 for (k = HARD_REGNO_NREGS (last_reload_reg, GET_MODE (reg)); k-- > 0; ) 7693 { 7694 spill_reg_store[last_reload_reg + k] = 0; 7695 spill_reg_stored_to[last_reload_reg + k] = 0; 7696 } 7697 7698 /* The caller has already checked that REG dies or is set in INSN. 7699 It has also checked that we are optimizing, and thus some 7700 inaccurancies in the debugging information are acceptable. 7701 So we could just delete output_reload_insn. But in some cases 7702 we can improve the debugging information without sacrificing 7703 optimization - maybe even improving the code: See if the pseudo 7704 reg has been completely replaced with reload regs. If so, delete 7705 the store insn and forget we had a stack slot for the pseudo. */ 7706 if (rld[j].out != rld[j].in 7707 && REG_N_DEATHS (REGNO (reg)) == 1 7708 && REG_N_SETS (REGNO (reg)) == 1 7709 && REG_BASIC_BLOCK (REGNO (reg)) >= 0 7710 && find_regno_note (insn, REG_DEAD, REGNO (reg))) 7711 { 7712 rtx i2; 7713 7714 /* We know that it was used only between here and the beginning of 7715 the current basic block. (We also know that the last use before 7716 INSN was the output reload we are thinking of deleting, but never 7717 mind that.) Search that range; see if any ref remains. */ 7718 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) 7719 { 7720 rtx set = single_set (i2); 7721 7722 /* Uses which just store in the pseudo don't count, 7723 since if they are the only uses, they are dead. */ 7724 if (set != 0 && SET_DEST (set) == reg) 7725 continue; 7726 if (GET_CODE (i2) == CODE_LABEL 7727 || GET_CODE (i2) == JUMP_INSN) 7728 break; 7729 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN) 7730 && reg_mentioned_p (reg, PATTERN (i2))) 7731 { 7732 /* Some other ref remains; just delete the output reload we 7733 know to be dead. */ 7734 delete_address_reloads (output_reload_insn, insn); 7735 delete_insn (output_reload_insn); 7736 return; 7737 } 7738 } 7739 7740 /* Delete the now-dead stores into this pseudo. Note that this 7741 loop also takes care of deleting output_reload_insn. */ 7742 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) 7743 { 7744 rtx set = single_set (i2); 7745 7746 if (set != 0 && SET_DEST (set) == reg) 7747 { 7748 delete_address_reloads (i2, insn); 7749 delete_insn (i2); 7750 } 7751 if (GET_CODE (i2) == CODE_LABEL 7752 || GET_CODE (i2) == JUMP_INSN) 7753 break; 7754 } 7755 7756 /* For the debugging info, say the pseudo lives in this reload reg. */ 7757 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx); 7758 alter_reg (REGNO (reg), -1); 7759 } 7760 else 7761 { 7762 delete_address_reloads (output_reload_insn, insn); 7763 delete_insn (output_reload_insn); 7764 } 7765} 7766 7767/* We are going to delete DEAD_INSN. Recursively delete loads of 7768 reload registers used in DEAD_INSN that are not used till CURRENT_INSN. 7769 CURRENT_INSN is being reloaded, so we have to check its reloads too. */ 7770static void 7771delete_address_reloads (dead_insn, current_insn) 7772 rtx dead_insn, current_insn; 7773{ 7774 rtx set = single_set (dead_insn); 7775 rtx set2, dst, prev, next; 7776 if (set) 7777 { 7778 rtx dst = SET_DEST (set); 7779 if (GET_CODE (dst) == MEM) 7780 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); 7781 } 7782 /* If we deleted the store from a reloaded post_{in,de}c expression, 7783 we can delete the matching adds. */ 7784 prev = PREV_INSN (dead_insn); 7785 next = NEXT_INSN (dead_insn); 7786 if (! prev || ! next) 7787 return; 7788 set = single_set (next); 7789 set2 = single_set (prev); 7790 if (! set || ! set2 7791 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS 7792 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT 7793 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT) 7794 return; 7795 dst = SET_DEST (set); 7796 if (! rtx_equal_p (dst, SET_DEST (set2)) 7797 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) 7798 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) 7799 || (INTVAL (XEXP (SET_SRC (set), 1)) 7800 != -INTVAL (XEXP (SET_SRC (set2), 1)))) 7801 return; 7802 delete_related_insns (prev); 7803 delete_related_insns (next); 7804} 7805 7806/* Subfunction of delete_address_reloads: process registers found in X. */ 7807static void 7808delete_address_reloads_1 (dead_insn, x, current_insn) 7809 rtx dead_insn, x, current_insn; 7810{ 7811 rtx prev, set, dst, i2; 7812 int i, j; 7813 enum rtx_code code = GET_CODE (x); 7814 7815 if (code != REG) 7816 { 7817 const char *fmt = GET_RTX_FORMAT (code); 7818 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 7819 { 7820 if (fmt[i] == 'e') 7821 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); 7822 else if (fmt[i] == 'E') 7823 { 7824 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 7825 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), 7826 current_insn); 7827 } 7828 } 7829 return; 7830 } 7831 7832 if (spill_reg_order[REGNO (x)] < 0) 7833 return; 7834 7835 /* Scan backwards for the insn that sets x. This might be a way back due 7836 to inheritance. */ 7837 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) 7838 { 7839 code = GET_CODE (prev); 7840 if (code == CODE_LABEL || code == JUMP_INSN) 7841 return; 7842 if (GET_RTX_CLASS (code) != 'i') 7843 continue; 7844 if (reg_set_p (x, PATTERN (prev))) 7845 break; 7846 if (reg_referenced_p (x, PATTERN (prev))) 7847 return; 7848 } 7849 if (! prev || INSN_UID (prev) < reload_first_uid) 7850 return; 7851 /* Check that PREV only sets the reload register. */ 7852 set = single_set (prev); 7853 if (! set) 7854 return; 7855 dst = SET_DEST (set); 7856 if (GET_CODE (dst) != REG 7857 || ! rtx_equal_p (dst, x)) 7858 return; 7859 if (! reg_set_p (dst, PATTERN (dead_insn))) 7860 { 7861 /* Check if DST was used in a later insn - 7862 it might have been inherited. */ 7863 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) 7864 { 7865 if (GET_CODE (i2) == CODE_LABEL) 7866 break; 7867 if (! INSN_P (i2)) 7868 continue; 7869 if (reg_referenced_p (dst, PATTERN (i2))) 7870 { 7871 /* If there is a reference to the register in the current insn, 7872 it might be loaded in a non-inherited reload. If no other 7873 reload uses it, that means the register is set before 7874 referenced. */ 7875 if (i2 == current_insn) 7876 { 7877 for (j = n_reloads - 1; j >= 0; j--) 7878 if ((rld[j].reg_rtx == dst && reload_inherited[j]) 7879 || reload_override_in[j] == dst) 7880 return; 7881 for (j = n_reloads - 1; j >= 0; j--) 7882 if (rld[j].in && rld[j].reg_rtx == dst) 7883 break; 7884 if (j >= 0) 7885 break; 7886 } 7887 return; 7888 } 7889 if (GET_CODE (i2) == JUMP_INSN) 7890 break; 7891 /* If DST is still live at CURRENT_INSN, check if it is used for 7892 any reload. Note that even if CURRENT_INSN sets DST, we still 7893 have to check the reloads. */ 7894 if (i2 == current_insn) 7895 { 7896 for (j = n_reloads - 1; j >= 0; j--) 7897 if ((rld[j].reg_rtx == dst && reload_inherited[j]) 7898 || reload_override_in[j] == dst) 7899 return; 7900 /* ??? We can't finish the loop here, because dst might be 7901 allocated to a pseudo in this block if no reload in this 7902 block needs any of the clsses containing DST - see 7903 spill_hard_reg. There is no easy way to tell this, so we 7904 have to scan till the end of the basic block. */ 7905 } 7906 if (reg_set_p (dst, PATTERN (i2))) 7907 break; 7908 } 7909 } 7910 delete_address_reloads_1 (prev, SET_SRC (set), current_insn); 7911 reg_reloaded_contents[REGNO (dst)] = -1; 7912 delete_insn (prev); 7913} 7914 7915/* Output reload-insns to reload VALUE into RELOADREG. 7916 VALUE is an autoincrement or autodecrement RTX whose operand 7917 is a register or memory location; 7918 so reloading involves incrementing that location. 7919 IN is either identical to VALUE, or some cheaper place to reload from. 7920 7921 INC_AMOUNT is the number to increment or decrement by (always positive). 7922 This cannot be deduced from VALUE. 7923 7924 Return the instruction that stores into RELOADREG. */ 7925 7926static rtx 7927inc_for_reload (reloadreg, in, value, inc_amount) 7928 rtx reloadreg; 7929 rtx in, value; 7930 int inc_amount; 7931{ 7932 /* REG or MEM to be copied and incremented. */ 7933 rtx incloc = XEXP (value, 0); 7934 /* Nonzero if increment after copying. */ 7935 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC); 7936 rtx last; 7937 rtx inc; 7938 rtx add_insn; 7939 int code; 7940 rtx store; 7941 rtx real_in = in == value ? XEXP (in, 0) : in; 7942 7943 /* No hard register is equivalent to this register after 7944 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero, 7945 we could inc/dec that register as well (maybe even using it for 7946 the source), but I'm not sure it's worth worrying about. */ 7947 if (GET_CODE (incloc) == REG) 7948 reg_last_reload_reg[REGNO (incloc)] = 0; 7949 7950 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) 7951 inc_amount = -inc_amount; 7952 7953 inc = GEN_INT (inc_amount); 7954 7955 /* If this is post-increment, first copy the location to the reload reg. */ 7956 if (post && real_in != reloadreg) 7957 emit_insn (gen_move_insn (reloadreg, real_in)); 7958 7959 if (in == value) 7960 { 7961 /* See if we can directly increment INCLOC. Use a method similar to 7962 that in gen_reload. */ 7963 7964 last = get_last_insn (); 7965 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc, 7966 gen_rtx_PLUS (GET_MODE (incloc), 7967 incloc, inc))); 7968 7969 code = recog_memoized (add_insn); 7970 if (code >= 0) 7971 { 7972 extract_insn (add_insn); 7973 if (constrain_operands (1)) 7974 { 7975 /* If this is a pre-increment and we have incremented the value 7976 where it lives, copy the incremented value to RELOADREG to 7977 be used as an address. */ 7978 7979 if (! post) 7980 emit_insn (gen_move_insn (reloadreg, incloc)); 7981 7982 return add_insn; 7983 } 7984 } 7985 delete_insns_since (last); 7986 } 7987 7988 /* If couldn't do the increment directly, must increment in RELOADREG. 7989 The way we do this depends on whether this is pre- or post-increment. 7990 For pre-increment, copy INCLOC to the reload register, increment it 7991 there, then save back. */ 7992 7993 if (! post) 7994 { 7995 if (in != reloadreg) 7996 emit_insn (gen_move_insn (reloadreg, real_in)); 7997 emit_insn (gen_add2_insn (reloadreg, inc)); 7998 store = emit_insn (gen_move_insn (incloc, reloadreg)); 7999 } 8000 else 8001 { 8002 /* Postincrement. 8003 Because this might be a jump insn or a compare, and because RELOADREG 8004 may not be available after the insn in an input reload, we must do 8005 the incrementation before the insn being reloaded for. 8006 8007 We have already copied IN to RELOADREG. Increment the copy in 8008 RELOADREG, save that back, then decrement RELOADREG so it has 8009 the original value. */ 8010 8011 emit_insn (gen_add2_insn (reloadreg, inc)); 8012 store = emit_insn (gen_move_insn (incloc, reloadreg)); 8013 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount))); 8014 } 8015 8016 return store; 8017} 8018 8019 8020/* See whether a single set SET is a noop. */ 8021static int 8022reload_cse_noop_set_p (set) 8023 rtx set; 8024{ 8025 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); 8026} 8027 8028/* Try to simplify INSN. */ 8029static void 8030reload_cse_simplify (insn, testreg) 8031 rtx insn; 8032 rtx testreg; 8033{ 8034 rtx body = PATTERN (insn); 8035 8036 if (GET_CODE (body) == SET) 8037 { 8038 int count = 0; 8039 8040 /* Simplify even if we may think it is a no-op. 8041 We may think a memory load of a value smaller than WORD_SIZE 8042 is redundant because we haven't taken into account possible 8043 implicit extension. reload_cse_simplify_set() will bring 8044 this out, so it's safer to simplify before we delete. */ 8045 count += reload_cse_simplify_set (body, insn); 8046 8047 if (!count && reload_cse_noop_set_p (body)) 8048 { 8049 rtx value = SET_DEST (body); 8050 if (REG_P (value) 8051 && ! REG_FUNCTION_VALUE_P (value)) 8052 value = 0; 8053 delete_insn_and_edges (insn); 8054 return; 8055 } 8056 8057 if (count > 0) 8058 apply_change_group (); 8059 else 8060 reload_cse_simplify_operands (insn, testreg); 8061 } 8062 else if (GET_CODE (body) == PARALLEL) 8063 { 8064 int i; 8065 int count = 0; 8066 rtx value = NULL_RTX; 8067 8068 /* If every action in a PARALLEL is a noop, we can delete 8069 the entire PARALLEL. */ 8070 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 8071 { 8072 rtx part = XVECEXP (body, 0, i); 8073 if (GET_CODE (part) == SET) 8074 { 8075 if (! reload_cse_noop_set_p (part)) 8076 break; 8077 if (REG_P (SET_DEST (part)) 8078 && REG_FUNCTION_VALUE_P (SET_DEST (part))) 8079 { 8080 if (value) 8081 break; 8082 value = SET_DEST (part); 8083 } 8084 } 8085 else if (GET_CODE (part) != CLOBBER) 8086 break; 8087 } 8088 8089 if (i < 0) 8090 { 8091 delete_insn_and_edges (insn); 8092 /* We're done with this insn. */ 8093 return; 8094 } 8095 8096 /* It's not a no-op, but we can try to simplify it. */ 8097 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 8098 if (GET_CODE (XVECEXP (body, 0, i)) == SET) 8099 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); 8100 8101 if (count > 0) 8102 apply_change_group (); 8103 else 8104 reload_cse_simplify_operands (insn, testreg); 8105 } 8106} 8107 8108/* Do a very simple CSE pass over the hard registers. 8109 8110 This function detects no-op moves where we happened to assign two 8111 different pseudo-registers to the same hard register, and then 8112 copied one to the other. Reload will generate a useless 8113 instruction copying a register to itself. 8114 8115 This function also detects cases where we load a value from memory 8116 into two different registers, and (if memory is more expensive than 8117 registers) changes it to simply copy the first register into the 8118 second register. 8119 8120 Another optimization is performed that scans the operands of each 8121 instruction to see whether the value is already available in a 8122 hard register. It then replaces the operand with the hard register 8123 if possible, much like an optional reload would. */ 8124 8125static void 8126reload_cse_regs_1 (first) 8127 rtx first; 8128{ 8129 rtx insn; 8130 rtx testreg = gen_rtx_REG (VOIDmode, -1); 8131 8132 cselib_init (); 8133 init_alias_analysis (); 8134 8135 for (insn = first; insn; insn = NEXT_INSN (insn)) 8136 { 8137 if (INSN_P (insn)) 8138 reload_cse_simplify (insn, testreg); 8139 8140 cselib_process_insn (insn); 8141 } 8142 8143 /* Clean up. */ 8144 end_alias_analysis (); 8145 cselib_finish (); 8146} 8147 8148/* Call cse / combine like post-reload optimization phases. 8149 FIRST is the first instruction. */ 8150void 8151reload_cse_regs (first) 8152 rtx first; 8153{ 8154 reload_cse_regs_1 (first); 8155 reload_combine (); 8156 reload_cse_move2add (first); 8157 if (flag_expensive_optimizations) 8158 reload_cse_regs_1 (first); 8159} 8160 8161/* Try to simplify a single SET instruction. SET is the set pattern. 8162 INSN is the instruction it came from. 8163 This function only handles one case: if we set a register to a value 8164 which is not a register, we try to find that value in some other register 8165 and change the set into a register copy. */ 8166 8167static int 8168reload_cse_simplify_set (set, insn) 8169 rtx set; 8170 rtx insn; 8171{ 8172 int did_change = 0; 8173 int dreg; 8174 rtx src; 8175 enum reg_class dclass; 8176 int old_cost; 8177 cselib_val *val; 8178 struct elt_loc_list *l; 8179#ifdef LOAD_EXTEND_OP 8180 enum rtx_code extend_op = NIL; 8181#endif 8182 8183 dreg = true_regnum (SET_DEST (set)); 8184 if (dreg < 0) 8185 return 0; 8186 8187 src = SET_SRC (set); 8188 if (side_effects_p (src) || true_regnum (src) >= 0) 8189 return 0; 8190 8191 dclass = REGNO_REG_CLASS (dreg); 8192 8193#ifdef LOAD_EXTEND_OP 8194 /* When replacing a memory with a register, we need to honor assumptions 8195 that combine made wrt the contents of sign bits. We'll do this by 8196 generating an extend instruction instead of a reg->reg copy. Thus 8197 the destination must be a register that we can widen. */ 8198 if (GET_CODE (src) == MEM 8199 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD 8200 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL 8201 && GET_CODE (SET_DEST (set)) != REG) 8202 return 0; 8203#endif 8204 8205 /* If memory loads are cheaper than register copies, don't change them. */ 8206 if (GET_CODE (src) == MEM) 8207 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1); 8208 else if (CONSTANT_P (src)) 8209 old_cost = rtx_cost (src, SET); 8210 else if (GET_CODE (src) == REG) 8211 old_cost = REGISTER_MOVE_COST (GET_MODE (src), 8212 REGNO_REG_CLASS (REGNO (src)), dclass); 8213 else 8214 /* ??? */ 8215 old_cost = rtx_cost (src, SET); 8216 8217 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0); 8218 if (! val) 8219 return 0; 8220 for (l = val->locs; l; l = l->next) 8221 { 8222 rtx this_rtx = l->loc; 8223 int this_cost; 8224 8225 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) 8226 { 8227#ifdef LOAD_EXTEND_OP 8228 if (extend_op != NIL) 8229 { 8230 HOST_WIDE_INT this_val; 8231 8232 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other 8233 constants, such as SYMBOL_REF, cannot be extended. */ 8234 if (GET_CODE (this_rtx) != CONST_INT) 8235 continue; 8236 8237 this_val = INTVAL (this_rtx); 8238 switch (extend_op) 8239 { 8240 case ZERO_EXTEND: 8241 this_val &= GET_MODE_MASK (GET_MODE (src)); 8242 break; 8243 case SIGN_EXTEND: 8244 /* ??? In theory we're already extended. */ 8245 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src))) 8246 break; 8247 default: 8248 abort (); 8249 } 8250 this_rtx = GEN_INT (this_val); 8251 } 8252#endif 8253 this_cost = rtx_cost (this_rtx, SET); 8254 } 8255 else if (GET_CODE (this_rtx) == REG) 8256 { 8257#ifdef LOAD_EXTEND_OP 8258 if (extend_op != NIL) 8259 { 8260 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); 8261 this_cost = rtx_cost (this_rtx, SET); 8262 } 8263 else 8264#endif 8265 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx), 8266 REGNO_REG_CLASS (REGNO (this_rtx)), 8267 dclass); 8268 } 8269 else 8270 continue; 8271 8272 /* If equal costs, prefer registers over anything else. That 8273 tends to lead to smaller instructions on some machines. */ 8274 if (this_cost < old_cost 8275 || (this_cost == old_cost 8276 && GET_CODE (this_rtx) == REG 8277 && GET_CODE (SET_SRC (set)) != REG)) 8278 { 8279#ifdef LOAD_EXTEND_OP 8280 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD 8281 && extend_op != NIL 8282#ifdef CANNOT_CHANGE_MODE_CLASS 8283 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), 8284 word_mode, 8285 REGNO_REG_CLASS (REGNO (SET_DEST (set)))) 8286#endif 8287 ) 8288 { 8289 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); 8290 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); 8291 validate_change (insn, &SET_DEST (set), wide_dest, 1); 8292 } 8293#endif 8294 8295 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1); 8296 old_cost = this_cost, did_change = 1; 8297 } 8298 } 8299 8300 return did_change; 8301} 8302 8303/* Try to replace operands in INSN with equivalent values that are already 8304 in registers. This can be viewed as optional reloading. 8305 8306 For each non-register operand in the insn, see if any hard regs are 8307 known to be equivalent to that operand. Record the alternatives which 8308 can accept these hard registers. Among all alternatives, select the 8309 ones which are better or equal to the one currently matching, where 8310 "better" is in terms of '?' and '!' constraints. Among the remaining 8311 alternatives, select the one which replaces most operands with 8312 hard registers. */ 8313 8314static int 8315reload_cse_simplify_operands (insn, testreg) 8316 rtx insn; 8317 rtx testreg; 8318{ 8319 int i, j; 8320 8321 /* For each operand, all registers that are equivalent to it. */ 8322 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; 8323 8324 const char *constraints[MAX_RECOG_OPERANDS]; 8325 8326 /* Vector recording how bad an alternative is. */ 8327 int *alternative_reject; 8328 /* Vector recording how many registers can be introduced by choosing 8329 this alternative. */ 8330 int *alternative_nregs; 8331 /* Array of vectors recording, for each operand and each alternative, 8332 which hard register to substitute, or -1 if the operand should be 8333 left as it is. */ 8334 int *op_alt_regno[MAX_RECOG_OPERANDS]; 8335 /* Array of alternatives, sorted in order of decreasing desirability. */ 8336 int *alternative_order; 8337 8338 extract_insn (insn); 8339 8340 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) 8341 return 0; 8342 8343 /* Figure out which alternative currently matches. */ 8344 if (! constrain_operands (1)) 8345 fatal_insn_not_found (insn); 8346 8347 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int)); 8348 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int)); 8349 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int)); 8350 memset ((char *) alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); 8351 memset ((char *) alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); 8352 8353 /* For each operand, find out which regs are equivalent. */ 8354 for (i = 0; i < recog_data.n_operands; i++) 8355 { 8356 cselib_val *v; 8357 struct elt_loc_list *l; 8358 8359 CLEAR_HARD_REG_SET (equiv_regs[i]); 8360 8361 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem 8362 right, so avoid the problem here. Likewise if we have a constant 8363 and the insn pattern doesn't tell us the mode we need. */ 8364 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL 8365 || (CONSTANT_P (recog_data.operand[i]) 8366 && recog_data.operand_mode[i] == VOIDmode)) 8367 continue; 8368 8369 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0); 8370 if (! v) 8371 continue; 8372 8373 for (l = v->locs; l; l = l->next) 8374 if (GET_CODE (l->loc) == REG) 8375 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); 8376 } 8377 8378 for (i = 0; i < recog_data.n_operands; i++) 8379 { 8380 enum machine_mode mode; 8381 int regno; 8382 const char *p; 8383 8384 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int)); 8385 for (j = 0; j < recog_data.n_alternatives; j++) 8386 op_alt_regno[i][j] = -1; 8387 8388 p = constraints[i] = recog_data.constraints[i]; 8389 mode = recog_data.operand_mode[i]; 8390 8391 /* Add the reject values for each alternative given by the constraints 8392 for this operand. */ 8393 j = 0; 8394 while (*p != '\0') 8395 { 8396 char c = *p++; 8397 if (c == ',') 8398 j++; 8399 else if (c == '?') 8400 alternative_reject[j] += 3; 8401 else if (c == '!') 8402 alternative_reject[j] += 300; 8403 } 8404 8405 /* We won't change operands which are already registers. We 8406 also don't want to modify output operands. */ 8407 regno = true_regnum (recog_data.operand[i]); 8408 if (regno >= 0 8409 || constraints[i][0] == '=' 8410 || constraints[i][0] == '+') 8411 continue; 8412 8413 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 8414 { 8415 int class = (int) NO_REGS; 8416 8417 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) 8418 continue; 8419 8420 REGNO (testreg) = regno; 8421 PUT_MODE (testreg, mode); 8422 8423 /* We found a register equal to this operand. Now look for all 8424 alternatives that can accept this register and have not been 8425 assigned a register they can use yet. */ 8426 j = 0; 8427 p = constraints[i]; 8428 for (;;) 8429 { 8430 char c = *p++; 8431 8432 switch (c) 8433 { 8434 case '=': case '+': case '?': 8435 case '#': case '&': case '!': 8436 case '*': case '%': 8437 case '0': case '1': case '2': case '3': case '4': 8438 case '5': case '6': case '7': case '8': case '9': 8439 case 'm': case '<': case '>': case 'V': case 'o': 8440 case 'E': case 'F': case 'G': case 'H': 8441 case 's': case 'i': case 'n': 8442 case 'I': case 'J': case 'K': case 'L': 8443 case 'M': case 'N': case 'O': case 'P': 8444 case 'p': case 'X': 8445 /* These don't say anything we care about. */ 8446 break; 8447 8448 case 'g': case 'r': 8449 class = reg_class_subunion[(int) class][(int) GENERAL_REGS]; 8450 break; 8451 8452 default: 8453 class 8454 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char) c)]; 8455 break; 8456 8457 case ',': case '\0': 8458 /* See if REGNO fits this alternative, and set it up as the 8459 replacement register if we don't have one for this 8460 alternative yet and the operand being replaced is not 8461 a cheap CONST_INT. */ 8462 if (op_alt_regno[i][j] == -1 8463 && reg_fits_class_p (testreg, class, 0, mode) 8464 && (GET_CODE (recog_data.operand[i]) != CONST_INT 8465 || (rtx_cost (recog_data.operand[i], SET) 8466 > rtx_cost (testreg, SET)))) 8467 { 8468 alternative_nregs[j]++; 8469 op_alt_regno[i][j] = regno; 8470 } 8471 j++; 8472 break; 8473 } 8474 8475 if (c == '\0') 8476 break; 8477 } 8478 } 8479 } 8480 8481 /* Record all alternatives which are better or equal to the currently 8482 matching one in the alternative_order array. */ 8483 for (i = j = 0; i < recog_data.n_alternatives; i++) 8484 if (alternative_reject[i] <= alternative_reject[which_alternative]) 8485 alternative_order[j++] = i; 8486 recog_data.n_alternatives = j; 8487 8488 /* Sort it. Given a small number of alternatives, a dumb algorithm 8489 won't hurt too much. */ 8490 for (i = 0; i < recog_data.n_alternatives - 1; i++) 8491 { 8492 int best = i; 8493 int best_reject = alternative_reject[alternative_order[i]]; 8494 int best_nregs = alternative_nregs[alternative_order[i]]; 8495 int tmp; 8496 8497 for (j = i + 1; j < recog_data.n_alternatives; j++) 8498 { 8499 int this_reject = alternative_reject[alternative_order[j]]; 8500 int this_nregs = alternative_nregs[alternative_order[j]]; 8501 8502 if (this_reject < best_reject 8503 || (this_reject == best_reject && this_nregs < best_nregs)) 8504 { 8505 best = j; 8506 best_reject = this_reject; 8507 best_nregs = this_nregs; 8508 } 8509 } 8510 8511 tmp = alternative_order[best]; 8512 alternative_order[best] = alternative_order[i]; 8513 alternative_order[i] = tmp; 8514 } 8515 8516 /* Substitute the operands as determined by op_alt_regno for the best 8517 alternative. */ 8518 j = alternative_order[0]; 8519 8520 for (i = 0; i < recog_data.n_operands; i++) 8521 { 8522 enum machine_mode mode = recog_data.operand_mode[i]; 8523 if (op_alt_regno[i][j] == -1) 8524 continue; 8525 8526 validate_change (insn, recog_data.operand_loc[i], 8527 gen_rtx_REG (mode, op_alt_regno[i][j]), 1); 8528 } 8529 8530 for (i = recog_data.n_dups - 1; i >= 0; i--) 8531 { 8532 int op = recog_data.dup_num[i]; 8533 enum machine_mode mode = recog_data.operand_mode[op]; 8534 8535 if (op_alt_regno[op][j] == -1) 8536 continue; 8537 8538 validate_change (insn, recog_data.dup_loc[i], 8539 gen_rtx_REG (mode, op_alt_regno[op][j]), 1); 8540 } 8541 8542 return apply_change_group (); 8543} 8544 8545/* If reload couldn't use reg+reg+offset addressing, try to use reg+reg 8546 addressing now. 8547 This code might also be useful when reload gave up on reg+reg addresssing 8548 because of clashes between the return register and INDEX_REG_CLASS. */ 8549 8550/* The maximum number of uses of a register we can keep track of to 8551 replace them with reg+reg addressing. */ 8552#define RELOAD_COMBINE_MAX_USES 6 8553 8554/* INSN is the insn where a register has ben used, and USEP points to the 8555 location of the register within the rtl. */ 8556struct reg_use { rtx insn, *usep; }; 8557 8558/* If the register is used in some unknown fashion, USE_INDEX is negative. 8559 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID 8560 indicates where it becomes live again. 8561 Otherwise, USE_INDEX is the index of the last encountered use of the 8562 register (which is first among these we have seen since we scan backwards), 8563 OFFSET contains the constant offset that is added to the register in 8564 all encountered uses, and USE_RUID indicates the first encountered, i.e. 8565 last, of these uses. 8566 STORE_RUID is always meaningful if we only want to use a value in a 8567 register in a different place: it denotes the next insn in the insn 8568 stream (i.e. the last ecountered) that sets or clobbers the register. */ 8569static struct 8570 { 8571 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; 8572 int use_index; 8573 rtx offset; 8574 int store_ruid; 8575 int use_ruid; 8576 } reg_state[FIRST_PSEUDO_REGISTER]; 8577 8578/* Reverse linear uid. This is increased in reload_combine while scanning 8579 the instructions from last to first. It is used to set last_label_ruid 8580 and the store_ruid / use_ruid fields in reg_state. */ 8581static int reload_combine_ruid; 8582 8583#define LABEL_LIVE(LABEL) \ 8584 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) 8585 8586static void 8587reload_combine () 8588{ 8589 rtx insn, set; 8590 int first_index_reg = -1; 8591 int last_index_reg = 0; 8592 int i; 8593 basic_block bb; 8594 unsigned int r; 8595 int last_label_ruid; 8596 int min_labelno, n_labels; 8597 HARD_REG_SET ever_live_at_start, *label_live; 8598 8599 /* If reg+reg can be used in offsetable memory addresses, the main chunk of 8600 reload has already used it where appropriate, so there is no use in 8601 trying to generate it now. */ 8602 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS) 8603 return; 8604 8605 /* To avoid wasting too much time later searching for an index register, 8606 determine the minimum and maximum index register numbers. */ 8607 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 8608 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) 8609 { 8610 if (first_index_reg == -1) 8611 first_index_reg = r; 8612 8613 last_index_reg = r; 8614 } 8615 8616 /* If no index register is available, we can quit now. */ 8617 if (first_index_reg == -1) 8618 return; 8619 8620 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime 8621 information is a bit fuzzy immediately after reload, but it's 8622 still good enough to determine which registers are live at a jump 8623 destination. */ 8624 min_labelno = get_first_label_num (); 8625 n_labels = max_label_num () - min_labelno; 8626 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET)); 8627 CLEAR_HARD_REG_SET (ever_live_at_start); 8628 8629 FOR_EACH_BB_REVERSE (bb) 8630 { 8631 insn = bb->head; 8632 if (GET_CODE (insn) == CODE_LABEL) 8633 { 8634 HARD_REG_SET live; 8635 8636 REG_SET_TO_HARD_REG_SET (live, 8637 bb->global_live_at_start); 8638 compute_use_by_pseudos (&live, 8639 bb->global_live_at_start); 8640 COPY_HARD_REG_SET (LABEL_LIVE (insn), live); 8641 IOR_HARD_REG_SET (ever_live_at_start, live); 8642 } 8643 } 8644 8645 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ 8646 last_label_ruid = reload_combine_ruid = 0; 8647 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 8648 { 8649 reg_state[r].store_ruid = reload_combine_ruid; 8650 if (fixed_regs[r]) 8651 reg_state[r].use_index = -1; 8652 else 8653 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; 8654 } 8655 8656 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn)) 8657 { 8658 rtx note; 8659 8660 /* We cannot do our optimization across labels. Invalidating all the use 8661 information we have would be costly, so we just note where the label 8662 is and then later disable any optimization that would cross it. */ 8663 if (GET_CODE (insn) == CODE_LABEL) 8664 last_label_ruid = reload_combine_ruid; 8665 else if (GET_CODE (insn) == BARRIER) 8666 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 8667 if (! fixed_regs[r]) 8668 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; 8669 8670 if (! INSN_P (insn)) 8671 continue; 8672 8673 reload_combine_ruid++; 8674 8675 /* Look for (set (REGX) (CONST_INT)) 8676 (set (REGX) (PLUS (REGX) (REGY))) 8677 ... 8678 ... (MEM (REGX)) ... 8679 and convert it to 8680 (set (REGZ) (CONST_INT)) 8681 ... 8682 ... (MEM (PLUS (REGZ) (REGY)))... . 8683 8684 First, check that we have (set (REGX) (PLUS (REGX) (REGY))) 8685 and that we know all uses of REGX before it dies. */ 8686 set = single_set (insn); 8687 if (set != NULL_RTX 8688 && GET_CODE (SET_DEST (set)) == REG 8689 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)), 8690 GET_MODE (SET_DEST (set))) 8691 == 1) 8692 && GET_CODE (SET_SRC (set)) == PLUS 8693 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG 8694 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set)) 8695 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid) 8696 { 8697 rtx reg = SET_DEST (set); 8698 rtx plus = SET_SRC (set); 8699 rtx base = XEXP (plus, 1); 8700 rtx prev = prev_nonnote_insn (insn); 8701 rtx prev_set = prev ? single_set (prev) : NULL_RTX; 8702 unsigned int regno = REGNO (reg); 8703 rtx const_reg = NULL_RTX; 8704 rtx reg_sum = NULL_RTX; 8705 8706 /* Now, we need an index register. 8707 We'll set index_reg to this index register, const_reg to the 8708 register that is to be loaded with the constant 8709 (denoted as REGZ in the substitution illustration above), 8710 and reg_sum to the register-register that we want to use to 8711 substitute uses of REG (typically in MEMs) with. 8712 First check REG and BASE for being index registers; 8713 we can use them even if they are not dead. */ 8714 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) 8715 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], 8716 REGNO (base))) 8717 { 8718 const_reg = reg; 8719 reg_sum = plus; 8720 } 8721 else 8722 { 8723 /* Otherwise, look for a free index register. Since we have 8724 checked above that neiter REG nor BASE are index registers, 8725 if we find anything at all, it will be different from these 8726 two registers. */ 8727 for (i = first_index_reg; i <= last_index_reg; i++) 8728 { 8729 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], 8730 i) 8731 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES 8732 && reg_state[i].store_ruid <= reg_state[regno].use_ruid 8733 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1) 8734 { 8735 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i); 8736 8737 const_reg = index_reg; 8738 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); 8739 break; 8740 } 8741 } 8742 } 8743 8744 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that 8745 (REGY), i.e. BASE, is not clobbered before the last use we'll 8746 create. */ 8747 if (prev_set != 0 8748 && GET_CODE (SET_SRC (prev_set)) == CONST_INT 8749 && rtx_equal_p (SET_DEST (prev_set), reg) 8750 && reg_state[regno].use_index >= 0 8751 && (reg_state[REGNO (base)].store_ruid 8752 <= reg_state[regno].use_ruid) 8753 && reg_sum != 0) 8754 { 8755 int i; 8756 8757 /* Change destination register and, if necessary, the 8758 constant value in PREV, the constant loading instruction. */ 8759 validate_change (prev, &SET_DEST (prev_set), const_reg, 1); 8760 if (reg_state[regno].offset != const0_rtx) 8761 validate_change (prev, 8762 &SET_SRC (prev_set), 8763 GEN_INT (INTVAL (SET_SRC (prev_set)) 8764 + INTVAL (reg_state[regno].offset)), 8765 1); 8766 8767 /* Now for every use of REG that we have recorded, replace REG 8768 with REG_SUM. */ 8769 for (i = reg_state[regno].use_index; 8770 i < RELOAD_COMBINE_MAX_USES; i++) 8771 validate_change (reg_state[regno].reg_use[i].insn, 8772 reg_state[regno].reg_use[i].usep, 8773 /* Each change must have its own 8774 replacement. */ 8775 copy_rtx (reg_sum), 1); 8776 8777 if (apply_change_group ()) 8778 { 8779 rtx *np; 8780 8781 /* Delete the reg-reg addition. */ 8782 delete_insn (insn); 8783 8784 if (reg_state[regno].offset != const0_rtx) 8785 /* Previous REG_EQUIV / REG_EQUAL notes for PREV 8786 are now invalid. */ 8787 for (np = ®_NOTES (prev); *np;) 8788 { 8789 if (REG_NOTE_KIND (*np) == REG_EQUAL 8790 || REG_NOTE_KIND (*np) == REG_EQUIV) 8791 *np = XEXP (*np, 1); 8792 else 8793 np = &XEXP (*np, 1); 8794 } 8795 8796 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; 8797 reg_state[REGNO (const_reg)].store_ruid 8798 = reload_combine_ruid; 8799 continue; 8800 } 8801 } 8802 } 8803 8804 note_stores (PATTERN (insn), reload_combine_note_store, NULL); 8805 8806 if (GET_CODE (insn) == CALL_INSN) 8807 { 8808 rtx link; 8809 8810 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 8811 if (call_used_regs[r]) 8812 { 8813 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; 8814 reg_state[r].store_ruid = reload_combine_ruid; 8815 } 8816 8817 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; 8818 link = XEXP (link, 1)) 8819 { 8820 rtx usage_rtx = XEXP (XEXP (link, 0), 0); 8821 if (GET_CODE (usage_rtx) == REG) 8822 { 8823 unsigned int i; 8824 unsigned int start_reg = REGNO (usage_rtx); 8825 unsigned int num_regs = 8826 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx)); 8827 unsigned int end_reg = start_reg + num_regs - 1; 8828 for (i = start_reg; i <= end_reg; i++) 8829 if (GET_CODE (XEXP (link, 0)) == CLOBBER) 8830 { 8831 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; 8832 reg_state[i].store_ruid = reload_combine_ruid; 8833 } 8834 else 8835 reg_state[i].use_index = -1; 8836 } 8837 } 8838 8839 } 8840 else if (GET_CODE (insn) == JUMP_INSN 8841 && GET_CODE (PATTERN (insn)) != RETURN) 8842 { 8843 /* Non-spill registers might be used at the call destination in 8844 some unknown fashion, so we have to mark the unknown use. */ 8845 HARD_REG_SET *live; 8846 8847 if ((condjump_p (insn) || condjump_in_parallel_p (insn)) 8848 && JUMP_LABEL (insn)) 8849 live = &LABEL_LIVE (JUMP_LABEL (insn)); 8850 else 8851 live = &ever_live_at_start; 8852 8853 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i) 8854 if (TEST_HARD_REG_BIT (*live, i)) 8855 reg_state[i].use_index = -1; 8856 } 8857 8858 reload_combine_note_use (&PATTERN (insn), insn); 8859 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 8860 { 8861 if (REG_NOTE_KIND (note) == REG_INC 8862 && GET_CODE (XEXP (note, 0)) == REG) 8863 { 8864 int regno = REGNO (XEXP (note, 0)); 8865 8866 reg_state[regno].store_ruid = reload_combine_ruid; 8867 reg_state[regno].use_index = -1; 8868 } 8869 } 8870 } 8871 8872 free (label_live); 8873} 8874 8875/* Check if DST is a register or a subreg of a register; if it is, 8876 update reg_state[regno].store_ruid and reg_state[regno].use_index 8877 accordingly. Called via note_stores from reload_combine. */ 8878 8879static void 8880reload_combine_note_store (dst, set, data) 8881 rtx dst, set; 8882 void *data ATTRIBUTE_UNUSED; 8883{ 8884 int regno = 0; 8885 int i; 8886 enum machine_mode mode = GET_MODE (dst); 8887 8888 if (GET_CODE (dst) == SUBREG) 8889 { 8890 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), 8891 GET_MODE (SUBREG_REG (dst)), 8892 SUBREG_BYTE (dst), 8893 GET_MODE (dst)); 8894 dst = SUBREG_REG (dst); 8895 } 8896 if (GET_CODE (dst) != REG) 8897 return; 8898 regno += REGNO (dst); 8899 8900 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be 8901 careful with registers / register parts that are not full words. 8902 8903 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */ 8904 if (GET_CODE (set) != SET 8905 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT 8906 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT 8907 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) 8908 { 8909 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) 8910 { 8911 reg_state[i].use_index = -1; 8912 reg_state[i].store_ruid = reload_combine_ruid; 8913 } 8914 } 8915 else 8916 { 8917 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--) 8918 { 8919 reg_state[i].store_ruid = reload_combine_ruid; 8920 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; 8921 } 8922 } 8923} 8924 8925/* XP points to a piece of rtl that has to be checked for any uses of 8926 registers. 8927 *XP is the pattern of INSN, or a part of it. 8928 Called from reload_combine, and recursively by itself. */ 8929static void 8930reload_combine_note_use (xp, insn) 8931 rtx *xp, insn; 8932{ 8933 rtx x = *xp; 8934 enum rtx_code code = x->code; 8935 const char *fmt; 8936 int i, j; 8937 rtx offset = const0_rtx; /* For the REG case below. */ 8938 8939 switch (code) 8940 { 8941 case SET: 8942 if (GET_CODE (SET_DEST (x)) == REG) 8943 { 8944 reload_combine_note_use (&SET_SRC (x), insn); 8945 return; 8946 } 8947 break; 8948 8949 case USE: 8950 /* If this is the USE of a return value, we can't change it. */ 8951 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0))) 8952 { 8953 /* Mark the return register as used in an unknown fashion. */ 8954 rtx reg = XEXP (x, 0); 8955 int regno = REGNO (reg); 8956 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg)); 8957 8958 while (--nregs >= 0) 8959 reg_state[regno + nregs].use_index = -1; 8960 return; 8961 } 8962 break; 8963 8964 case CLOBBER: 8965 if (GET_CODE (SET_DEST (x)) == REG) 8966 { 8967 /* No spurious CLOBBERs of pseudo registers may remain. */ 8968 if (REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER) 8969 abort (); 8970 return; 8971 } 8972 break; 8973 8974 case PLUS: 8975 /* We are interested in (plus (reg) (const_int)) . */ 8976 if (GET_CODE (XEXP (x, 0)) != REG 8977 || GET_CODE (XEXP (x, 1)) != CONST_INT) 8978 break; 8979 offset = XEXP (x, 1); 8980 x = XEXP (x, 0); 8981 /* Fall through. */ 8982 case REG: 8983 { 8984 int regno = REGNO (x); 8985 int use_index; 8986 int nregs; 8987 8988 /* No spurious USEs of pseudo registers may remain. */ 8989 if (regno >= FIRST_PSEUDO_REGISTER) 8990 abort (); 8991 8992 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x)); 8993 8994 /* We can't substitute into multi-hard-reg uses. */ 8995 if (nregs > 1) 8996 { 8997 while (--nregs >= 0) 8998 reg_state[regno + nregs].use_index = -1; 8999 return; 9000 } 9001 9002 /* If this register is already used in some unknown fashion, we 9003 can't do anything. 9004 If we decrement the index from zero to -1, we can't store more 9005 uses, so this register becomes used in an unknown fashion. */ 9006 use_index = --reg_state[regno].use_index; 9007 if (use_index < 0) 9008 return; 9009 9010 if (use_index != RELOAD_COMBINE_MAX_USES - 1) 9011 { 9012 /* We have found another use for a register that is already 9013 used later. Check if the offsets match; if not, mark the 9014 register as used in an unknown fashion. */ 9015 if (! rtx_equal_p (offset, reg_state[regno].offset)) 9016 { 9017 reg_state[regno].use_index = -1; 9018 return; 9019 } 9020 } 9021 else 9022 { 9023 /* This is the first use of this register we have seen since we 9024 marked it as dead. */ 9025 reg_state[regno].offset = offset; 9026 reg_state[regno].use_ruid = reload_combine_ruid; 9027 } 9028 reg_state[regno].reg_use[use_index].insn = insn; 9029 reg_state[regno].reg_use[use_index].usep = xp; 9030 return; 9031 } 9032 9033 default: 9034 break; 9035 } 9036 9037 /* Recursively process the components of X. */ 9038 fmt = GET_RTX_FORMAT (code); 9039 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 9040 { 9041 if (fmt[i] == 'e') 9042 reload_combine_note_use (&XEXP (x, i), insn); 9043 else if (fmt[i] == 'E') 9044 { 9045 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 9046 reload_combine_note_use (&XVECEXP (x, i, j), insn); 9047 } 9048 } 9049} 9050 9051/* See if we can reduce the cost of a constant by replacing a move 9052 with an add. We track situations in which a register is set to a 9053 constant or to a register plus a constant. */ 9054/* We cannot do our optimization across labels. Invalidating all the 9055 information about register contents we have would be costly, so we 9056 use move2add_last_label_luid to note where the label is and then 9057 later disable any optimization that would cross it. 9058 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if 9059 reg_set_luid[n] is greater than last_label_luid[n] . */ 9060static int reg_set_luid[FIRST_PSEUDO_REGISTER]; 9061 9062/* If reg_base_reg[n] is negative, register n has been set to 9063 reg_offset[n] in mode reg_mode[n] . 9064 If reg_base_reg[n] is non-negative, register n has been set to the 9065 sum of reg_offset[n] and the value of register reg_base_reg[n] 9066 before reg_set_luid[n], calculated in mode reg_mode[n] . */ 9067static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; 9068static int reg_base_reg[FIRST_PSEUDO_REGISTER]; 9069static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; 9070 9071/* move2add_luid is linearily increased while scanning the instructions 9072 from first to last. It is used to set reg_set_luid in 9073 reload_cse_move2add and move2add_note_store. */ 9074static int move2add_luid; 9075 9076/* move2add_last_label_luid is set whenever a label is found. Labels 9077 invalidate all previously collected reg_offset data. */ 9078static int move2add_last_label_luid; 9079 9080/* Generate a CONST_INT and force it in the range of MODE. */ 9081 9082static HOST_WIDE_INT 9083sext_for_mode (mode, value) 9084 enum machine_mode mode; 9085 HOST_WIDE_INT value; 9086{ 9087 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode); 9088 int width = GET_MODE_BITSIZE (mode); 9089 9090 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number, 9091 sign extend it. */ 9092 if (width > 0 && width < HOST_BITS_PER_WIDE_INT 9093 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0) 9094 cval |= (HOST_WIDE_INT) -1 << width; 9095 9096 return cval; 9097} 9098 9099/* ??? We don't know how zero / sign extension is handled, hence we 9100 can't go from a narrower to a wider mode. */ 9101#define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ 9102 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ 9103 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ 9104 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \ 9105 GET_MODE_BITSIZE (INMODE)))) 9106 9107static void 9108reload_cse_move2add (first) 9109 rtx first; 9110{ 9111 int i; 9112 rtx insn; 9113 9114 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) 9115 reg_set_luid[i] = 0; 9116 9117 move2add_last_label_luid = 0; 9118 move2add_luid = 2; 9119 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) 9120 { 9121 rtx pat, note; 9122 9123 if (GET_CODE (insn) == CODE_LABEL) 9124 { 9125 move2add_last_label_luid = move2add_luid; 9126 /* We're going to increment move2add_luid twice after a 9127 label, so that we can use move2add_last_label_luid + 1 as 9128 the luid for constants. */ 9129 move2add_luid++; 9130 continue; 9131 } 9132 if (! INSN_P (insn)) 9133 continue; 9134 pat = PATTERN (insn); 9135 /* For simplicity, we only perform this optimization on 9136 straightforward SETs. */ 9137 if (GET_CODE (pat) == SET 9138 && GET_CODE (SET_DEST (pat)) == REG) 9139 { 9140 rtx reg = SET_DEST (pat); 9141 int regno = REGNO (reg); 9142 rtx src = SET_SRC (pat); 9143 9144 /* Check if we have valid information on the contents of this 9145 register in the mode of REG. */ 9146 if (reg_set_luid[regno] > move2add_last_label_luid 9147 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno])) 9148 { 9149 /* Try to transform (set (REGX) (CONST_INT A)) 9150 ... 9151 (set (REGX) (CONST_INT B)) 9152 to 9153 (set (REGX) (CONST_INT A)) 9154 ... 9155 (set (REGX) (plus (REGX) (CONST_INT B-A))) */ 9156 9157 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0) 9158 { 9159 int success = 0; 9160 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg), 9161 INTVAL (src) 9162 - reg_offset[regno])); 9163 /* (set (reg) (plus (reg) (const_int 0))) is not canonical; 9164 use (set (reg) (reg)) instead. 9165 We don't delete this insn, nor do we convert it into a 9166 note, to avoid losing register notes or the return 9167 value flag. jump2 already knowns how to get rid of 9168 no-op moves. */ 9169 if (new_src == const0_rtx) 9170 success = validate_change (insn, &SET_SRC (pat), reg, 0); 9171 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET) 9172 && have_add2_insn (reg, new_src)) 9173 success = validate_change (insn, &PATTERN (insn), 9174 gen_add2_insn (reg, new_src), 0); 9175 reg_set_luid[regno] = move2add_luid; 9176 reg_mode[regno] = GET_MODE (reg); 9177 reg_offset[regno] = INTVAL (src); 9178 continue; 9179 } 9180 9181 /* Try to transform (set (REGX) (REGY)) 9182 (set (REGX) (PLUS (REGX) (CONST_INT A))) 9183 ... 9184 (set (REGX) (REGY)) 9185 (set (REGX) (PLUS (REGX) (CONST_INT B))) 9186 to 9187 (REGX) (REGY)) 9188 (set (REGX) (PLUS (REGX) (CONST_INT A))) 9189 ... 9190 (set (REGX) (plus (REGX) (CONST_INT B-A))) */ 9191 else if (GET_CODE (src) == REG 9192 && reg_set_luid[regno] == reg_set_luid[REGNO (src)] 9193 && reg_base_reg[regno] == reg_base_reg[REGNO (src)] 9194 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), 9195 reg_mode[REGNO (src)])) 9196 { 9197 rtx next = next_nonnote_insn (insn); 9198 rtx set = NULL_RTX; 9199 if (next) 9200 set = single_set (next); 9201 if (set 9202 && SET_DEST (set) == reg 9203 && GET_CODE (SET_SRC (set)) == PLUS 9204 && XEXP (SET_SRC (set), 0) == reg 9205 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT) 9206 { 9207 rtx src3 = XEXP (SET_SRC (set), 1); 9208 HOST_WIDE_INT added_offset = INTVAL (src3); 9209 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; 9210 HOST_WIDE_INT regno_offset = reg_offset[regno]; 9211 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg), 9212 added_offset 9213 + base_offset 9214 - regno_offset)); 9215 int success = 0; 9216 9217 if (new_src == const0_rtx) 9218 /* See above why we create (set (reg) (reg)) here. */ 9219 success 9220 = validate_change (next, &SET_SRC (set), reg, 0); 9221 else if ((rtx_cost (new_src, PLUS) 9222 < COSTS_N_INSNS (1) + rtx_cost (src3, SET)) 9223 && have_add2_insn (reg, new_src)) 9224 success 9225 = validate_change (next, &PATTERN (next), 9226 gen_add2_insn (reg, new_src), 0); 9227 if (success) 9228 delete_insn (insn); 9229 insn = next; 9230 reg_mode[regno] = GET_MODE (reg); 9231 reg_offset[regno] = sext_for_mode (GET_MODE (reg), 9232 added_offset 9233 + base_offset); 9234 continue; 9235 } 9236 } 9237 } 9238 } 9239 9240 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 9241 { 9242 if (REG_NOTE_KIND (note) == REG_INC 9243 && GET_CODE (XEXP (note, 0)) == REG) 9244 { 9245 /* Reset the information about this register. */ 9246 int regno = REGNO (XEXP (note, 0)); 9247 if (regno < FIRST_PSEUDO_REGISTER) 9248 reg_set_luid[regno] = 0; 9249 } 9250 } 9251 note_stores (PATTERN (insn), move2add_note_store, NULL); 9252 /* If this is a CALL_INSN, all call used registers are stored with 9253 unknown values. */ 9254 if (GET_CODE (insn) == CALL_INSN) 9255 { 9256 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) 9257 { 9258 if (call_used_regs[i]) 9259 /* Reset the information about this register. */ 9260 reg_set_luid[i] = 0; 9261 } 9262 } 9263 } 9264} 9265 9266/* SET is a SET or CLOBBER that sets DST. 9267 Update reg_set_luid, reg_offset and reg_base_reg accordingly. 9268 Called from reload_cse_move2add via note_stores. */ 9269 9270static void 9271move2add_note_store (dst, set, data) 9272 rtx dst, set; 9273 void *data ATTRIBUTE_UNUSED; 9274{ 9275 unsigned int regno = 0; 9276 unsigned int i; 9277 enum machine_mode mode = GET_MODE (dst); 9278 9279 if (GET_CODE (dst) == SUBREG) 9280 { 9281 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), 9282 GET_MODE (SUBREG_REG (dst)), 9283 SUBREG_BYTE (dst), 9284 GET_MODE (dst)); 9285 dst = SUBREG_REG (dst); 9286 } 9287 9288 /* Some targets do argument pushes without adding REG_INC notes. */ 9289 9290 if (GET_CODE (dst) == MEM) 9291 { 9292 dst = XEXP (dst, 0); 9293 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC 9294 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) 9295 reg_set_luid[REGNO (XEXP (dst, 0))] = 0; 9296 return; 9297 } 9298 if (GET_CODE (dst) != REG) 9299 return; 9300 9301 regno += REGNO (dst); 9302 9303 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET 9304 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT 9305 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT 9306 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) 9307 { 9308 rtx src = SET_SRC (set); 9309 rtx base_reg; 9310 HOST_WIDE_INT offset; 9311 int base_regno; 9312 /* This may be different from mode, if SET_DEST (set) is a 9313 SUBREG. */ 9314 enum machine_mode dst_mode = GET_MODE (dst); 9315 9316 switch (GET_CODE (src)) 9317 { 9318 case PLUS: 9319 if (GET_CODE (XEXP (src, 0)) == REG) 9320 { 9321 base_reg = XEXP (src, 0); 9322 9323 if (GET_CODE (XEXP (src, 1)) == CONST_INT) 9324 offset = INTVAL (XEXP (src, 1)); 9325 else if (GET_CODE (XEXP (src, 1)) == REG 9326 && (reg_set_luid[REGNO (XEXP (src, 1))] 9327 > move2add_last_label_luid) 9328 && (MODES_OK_FOR_MOVE2ADD 9329 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))) 9330 { 9331 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0) 9332 offset = reg_offset[REGNO (XEXP (src, 1))]; 9333 /* Maybe the first register is known to be a 9334 constant. */ 9335 else if (reg_set_luid[REGNO (base_reg)] 9336 > move2add_last_label_luid 9337 && (MODES_OK_FOR_MOVE2ADD 9338 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])) 9339 && reg_base_reg[REGNO (base_reg)] < 0) 9340 { 9341 offset = reg_offset[REGNO (base_reg)]; 9342 base_reg = XEXP (src, 1); 9343 } 9344 else 9345 goto invalidate; 9346 } 9347 else 9348 goto invalidate; 9349 9350 break; 9351 } 9352 9353 goto invalidate; 9354 9355 case REG: 9356 base_reg = src; 9357 offset = 0; 9358 break; 9359 9360 case CONST_INT: 9361 /* Start tracking the register as a constant. */ 9362 reg_base_reg[regno] = -1; 9363 reg_offset[regno] = INTVAL (SET_SRC (set)); 9364 /* We assign the same luid to all registers set to constants. */ 9365 reg_set_luid[regno] = move2add_last_label_luid + 1; 9366 reg_mode[regno] = mode; 9367 return; 9368 9369 default: 9370 invalidate: 9371 /* Invalidate the contents of the register. */ 9372 reg_set_luid[regno] = 0; 9373 return; 9374 } 9375 9376 base_regno = REGNO (base_reg); 9377 /* If information about the base register is not valid, set it 9378 up as a new base register, pretending its value is known 9379 starting from the current insn. */ 9380 if (reg_set_luid[base_regno] <= move2add_last_label_luid) 9381 { 9382 reg_base_reg[base_regno] = base_regno; 9383 reg_offset[base_regno] = 0; 9384 reg_set_luid[base_regno] = move2add_luid; 9385 reg_mode[base_regno] = mode; 9386 } 9387 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode, 9388 reg_mode[base_regno])) 9389 goto invalidate; 9390 9391 reg_mode[regno] = mode; 9392 9393 /* Copy base information from our base register. */ 9394 reg_set_luid[regno] = reg_set_luid[base_regno]; 9395 reg_base_reg[regno] = reg_base_reg[base_regno]; 9396 9397 /* Compute the sum of the offsets or constants. */ 9398 reg_offset[regno] = sext_for_mode (dst_mode, 9399 offset 9400 + reg_offset[base_regno]); 9401 } 9402 else 9403 { 9404 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode); 9405 9406 for (i = regno; i < endregno; i++) 9407 /* Reset the information about this register. */ 9408 reg_set_luid[i] = 0; 9409 } 9410} 9411 9412#ifdef AUTO_INC_DEC 9413static void 9414add_auto_inc_notes (insn, x) 9415 rtx insn; 9416 rtx x; 9417{ 9418 enum rtx_code code = GET_CODE (x); 9419 const char *fmt; 9420 int i, j; 9421 9422 if (code == MEM && auto_inc_p (XEXP (x, 0))) 9423 { 9424 REG_NOTES (insn) 9425 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn)); 9426 return; 9427 } 9428 9429 /* Scan all the operand sub-expressions. */ 9430 fmt = GET_RTX_FORMAT (code); 9431 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 9432 { 9433 if (fmt[i] == 'e') 9434 add_auto_inc_notes (insn, XEXP (x, i)); 9435 else if (fmt[i] == 'E') 9436 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 9437 add_auto_inc_notes (insn, XVECEXP (x, i, j)); 9438 } 9439} 9440#endif 9441 9442/* Copy EH notes from an insn to its reloads. */ 9443static void 9444copy_eh_notes (insn, x) 9445 rtx insn; 9446 rtx x; 9447{ 9448 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); 9449 if (eh_note) 9450 { 9451 for (; x != 0; x = NEXT_INSN (x)) 9452 { 9453 if (may_trap_p (PATTERN (x))) 9454 REG_NOTES (x) 9455 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0), 9456 REG_NOTES (x)); 9457 } 9458 } 9459} 9460 9461/* This is used by reload pass, that does emit some instructions after 9462 abnormal calls moving basic block end, but in fact it wants to emit 9463 them on the edge. Looks for abnormal call edges, find backward the 9464 proper call and fix the damage. 9465 9466 Similar handle instructions throwing exceptions internally. */ 9467void 9468fixup_abnormal_edges () 9469{ 9470 bool inserted = false; 9471 basic_block bb; 9472 9473 FOR_EACH_BB (bb) 9474 { 9475 edge e; 9476 9477 /* Look for cases we are interested in - calls or instructions causing 9478 exceptions. */ 9479 for (e = bb->succ; e; e = e->succ_next) 9480 { 9481 if (e->flags & EDGE_ABNORMAL_CALL) 9482 break; 9483 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH)) 9484 == (EDGE_ABNORMAL | EDGE_EH)) 9485 break; 9486 } 9487 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end)) 9488 { 9489 rtx insn = bb->end, stop = NEXT_INSN (bb->end); 9490 rtx next; 9491 for (e = bb->succ; e; e = e->succ_next) 9492 if (e->flags & EDGE_FALLTHRU) 9493 break; 9494 /* Get past the new insns generated. Allow notes, as the insns may 9495 be already deleted. */ 9496 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE) 9497 && !can_throw_internal (insn) 9498 && insn != bb->head) 9499 insn = PREV_INSN (insn); 9500 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn)) 9501 abort (); 9502 bb->end = insn; 9503 inserted = true; 9504 insn = NEXT_INSN (insn); 9505 while (insn && insn != stop) 9506 { 9507 next = NEXT_INSN (insn); 9508 if (INSN_P (insn)) 9509 { 9510 delete_insn (insn); 9511 9512 /* Sometimes there's still the return value USE. 9513 If it's placed after a trapping call (i.e. that 9514 call is the last insn anyway), we have no fallthru 9515 edge. Simply delete this use and don't try to insert 9516 on the non-existant edge. */ 9517 if (GET_CODE (PATTERN (insn)) != USE) 9518 { 9519 /* We're not deleting it, we're moving it. */ 9520 INSN_DELETED_P (insn) = 0; 9521 PREV_INSN (insn) = NULL_RTX; 9522 NEXT_INSN (insn) = NULL_RTX; 9523 9524 insert_insn_on_edge (insn, e); 9525 } 9526 } 9527 insn = next; 9528 } 9529 } 9530 } 9531 if (inserted) 9532 commit_edge_insertions (); 9533} 9534