1132718Skan;; Pipeline description for Motorola PowerPC 8540 processor. 2169689Skan;; Copyright (C) 2003, 2004 Free Software Foundation, Inc. 3132718Skan;; 4132718Skan;; This file is part of GCC. 5132718Skan 6132718Skan;; GCC is free software; you can redistribute it and/or modify it 7132718Skan;; under the terms of the GNU General Public License as published 8132718Skan;; by the Free Software Foundation; either version 2, or (at your 9132718Skan;; option) any later version. 10132718Skan 11132718Skan;; GCC is distributed in the hope that it will be useful, but WITHOUT 12132718Skan;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13132718Skan;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14132718Skan;; License for more details. 15132718Skan 16132718Skan;; You should have received a copy of the GNU General Public License 17132718Skan;; along with GCC; see the file COPYING. If not, write to the 18169689Skan;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 19169689Skan;; MA 02110-1301, USA. 20132718Skan 21132718Skan(define_automaton "ppc8540_most,ppc8540_long,ppc8540_retire") 22132718Skan(define_cpu_unit "ppc8540_decode_0,ppc8540_decode_1" "ppc8540_most") 23132718Skan 24132718Skan;; We don't simulate general issue queue (GIC). If we have SU insn 25169689Skan;; and then SU1 insn, they cannot be issued on the same cycle 26132718Skan;; (although SU1 insn and then SU insn can be issued) because the SU 27132718Skan;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle 28132718Skan;; multipass insn scheduling will find the situation and issue the SU1 29132718Skan;; insn and then the SU insn. 30132718Skan(define_cpu_unit "ppc8540_issue_0,ppc8540_issue_1" "ppc8540_most") 31132718Skan 32132718Skan;; We could describe completion buffers slots in combination with the 33132718Skan;; retirement units and the order of completion but the result 34169689Skan;; automaton would behave in the same way because we cannot describe 35132718Skan;; real latency time with taking in order completion into account. 36132718Skan;; Actually we could define the real latency time by querying reserved 37132718Skan;; automaton units but the current scheduler uses latency time before 38132718Skan;; issuing insns and making any reservations. 39132718Skan;; 40132718Skan;; So our description is aimed to achieve a insn schedule in which the 41132718Skan;; insns would not wait in the completion buffer. 42132718Skan(define_cpu_unit "ppc8540_retire_0,ppc8540_retire_1" "ppc8540_retire") 43132718Skan 44132718Skan;; Branch unit: 45132718Skan(define_cpu_unit "ppc8540_bu" "ppc8540_most") 46132718Skan 47132718Skan;; SU: 48132718Skan(define_cpu_unit "ppc8540_su0_stage0,ppc8540_su1_stage0" "ppc8540_most") 49132718Skan 50132718Skan;; We could describe here MU subunits for float multiply, float add 51132718Skan;; etc. But the result automaton would behave the same way as the 52132718Skan;; described one pipeline below because MU can start only one insn 53132718Skan;; per cycle. Actually we could simplify the automaton more not 54132718Skan;; describing stages 1-3, the result automata would be the same. 55132718Skan(define_cpu_unit "ppc8540_mu_stage0,ppc8540_mu_stage1" "ppc8540_most") 56132718Skan(define_cpu_unit "ppc8540_mu_stage2,ppc8540_mu_stage3" "ppc8540_most") 57132718Skan 58132718Skan;; The following unit is used to describe non-pipelined division. 59132718Skan(define_cpu_unit "ppc8540_mu_div" "ppc8540_long") 60132718Skan 61132718Skan;; Here we simplified LSU unit description not describing the stages. 62132718Skan(define_cpu_unit "ppc8540_lsu" "ppc8540_most") 63132718Skan 64132718Skan;; The following units are used to make automata deterministic 65132718Skan(define_cpu_unit "present_ppc8540_decode_0" "ppc8540_most") 66132718Skan(define_cpu_unit "present_ppc8540_issue_0" "ppc8540_most") 67132718Skan(define_cpu_unit "present_ppc8540_retire_0" "ppc8540_retire") 68132718Skan(define_cpu_unit "present_ppc8540_su0_stage0" "ppc8540_most") 69132718Skan 70132718Skan;; The following sets to make automata deterministic when option ndfa is used. 71132718Skan(presence_set "present_ppc8540_decode_0" "ppc8540_decode_0") 72132718Skan(presence_set "present_ppc8540_issue_0" "ppc8540_issue_0") 73132718Skan(presence_set "present_ppc8540_retire_0" "ppc8540_retire_0") 74132718Skan(presence_set "present_ppc8540_su0_stage0" "ppc8540_su0_stage0") 75132718Skan 76132718Skan;; Some useful abbreviations. 77132718Skan(define_reservation "ppc8540_decode" 78132718Skan "ppc8540_decode_0|ppc8540_decode_1+present_ppc8540_decode_0") 79132718Skan(define_reservation "ppc8540_issue" 80132718Skan "ppc8540_issue_0|ppc8540_issue_1+present_ppc8540_issue_0") 81132718Skan(define_reservation "ppc8540_retire" 82132718Skan "ppc8540_retire_0|ppc8540_retire_1+present_ppc8540_retire_0") 83132718Skan(define_reservation "ppc8540_su_stage0" 84132718Skan "ppc8540_su0_stage0|ppc8540_su1_stage0+present_ppc8540_su0_stage0") 85132718Skan 86132718Skan;; Simple SU insns 87132718Skan(define_insn_reservation "ppc8540_su" 1 88132718Skan (and (eq_attr "type" "integer,insert_word,cmp,compare,delayed_compare,fast_compare") 89132718Skan (eq_attr "cpu" "ppc8540")) 90132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") 91132718Skan 92169689Skan(define_insn_reservation "ppc8540_two" 1 93169689Skan (and (eq_attr "type" "two") 94169689Skan (eq_attr "cpu" "ppc8540")) 95169689Skan "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\ 96169689Skan ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") 97169689Skan 98169689Skan(define_insn_reservation "ppc8540_three" 1 99169689Skan (and (eq_attr "type" "three") 100169689Skan (eq_attr "cpu" "ppc8540")) 101169689Skan "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\ 102169689Skan ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\ 103169689Skan ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") 104169689Skan 105132718Skan;; Branch. Actually this latency time is not used by the scheduler. 106132718Skan(define_insn_reservation "ppc8540_branch" 1 107169689Skan (and (eq_attr "type" "jmpreg,branch,isync") 108132718Skan (eq_attr "cpu" "ppc8540")) 109132718Skan "ppc8540_decode,ppc8540_bu,ppc8540_retire") 110132718Skan 111132718Skan;; Multiply 112132718Skan(define_insn_reservation "ppc8540_multiply" 4 113132718Skan (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 114132718Skan (eq_attr "cpu" "ppc8540")) 115132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ 116132718Skan ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") 117132718Skan 118132718Skan;; Divide. We use the average latency time here. We omit reserving a 119132718Skan;; retire unit because of the result automata will be huge. We ignore 120132718Skan;; reservation of miu_stage3 here because we use the average latency 121132718Skan;; time. 122132718Skan(define_insn_reservation "ppc8540_divide" 14 123132718Skan (and (eq_attr "type" "idiv") 124132718Skan (eq_attr "cpu" "ppc8540")) 125132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\ 126132718Skan ppc8540_mu_div*13") 127132718Skan 128132718Skan;; CR logical 129132718Skan(define_insn_reservation "ppc8540_cr_logical" 1 130132718Skan (and (eq_attr "type" "cr_logical,delayed_cr") 131132718Skan (eq_attr "cpu" "ppc8540")) 132132718Skan "ppc8540_decode,ppc8540_bu,ppc8540_retire") 133132718Skan 134132718Skan;; Mfcr 135132718Skan(define_insn_reservation "ppc8540_mfcr" 1 136132718Skan (and (eq_attr "type" "mfcr") 137132718Skan (eq_attr "cpu" "ppc8540")) 138132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") 139132718Skan 140132718Skan;; Mtcrf 141132718Skan(define_insn_reservation "ppc8540_mtcrf" 1 142132718Skan (and (eq_attr "type" "mtcr") 143132718Skan (eq_attr "cpu" "ppc8540")) 144132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") 145132718Skan 146132718Skan;; Mtjmpr 147132718Skan(define_insn_reservation "ppc8540_mtjmpr" 1 148132718Skan (and (eq_attr "type" "mtjmpr,mfjmpr") 149132718Skan (eq_attr "cpu" "ppc8540")) 150132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") 151132718Skan 152132718Skan;; Loads 153132718Skan(define_insn_reservation "ppc8540_load" 3 154169689Skan (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ 155169689Skan load_l,sync") 156132718Skan (eq_attr "cpu" "ppc8540")) 157132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") 158132718Skan 159132718Skan;; Stores. 160132718Skan(define_insn_reservation "ppc8540_store" 3 161169689Skan (and (eq_attr "type" "store,store_ux,store_u,store_c") 162132718Skan (eq_attr "cpu" "ppc8540")) 163132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") 164132718Skan 165132718Skan;; Simple FP 166132718Skan(define_insn_reservation "ppc8540_simple_float" 1 167132718Skan (and (eq_attr "type" "fpsimple") 168132718Skan (eq_attr "cpu" "ppc8540")) 169132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") 170132718Skan 171132718Skan;; FP 172132718Skan(define_insn_reservation "ppc8540_float" 4 173132718Skan (and (eq_attr "type" "fp") 174132718Skan (eq_attr "cpu" "ppc8540")) 175132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ 176132718Skan ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") 177132718Skan 178132718Skan;; float divides. We omit reserving a retire unit and miu_stage3 179132718Skan;; because of the result automata will be huge. 180132718Skan(define_insn_reservation "ppc8540_float_vector_divide" 29 181132718Skan (and (eq_attr "type" "vecfdiv") 182132718Skan (eq_attr "cpu" "ppc8540")) 183132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\ 184132718Skan ppc8540_mu_div*28") 185132718Skan 186132718Skan;; Brinc 187132718Skan(define_insn_reservation "ppc8540_brinc" 1 188132718Skan (and (eq_attr "type" "brinc") 189132718Skan (eq_attr "cpu" "ppc8540")) 190132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") 191132718Skan 192132718Skan;; Simple vector 193132718Skan(define_insn_reservation "ppc8540_simple_vector" 1 194132718Skan (and (eq_attr "type" "vecsimple") 195132718Skan (eq_attr "cpu" "ppc8540")) 196132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") 197132718Skan 198132718Skan;; Simple vector compare 199132718Skan(define_insn_reservation "ppc8540_simple_vector_compare" 1 200132718Skan (and (eq_attr "type" "veccmpsimple") 201132718Skan (eq_attr "cpu" "ppc8540")) 202132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire") 203132718Skan 204132718Skan;; Vector compare 205132718Skan(define_insn_reservation "ppc8540_vector_compare" 1 206132718Skan (and (eq_attr "type" "veccmp") 207132718Skan (eq_attr "cpu" "ppc8540")) 208132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") 209132718Skan 210132718Skan;; evsplatfi evsplati 211132718Skan(define_insn_reservation "ppc8540_vector_perm" 1 212132718Skan (and (eq_attr "type" "vecperm") 213132718Skan (eq_attr "cpu" "ppc8540")) 214132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire") 215132718Skan 216132718Skan;; Vector float 217132718Skan(define_insn_reservation "ppc8540_float_vector" 4 218132718Skan (and (eq_attr "type" "vecfloat") 219132718Skan (eq_attr "cpu" "ppc8540")) 220132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ 221132718Skan ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") 222132718Skan 223132718Skan;; Vector divides: Use the average. We omit reserving a retire unit 224132718Skan;; because of the result automata will be huge. We ignore reservation 225132718Skan;; of miu_stage3 here because we use the average latency time. 226132718Skan(define_insn_reservation "ppc8540_vector_divide" 14 227132718Skan (and (eq_attr "type" "vecdiv") 228132718Skan (eq_attr "cpu" "ppc8540")) 229132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\ 230132718Skan ppc8540_mu_div*13") 231132718Skan 232132718Skan;; Complex vector. 233132718Skan(define_insn_reservation "ppc8540_complex_vector" 4 234132718Skan (and (eq_attr "type" "veccomplex") 235132718Skan (eq_attr "cpu" "ppc8540")) 236132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\ 237132718Skan ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire") 238132718Skan 239132718Skan;; Vector load 240132718Skan(define_insn_reservation "ppc8540_vector_load" 3 241132718Skan (and (eq_attr "type" "vecload") 242132718Skan (eq_attr "cpu" "ppc8540")) 243132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") 244132718Skan 245132718Skan;; Vector store 246132718Skan(define_insn_reservation "ppc8540_vector_store" 3 247132718Skan (and (eq_attr "type" "vecstore") 248132718Skan (eq_attr "cpu" "ppc8540")) 249132718Skan "ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire") 250