arm.c revision 169689
1/* Output routines for GCC for ARM. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. 4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 5 and Martin Simmons (@harleqn.co.uk). 6 More major hacks by Richard Earnshaw (rearnsha@arm.com). 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 2, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GCC; see the file COPYING. If not, write to 22 the Free Software Foundation, 51 Franklin Street, Fifth Floor, 23 Boston, MA 02110-1301, USA. */ 24 25#include "config.h" 26#include "system.h" 27#include "coretypes.h" 28#include "tm.h" 29#include "rtl.h" 30#include "tree.h" 31#include "obstack.h" 32#include "regs.h" 33#include "hard-reg-set.h" 34#include "real.h" 35#include "insn-config.h" 36#include "conditions.h" 37#include "output.h" 38#include "insn-attr.h" 39#include "flags.h" 40#include "reload.h" 41#include "function.h" 42#include "expr.h" 43#include "optabs.h" 44#include "toplev.h" 45#include "recog.h" 46#include "ggc.h" 47#include "except.h" 48#include "c-pragma.h" 49#include "integrate.h" 50#include "tm_p.h" 51#include "target.h" 52#include "target-def.h" 53#include "debug.h" 54#include "langhooks.h" 55 56/* Forward definitions of types. */ 57typedef struct minipool_node Mnode; 58typedef struct minipool_fixup Mfix; 59 60const struct attribute_spec arm_attribute_table[]; 61 62/* Forward function declarations. */ 63static arm_stack_offsets *arm_get_frame_offsets (void); 64static void arm_add_gc_roots (void); 65static int arm_gen_constant (enum rtx_code, enum machine_mode, rtx, 66 HOST_WIDE_INT, rtx, rtx, int, int); 67static unsigned bit_count (unsigned long); 68static int arm_address_register_rtx_p (rtx, int); 69static int arm_legitimate_index_p (enum machine_mode, rtx, RTX_CODE, int); 70static int thumb_base_register_rtx_p (rtx, enum machine_mode, int); 71inline static int thumb_index_register_rtx_p (rtx, int); 72static int thumb_far_jump_used_p (void); 73static bool thumb_force_lr_save (void); 74static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); 75static rtx emit_sfm (int, int); 76static int arm_size_return_regs (void); 77#ifndef AOF_ASSEMBLER 78static bool arm_assemble_integer (rtx, unsigned int, int); 79#endif 80static const char *fp_const_from_val (REAL_VALUE_TYPE *); 81static arm_cc get_arm_condition_code (rtx); 82static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); 83static rtx is_jump_table (rtx); 84static const char *output_multi_immediate (rtx *, const char *, const char *, 85 int, HOST_WIDE_INT); 86static const char *shift_op (rtx, HOST_WIDE_INT *); 87static struct machine_function *arm_init_machine_status (void); 88static void thumb_exit (FILE *, int); 89static rtx is_jump_table (rtx); 90static HOST_WIDE_INT get_jump_table_size (rtx); 91static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); 92static Mnode *add_minipool_forward_ref (Mfix *); 93static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT); 94static Mnode *add_minipool_backward_ref (Mfix *); 95static void assign_minipool_offsets (Mfix *); 96static void arm_print_value (FILE *, rtx); 97static void dump_minipool (rtx); 98static int arm_barrier_cost (rtx); 99static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT); 100static void push_minipool_barrier (rtx, HOST_WIDE_INT); 101static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode, 102 rtx); 103static void arm_reorg (void); 104static bool note_invalid_constants (rtx, HOST_WIDE_INT, int); 105static int current_file_function_operand (rtx); 106static unsigned long arm_compute_save_reg0_reg12_mask (void); 107static unsigned long arm_compute_save_reg_mask (void); 108static unsigned long arm_isr_value (tree); 109static unsigned long arm_compute_func_type (void); 110static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); 111static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); 112#if TARGET_DLLIMPORT_DECL_ATTRIBUTES 113static tree arm_handle_notshared_attribute (tree *, tree, tree, int, bool *); 114#endif 115static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); 116static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); 117static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT); 118static int arm_comp_type_attributes (tree, tree); 119static void arm_set_default_type_attributes (tree); 120static int arm_adjust_cost (rtx, rtx, rtx, int); 121static int count_insns_for_constant (HOST_WIDE_INT, int); 122static int arm_get_strip_length (int); 123static bool arm_function_ok_for_sibcall (tree, tree); 124static void arm_internal_label (FILE *, const char *, unsigned long); 125static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, 126 tree); 127static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code); 128static bool arm_size_rtx_costs (rtx, int, int, int *); 129static bool arm_slowmul_rtx_costs (rtx, int, int, int *); 130static bool arm_fastmul_rtx_costs (rtx, int, int, int *); 131static bool arm_xscale_rtx_costs (rtx, int, int, int *); 132static bool arm_9e_rtx_costs (rtx, int, int, int *); 133static int arm_address_cost (rtx); 134static bool arm_memory_load_p (rtx); 135static bool arm_cirrus_insn_p (rtx); 136static void cirrus_reorg (rtx); 137static void arm_init_builtins (void); 138static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); 139static void arm_init_iwmmxt_builtins (void); 140static rtx safe_vector_operand (rtx, enum machine_mode); 141static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); 142static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); 143static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); 144static void emit_constant_insn (rtx cond, rtx pattern); 145static rtx emit_set_insn (rtx, rtx); 146static int arm_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode, 147 tree, bool); 148 149#ifdef OBJECT_FORMAT_ELF 150static void arm_elf_asm_constructor (rtx, int); 151#endif 152#ifndef ARM_PE 153static void arm_encode_section_info (tree, rtx, int); 154#endif 155 156static void arm_file_end (void); 157 158#ifdef AOF_ASSEMBLER 159static void aof_globalize_label (FILE *, const char *); 160static void aof_dump_imports (FILE *); 161static void aof_dump_pic_table (FILE *); 162static void aof_file_start (void); 163static void aof_file_end (void); 164static void aof_asm_init_sections (void); 165#endif 166static void arm_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, 167 tree, int *, int); 168static bool arm_pass_by_reference (CUMULATIVE_ARGS *, 169 enum machine_mode, tree, bool); 170static bool arm_promote_prototypes (tree); 171static bool arm_default_short_enums (void); 172static bool arm_align_anon_bitfield (void); 173static bool arm_return_in_msb (tree); 174static bool arm_must_pass_in_stack (enum machine_mode, tree); 175#ifdef TARGET_UNWIND_INFO 176static void arm_unwind_emit (FILE *, rtx); 177static bool arm_output_ttype (rtx); 178#endif 179 180static tree arm_cxx_guard_type (void); 181static bool arm_cxx_guard_mask_bit (void); 182static tree arm_get_cookie_size (tree); 183static bool arm_cookie_has_size (void); 184static bool arm_cxx_cdtor_returns_this (void); 185static bool arm_cxx_key_method_may_be_inline (void); 186static void arm_cxx_determine_class_data_visibility (tree); 187static bool arm_cxx_class_data_always_comdat (void); 188static bool arm_cxx_use_aeabi_atexit (void); 189static void arm_init_libfuncs (void); 190static bool arm_handle_option (size_t, const char *, int); 191static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode); 192static bool arm_cannot_copy_insn_p (rtx); 193static bool arm_tls_symbol_p (rtx x); 194 195 196/* Initialize the GCC target structure. */ 197#if TARGET_DLLIMPORT_DECL_ATTRIBUTES 198#undef TARGET_MERGE_DECL_ATTRIBUTES 199#define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes 200#endif 201 202#undef TARGET_ATTRIBUTE_TABLE 203#define TARGET_ATTRIBUTE_TABLE arm_attribute_table 204 205#undef TARGET_ASM_FILE_END 206#define TARGET_ASM_FILE_END arm_file_end 207 208#ifdef AOF_ASSEMBLER 209#undef TARGET_ASM_BYTE_OP 210#define TARGET_ASM_BYTE_OP "\tDCB\t" 211#undef TARGET_ASM_ALIGNED_HI_OP 212#define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t" 213#undef TARGET_ASM_ALIGNED_SI_OP 214#define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t" 215#undef TARGET_ASM_GLOBALIZE_LABEL 216#define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label 217#undef TARGET_ASM_FILE_START 218#define TARGET_ASM_FILE_START aof_file_start 219#undef TARGET_ASM_FILE_END 220#define TARGET_ASM_FILE_END aof_file_end 221#else 222#undef TARGET_ASM_ALIGNED_SI_OP 223#define TARGET_ASM_ALIGNED_SI_OP NULL 224#undef TARGET_ASM_INTEGER 225#define TARGET_ASM_INTEGER arm_assemble_integer 226#endif 227 228#undef TARGET_ASM_FUNCTION_PROLOGUE 229#define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue 230 231#undef TARGET_ASM_FUNCTION_EPILOGUE 232#define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue 233 234#undef TARGET_DEFAULT_TARGET_FLAGS 235#define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | MASK_SCHED_PROLOG) 236#undef TARGET_HANDLE_OPTION 237#define TARGET_HANDLE_OPTION arm_handle_option 238 239#undef TARGET_COMP_TYPE_ATTRIBUTES 240#define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes 241 242#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES 243#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes 244 245#undef TARGET_SCHED_ADJUST_COST 246#define TARGET_SCHED_ADJUST_COST arm_adjust_cost 247 248#undef TARGET_ENCODE_SECTION_INFO 249#ifdef ARM_PE 250#define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info 251#else 252#define TARGET_ENCODE_SECTION_INFO arm_encode_section_info 253#endif 254 255#undef TARGET_STRIP_NAME_ENCODING 256#define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding 257 258#undef TARGET_ASM_INTERNAL_LABEL 259#define TARGET_ASM_INTERNAL_LABEL arm_internal_label 260 261#undef TARGET_FUNCTION_OK_FOR_SIBCALL 262#define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall 263 264#undef TARGET_ASM_OUTPUT_MI_THUNK 265#define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk 266#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 267#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall 268 269/* This will be overridden in arm_override_options. */ 270#undef TARGET_RTX_COSTS 271#define TARGET_RTX_COSTS arm_slowmul_rtx_costs 272#undef TARGET_ADDRESS_COST 273#define TARGET_ADDRESS_COST arm_address_cost 274 275#undef TARGET_SHIFT_TRUNCATION_MASK 276#define TARGET_SHIFT_TRUNCATION_MASK arm_shift_truncation_mask 277#undef TARGET_VECTOR_MODE_SUPPORTED_P 278#define TARGET_VECTOR_MODE_SUPPORTED_P arm_vector_mode_supported_p 279 280#undef TARGET_MACHINE_DEPENDENT_REORG 281#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg 282 283#undef TARGET_INIT_BUILTINS 284#define TARGET_INIT_BUILTINS arm_init_builtins 285#undef TARGET_EXPAND_BUILTIN 286#define TARGET_EXPAND_BUILTIN arm_expand_builtin 287 288#undef TARGET_INIT_LIBFUNCS 289#define TARGET_INIT_LIBFUNCS arm_init_libfuncs 290 291#undef TARGET_PROMOTE_FUNCTION_ARGS 292#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true 293#undef TARGET_PROMOTE_FUNCTION_RETURN 294#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true 295#undef TARGET_PROMOTE_PROTOTYPES 296#define TARGET_PROMOTE_PROTOTYPES arm_promote_prototypes 297#undef TARGET_PASS_BY_REFERENCE 298#define TARGET_PASS_BY_REFERENCE arm_pass_by_reference 299#undef TARGET_ARG_PARTIAL_BYTES 300#define TARGET_ARG_PARTIAL_BYTES arm_arg_partial_bytes 301 302#undef TARGET_SETUP_INCOMING_VARARGS 303#define TARGET_SETUP_INCOMING_VARARGS arm_setup_incoming_varargs 304 305#undef TARGET_DEFAULT_SHORT_ENUMS 306#define TARGET_DEFAULT_SHORT_ENUMS arm_default_short_enums 307 308#undef TARGET_ALIGN_ANON_BITFIELD 309#define TARGET_ALIGN_ANON_BITFIELD arm_align_anon_bitfield 310 311#undef TARGET_NARROW_VOLATILE_BITFIELD 312#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false 313 314#undef TARGET_CXX_GUARD_TYPE 315#define TARGET_CXX_GUARD_TYPE arm_cxx_guard_type 316 317#undef TARGET_CXX_GUARD_MASK_BIT 318#define TARGET_CXX_GUARD_MASK_BIT arm_cxx_guard_mask_bit 319 320#undef TARGET_CXX_GET_COOKIE_SIZE 321#define TARGET_CXX_GET_COOKIE_SIZE arm_get_cookie_size 322 323#undef TARGET_CXX_COOKIE_HAS_SIZE 324#define TARGET_CXX_COOKIE_HAS_SIZE arm_cookie_has_size 325 326#undef TARGET_CXX_CDTOR_RETURNS_THIS 327#define TARGET_CXX_CDTOR_RETURNS_THIS arm_cxx_cdtor_returns_this 328 329#undef TARGET_CXX_KEY_METHOD_MAY_BE_INLINE 330#define TARGET_CXX_KEY_METHOD_MAY_BE_INLINE arm_cxx_key_method_may_be_inline 331 332#undef TARGET_CXX_USE_AEABI_ATEXIT 333#define TARGET_CXX_USE_AEABI_ATEXIT arm_cxx_use_aeabi_atexit 334 335#undef TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY 336#define TARGET_CXX_DETERMINE_CLASS_DATA_VISIBILITY \ 337 arm_cxx_determine_class_data_visibility 338 339#undef TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT 340#define TARGET_CXX_CLASS_DATA_ALWAYS_COMDAT arm_cxx_class_data_always_comdat 341 342#undef TARGET_RETURN_IN_MSB 343#define TARGET_RETURN_IN_MSB arm_return_in_msb 344 345#undef TARGET_MUST_PASS_IN_STACK 346#define TARGET_MUST_PASS_IN_STACK arm_must_pass_in_stack 347 348#ifdef TARGET_UNWIND_INFO 349#undef TARGET_UNWIND_EMIT 350#define TARGET_UNWIND_EMIT arm_unwind_emit 351 352/* EABI unwinding tables use a different format for the typeinfo tables. */ 353#undef TARGET_ASM_TTYPE 354#define TARGET_ASM_TTYPE arm_output_ttype 355 356#undef TARGET_ARM_EABI_UNWINDER 357#define TARGET_ARM_EABI_UNWINDER true 358#endif /* TARGET_UNWIND_INFO */ 359 360#undef TARGET_CANNOT_COPY_INSN_P 361#define TARGET_CANNOT_COPY_INSN_P arm_cannot_copy_insn_p 362 363#ifdef HAVE_AS_TLS 364#undef TARGET_HAVE_TLS 365#define TARGET_HAVE_TLS true 366#endif 367 368#undef TARGET_CANNOT_FORCE_CONST_MEM 369#define TARGET_CANNOT_FORCE_CONST_MEM arm_tls_referenced_p 370 371struct gcc_target targetm = TARGET_INITIALIZER; 372 373/* Obstack for minipool constant handling. */ 374static struct obstack minipool_obstack; 375static char * minipool_startobj; 376 377/* The maximum number of insns skipped which 378 will be conditionalised if possible. */ 379static int max_insns_skipped = 5; 380 381extern FILE * asm_out_file; 382 383/* True if we are currently building a constant table. */ 384int making_const_table; 385 386/* Define the information needed to generate branch insns. This is 387 stored from the compare operation. */ 388rtx arm_compare_op0, arm_compare_op1; 389 390/* The processor for which instructions should be scheduled. */ 391enum processor_type arm_tune = arm_none; 392 393/* Which floating point model to use. */ 394enum arm_fp_model arm_fp_model; 395 396/* Which floating point hardware is available. */ 397enum fputype arm_fpu_arch; 398 399/* Which floating point hardware to schedule for. */ 400enum fputype arm_fpu_tune; 401 402/* Whether to use floating point hardware. */ 403enum float_abi_type arm_float_abi; 404 405/* Which ABI to use. */ 406enum arm_abi_type arm_abi; 407 408/* Which thread pointer model to use. */ 409enum arm_tp_type target_thread_pointer = TP_AUTO; 410 411/* Used to parse -mstructure_size_boundary command line option. */ 412int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; 413 414/* Used for Thumb call_via trampolines. */ 415rtx thumb_call_via_label[14]; 416static int thumb_call_reg_needed; 417 418/* Bit values used to identify processor capabilities. */ 419#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ 420#define FL_ARCH3M (1 << 1) /* Extended multiply */ 421#define FL_MODE26 (1 << 2) /* 26-bit mode support */ 422#define FL_MODE32 (1 << 3) /* 32-bit mode support */ 423#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ 424#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ 425#define FL_THUMB (1 << 6) /* Thumb aware */ 426#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ 427#define FL_STRONG (1 << 8) /* StrongARM */ 428#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ 429#define FL_XSCALE (1 << 10) /* XScale */ 430#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ 431#define FL_ARCH6 (1 << 12) /* Architecture rel 6. Adds 432 media instructions. */ 433#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ 434#define FL_WBUF (1 << 14) /* Schedule for write buffer ops. 435 Note: ARM6 & 7 derivatives only. */ 436#define FL_ARCH6K (1 << 15) /* Architecture rel 6 K extensions. */ 437 438#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ 439 440#define FL_FOR_ARCH2 0 441#define FL_FOR_ARCH3 FL_MODE32 442#define FL_FOR_ARCH3M (FL_FOR_ARCH3 | FL_ARCH3M) 443#define FL_FOR_ARCH4 (FL_FOR_ARCH3M | FL_ARCH4) 444#define FL_FOR_ARCH4T (FL_FOR_ARCH4 | FL_THUMB) 445#define FL_FOR_ARCH5 (FL_FOR_ARCH4 | FL_ARCH5) 446#define FL_FOR_ARCH5T (FL_FOR_ARCH5 | FL_THUMB) 447#define FL_FOR_ARCH5E (FL_FOR_ARCH5 | FL_ARCH5E) 448#define FL_FOR_ARCH5TE (FL_FOR_ARCH5E | FL_THUMB) 449#define FL_FOR_ARCH5TEJ FL_FOR_ARCH5TE 450#define FL_FOR_ARCH6 (FL_FOR_ARCH5TE | FL_ARCH6) 451#define FL_FOR_ARCH6J FL_FOR_ARCH6 452#define FL_FOR_ARCH6K (FL_FOR_ARCH6 | FL_ARCH6K) 453#define FL_FOR_ARCH6Z FL_FOR_ARCH6 454#define FL_FOR_ARCH6ZK FL_FOR_ARCH6K 455 456/* The bits in this mask specify which 457 instructions we are allowed to generate. */ 458static unsigned long insn_flags = 0; 459 460/* The bits in this mask specify which instruction scheduling options should 461 be used. */ 462static unsigned long tune_flags = 0; 463 464/* The following are used in the arm.md file as equivalents to bits 465 in the above two flag variables. */ 466 467/* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 468int arm_arch3m = 0; 469 470/* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 471int arm_arch4 = 0; 472 473/* Nonzero if this chip supports the ARM Architecture 4t extensions. */ 474int arm_arch4t = 0; 475 476/* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 477int arm_arch5 = 0; 478 479/* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 480int arm_arch5e = 0; 481 482/* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 483int arm_arch6 = 0; 484 485/* Nonzero if this chip supports the ARM 6K extensions. */ 486int arm_arch6k = 0; 487 488/* Nonzero if this chip can benefit from load scheduling. */ 489int arm_ld_sched = 0; 490 491/* Nonzero if this chip is a StrongARM. */ 492int arm_tune_strongarm = 0; 493 494/* Nonzero if this chip is a Cirrus variant. */ 495int arm_arch_cirrus = 0; 496 497/* Nonzero if this chip supports Intel Wireless MMX technology. */ 498int arm_arch_iwmmxt = 0; 499 500/* Nonzero if this chip is an XScale. */ 501int arm_arch_xscale = 0; 502 503/* Nonzero if tuning for XScale */ 504int arm_tune_xscale = 0; 505 506/* Nonzero if we want to tune for stores that access the write-buffer. 507 This typically means an ARM6 or ARM7 with MMU or MPU. */ 508int arm_tune_wbuf = 0; 509 510/* Nonzero if generating Thumb instructions. */ 511int thumb_code = 0; 512 513/* Nonzero if we should define __THUMB_INTERWORK__ in the 514 preprocessor. 515 XXX This is a bit of a hack, it's intended to help work around 516 problems in GLD which doesn't understand that armv5t code is 517 interworking clean. */ 518int arm_cpp_interwork = 0; 519 520/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we 521 must report the mode of the memory reference from PRINT_OPERAND to 522 PRINT_OPERAND_ADDRESS. */ 523enum machine_mode output_memory_reference_mode; 524 525/* The register number to be used for the PIC offset register. */ 526unsigned arm_pic_register = INVALID_REGNUM; 527 528/* Set to 1 when a return insn is output, this means that the epilogue 529 is not needed. */ 530int return_used_this_function; 531 532/* Set to 1 after arm_reorg has started. Reset to start at the start of 533 the next function. */ 534static int after_arm_reorg = 0; 535 536/* The maximum number of insns to be used when loading a constant. */ 537static int arm_constant_limit = 3; 538 539/* For an explanation of these variables, see final_prescan_insn below. */ 540int arm_ccfsm_state; 541enum arm_cond_code arm_current_cc; 542rtx arm_target_insn; 543int arm_target_label; 544 545/* The condition codes of the ARM, and the inverse function. */ 546static const char * const arm_condition_codes[] = 547{ 548 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 549 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" 550}; 551 552#define streq(string1, string2) (strcmp (string1, string2) == 0) 553 554/* Initialization code. */ 555 556struct processors 557{ 558 const char *const name; 559 enum processor_type core; 560 const char *arch; 561 const unsigned long flags; 562 bool (* rtx_costs) (rtx, int, int, int *); 563}; 564 565/* Not all of these give usefully different compilation alternatives, 566 but there is no simple way of generalizing them. */ 567static const struct processors all_cores[] = 568{ 569 /* ARM Cores */ 570#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 571 {NAME, arm_none, #ARCH, FLAGS | FL_FOR_ARCH##ARCH, arm_##COSTS##_rtx_costs}, 572#include "arm-cores.def" 573#undef ARM_CORE 574 {NULL, arm_none, NULL, 0, NULL} 575}; 576 577static const struct processors all_architectures[] = 578{ 579 /* ARM Architectures */ 580 /* We don't specify rtx_costs here as it will be figured out 581 from the core. */ 582 583 {"armv2", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, 584 {"armv2a", arm2, "2", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH2, NULL}, 585 {"armv3", arm6, "3", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3, NULL}, 586 {"armv3m", arm7m, "3M", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH3M, NULL}, 587 {"armv4", arm7tdmi, "4", FL_CO_PROC | FL_MODE26 | FL_FOR_ARCH4, NULL}, 588 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no 589 implementations that support it, so we will leave it out for now. */ 590 {"armv4t", arm7tdmi, "4T", FL_CO_PROC | FL_FOR_ARCH4T, NULL}, 591 {"armv5", arm10tdmi, "5", FL_CO_PROC | FL_FOR_ARCH5, NULL}, 592 {"armv5t", arm10tdmi, "5T", FL_CO_PROC | FL_FOR_ARCH5T, NULL}, 593 {"armv5e", arm1026ejs, "5E", FL_CO_PROC | FL_FOR_ARCH5E, NULL}, 594 {"armv5te", arm1026ejs, "5TE", FL_CO_PROC | FL_FOR_ARCH5TE, NULL}, 595 {"armv6", arm1136js, "6", FL_CO_PROC | FL_FOR_ARCH6, NULL}, 596 {"armv6j", arm1136js, "6J", FL_CO_PROC | FL_FOR_ARCH6J, NULL}, 597 {"armv6k", mpcore, "6K", FL_CO_PROC | FL_FOR_ARCH6K, NULL}, 598 {"armv6z", arm1176jzs, "6Z", FL_CO_PROC | FL_FOR_ARCH6Z, NULL}, 599 {"armv6zk", arm1176jzs, "6ZK", FL_CO_PROC | FL_FOR_ARCH6ZK, NULL}, 600 {"ep9312", ep9312, "4T", FL_LDSCHED | FL_CIRRUS | FL_FOR_ARCH4, NULL}, 601 {"iwmmxt", iwmmxt, "5TE", FL_LDSCHED | FL_STRONG | FL_FOR_ARCH5TE | FL_XSCALE | FL_IWMMXT , NULL}, 602 {NULL, arm_none, NULL, 0 , NULL} 603}; 604 605struct arm_cpu_select 606{ 607 const char * string; 608 const char * name; 609 const struct processors * processors; 610}; 611 612/* This is a magic structure. The 'string' field is magically filled in 613 with a pointer to the value specified by the user on the command line 614 assuming that the user has specified such a value. */ 615 616static struct arm_cpu_select arm_select[] = 617{ 618 /* string name processors */ 619 { NULL, "-mcpu=", all_cores }, 620 { NULL, "-march=", all_architectures }, 621 { NULL, "-mtune=", all_cores } 622}; 623 624/* Defines representing the indexes into the above table. */ 625#define ARM_OPT_SET_CPU 0 626#define ARM_OPT_SET_ARCH 1 627#define ARM_OPT_SET_TUNE 2 628 629/* The name of the preprocessor macro to define for this architecture. */ 630 631char arm_arch_name[] = "__ARM_ARCH_0UNK__"; 632 633struct fpu_desc 634{ 635 const char * name; 636 enum fputype fpu; 637}; 638 639 640/* Available values for -mfpu=. */ 641 642static const struct fpu_desc all_fpus[] = 643{ 644 {"fpa", FPUTYPE_FPA}, 645 {"fpe2", FPUTYPE_FPA_EMU2}, 646 {"fpe3", FPUTYPE_FPA_EMU2}, 647 {"maverick", FPUTYPE_MAVERICK}, 648 {"vfp", FPUTYPE_VFP} 649}; 650 651 652/* Floating point models used by the different hardware. 653 See fputype in arm.h. */ 654 655static const enum fputype fp_model_for_fpu[] = 656{ 657 /* No FP hardware. */ 658 ARM_FP_MODEL_UNKNOWN, /* FPUTYPE_NONE */ 659 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA */ 660 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU2 */ 661 ARM_FP_MODEL_FPA, /* FPUTYPE_FPA_EMU3 */ 662 ARM_FP_MODEL_MAVERICK, /* FPUTYPE_MAVERICK */ 663 ARM_FP_MODEL_VFP /* FPUTYPE_VFP */ 664}; 665 666 667struct float_abi 668{ 669 const char * name; 670 enum float_abi_type abi_type; 671}; 672 673 674/* Available values for -mfloat-abi=. */ 675 676static const struct float_abi all_float_abis[] = 677{ 678 {"soft", ARM_FLOAT_ABI_SOFT}, 679 {"softfp", ARM_FLOAT_ABI_SOFTFP}, 680 {"hard", ARM_FLOAT_ABI_HARD} 681}; 682 683 684struct abi_name 685{ 686 const char *name; 687 enum arm_abi_type abi_type; 688}; 689 690 691/* Available values for -mabi=. */ 692 693static const struct abi_name arm_all_abis[] = 694{ 695 {"apcs-gnu", ARM_ABI_APCS}, 696 {"atpcs", ARM_ABI_ATPCS}, 697 {"aapcs", ARM_ABI_AAPCS}, 698 {"iwmmxt", ARM_ABI_IWMMXT}, 699 {"aapcs-linux", ARM_ABI_AAPCS_LINUX} 700}; 701 702/* Supported TLS relocations. */ 703 704enum tls_reloc { 705 TLS_GD32, 706 TLS_LDM32, 707 TLS_LDO32, 708 TLS_IE32, 709 TLS_LE32 710}; 711 712/* Emit an insn that's a simple single-set. Both the operands must be known 713 to be valid. */ 714inline static rtx 715emit_set_insn (rtx x, rtx y) 716{ 717 return emit_insn (gen_rtx_SET (VOIDmode, x, y)); 718} 719 720/* Return the number of bits set in VALUE. */ 721static unsigned 722bit_count (unsigned long value) 723{ 724 unsigned long count = 0; 725 726 while (value) 727 { 728 count++; 729 value &= value - 1; /* Clear the least-significant set bit. */ 730 } 731 732 return count; 733} 734 735/* Set up library functions unique to ARM. */ 736 737static void 738arm_init_libfuncs (void) 739{ 740 /* There are no special library functions unless we are using the 741 ARM BPABI. */ 742 if (!TARGET_BPABI) 743 return; 744 745 /* The functions below are described in Section 4 of the "Run-Time 746 ABI for the ARM architecture", Version 1.0. */ 747 748 /* Double-precision floating-point arithmetic. Table 2. */ 749 set_optab_libfunc (add_optab, DFmode, "__aeabi_dadd"); 750 set_optab_libfunc (sdiv_optab, DFmode, "__aeabi_ddiv"); 751 set_optab_libfunc (smul_optab, DFmode, "__aeabi_dmul"); 752 set_optab_libfunc (neg_optab, DFmode, "__aeabi_dneg"); 753 set_optab_libfunc (sub_optab, DFmode, "__aeabi_dsub"); 754 755 /* Double-precision comparisons. Table 3. */ 756 set_optab_libfunc (eq_optab, DFmode, "__aeabi_dcmpeq"); 757 set_optab_libfunc (ne_optab, DFmode, NULL); 758 set_optab_libfunc (lt_optab, DFmode, "__aeabi_dcmplt"); 759 set_optab_libfunc (le_optab, DFmode, "__aeabi_dcmple"); 760 set_optab_libfunc (ge_optab, DFmode, "__aeabi_dcmpge"); 761 set_optab_libfunc (gt_optab, DFmode, "__aeabi_dcmpgt"); 762 set_optab_libfunc (unord_optab, DFmode, "__aeabi_dcmpun"); 763 764 /* Single-precision floating-point arithmetic. Table 4. */ 765 set_optab_libfunc (add_optab, SFmode, "__aeabi_fadd"); 766 set_optab_libfunc (sdiv_optab, SFmode, "__aeabi_fdiv"); 767 set_optab_libfunc (smul_optab, SFmode, "__aeabi_fmul"); 768 set_optab_libfunc (neg_optab, SFmode, "__aeabi_fneg"); 769 set_optab_libfunc (sub_optab, SFmode, "__aeabi_fsub"); 770 771 /* Single-precision comparisons. Table 5. */ 772 set_optab_libfunc (eq_optab, SFmode, "__aeabi_fcmpeq"); 773 set_optab_libfunc (ne_optab, SFmode, NULL); 774 set_optab_libfunc (lt_optab, SFmode, "__aeabi_fcmplt"); 775 set_optab_libfunc (le_optab, SFmode, "__aeabi_fcmple"); 776 set_optab_libfunc (ge_optab, SFmode, "__aeabi_fcmpge"); 777 set_optab_libfunc (gt_optab, SFmode, "__aeabi_fcmpgt"); 778 set_optab_libfunc (unord_optab, SFmode, "__aeabi_fcmpun"); 779 780 /* Floating-point to integer conversions. Table 6. */ 781 set_conv_libfunc (sfix_optab, SImode, DFmode, "__aeabi_d2iz"); 782 set_conv_libfunc (ufix_optab, SImode, DFmode, "__aeabi_d2uiz"); 783 set_conv_libfunc (sfix_optab, DImode, DFmode, "__aeabi_d2lz"); 784 set_conv_libfunc (ufix_optab, DImode, DFmode, "__aeabi_d2ulz"); 785 set_conv_libfunc (sfix_optab, SImode, SFmode, "__aeabi_f2iz"); 786 set_conv_libfunc (ufix_optab, SImode, SFmode, "__aeabi_f2uiz"); 787 set_conv_libfunc (sfix_optab, DImode, SFmode, "__aeabi_f2lz"); 788 set_conv_libfunc (ufix_optab, DImode, SFmode, "__aeabi_f2ulz"); 789 790 /* Conversions between floating types. Table 7. */ 791 set_conv_libfunc (trunc_optab, SFmode, DFmode, "__aeabi_d2f"); 792 set_conv_libfunc (sext_optab, DFmode, SFmode, "__aeabi_f2d"); 793 794 /* Integer to floating-point conversions. Table 8. */ 795 set_conv_libfunc (sfloat_optab, DFmode, SImode, "__aeabi_i2d"); 796 set_conv_libfunc (ufloat_optab, DFmode, SImode, "__aeabi_ui2d"); 797 set_conv_libfunc (sfloat_optab, DFmode, DImode, "__aeabi_l2d"); 798 set_conv_libfunc (ufloat_optab, DFmode, DImode, "__aeabi_ul2d"); 799 set_conv_libfunc (sfloat_optab, SFmode, SImode, "__aeabi_i2f"); 800 set_conv_libfunc (ufloat_optab, SFmode, SImode, "__aeabi_ui2f"); 801 set_conv_libfunc (sfloat_optab, SFmode, DImode, "__aeabi_l2f"); 802 set_conv_libfunc (ufloat_optab, SFmode, DImode, "__aeabi_ul2f"); 803 804 /* Long long. Table 9. */ 805 set_optab_libfunc (smul_optab, DImode, "__aeabi_lmul"); 806 set_optab_libfunc (sdivmod_optab, DImode, "__aeabi_ldivmod"); 807 set_optab_libfunc (udivmod_optab, DImode, "__aeabi_uldivmod"); 808 set_optab_libfunc (ashl_optab, DImode, "__aeabi_llsl"); 809 set_optab_libfunc (lshr_optab, DImode, "__aeabi_llsr"); 810 set_optab_libfunc (ashr_optab, DImode, "__aeabi_lasr"); 811 set_optab_libfunc (cmp_optab, DImode, "__aeabi_lcmp"); 812 set_optab_libfunc (ucmp_optab, DImode, "__aeabi_ulcmp"); 813 814 /* Integer (32/32->32) division. \S 4.3.1. */ 815 set_optab_libfunc (sdivmod_optab, SImode, "__aeabi_idivmod"); 816 set_optab_libfunc (udivmod_optab, SImode, "__aeabi_uidivmod"); 817 818 /* The divmod functions are designed so that they can be used for 819 plain division, even though they return both the quotient and the 820 remainder. The quotient is returned in the usual location (i.e., 821 r0 for SImode, {r0, r1} for DImode), just as would be expected 822 for an ordinary division routine. Because the AAPCS calling 823 conventions specify that all of { r0, r1, r2, r3 } are 824 callee-saved registers, there is no need to tell the compiler 825 explicitly that those registers are clobbered by these 826 routines. */ 827 set_optab_libfunc (sdiv_optab, DImode, "__aeabi_ldivmod"); 828 set_optab_libfunc (udiv_optab, DImode, "__aeabi_uldivmod"); 829 830 /* For SImode division the ABI provides div-without-mod routines, 831 which are faster. */ 832 set_optab_libfunc (sdiv_optab, SImode, "__aeabi_idiv"); 833 set_optab_libfunc (udiv_optab, SImode, "__aeabi_uidiv"); 834 835 /* We don't have mod libcalls. Fortunately gcc knows how to use the 836 divmod libcalls instead. */ 837 set_optab_libfunc (smod_optab, DImode, NULL); 838 set_optab_libfunc (umod_optab, DImode, NULL); 839 set_optab_libfunc (smod_optab, SImode, NULL); 840 set_optab_libfunc (umod_optab, SImode, NULL); 841} 842 843/* Implement TARGET_HANDLE_OPTION. */ 844 845static bool 846arm_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED) 847{ 848 switch (code) 849 { 850 case OPT_march_: 851 arm_select[1].string = arg; 852 return true; 853 854 case OPT_mcpu_: 855 arm_select[0].string = arg; 856 return true; 857 858 case OPT_mhard_float: 859 target_float_abi_name = "hard"; 860 return true; 861 862 case OPT_msoft_float: 863 target_float_abi_name = "soft"; 864 return true; 865 866 case OPT_mtune_: 867 arm_select[2].string = arg; 868 return true; 869 870 default: 871 return true; 872 } 873} 874 875/* Fix up any incompatible options that the user has specified. 876 This has now turned into a maze. */ 877void 878arm_override_options (void) 879{ 880 unsigned i; 881 enum processor_type target_arch_cpu = arm_none; 882 883 /* Set up the flags based on the cpu/architecture selected by the user. */ 884 for (i = ARRAY_SIZE (arm_select); i--;) 885 { 886 struct arm_cpu_select * ptr = arm_select + i; 887 888 if (ptr->string != NULL && ptr->string[0] != '\0') 889 { 890 const struct processors * sel; 891 892 for (sel = ptr->processors; sel->name != NULL; sel++) 893 if (streq (ptr->string, sel->name)) 894 { 895 /* Set the architecture define. */ 896 if (i != ARM_OPT_SET_TUNE) 897 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); 898 899 /* Determine the processor core for which we should 900 tune code-generation. */ 901 if (/* -mcpu= is a sensible default. */ 902 i == ARM_OPT_SET_CPU 903 /* -mtune= overrides -mcpu= and -march=. */ 904 || i == ARM_OPT_SET_TUNE) 905 arm_tune = (enum processor_type) (sel - ptr->processors); 906 907 /* Remember the CPU associated with this architecture. 908 If no other option is used to set the CPU type, 909 we'll use this to guess the most suitable tuning 910 options. */ 911 if (i == ARM_OPT_SET_ARCH) 912 target_arch_cpu = sel->core; 913 914 if (i != ARM_OPT_SET_TUNE) 915 { 916 /* If we have been given an architecture and a processor 917 make sure that they are compatible. We only generate 918 a warning though, and we prefer the CPU over the 919 architecture. */ 920 if (insn_flags != 0 && (insn_flags ^ sel->flags)) 921 warning (0, "switch -mcpu=%s conflicts with -march= switch", 922 ptr->string); 923 924 insn_flags = sel->flags; 925 } 926 927 break; 928 } 929 930 if (sel->name == NULL) 931 error ("bad value (%s) for %s switch", ptr->string, ptr->name); 932 } 933 } 934 935 /* Guess the tuning options from the architecture if necessary. */ 936 if (arm_tune == arm_none) 937 arm_tune = target_arch_cpu; 938 939 /* If the user did not specify a processor, choose one for them. */ 940 if (insn_flags == 0) 941 { 942 const struct processors * sel; 943 unsigned int sought; 944 enum processor_type cpu; 945 946 cpu = TARGET_CPU_DEFAULT; 947 if (cpu == arm_none) 948 { 949#ifdef SUBTARGET_CPU_DEFAULT 950 /* Use the subtarget default CPU if none was specified by 951 configure. */ 952 cpu = SUBTARGET_CPU_DEFAULT; 953#endif 954 /* Default to ARM6. */ 955 if (cpu == arm_none) 956 cpu = arm6; 957 } 958 sel = &all_cores[cpu]; 959 960 insn_flags = sel->flags; 961 962 /* Now check to see if the user has specified some command line 963 switch that require certain abilities from the cpu. */ 964 sought = 0; 965 966 if (TARGET_INTERWORK || TARGET_THUMB) 967 { 968 sought |= (FL_THUMB | FL_MODE32); 969 970 /* There are no ARM processors that support both APCS-26 and 971 interworking. Therefore we force FL_MODE26 to be removed 972 from insn_flags here (if it was set), so that the search 973 below will always be able to find a compatible processor. */ 974 insn_flags &= ~FL_MODE26; 975 } 976 977 if (sought != 0 && ((sought & insn_flags) != sought)) 978 { 979 /* Try to locate a CPU type that supports all of the abilities 980 of the default CPU, plus the extra abilities requested by 981 the user. */ 982 for (sel = all_cores; sel->name != NULL; sel++) 983 if ((sel->flags & sought) == (sought | insn_flags)) 984 break; 985 986 if (sel->name == NULL) 987 { 988 unsigned current_bit_count = 0; 989 const struct processors * best_fit = NULL; 990 991 /* Ideally we would like to issue an error message here 992 saying that it was not possible to find a CPU compatible 993 with the default CPU, but which also supports the command 994 line options specified by the programmer, and so they 995 ought to use the -mcpu=<name> command line option to 996 override the default CPU type. 997 998 If we cannot find a cpu that has both the 999 characteristics of the default cpu and the given 1000 command line options we scan the array again looking 1001 for a best match. */ 1002 for (sel = all_cores; sel->name != NULL; sel++) 1003 if ((sel->flags & sought) == sought) 1004 { 1005 unsigned count; 1006 1007 count = bit_count (sel->flags & insn_flags); 1008 1009 if (count >= current_bit_count) 1010 { 1011 best_fit = sel; 1012 current_bit_count = count; 1013 } 1014 } 1015 1016 gcc_assert (best_fit); 1017 sel = best_fit; 1018 } 1019 1020 insn_flags = sel->flags; 1021 } 1022 sprintf (arm_arch_name, "__ARM_ARCH_%s__", sel->arch); 1023 if (arm_tune == arm_none) 1024 arm_tune = (enum processor_type) (sel - all_cores); 1025 } 1026 1027 /* The processor for which we should tune should now have been 1028 chosen. */ 1029 gcc_assert (arm_tune != arm_none); 1030 1031 tune_flags = all_cores[(int)arm_tune].flags; 1032 if (optimize_size) 1033 targetm.rtx_costs = arm_size_rtx_costs; 1034 else 1035 targetm.rtx_costs = all_cores[(int)arm_tune].rtx_costs; 1036 1037 /* Make sure that the processor choice does not conflict with any of the 1038 other command line choices. */ 1039 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB)) 1040 { 1041 warning (0, "target CPU does not support interworking" ); 1042 target_flags &= ~MASK_INTERWORK; 1043 } 1044 1045 if (TARGET_THUMB && !(insn_flags & FL_THUMB)) 1046 { 1047 warning (0, "target CPU does not support THUMB instructions"); 1048 target_flags &= ~MASK_THUMB; 1049 } 1050 1051 if (TARGET_APCS_FRAME && TARGET_THUMB) 1052 { 1053 /* warning (0, "ignoring -mapcs-frame because -mthumb was used"); */ 1054 target_flags &= ~MASK_APCS_FRAME; 1055 } 1056 1057 /* Callee super interworking implies thumb interworking. Adding 1058 this to the flags here simplifies the logic elsewhere. */ 1059 if (TARGET_THUMB && TARGET_CALLEE_INTERWORKING) 1060 target_flags |= MASK_INTERWORK; 1061 1062 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done 1063 from here where no function is being compiled currently. */ 1064 if ((TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) && TARGET_ARM) 1065 warning (0, "enabling backtrace support is only meaningful when compiling for the Thumb"); 1066 1067 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) 1068 warning (0, "enabling callee interworking support is only meaningful when compiling for the Thumb"); 1069 1070 if (TARGET_ARM && TARGET_CALLER_INTERWORKING) 1071 warning (0, "enabling caller interworking support is only meaningful when compiling for the Thumb"); 1072 1073 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) 1074 { 1075 warning (0, "-mapcs-stack-check incompatible with -mno-apcs-frame"); 1076 target_flags |= MASK_APCS_FRAME; 1077 } 1078 1079 if (TARGET_POKE_FUNCTION_NAME) 1080 target_flags |= MASK_APCS_FRAME; 1081 1082 if (TARGET_APCS_REENT && flag_pic) 1083 error ("-fpic and -mapcs-reent are incompatible"); 1084 1085 if (TARGET_APCS_REENT) 1086 warning (0, "APCS reentrant code not supported. Ignored"); 1087 1088 /* If this target is normally configured to use APCS frames, warn if they 1089 are turned off and debugging is turned on. */ 1090 if (TARGET_ARM 1091 && write_symbols != NO_DEBUG 1092 && !TARGET_APCS_FRAME 1093 && (TARGET_DEFAULT & MASK_APCS_FRAME)) 1094 warning (0, "-g with -mno-apcs-frame may not give sensible debugging"); 1095 1096 /* If stack checking is disabled, we can use r10 as the PIC register, 1097 which keeps r9 available. */ 1098 if (flag_pic && TARGET_SINGLE_PIC_BASE) 1099 arm_pic_register = TARGET_APCS_STACK ? 9 : 10; 1100 1101 if (TARGET_APCS_FLOAT) 1102 warning (0, "passing floating point arguments in fp regs not yet supported"); 1103 1104 /* Initialize boolean versions of the flags, for use in the arm.md file. */ 1105 arm_arch3m = (insn_flags & FL_ARCH3M) != 0; 1106 arm_arch4 = (insn_flags & FL_ARCH4) != 0; 1107 arm_arch4t = arm_arch4 & ((insn_flags & FL_THUMB) != 0); 1108 arm_arch5 = (insn_flags & FL_ARCH5) != 0; 1109 arm_arch5e = (insn_flags & FL_ARCH5E) != 0; 1110 arm_arch6 = (insn_flags & FL_ARCH6) != 0; 1111 arm_arch6k = (insn_flags & FL_ARCH6K) != 0; 1112 arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; 1113 arm_arch_cirrus = (insn_flags & FL_CIRRUS) != 0; 1114 1115 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; 1116 arm_tune_strongarm = (tune_flags & FL_STRONG) != 0; 1117 thumb_code = (TARGET_ARM == 0); 1118 arm_tune_wbuf = (tune_flags & FL_WBUF) != 0; 1119 arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; 1120 arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; 1121 1122 /* V5 code we generate is completely interworking capable, so we turn off 1123 TARGET_INTERWORK here to avoid many tests later on. */ 1124 1125 /* XXX However, we must pass the right pre-processor defines to CPP 1126 or GLD can get confused. This is a hack. */ 1127 if (TARGET_INTERWORK) 1128 arm_cpp_interwork = 1; 1129 1130 if (arm_arch5) 1131 target_flags &= ~MASK_INTERWORK; 1132 1133 if (target_abi_name) 1134 { 1135 for (i = 0; i < ARRAY_SIZE (arm_all_abis); i++) 1136 { 1137 if (streq (arm_all_abis[i].name, target_abi_name)) 1138 { 1139 arm_abi = arm_all_abis[i].abi_type; 1140 break; 1141 } 1142 } 1143 if (i == ARRAY_SIZE (arm_all_abis)) 1144 error ("invalid ABI option: -mabi=%s", target_abi_name); 1145 } 1146 else 1147 arm_abi = ARM_DEFAULT_ABI; 1148 1149 if (TARGET_IWMMXT && !ARM_DOUBLEWORD_ALIGN) 1150 error ("iwmmxt requires an AAPCS compatible ABI for proper operation"); 1151 1152 if (TARGET_IWMMXT_ABI && !TARGET_IWMMXT) 1153 error ("iwmmxt abi requires an iwmmxt capable cpu"); 1154 1155 arm_fp_model = ARM_FP_MODEL_UNKNOWN; 1156 if (target_fpu_name == NULL && target_fpe_name != NULL) 1157 { 1158 if (streq (target_fpe_name, "2")) 1159 target_fpu_name = "fpe2"; 1160 else if (streq (target_fpe_name, "3")) 1161 target_fpu_name = "fpe3"; 1162 else 1163 error ("invalid floating point emulation option: -mfpe=%s", 1164 target_fpe_name); 1165 } 1166 if (target_fpu_name != NULL) 1167 { 1168 /* The user specified a FPU. */ 1169 for (i = 0; i < ARRAY_SIZE (all_fpus); i++) 1170 { 1171 if (streq (all_fpus[i].name, target_fpu_name)) 1172 { 1173 arm_fpu_arch = all_fpus[i].fpu; 1174 arm_fpu_tune = arm_fpu_arch; 1175 arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; 1176 break; 1177 } 1178 } 1179 if (arm_fp_model == ARM_FP_MODEL_UNKNOWN) 1180 error ("invalid floating point option: -mfpu=%s", target_fpu_name); 1181 } 1182 else 1183 { 1184#ifdef FPUTYPE_DEFAULT 1185 /* Use the default if it is specified for this platform. */ 1186 arm_fpu_arch = FPUTYPE_DEFAULT; 1187 arm_fpu_tune = FPUTYPE_DEFAULT; 1188#else 1189 /* Pick one based on CPU type. */ 1190 /* ??? Some targets assume FPA is the default. 1191 if ((insn_flags & FL_VFP) != 0) 1192 arm_fpu_arch = FPUTYPE_VFP; 1193 else 1194 */ 1195 if (arm_arch_cirrus) 1196 arm_fpu_arch = FPUTYPE_MAVERICK; 1197 else 1198 arm_fpu_arch = FPUTYPE_FPA_EMU2; 1199#endif 1200 if (tune_flags & FL_CO_PROC && arm_fpu_arch == FPUTYPE_FPA_EMU2) 1201 arm_fpu_tune = FPUTYPE_FPA; 1202 else 1203 arm_fpu_tune = arm_fpu_arch; 1204 arm_fp_model = fp_model_for_fpu[arm_fpu_arch]; 1205 gcc_assert (arm_fp_model != ARM_FP_MODEL_UNKNOWN); 1206 } 1207 1208 if (target_float_abi_name != NULL) 1209 { 1210 /* The user specified a FP ABI. */ 1211 for (i = 0; i < ARRAY_SIZE (all_float_abis); i++) 1212 { 1213 if (streq (all_float_abis[i].name, target_float_abi_name)) 1214 { 1215 arm_float_abi = all_float_abis[i].abi_type; 1216 break; 1217 } 1218 } 1219 if (i == ARRAY_SIZE (all_float_abis)) 1220 error ("invalid floating point abi: -mfloat-abi=%s", 1221 target_float_abi_name); 1222 } 1223 else 1224 arm_float_abi = TARGET_DEFAULT_FLOAT_ABI; 1225 1226 if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_VFP) 1227 sorry ("-mfloat-abi=hard and VFP"); 1228 1229 /* FPA and iWMMXt are incompatible because the insn encodings overlap. 1230 VFP and iWMMXt can theoretically coexist, but it's unlikely such silicon 1231 will ever exist. GCC makes no attempt to support this combination. */ 1232 if (TARGET_IWMMXT && !TARGET_SOFT_FLOAT) 1233 sorry ("iWMMXt and hardware floating point"); 1234 1235 /* If soft-float is specified then don't use FPU. */ 1236 if (TARGET_SOFT_FLOAT) 1237 arm_fpu_arch = FPUTYPE_NONE; 1238 1239 /* For arm2/3 there is no need to do any scheduling if there is only 1240 a floating point emulator, or we are doing software floating-point. */ 1241 if ((TARGET_SOFT_FLOAT 1242 || arm_fpu_tune == FPUTYPE_FPA_EMU2 1243 || arm_fpu_tune == FPUTYPE_FPA_EMU3) 1244 && (tune_flags & FL_MODE32) == 0) 1245 flag_schedule_insns = flag_schedule_insns_after_reload = 0; 1246 1247 if (target_thread_switch) 1248 { 1249 if (strcmp (target_thread_switch, "soft") == 0) 1250 target_thread_pointer = TP_SOFT; 1251 else if (strcmp (target_thread_switch, "auto") == 0) 1252 target_thread_pointer = TP_AUTO; 1253 else if (strcmp (target_thread_switch, "cp15") == 0) 1254 target_thread_pointer = TP_CP15; 1255 else 1256 error ("invalid thread pointer option: -mtp=%s", target_thread_switch); 1257 } 1258 1259 /* Use the cp15 method if it is available. */ 1260 if (target_thread_pointer == TP_AUTO) 1261 { 1262 if (arm_arch6k && !TARGET_THUMB) 1263 target_thread_pointer = TP_CP15; 1264 else 1265 target_thread_pointer = TP_SOFT; 1266 } 1267 1268 if (TARGET_HARD_TP && TARGET_THUMB) 1269 error ("can not use -mtp=cp15 with -mthumb"); 1270 1271 /* Override the default structure alignment for AAPCS ABI. */ 1272 if (TARGET_AAPCS_BASED) 1273 arm_structure_size_boundary = 8; 1274 1275 if (structure_size_string != NULL) 1276 { 1277 int size = strtol (structure_size_string, NULL, 0); 1278 1279 if (size == 8 || size == 32 1280 || (ARM_DOUBLEWORD_ALIGN && size == 64)) 1281 arm_structure_size_boundary = size; 1282 else 1283 warning (0, "structure size boundary can only be set to %s", 1284 ARM_DOUBLEWORD_ALIGN ? "8, 32 or 64": "8 or 32"); 1285 } 1286 1287 if (arm_pic_register_string != NULL) 1288 { 1289 int pic_register = decode_reg_name (arm_pic_register_string); 1290 1291 if (!flag_pic) 1292 warning (0, "-mpic-register= is useless without -fpic"); 1293 1294 /* Prevent the user from choosing an obviously stupid PIC register. */ 1295 else if (pic_register < 0 || call_used_regs[pic_register] 1296 || pic_register == HARD_FRAME_POINTER_REGNUM 1297 || pic_register == STACK_POINTER_REGNUM 1298 || pic_register >= PC_REGNUM) 1299 error ("unable to use '%s' for PIC register", arm_pic_register_string); 1300 else 1301 arm_pic_register = pic_register; 1302 } 1303 1304 if (TARGET_THUMB && flag_schedule_insns) 1305 { 1306 /* Don't warn since it's on by default in -O2. */ 1307 flag_schedule_insns = 0; 1308 } 1309 1310 if (optimize_size) 1311 { 1312 arm_constant_limit = 1; 1313 1314 /* If optimizing for size, bump the number of instructions that we 1315 are prepared to conditionally execute (even on a StrongARM). */ 1316 max_insns_skipped = 6; 1317 } 1318 else 1319 { 1320 /* For processors with load scheduling, it never costs more than 1321 2 cycles to load a constant, and the load scheduler may well 1322 reduce that to 1. */ 1323 if (arm_ld_sched) 1324 arm_constant_limit = 1; 1325 1326 /* On XScale the longer latency of a load makes it more difficult 1327 to achieve a good schedule, so it's faster to synthesize 1328 constants that can be done in two insns. */ 1329 if (arm_tune_xscale) 1330 arm_constant_limit = 2; 1331 1332 /* StrongARM has early execution of branches, so a sequence 1333 that is worth skipping is shorter. */ 1334 if (arm_tune_strongarm) 1335 max_insns_skipped = 3; 1336 } 1337 1338 /* Register global variables with the garbage collector. */ 1339 arm_add_gc_roots (); 1340} 1341 1342static void 1343arm_add_gc_roots (void) 1344{ 1345 gcc_obstack_init(&minipool_obstack); 1346 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); 1347} 1348 1349/* A table of known ARM exception types. 1350 For use with the interrupt function attribute. */ 1351 1352typedef struct 1353{ 1354 const char *const arg; 1355 const unsigned long return_value; 1356} 1357isr_attribute_arg; 1358 1359static const isr_attribute_arg isr_attribute_args [] = 1360{ 1361 { "IRQ", ARM_FT_ISR }, 1362 { "irq", ARM_FT_ISR }, 1363 { "FIQ", ARM_FT_FIQ }, 1364 { "fiq", ARM_FT_FIQ }, 1365 { "ABORT", ARM_FT_ISR }, 1366 { "abort", ARM_FT_ISR }, 1367 { "ABORT", ARM_FT_ISR }, 1368 { "abort", ARM_FT_ISR }, 1369 { "UNDEF", ARM_FT_EXCEPTION }, 1370 { "undef", ARM_FT_EXCEPTION }, 1371 { "SWI", ARM_FT_EXCEPTION }, 1372 { "swi", ARM_FT_EXCEPTION }, 1373 { NULL, ARM_FT_NORMAL } 1374}; 1375 1376/* Returns the (interrupt) function type of the current 1377 function, or ARM_FT_UNKNOWN if the type cannot be determined. */ 1378 1379static unsigned long 1380arm_isr_value (tree argument) 1381{ 1382 const isr_attribute_arg * ptr; 1383 const char * arg; 1384 1385 /* No argument - default to IRQ. */ 1386 if (argument == NULL_TREE) 1387 return ARM_FT_ISR; 1388 1389 /* Get the value of the argument. */ 1390 if (TREE_VALUE (argument) == NULL_TREE 1391 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) 1392 return ARM_FT_UNKNOWN; 1393 1394 arg = TREE_STRING_POINTER (TREE_VALUE (argument)); 1395 1396 /* Check it against the list of known arguments. */ 1397 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) 1398 if (streq (arg, ptr->arg)) 1399 return ptr->return_value; 1400 1401 /* An unrecognized interrupt type. */ 1402 return ARM_FT_UNKNOWN; 1403} 1404 1405/* Computes the type of the current function. */ 1406 1407static unsigned long 1408arm_compute_func_type (void) 1409{ 1410 unsigned long type = ARM_FT_UNKNOWN; 1411 tree a; 1412 tree attr; 1413 1414 gcc_assert (TREE_CODE (current_function_decl) == FUNCTION_DECL); 1415 1416 /* Decide if the current function is volatile. Such functions 1417 never return, and many memory cycles can be saved by not storing 1418 register values that will never be needed again. This optimization 1419 was added to speed up context switching in a kernel application. */ 1420 if (optimize > 0 1421 && (TREE_NOTHROW (current_function_decl) 1422 || !(flag_unwind_tables 1423 || (flag_exceptions && !USING_SJLJ_EXCEPTIONS))) 1424 && TREE_THIS_VOLATILE (current_function_decl)) 1425 type |= ARM_FT_VOLATILE; 1426 1427 if (cfun->static_chain_decl != NULL) 1428 type |= ARM_FT_NESTED; 1429 1430 attr = DECL_ATTRIBUTES (current_function_decl); 1431 1432 a = lookup_attribute ("naked", attr); 1433 if (a != NULL_TREE) 1434 type |= ARM_FT_NAKED; 1435 1436 a = lookup_attribute ("isr", attr); 1437 if (a == NULL_TREE) 1438 a = lookup_attribute ("interrupt", attr); 1439 1440 if (a == NULL_TREE) 1441 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; 1442 else 1443 type |= arm_isr_value (TREE_VALUE (a)); 1444 1445 return type; 1446} 1447 1448/* Returns the type of the current function. */ 1449 1450unsigned long 1451arm_current_func_type (void) 1452{ 1453 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) 1454 cfun->machine->func_type = arm_compute_func_type (); 1455 1456 return cfun->machine->func_type; 1457} 1458 1459/* Return 1 if it is possible to return using a single instruction. 1460 If SIBLING is non-null, this is a test for a return before a sibling 1461 call. SIBLING is the call insn, so we can examine its register usage. */ 1462 1463int 1464use_return_insn (int iscond, rtx sibling) 1465{ 1466 int regno; 1467 unsigned int func_type; 1468 unsigned long saved_int_regs; 1469 unsigned HOST_WIDE_INT stack_adjust; 1470 arm_stack_offsets *offsets; 1471 1472 /* Never use a return instruction before reload has run. */ 1473 if (!reload_completed) 1474 return 0; 1475 1476 func_type = arm_current_func_type (); 1477 1478 /* Naked functions and volatile functions need special 1479 consideration. */ 1480 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED)) 1481 return 0; 1482 1483 /* So do interrupt functions that use the frame pointer. */ 1484 if (IS_INTERRUPT (func_type) && frame_pointer_needed) 1485 return 0; 1486 1487 offsets = arm_get_frame_offsets (); 1488 stack_adjust = offsets->outgoing_args - offsets->saved_regs; 1489 1490 /* As do variadic functions. */ 1491 if (current_function_pretend_args_size 1492 || cfun->machine->uses_anonymous_args 1493 /* Or if the function calls __builtin_eh_return () */ 1494 || current_function_calls_eh_return 1495 /* Or if the function calls alloca */ 1496 || current_function_calls_alloca 1497 /* Or if there is a stack adjustment. However, if the stack pointer 1498 is saved on the stack, we can use a pre-incrementing stack load. */ 1499 || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4))) 1500 return 0; 1501 1502 saved_int_regs = arm_compute_save_reg_mask (); 1503 1504 /* Unfortunately, the insn 1505 1506 ldmib sp, {..., sp, ...} 1507 1508 triggers a bug on most SA-110 based devices, such that the stack 1509 pointer won't be correctly restored if the instruction takes a 1510 page fault. We work around this problem by popping r3 along with 1511 the other registers, since that is never slower than executing 1512 another instruction. 1513 1514 We test for !arm_arch5 here, because code for any architecture 1515 less than this could potentially be run on one of the buggy 1516 chips. */ 1517 if (stack_adjust == 4 && !arm_arch5) 1518 { 1519 /* Validate that r3 is a call-clobbered register (always true in 1520 the default abi) ... */ 1521 if (!call_used_regs[3]) 1522 return 0; 1523 1524 /* ... that it isn't being used for a return value ... */ 1525 if (arm_size_return_regs () >= (4 * UNITS_PER_WORD)) 1526 return 0; 1527 1528 /* ... or for a tail-call argument ... */ 1529 if (sibling) 1530 { 1531 gcc_assert (GET_CODE (sibling) == CALL_INSN); 1532 1533 if (find_regno_fusage (sibling, USE, 3)) 1534 return 0; 1535 } 1536 1537 /* ... and that there are no call-saved registers in r0-r2 1538 (always true in the default ABI). */ 1539 if (saved_int_regs & 0x7) 1540 return 0; 1541 } 1542 1543 /* Can't be done if interworking with Thumb, and any registers have been 1544 stacked. */ 1545 if (TARGET_INTERWORK && saved_int_regs != 0) 1546 return 0; 1547 1548 /* On StrongARM, conditional returns are expensive if they aren't 1549 taken and multiple registers have been stacked. */ 1550 if (iscond && arm_tune_strongarm) 1551 { 1552 /* Conditional return when just the LR is stored is a simple 1553 conditional-load instruction, that's not expensive. */ 1554 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) 1555 return 0; 1556 1557 if (flag_pic 1558 && arm_pic_register != INVALID_REGNUM 1559 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) 1560 return 0; 1561 } 1562 1563 /* If there are saved registers but the LR isn't saved, then we need 1564 two instructions for the return. */ 1565 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) 1566 return 0; 1567 1568 /* Can't be done if any of the FPA regs are pushed, 1569 since this also requires an insn. */ 1570 if (TARGET_HARD_FLOAT && TARGET_FPA) 1571 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) 1572 if (regs_ever_live[regno] && !call_used_regs[regno]) 1573 return 0; 1574 1575 /* Likewise VFP regs. */ 1576 if (TARGET_HARD_FLOAT && TARGET_VFP) 1577 for (regno = FIRST_VFP_REGNUM; regno <= LAST_VFP_REGNUM; regno++) 1578 if (regs_ever_live[regno] && !call_used_regs[regno]) 1579 return 0; 1580 1581 if (TARGET_REALLY_IWMMXT) 1582 for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) 1583 if (regs_ever_live[regno] && ! call_used_regs [regno]) 1584 return 0; 1585 1586 return 1; 1587} 1588 1589/* Return TRUE if int I is a valid immediate ARM constant. */ 1590 1591int 1592const_ok_for_arm (HOST_WIDE_INT i) 1593{ 1594 int lowbit; 1595 1596 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must 1597 be all zero, or all one. */ 1598 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 1599 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) 1600 != ((~(unsigned HOST_WIDE_INT) 0) 1601 & ~(unsigned HOST_WIDE_INT) 0xffffffff))) 1602 return FALSE; 1603 1604 i &= (unsigned HOST_WIDE_INT) 0xffffffff; 1605 1606 /* Fast return for 0 and small values. We must do this for zero, since 1607 the code below can't handle that one case. */ 1608 if ((i & ~(unsigned HOST_WIDE_INT) 0xff) == 0) 1609 return TRUE; 1610 1611 /* Get the number of trailing zeros, rounded down to the nearest even 1612 number. */ 1613 lowbit = (ffs ((int) i) - 1) & ~1; 1614 1615 if ((i & ~(((unsigned HOST_WIDE_INT) 0xff) << lowbit)) == 0) 1616 return TRUE; 1617 else if (lowbit <= 4 1618 && ((i & ~0xc000003f) == 0 1619 || (i & ~0xf000000f) == 0 1620 || (i & ~0xfc000003) == 0)) 1621 return TRUE; 1622 1623 return FALSE; 1624} 1625 1626/* Return true if I is a valid constant for the operation CODE. */ 1627static int 1628const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) 1629{ 1630 if (const_ok_for_arm (i)) 1631 return 1; 1632 1633 switch (code) 1634 { 1635 case PLUS: 1636 return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); 1637 1638 case MINUS: /* Should only occur with (MINUS I reg) => rsb */ 1639 case XOR: 1640 case IOR: 1641 return 0; 1642 1643 case AND: 1644 return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); 1645 1646 default: 1647 gcc_unreachable (); 1648 } 1649} 1650 1651/* Emit a sequence of insns to handle a large constant. 1652 CODE is the code of the operation required, it can be any of SET, PLUS, 1653 IOR, AND, XOR, MINUS; 1654 MODE is the mode in which the operation is being performed; 1655 VAL is the integer to operate on; 1656 SOURCE is the other operand (a register, or a null-pointer for SET); 1657 SUBTARGETS means it is safe to create scratch registers if that will 1658 either produce a simpler sequence, or we will want to cse the values. 1659 Return value is the number of insns emitted. */ 1660 1661int 1662arm_split_constant (enum rtx_code code, enum machine_mode mode, rtx insn, 1663 HOST_WIDE_INT val, rtx target, rtx source, int subtargets) 1664{ 1665 rtx cond; 1666 1667 if (insn && GET_CODE (PATTERN (insn)) == COND_EXEC) 1668 cond = COND_EXEC_TEST (PATTERN (insn)); 1669 else 1670 cond = NULL_RTX; 1671 1672 if (subtargets || code == SET 1673 || (GET_CODE (target) == REG && GET_CODE (source) == REG 1674 && REGNO (target) != REGNO (source))) 1675 { 1676 /* After arm_reorg has been called, we can't fix up expensive 1677 constants by pushing them into memory so we must synthesize 1678 them in-line, regardless of the cost. This is only likely to 1679 be more costly on chips that have load delay slots and we are 1680 compiling without running the scheduler (so no splitting 1681 occurred before the final instruction emission). 1682 1683 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c 1684 */ 1685 if (!after_arm_reorg 1686 && !cond 1687 && (arm_gen_constant (code, mode, NULL_RTX, val, target, source, 1688 1, 0) 1689 > arm_constant_limit + (code != SET))) 1690 { 1691 if (code == SET) 1692 { 1693 /* Currently SET is the only monadic value for CODE, all 1694 the rest are diadic. */ 1695 emit_set_insn (target, GEN_INT (val)); 1696 return 1; 1697 } 1698 else 1699 { 1700 rtx temp = subtargets ? gen_reg_rtx (mode) : target; 1701 1702 emit_set_insn (temp, GEN_INT (val)); 1703 /* For MINUS, the value is subtracted from, since we never 1704 have subtraction of a constant. */ 1705 if (code == MINUS) 1706 emit_set_insn (target, gen_rtx_MINUS (mode, temp, source)); 1707 else 1708 emit_set_insn (target, 1709 gen_rtx_fmt_ee (code, mode, source, temp)); 1710 return 2; 1711 } 1712 } 1713 } 1714 1715 return arm_gen_constant (code, mode, cond, val, target, source, subtargets, 1716 1); 1717} 1718 1719static int 1720count_insns_for_constant (HOST_WIDE_INT remainder, int i) 1721{ 1722 HOST_WIDE_INT temp1; 1723 int num_insns = 0; 1724 do 1725 { 1726 int end; 1727 1728 if (i <= 0) 1729 i += 32; 1730 if (remainder & (3 << (i - 2))) 1731 { 1732 end = i - 8; 1733 if (end < 0) 1734 end += 32; 1735 temp1 = remainder & ((0x0ff << end) 1736 | ((i < end) ? (0xff >> (32 - end)) : 0)); 1737 remainder &= ~temp1; 1738 num_insns++; 1739 i -= 6; 1740 } 1741 i -= 2; 1742 } while (remainder); 1743 return num_insns; 1744} 1745 1746/* Emit an instruction with the indicated PATTERN. If COND is 1747 non-NULL, conditionalize the execution of the instruction on COND 1748 being true. */ 1749 1750static void 1751emit_constant_insn (rtx cond, rtx pattern) 1752{ 1753 if (cond) 1754 pattern = gen_rtx_COND_EXEC (VOIDmode, copy_rtx (cond), pattern); 1755 emit_insn (pattern); 1756} 1757 1758/* As above, but extra parameter GENERATE which, if clear, suppresses 1759 RTL generation. */ 1760 1761static int 1762arm_gen_constant (enum rtx_code code, enum machine_mode mode, rtx cond, 1763 HOST_WIDE_INT val, rtx target, rtx source, int subtargets, 1764 int generate) 1765{ 1766 int can_invert = 0; 1767 int can_negate = 0; 1768 int can_negate_initial = 0; 1769 int can_shift = 0; 1770 int i; 1771 int num_bits_set = 0; 1772 int set_sign_bit_copies = 0; 1773 int clear_sign_bit_copies = 0; 1774 int clear_zero_bit_copies = 0; 1775 int set_zero_bit_copies = 0; 1776 int insns = 0; 1777 unsigned HOST_WIDE_INT temp1, temp2; 1778 unsigned HOST_WIDE_INT remainder = val & 0xffffffff; 1779 1780 /* Find out which operations are safe for a given CODE. Also do a quick 1781 check for degenerate cases; these can occur when DImode operations 1782 are split. */ 1783 switch (code) 1784 { 1785 case SET: 1786 can_invert = 1; 1787 can_shift = 1; 1788 can_negate = 1; 1789 break; 1790 1791 case PLUS: 1792 can_negate = 1; 1793 can_negate_initial = 1; 1794 break; 1795 1796 case IOR: 1797 if (remainder == 0xffffffff) 1798 { 1799 if (generate) 1800 emit_constant_insn (cond, 1801 gen_rtx_SET (VOIDmode, target, 1802 GEN_INT (ARM_SIGN_EXTEND (val)))); 1803 return 1; 1804 } 1805 if (remainder == 0) 1806 { 1807 if (reload_completed && rtx_equal_p (target, source)) 1808 return 0; 1809 if (generate) 1810 emit_constant_insn (cond, 1811 gen_rtx_SET (VOIDmode, target, source)); 1812 return 1; 1813 } 1814 break; 1815 1816 case AND: 1817 if (remainder == 0) 1818 { 1819 if (generate) 1820 emit_constant_insn (cond, 1821 gen_rtx_SET (VOIDmode, target, const0_rtx)); 1822 return 1; 1823 } 1824 if (remainder == 0xffffffff) 1825 { 1826 if (reload_completed && rtx_equal_p (target, source)) 1827 return 0; 1828 if (generate) 1829 emit_constant_insn (cond, 1830 gen_rtx_SET (VOIDmode, target, source)); 1831 return 1; 1832 } 1833 can_invert = 1; 1834 break; 1835 1836 case XOR: 1837 if (remainder == 0) 1838 { 1839 if (reload_completed && rtx_equal_p (target, source)) 1840 return 0; 1841 if (generate) 1842 emit_constant_insn (cond, 1843 gen_rtx_SET (VOIDmode, target, source)); 1844 return 1; 1845 } 1846 1847 /* We don't know how to handle other cases yet. */ 1848 gcc_assert (remainder == 0xffffffff); 1849 1850 if (generate) 1851 emit_constant_insn (cond, 1852 gen_rtx_SET (VOIDmode, target, 1853 gen_rtx_NOT (mode, source))); 1854 return 1; 1855 1856 case MINUS: 1857 /* We treat MINUS as (val - source), since (source - val) is always 1858 passed as (source + (-val)). */ 1859 if (remainder == 0) 1860 { 1861 if (generate) 1862 emit_constant_insn (cond, 1863 gen_rtx_SET (VOIDmode, target, 1864 gen_rtx_NEG (mode, source))); 1865 return 1; 1866 } 1867 if (const_ok_for_arm (val)) 1868 { 1869 if (generate) 1870 emit_constant_insn (cond, 1871 gen_rtx_SET (VOIDmode, target, 1872 gen_rtx_MINUS (mode, GEN_INT (val), 1873 source))); 1874 return 1; 1875 } 1876 can_negate = 1; 1877 1878 break; 1879 1880 default: 1881 gcc_unreachable (); 1882 } 1883 1884 /* If we can do it in one insn get out quickly. */ 1885 if (const_ok_for_arm (val) 1886 || (can_negate_initial && const_ok_for_arm (-val)) 1887 || (can_invert && const_ok_for_arm (~val))) 1888 { 1889 if (generate) 1890 emit_constant_insn (cond, 1891 gen_rtx_SET (VOIDmode, target, 1892 (source 1893 ? gen_rtx_fmt_ee (code, mode, source, 1894 GEN_INT (val)) 1895 : GEN_INT (val)))); 1896 return 1; 1897 } 1898 1899 /* Calculate a few attributes that may be useful for specific 1900 optimizations. */ 1901 for (i = 31; i >= 0; i--) 1902 { 1903 if ((remainder & (1 << i)) == 0) 1904 clear_sign_bit_copies++; 1905 else 1906 break; 1907 } 1908 1909 for (i = 31; i >= 0; i--) 1910 { 1911 if ((remainder & (1 << i)) != 0) 1912 set_sign_bit_copies++; 1913 else 1914 break; 1915 } 1916 1917 for (i = 0; i <= 31; i++) 1918 { 1919 if ((remainder & (1 << i)) == 0) 1920 clear_zero_bit_copies++; 1921 else 1922 break; 1923 } 1924 1925 for (i = 0; i <= 31; i++) 1926 { 1927 if ((remainder & (1 << i)) != 0) 1928 set_zero_bit_copies++; 1929 else 1930 break; 1931 } 1932 1933 switch (code) 1934 { 1935 case SET: 1936 /* See if we can do this by sign_extending a constant that is known 1937 to be negative. This is a good, way of doing it, since the shift 1938 may well merge into a subsequent insn. */ 1939 if (set_sign_bit_copies > 1) 1940 { 1941 if (const_ok_for_arm 1942 (temp1 = ARM_SIGN_EXTEND (remainder 1943 << (set_sign_bit_copies - 1)))) 1944 { 1945 if (generate) 1946 { 1947 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1948 emit_constant_insn (cond, 1949 gen_rtx_SET (VOIDmode, new_src, 1950 GEN_INT (temp1))); 1951 emit_constant_insn (cond, 1952 gen_ashrsi3 (target, new_src, 1953 GEN_INT (set_sign_bit_copies - 1))); 1954 } 1955 return 2; 1956 } 1957 /* For an inverted constant, we will need to set the low bits, 1958 these will be shifted out of harm's way. */ 1959 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; 1960 if (const_ok_for_arm (~temp1)) 1961 { 1962 if (generate) 1963 { 1964 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1965 emit_constant_insn (cond, 1966 gen_rtx_SET (VOIDmode, new_src, 1967 GEN_INT (temp1))); 1968 emit_constant_insn (cond, 1969 gen_ashrsi3 (target, new_src, 1970 GEN_INT (set_sign_bit_copies - 1))); 1971 } 1972 return 2; 1973 } 1974 } 1975 1976 /* See if we can calculate the value as the difference between two 1977 valid immediates. */ 1978 if (clear_sign_bit_copies + clear_zero_bit_copies <= 16) 1979 { 1980 int topshift = clear_sign_bit_copies & ~1; 1981 1982 temp1 = ARM_SIGN_EXTEND ((remainder + (0x00800000 >> topshift)) 1983 & (0xff000000 >> topshift)); 1984 1985 /* If temp1 is zero, then that means the 9 most significant 1986 bits of remainder were 1 and we've caused it to overflow. 1987 When topshift is 0 we don't need to do anything since we 1988 can borrow from 'bit 32'. */ 1989 if (temp1 == 0 && topshift != 0) 1990 temp1 = 0x80000000 >> (topshift - 1); 1991 1992 temp2 = ARM_SIGN_EXTEND (temp1 - remainder); 1993 1994 if (const_ok_for_arm (temp2)) 1995 { 1996 if (generate) 1997 { 1998 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1999 emit_constant_insn (cond, 2000 gen_rtx_SET (VOIDmode, new_src, 2001 GEN_INT (temp1))); 2002 emit_constant_insn (cond, 2003 gen_addsi3 (target, new_src, 2004 GEN_INT (-temp2))); 2005 } 2006 2007 return 2; 2008 } 2009 } 2010 2011 /* See if we can generate this by setting the bottom (or the top) 2012 16 bits, and then shifting these into the other half of the 2013 word. We only look for the simplest cases, to do more would cost 2014 too much. Be careful, however, not to generate this when the 2015 alternative would take fewer insns. */ 2016 if (val & 0xffff0000) 2017 { 2018 temp1 = remainder & 0xffff0000; 2019 temp2 = remainder & 0x0000ffff; 2020 2021 /* Overlaps outside this range are best done using other methods. */ 2022 for (i = 9; i < 24; i++) 2023 { 2024 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) 2025 && !const_ok_for_arm (temp2)) 2026 { 2027 rtx new_src = (subtargets 2028 ? (generate ? gen_reg_rtx (mode) : NULL_RTX) 2029 : target); 2030 insns = arm_gen_constant (code, mode, cond, temp2, new_src, 2031 source, subtargets, generate); 2032 source = new_src; 2033 if (generate) 2034 emit_constant_insn 2035 (cond, 2036 gen_rtx_SET 2037 (VOIDmode, target, 2038 gen_rtx_IOR (mode, 2039 gen_rtx_ASHIFT (mode, source, 2040 GEN_INT (i)), 2041 source))); 2042 return insns + 1; 2043 } 2044 } 2045 2046 /* Don't duplicate cases already considered. */ 2047 for (i = 17; i < 24; i++) 2048 { 2049 if (((temp1 | (temp1 >> i)) == remainder) 2050 && !const_ok_for_arm (temp1)) 2051 { 2052 rtx new_src = (subtargets 2053 ? (generate ? gen_reg_rtx (mode) : NULL_RTX) 2054 : target); 2055 insns = arm_gen_constant (code, mode, cond, temp1, new_src, 2056 source, subtargets, generate); 2057 source = new_src; 2058 if (generate) 2059 emit_constant_insn 2060 (cond, 2061 gen_rtx_SET (VOIDmode, target, 2062 gen_rtx_IOR 2063 (mode, 2064 gen_rtx_LSHIFTRT (mode, source, 2065 GEN_INT (i)), 2066 source))); 2067 return insns + 1; 2068 } 2069 } 2070 } 2071 break; 2072 2073 case IOR: 2074 case XOR: 2075 /* If we have IOR or XOR, and the constant can be loaded in a 2076 single instruction, and we can find a temporary to put it in, 2077 then this can be done in two instructions instead of 3-4. */ 2078 if (subtargets 2079 /* TARGET can't be NULL if SUBTARGETS is 0 */ 2080 || (reload_completed && !reg_mentioned_p (target, source))) 2081 { 2082 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) 2083 { 2084 if (generate) 2085 { 2086 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 2087 2088 emit_constant_insn (cond, 2089 gen_rtx_SET (VOIDmode, sub, 2090 GEN_INT (val))); 2091 emit_constant_insn (cond, 2092 gen_rtx_SET (VOIDmode, target, 2093 gen_rtx_fmt_ee (code, mode, 2094 source, sub))); 2095 } 2096 return 2; 2097 } 2098 } 2099 2100 if (code == XOR) 2101 break; 2102 2103 if (set_sign_bit_copies > 8 2104 && (val & (-1 << (32 - set_sign_bit_copies))) == val) 2105 { 2106 if (generate) 2107 { 2108 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 2109 rtx shift = GEN_INT (set_sign_bit_copies); 2110 2111 emit_constant_insn 2112 (cond, 2113 gen_rtx_SET (VOIDmode, sub, 2114 gen_rtx_NOT (mode, 2115 gen_rtx_ASHIFT (mode, 2116 source, 2117 shift)))); 2118 emit_constant_insn 2119 (cond, 2120 gen_rtx_SET (VOIDmode, target, 2121 gen_rtx_NOT (mode, 2122 gen_rtx_LSHIFTRT (mode, sub, 2123 shift)))); 2124 } 2125 return 2; 2126 } 2127 2128 if (set_zero_bit_copies > 8 2129 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) 2130 { 2131 if (generate) 2132 { 2133 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 2134 rtx shift = GEN_INT (set_zero_bit_copies); 2135 2136 emit_constant_insn 2137 (cond, 2138 gen_rtx_SET (VOIDmode, sub, 2139 gen_rtx_NOT (mode, 2140 gen_rtx_LSHIFTRT (mode, 2141 source, 2142 shift)))); 2143 emit_constant_insn 2144 (cond, 2145 gen_rtx_SET (VOIDmode, target, 2146 gen_rtx_NOT (mode, 2147 gen_rtx_ASHIFT (mode, sub, 2148 shift)))); 2149 } 2150 return 2; 2151 } 2152 2153 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) 2154 { 2155 if (generate) 2156 { 2157 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 2158 emit_constant_insn (cond, 2159 gen_rtx_SET (VOIDmode, sub, 2160 gen_rtx_NOT (mode, source))); 2161 source = sub; 2162 if (subtargets) 2163 sub = gen_reg_rtx (mode); 2164 emit_constant_insn (cond, 2165 gen_rtx_SET (VOIDmode, sub, 2166 gen_rtx_AND (mode, source, 2167 GEN_INT (temp1)))); 2168 emit_constant_insn (cond, 2169 gen_rtx_SET (VOIDmode, target, 2170 gen_rtx_NOT (mode, sub))); 2171 } 2172 return 3; 2173 } 2174 break; 2175 2176 case AND: 2177 /* See if two shifts will do 2 or more insn's worth of work. */ 2178 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) 2179 { 2180 HOST_WIDE_INT shift_mask = ((0xffffffff 2181 << (32 - clear_sign_bit_copies)) 2182 & 0xffffffff); 2183 2184 if ((remainder | shift_mask) != 0xffffffff) 2185 { 2186 if (generate) 2187 { 2188 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 2189 insns = arm_gen_constant (AND, mode, cond, 2190 remainder | shift_mask, 2191 new_src, source, subtargets, 1); 2192 source = new_src; 2193 } 2194 else 2195 { 2196 rtx targ = subtargets ? NULL_RTX : target; 2197 insns = arm_gen_constant (AND, mode, cond, 2198 remainder | shift_mask, 2199 targ, source, subtargets, 0); 2200 } 2201 } 2202 2203 if (generate) 2204 { 2205 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 2206 rtx shift = GEN_INT (clear_sign_bit_copies); 2207 2208 emit_insn (gen_ashlsi3 (new_src, source, shift)); 2209 emit_insn (gen_lshrsi3 (target, new_src, shift)); 2210 } 2211 2212 return insns + 2; 2213 } 2214 2215 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) 2216 { 2217 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; 2218 2219 if ((remainder | shift_mask) != 0xffffffff) 2220 { 2221 if (generate) 2222 { 2223 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 2224 2225 insns = arm_gen_constant (AND, mode, cond, 2226 remainder | shift_mask, 2227 new_src, source, subtargets, 1); 2228 source = new_src; 2229 } 2230 else 2231 { 2232 rtx targ = subtargets ? NULL_RTX : target; 2233 2234 insns = arm_gen_constant (AND, mode, cond, 2235 remainder | shift_mask, 2236 targ, source, subtargets, 0); 2237 } 2238 } 2239 2240 if (generate) 2241 { 2242 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 2243 rtx shift = GEN_INT (clear_zero_bit_copies); 2244 2245 emit_insn (gen_lshrsi3 (new_src, source, shift)); 2246 emit_insn (gen_ashlsi3 (target, new_src, shift)); 2247 } 2248 2249 return insns + 2; 2250 } 2251 2252 break; 2253 2254 default: 2255 break; 2256 } 2257 2258 for (i = 0; i < 32; i++) 2259 if (remainder & (1 << i)) 2260 num_bits_set++; 2261 2262 if (code == AND || (can_invert && num_bits_set > 16)) 2263 remainder = (~remainder) & 0xffffffff; 2264 else if (code == PLUS && num_bits_set > 16) 2265 remainder = (-remainder) & 0xffffffff; 2266 else 2267 { 2268 can_invert = 0; 2269 can_negate = 0; 2270 } 2271 2272 /* Now try and find a way of doing the job in either two or three 2273 instructions. 2274 We start by looking for the largest block of zeros that are aligned on 2275 a 2-bit boundary, we then fill up the temps, wrapping around to the 2276 top of the word when we drop off the bottom. 2277 In the worst case this code should produce no more than four insns. */ 2278 { 2279 int best_start = 0; 2280 int best_consecutive_zeros = 0; 2281 2282 for (i = 0; i < 32; i += 2) 2283 { 2284 int consecutive_zeros = 0; 2285 2286 if (!(remainder & (3 << i))) 2287 { 2288 while ((i < 32) && !(remainder & (3 << i))) 2289 { 2290 consecutive_zeros += 2; 2291 i += 2; 2292 } 2293 if (consecutive_zeros > best_consecutive_zeros) 2294 { 2295 best_consecutive_zeros = consecutive_zeros; 2296 best_start = i - consecutive_zeros; 2297 } 2298 i -= 2; 2299 } 2300 } 2301 2302 /* So long as it won't require any more insns to do so, it's 2303 desirable to emit a small constant (in bits 0...9) in the last 2304 insn. This way there is more chance that it can be combined with 2305 a later addressing insn to form a pre-indexed load or store 2306 operation. Consider: 2307 2308 *((volatile int *)0xe0000100) = 1; 2309 *((volatile int *)0xe0000110) = 2; 2310 2311 We want this to wind up as: 2312 2313 mov rA, #0xe0000000 2314 mov rB, #1 2315 str rB, [rA, #0x100] 2316 mov rB, #2 2317 str rB, [rA, #0x110] 2318 2319 rather than having to synthesize both large constants from scratch. 2320 2321 Therefore, we calculate how many insns would be required to emit 2322 the constant starting from `best_start', and also starting from 2323 zero (i.e. with bit 31 first to be output). If `best_start' doesn't 2324 yield a shorter sequence, we may as well use zero. */ 2325 if (best_start != 0 2326 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) 2327 && (count_insns_for_constant (remainder, 0) <= 2328 count_insns_for_constant (remainder, best_start))) 2329 best_start = 0; 2330 2331 /* Now start emitting the insns. */ 2332 i = best_start; 2333 do 2334 { 2335 int end; 2336 2337 if (i <= 0) 2338 i += 32; 2339 if (remainder & (3 << (i - 2))) 2340 { 2341 end = i - 8; 2342 if (end < 0) 2343 end += 32; 2344 temp1 = remainder & ((0x0ff << end) 2345 | ((i < end) ? (0xff >> (32 - end)) : 0)); 2346 remainder &= ~temp1; 2347 2348 if (generate) 2349 { 2350 rtx new_src, temp1_rtx; 2351 2352 if (code == SET || code == MINUS) 2353 { 2354 new_src = (subtargets ? gen_reg_rtx (mode) : target); 2355 if (can_invert && code != MINUS) 2356 temp1 = ~temp1; 2357 } 2358 else 2359 { 2360 if (remainder && subtargets) 2361 new_src = gen_reg_rtx (mode); 2362 else 2363 new_src = target; 2364 if (can_invert) 2365 temp1 = ~temp1; 2366 else if (can_negate) 2367 temp1 = -temp1; 2368 } 2369 2370 temp1 = trunc_int_for_mode (temp1, mode); 2371 temp1_rtx = GEN_INT (temp1); 2372 2373 if (code == SET) 2374 ; 2375 else if (code == MINUS) 2376 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); 2377 else 2378 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); 2379 2380 emit_constant_insn (cond, 2381 gen_rtx_SET (VOIDmode, new_src, 2382 temp1_rtx)); 2383 source = new_src; 2384 } 2385 2386 if (code == SET) 2387 { 2388 can_invert = 0; 2389 code = PLUS; 2390 } 2391 else if (code == MINUS) 2392 code = PLUS; 2393 2394 insns++; 2395 i -= 6; 2396 } 2397 i -= 2; 2398 } 2399 while (remainder); 2400 } 2401 2402 return insns; 2403} 2404 2405/* Canonicalize a comparison so that we are more likely to recognize it. 2406 This can be done for a few constant compares, where we can make the 2407 immediate value easier to load. */ 2408 2409enum rtx_code 2410arm_canonicalize_comparison (enum rtx_code code, enum machine_mode mode, 2411 rtx * op1) 2412{ 2413 unsigned HOST_WIDE_INT i = INTVAL (*op1); 2414 unsigned HOST_WIDE_INT maxval; 2415 maxval = (((unsigned HOST_WIDE_INT) 1) << (GET_MODE_BITSIZE(mode) - 1)) - 1; 2416 2417 switch (code) 2418 { 2419 case EQ: 2420 case NE: 2421 return code; 2422 2423 case GT: 2424 case LE: 2425 if (i != maxval 2426 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) 2427 { 2428 *op1 = GEN_INT (i + 1); 2429 return code == GT ? GE : LT; 2430 } 2431 break; 2432 2433 case GE: 2434 case LT: 2435 if (i != ~maxval 2436 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) 2437 { 2438 *op1 = GEN_INT (i - 1); 2439 return code == GE ? GT : LE; 2440 } 2441 break; 2442 2443 case GTU: 2444 case LEU: 2445 if (i != ~((unsigned HOST_WIDE_INT) 0) 2446 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) 2447 { 2448 *op1 = GEN_INT (i + 1); 2449 return code == GTU ? GEU : LTU; 2450 } 2451 break; 2452 2453 case GEU: 2454 case LTU: 2455 if (i != 0 2456 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) 2457 { 2458 *op1 = GEN_INT (i - 1); 2459 return code == GEU ? GTU : LEU; 2460 } 2461 break; 2462 2463 default: 2464 gcc_unreachable (); 2465 } 2466 2467 return code; 2468} 2469 2470 2471/* Define how to find the value returned by a function. */ 2472 2473rtx 2474arm_function_value(tree type, tree func ATTRIBUTE_UNUSED) 2475{ 2476 enum machine_mode mode; 2477 int unsignedp ATTRIBUTE_UNUSED; 2478 rtx r ATTRIBUTE_UNUSED; 2479 2480 mode = TYPE_MODE (type); 2481 /* Promote integer types. */ 2482 if (INTEGRAL_TYPE_P (type)) 2483 PROMOTE_FUNCTION_MODE (mode, unsignedp, type); 2484 2485 /* Promotes small structs returned in a register to full-word size 2486 for big-endian AAPCS. */ 2487 if (arm_return_in_msb (type)) 2488 { 2489 HOST_WIDE_INT size = int_size_in_bytes (type); 2490 if (size % UNITS_PER_WORD != 0) 2491 { 2492 size += UNITS_PER_WORD - size % UNITS_PER_WORD; 2493 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); 2494 } 2495 } 2496 2497 return LIBCALL_VALUE(mode); 2498} 2499 2500/* Determine the amount of memory needed to store the possible return 2501 registers of an untyped call. */ 2502int 2503arm_apply_result_size (void) 2504{ 2505 int size = 16; 2506 2507 if (TARGET_ARM) 2508 { 2509 if (TARGET_HARD_FLOAT_ABI) 2510 { 2511 if (TARGET_FPA) 2512 size += 12; 2513 if (TARGET_MAVERICK) 2514 size += 8; 2515 } 2516 if (TARGET_IWMMXT_ABI) 2517 size += 8; 2518 } 2519 2520 return size; 2521} 2522 2523/* Decide whether a type should be returned in memory (true) 2524 or in a register (false). This is called by the macro 2525 RETURN_IN_MEMORY. */ 2526int 2527arm_return_in_memory (tree type) 2528{ 2529 HOST_WIDE_INT size; 2530 2531 if (!AGGREGATE_TYPE_P (type) && 2532 (TREE_CODE (type) != VECTOR_TYPE) && 2533 !(TARGET_AAPCS_BASED && TREE_CODE (type) == COMPLEX_TYPE)) 2534 /* All simple types are returned in registers. 2535 For AAPCS, complex types are treated the same as aggregates. */ 2536 return 0; 2537 2538 size = int_size_in_bytes (type); 2539 2540 if (arm_abi != ARM_ABI_APCS) 2541 { 2542 /* ATPCS and later return aggregate types in memory only if they are 2543 larger than a word (or are variable size). */ 2544 return (size < 0 || size > UNITS_PER_WORD); 2545 } 2546 2547 /* To maximize backwards compatibility with previous versions of gcc, 2548 return vectors up to 4 words in registers. */ 2549 if (TREE_CODE (type) == VECTOR_TYPE) 2550 return (size < 0 || size > (4 * UNITS_PER_WORD)); 2551 2552 /* For the arm-wince targets we choose to be compatible with Microsoft's 2553 ARM and Thumb compilers, which always return aggregates in memory. */ 2554#ifndef ARM_WINCE 2555 /* All structures/unions bigger than one word are returned in memory. 2556 Also catch the case where int_size_in_bytes returns -1. In this case 2557 the aggregate is either huge or of variable size, and in either case 2558 we will want to return it via memory and not in a register. */ 2559 if (size < 0 || size > UNITS_PER_WORD) 2560 return 1; 2561 2562 if (TREE_CODE (type) == RECORD_TYPE) 2563 { 2564 tree field; 2565 2566 /* For a struct the APCS says that we only return in a register 2567 if the type is 'integer like' and every addressable element 2568 has an offset of zero. For practical purposes this means 2569 that the structure can have at most one non bit-field element 2570 and that this element must be the first one in the structure. */ 2571 2572 /* Find the first field, ignoring non FIELD_DECL things which will 2573 have been created by C++. */ 2574 for (field = TYPE_FIELDS (type); 2575 field && TREE_CODE (field) != FIELD_DECL; 2576 field = TREE_CHAIN (field)) 2577 continue; 2578 2579 if (field == NULL) 2580 return 0; /* An empty structure. Allowed by an extension to ANSI C. */ 2581 2582 /* Check that the first field is valid for returning in a register. */ 2583 2584 /* ... Floats are not allowed */ 2585 if (FLOAT_TYPE_P (TREE_TYPE (field))) 2586 return 1; 2587 2588 /* ... Aggregates that are not themselves valid for returning in 2589 a register are not allowed. */ 2590 if (RETURN_IN_MEMORY (TREE_TYPE (field))) 2591 return 1; 2592 2593 /* Now check the remaining fields, if any. Only bitfields are allowed, 2594 since they are not addressable. */ 2595 for (field = TREE_CHAIN (field); 2596 field; 2597 field = TREE_CHAIN (field)) 2598 { 2599 if (TREE_CODE (field) != FIELD_DECL) 2600 continue; 2601 2602 if (!DECL_BIT_FIELD_TYPE (field)) 2603 return 1; 2604 } 2605 2606 return 0; 2607 } 2608 2609 if (TREE_CODE (type) == UNION_TYPE) 2610 { 2611 tree field; 2612 2613 /* Unions can be returned in registers if every element is 2614 integral, or can be returned in an integer register. */ 2615 for (field = TYPE_FIELDS (type); 2616 field; 2617 field = TREE_CHAIN (field)) 2618 { 2619 if (TREE_CODE (field) != FIELD_DECL) 2620 continue; 2621 2622 if (FLOAT_TYPE_P (TREE_TYPE (field))) 2623 return 1; 2624 2625 if (RETURN_IN_MEMORY (TREE_TYPE (field))) 2626 return 1; 2627 } 2628 2629 return 0; 2630 } 2631#endif /* not ARM_WINCE */ 2632 2633 /* Return all other types in memory. */ 2634 return 1; 2635} 2636 2637/* Indicate whether or not words of a double are in big-endian order. */ 2638 2639int 2640arm_float_words_big_endian (void) 2641{ 2642 if (TARGET_MAVERICK) 2643 return 0; 2644 2645 /* For FPA, float words are always big-endian. For VFP, floats words 2646 follow the memory system mode. */ 2647 2648 if (TARGET_FPA) 2649 { 2650 return 1; 2651 } 2652 2653 if (TARGET_VFP) 2654 return (TARGET_BIG_END ? 1 : 0); 2655 2656 return 1; 2657} 2658 2659/* Initialize a variable CUM of type CUMULATIVE_ARGS 2660 for a call to a function whose data type is FNTYPE. 2661 For a library call, FNTYPE is NULL. */ 2662void 2663arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, 2664 rtx libname ATTRIBUTE_UNUSED, 2665 tree fndecl ATTRIBUTE_UNUSED) 2666{ 2667 /* On the ARM, the offset starts at 0. */ 2668 pcum->nregs = 0; 2669 pcum->iwmmxt_nregs = 0; 2670 pcum->can_split = true; 2671 2672 pcum->call_cookie = CALL_NORMAL; 2673 2674 if (TARGET_LONG_CALLS) 2675 pcum->call_cookie = CALL_LONG; 2676 2677 /* Check for long call/short call attributes. The attributes 2678 override any command line option. */ 2679 if (fntype) 2680 { 2681 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype))) 2682 pcum->call_cookie = CALL_SHORT; 2683 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype))) 2684 pcum->call_cookie = CALL_LONG; 2685 } 2686 2687 /* Varargs vectors are treated the same as long long. 2688 named_count avoids having to change the way arm handles 'named' */ 2689 pcum->named_count = 0; 2690 pcum->nargs = 0; 2691 2692 if (TARGET_REALLY_IWMMXT && fntype) 2693 { 2694 tree fn_arg; 2695 2696 for (fn_arg = TYPE_ARG_TYPES (fntype); 2697 fn_arg; 2698 fn_arg = TREE_CHAIN (fn_arg)) 2699 pcum->named_count += 1; 2700 2701 if (! pcum->named_count) 2702 pcum->named_count = INT_MAX; 2703 } 2704} 2705 2706 2707/* Return true if mode/type need doubleword alignment. */ 2708bool 2709arm_needs_doubleword_align (enum machine_mode mode, tree type) 2710{ 2711 return (GET_MODE_ALIGNMENT (mode) > PARM_BOUNDARY 2712 || (type && TYPE_ALIGN (type) > PARM_BOUNDARY)); 2713} 2714 2715 2716/* Determine where to put an argument to a function. 2717 Value is zero to push the argument on the stack, 2718 or a hard register in which to store the argument. 2719 2720 MODE is the argument's machine mode. 2721 TYPE is the data type of the argument (as a tree). 2722 This is null for libcalls where that information may 2723 not be available. 2724 CUM is a variable of type CUMULATIVE_ARGS which gives info about 2725 the preceding args and about the function being called. 2726 NAMED is nonzero if this argument is a named parameter 2727 (otherwise it is an extra parameter matching an ellipsis). */ 2728 2729rtx 2730arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, 2731 tree type, int named) 2732{ 2733 int nregs; 2734 2735 /* Varargs vectors are treated the same as long long. 2736 named_count avoids having to change the way arm handles 'named' */ 2737 if (TARGET_IWMMXT_ABI 2738 && arm_vector_mode_supported_p (mode) 2739 && pcum->named_count > pcum->nargs + 1) 2740 { 2741 if (pcum->iwmmxt_nregs <= 9) 2742 return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); 2743 else 2744 { 2745 pcum->can_split = false; 2746 return NULL_RTX; 2747 } 2748 } 2749 2750 /* Put doubleword aligned quantities in even register pairs. */ 2751 if (pcum->nregs & 1 2752 && ARM_DOUBLEWORD_ALIGN 2753 && arm_needs_doubleword_align (mode, type)) 2754 pcum->nregs++; 2755 2756 if (mode == VOIDmode) 2757 /* Compute operand 2 of the call insn. */ 2758 return GEN_INT (pcum->call_cookie); 2759 2760 /* Only allow splitting an arg between regs and memory if all preceding 2761 args were allocated to regs. For args passed by reference we only count 2762 the reference pointer. */ 2763 if (pcum->can_split) 2764 nregs = 1; 2765 else 2766 nregs = ARM_NUM_REGS2 (mode, type); 2767 2768 if (!named || pcum->nregs + nregs > NUM_ARG_REGS) 2769 return NULL_RTX; 2770 2771 return gen_rtx_REG (mode, pcum->nregs); 2772} 2773 2774static int 2775arm_arg_partial_bytes (CUMULATIVE_ARGS *pcum, enum machine_mode mode, 2776 tree type, bool named ATTRIBUTE_UNUSED) 2777{ 2778 int nregs = pcum->nregs; 2779 2780 if (arm_vector_mode_supported_p (mode)) 2781 return 0; 2782 2783 if (NUM_ARG_REGS > nregs 2784 && (NUM_ARG_REGS < nregs + ARM_NUM_REGS2 (mode, type)) 2785 && pcum->can_split) 2786 return (NUM_ARG_REGS - nregs) * UNITS_PER_WORD; 2787 2788 return 0; 2789} 2790 2791/* Variable sized types are passed by reference. This is a GCC 2792 extension to the ARM ABI. */ 2793 2794static bool 2795arm_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, 2796 enum machine_mode mode ATTRIBUTE_UNUSED, 2797 tree type, bool named ATTRIBUTE_UNUSED) 2798{ 2799 return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; 2800} 2801 2802/* Encode the current state of the #pragma [no_]long_calls. */ 2803typedef enum 2804{ 2805 OFF, /* No #pragma [no_]long_calls is in effect. */ 2806 LONG, /* #pragma long_calls is in effect. */ 2807 SHORT /* #pragma no_long_calls is in effect. */ 2808} arm_pragma_enum; 2809 2810static arm_pragma_enum arm_pragma_long_calls = OFF; 2811 2812void 2813arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) 2814{ 2815 arm_pragma_long_calls = LONG; 2816} 2817 2818void 2819arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) 2820{ 2821 arm_pragma_long_calls = SHORT; 2822} 2823 2824void 2825arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED) 2826{ 2827 arm_pragma_long_calls = OFF; 2828} 2829 2830/* Table of machine attributes. */ 2831const struct attribute_spec arm_attribute_table[] = 2832{ 2833 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ 2834 /* Function calls made to this symbol must be done indirectly, because 2835 it may lie outside of the 26 bit addressing range of a normal function 2836 call. */ 2837 { "long_call", 0, 0, false, true, true, NULL }, 2838 /* Whereas these functions are always known to reside within the 26 bit 2839 addressing range. */ 2840 { "short_call", 0, 0, false, true, true, NULL }, 2841 /* Interrupt Service Routines have special prologue and epilogue requirements. */ 2842 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, 2843 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, 2844 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, 2845#ifdef ARM_PE 2846 /* ARM/PE has three new attributes: 2847 interfacearm - ? 2848 dllexport - for exporting a function/variable that will live in a dll 2849 dllimport - for importing a function/variable from a dll 2850 2851 Microsoft allows multiple declspecs in one __declspec, separating 2852 them with spaces. We do NOT support this. Instead, use __declspec 2853 multiple times. 2854 */ 2855 { "dllimport", 0, 0, true, false, false, NULL }, 2856 { "dllexport", 0, 0, true, false, false, NULL }, 2857 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, 2858#elif TARGET_DLLIMPORT_DECL_ATTRIBUTES 2859 { "dllimport", 0, 0, false, false, false, handle_dll_attribute }, 2860 { "dllexport", 0, 0, false, false, false, handle_dll_attribute }, 2861 { "notshared", 0, 0, false, true, false, arm_handle_notshared_attribute }, 2862#endif 2863 { NULL, 0, 0, false, false, false, NULL } 2864}; 2865 2866/* Handle an attribute requiring a FUNCTION_DECL; 2867 arguments as in struct attribute_spec.handler. */ 2868static tree 2869arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, 2870 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) 2871{ 2872 if (TREE_CODE (*node) != FUNCTION_DECL) 2873 { 2874 warning (OPT_Wattributes, "%qs attribute only applies to functions", 2875 IDENTIFIER_POINTER (name)); 2876 *no_add_attrs = true; 2877 } 2878 2879 return NULL_TREE; 2880} 2881 2882/* Handle an "interrupt" or "isr" attribute; 2883 arguments as in struct attribute_spec.handler. */ 2884static tree 2885arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, 2886 bool *no_add_attrs) 2887{ 2888 if (DECL_P (*node)) 2889 { 2890 if (TREE_CODE (*node) != FUNCTION_DECL) 2891 { 2892 warning (OPT_Wattributes, "%qs attribute only applies to functions", 2893 IDENTIFIER_POINTER (name)); 2894 *no_add_attrs = true; 2895 } 2896 /* FIXME: the argument if any is checked for type attributes; 2897 should it be checked for decl ones? */ 2898 } 2899 else 2900 { 2901 if (TREE_CODE (*node) == FUNCTION_TYPE 2902 || TREE_CODE (*node) == METHOD_TYPE) 2903 { 2904 if (arm_isr_value (args) == ARM_FT_UNKNOWN) 2905 { 2906 warning (OPT_Wattributes, "%qs attribute ignored", 2907 IDENTIFIER_POINTER (name)); 2908 *no_add_attrs = true; 2909 } 2910 } 2911 else if (TREE_CODE (*node) == POINTER_TYPE 2912 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE 2913 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) 2914 && arm_isr_value (args) != ARM_FT_UNKNOWN) 2915 { 2916 *node = build_variant_type_copy (*node); 2917 TREE_TYPE (*node) = build_type_attribute_variant 2918 (TREE_TYPE (*node), 2919 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); 2920 *no_add_attrs = true; 2921 } 2922 else 2923 { 2924 /* Possibly pass this attribute on from the type to a decl. */ 2925 if (flags & ((int) ATTR_FLAG_DECL_NEXT 2926 | (int) ATTR_FLAG_FUNCTION_NEXT 2927 | (int) ATTR_FLAG_ARRAY_NEXT)) 2928 { 2929 *no_add_attrs = true; 2930 return tree_cons (name, args, NULL_TREE); 2931 } 2932 else 2933 { 2934 warning (OPT_Wattributes, "%qs attribute ignored", 2935 IDENTIFIER_POINTER (name)); 2936 } 2937 } 2938 } 2939 2940 return NULL_TREE; 2941} 2942 2943#if TARGET_DLLIMPORT_DECL_ATTRIBUTES 2944/* Handle the "notshared" attribute. This attribute is another way of 2945 requesting hidden visibility. ARM's compiler supports 2946 "__declspec(notshared)"; we support the same thing via an 2947 attribute. */ 2948 2949static tree 2950arm_handle_notshared_attribute (tree *node, 2951 tree name ATTRIBUTE_UNUSED, 2952 tree args ATTRIBUTE_UNUSED, 2953 int flags ATTRIBUTE_UNUSED, 2954 bool *no_add_attrs) 2955{ 2956 tree decl = TYPE_NAME (*node); 2957 2958 if (decl) 2959 { 2960 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; 2961 DECL_VISIBILITY_SPECIFIED (decl) = 1; 2962 *no_add_attrs = false; 2963 } 2964 return NULL_TREE; 2965} 2966#endif 2967 2968/* Return 0 if the attributes for two types are incompatible, 1 if they 2969 are compatible, and 2 if they are nearly compatible (which causes a 2970 warning to be generated). */ 2971static int 2972arm_comp_type_attributes (tree type1, tree type2) 2973{ 2974 int l1, l2, s1, s2; 2975 2976 /* Check for mismatch of non-default calling convention. */ 2977 if (TREE_CODE (type1) != FUNCTION_TYPE) 2978 return 1; 2979 2980 /* Check for mismatched call attributes. */ 2981 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; 2982 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; 2983 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; 2984 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; 2985 2986 /* Only bother to check if an attribute is defined. */ 2987 if (l1 | l2 | s1 | s2) 2988 { 2989 /* If one type has an attribute, the other must have the same attribute. */ 2990 if ((l1 != l2) || (s1 != s2)) 2991 return 0; 2992 2993 /* Disallow mixed attributes. */ 2994 if ((l1 & s2) || (l2 & s1)) 2995 return 0; 2996 } 2997 2998 /* Check for mismatched ISR attribute. */ 2999 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; 3000 if (! l1) 3001 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; 3002 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; 3003 if (! l2) 3004 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; 3005 if (l1 != l2) 3006 return 0; 3007 3008 return 1; 3009} 3010 3011/* Encode long_call or short_call attribute by prefixing 3012 symbol name in DECL with a special character FLAG. */ 3013void 3014arm_encode_call_attribute (tree decl, int flag) 3015{ 3016 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0); 3017 int len = strlen (str); 3018 char * newstr; 3019 3020 /* Do not allow weak functions to be treated as short call. */ 3021 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR) 3022 return; 3023 3024 newstr = alloca (len + 2); 3025 newstr[0] = flag; 3026 strcpy (newstr + 1, str); 3027 3028 newstr = (char *) ggc_alloc_string (newstr, len + 1); 3029 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr; 3030} 3031 3032/* Assigns default attributes to newly defined type. This is used to 3033 set short_call/long_call attributes for function types of 3034 functions defined inside corresponding #pragma scopes. */ 3035static void 3036arm_set_default_type_attributes (tree type) 3037{ 3038 /* Add __attribute__ ((long_call)) to all functions, when 3039 inside #pragma long_calls or __attribute__ ((short_call)), 3040 when inside #pragma no_long_calls. */ 3041 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) 3042 { 3043 tree type_attr_list, attr_name; 3044 type_attr_list = TYPE_ATTRIBUTES (type); 3045 3046 if (arm_pragma_long_calls == LONG) 3047 attr_name = get_identifier ("long_call"); 3048 else if (arm_pragma_long_calls == SHORT) 3049 attr_name = get_identifier ("short_call"); 3050 else 3051 return; 3052 3053 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); 3054 TYPE_ATTRIBUTES (type) = type_attr_list; 3055 } 3056} 3057 3058/* Return 1 if the operand is a SYMBOL_REF for a function known to be 3059 defined within the current compilation unit. If this cannot be 3060 determined, then 0 is returned. */ 3061static int 3062current_file_function_operand (rtx sym_ref) 3063{ 3064 /* This is a bit of a fib. A function will have a short call flag 3065 applied to its name if it has the short call attribute, or it has 3066 already been defined within the current compilation unit. */ 3067 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0))) 3068 return 1; 3069 3070 /* The current function is always defined within the current compilation 3071 unit. If it s a weak definition however, then this may not be the real 3072 definition of the function, and so we have to say no. */ 3073 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0) 3074 && !DECL_WEAK (current_function_decl)) 3075 return 1; 3076 3077 /* We cannot make the determination - default to returning 0. */ 3078 return 0; 3079} 3080 3081/* Return nonzero if a 32 bit "long_call" should be generated for 3082 this call. We generate a long_call if the function: 3083 3084 a. has an __attribute__((long call)) 3085 or b. is within the scope of a #pragma long_calls 3086 or c. the -mlong-calls command line switch has been specified 3087 . and either: 3088 1. -ffunction-sections is in effect 3089 or 2. the current function has __attribute__ ((section)) 3090 or 3. the target function has __attribute__ ((section)) 3091 3092 However we do not generate a long call if the function: 3093 3094 d. has an __attribute__ ((short_call)) 3095 or e. is inside the scope of a #pragma no_long_calls 3096 or f. is defined within the current compilation unit. 3097 3098 This function will be called by C fragments contained in the machine 3099 description file. SYM_REF and CALL_COOKIE correspond to the matched 3100 rtl operands. CALL_SYMBOL is used to distinguish between 3101 two different callers of the function. It is set to 1 in the 3102 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call" 3103 and "call_value" patterns. This is because of the difference in the 3104 SYM_REFs passed by these patterns. */ 3105int 3106arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol) 3107{ 3108 if (!call_symbol) 3109 { 3110 if (GET_CODE (sym_ref) != MEM) 3111 return 0; 3112 3113 sym_ref = XEXP (sym_ref, 0); 3114 } 3115 3116 if (GET_CODE (sym_ref) != SYMBOL_REF) 3117 return 0; 3118 3119 if (call_cookie & CALL_SHORT) 3120 return 0; 3121 3122 if (TARGET_LONG_CALLS) 3123 { 3124 if (flag_function_sections 3125 || DECL_SECTION_NAME (current_function_decl)) 3126 /* c.3 is handled by the definition of the 3127 ARM_DECLARE_FUNCTION_SIZE macro. */ 3128 return 1; 3129 } 3130 3131 if (current_file_function_operand (sym_ref)) 3132 return 0; 3133 3134 return (call_cookie & CALL_LONG) 3135 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0)) 3136 || TARGET_LONG_CALLS; 3137} 3138 3139/* Return nonzero if it is ok to make a tail-call to DECL. */ 3140static bool 3141arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) 3142{ 3143 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL; 3144 3145 if (cfun->machine->sibcall_blocked) 3146 return false; 3147 3148 /* Never tailcall something for which we have no decl, or if we 3149 are in Thumb mode. */ 3150 if (decl == NULL || TARGET_THUMB) 3151 return false; 3152 3153 /* Get the calling method. */ 3154 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) 3155 call_type = CALL_SHORT; 3156 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) 3157 call_type = CALL_LONG; 3158 3159 /* Cannot tail-call to long calls, since these are out of range of 3160 a branch instruction. However, if not compiling PIC, we know 3161 we can reach the symbol if it is in this compilation unit. */ 3162 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl))) 3163 return false; 3164 3165 /* If we are interworking and the function is not declared static 3166 then we can't tail-call it unless we know that it exists in this 3167 compilation unit (since it might be a Thumb routine). */ 3168 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) 3169 return false; 3170 3171 /* Never tailcall from an ISR routine - it needs a special exit sequence. */ 3172 if (IS_INTERRUPT (arm_current_func_type ())) 3173 return false; 3174 3175 /* Everything else is ok. */ 3176 return true; 3177} 3178 3179 3180/* Addressing mode support functions. */ 3181 3182/* Return nonzero if X is a legitimate immediate operand when compiling 3183 for PIC. We know that X satisfies CONSTANT_P and flag_pic is true. */ 3184int 3185legitimate_pic_operand_p (rtx x) 3186{ 3187 if (GET_CODE (x) == SYMBOL_REF 3188 || (GET_CODE (x) == CONST 3189 && GET_CODE (XEXP (x, 0)) == PLUS 3190 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)) 3191 return 0; 3192 3193 return 1; 3194} 3195 3196rtx 3197legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) 3198{ 3199 if (GET_CODE (orig) == SYMBOL_REF 3200 || GET_CODE (orig) == LABEL_REF) 3201 { 3202#ifndef AOF_ASSEMBLER 3203 rtx pic_ref, address; 3204#endif 3205 rtx insn; 3206 int subregs = 0; 3207 3208 /* If this function doesn't have a pic register, create one now. 3209 A lot of the logic here is made obscure by the fact that this 3210 routine gets called as part of the rtx cost estimation 3211 process. We don't want those calls to affect any assumptions 3212 about the real function; and further, we can't call 3213 entry_of_function() until we start the real expansion 3214 process. */ 3215 if (!current_function_uses_pic_offset_table) 3216 { 3217 gcc_assert (!no_new_pseudos); 3218 if (arm_pic_register != INVALID_REGNUM) 3219 { 3220 cfun->machine->pic_reg = gen_rtx_REG (Pmode, arm_pic_register); 3221 3222 /* Play games to avoid marking the function as needing pic 3223 if we are being called as part of the cost-estimation 3224 process. */ 3225 if (!ir_type()) 3226 current_function_uses_pic_offset_table = 1; 3227 } 3228 else 3229 { 3230 rtx seq; 3231 3232 cfun->machine->pic_reg = gen_reg_rtx (Pmode); 3233 3234 /* Play games to avoid marking the function as needing pic 3235 if we are being called as part of the cost-estimation 3236 process. */ 3237 if (!ir_type()) 3238 { 3239 current_function_uses_pic_offset_table = 1; 3240 start_sequence (); 3241 3242 arm_load_pic_register (0UL); 3243 3244 seq = get_insns (); 3245 end_sequence (); 3246 emit_insn_after (seq, entry_of_function ()); 3247 } 3248 } 3249 } 3250 3251 if (reg == 0) 3252 { 3253 gcc_assert (!no_new_pseudos); 3254 reg = gen_reg_rtx (Pmode); 3255 3256 subregs = 1; 3257 } 3258 3259#ifdef AOF_ASSEMBLER 3260 /* The AOF assembler can generate relocations for these directly, and 3261 understands that the PIC register has to be added into the offset. */ 3262 insn = emit_insn (gen_pic_load_addr_based (reg, orig)); 3263#else 3264 if (subregs) 3265 address = gen_reg_rtx (Pmode); 3266 else 3267 address = reg; 3268 3269 if (TARGET_ARM) 3270 emit_insn (gen_pic_load_addr_arm (address, orig)); 3271 else 3272 emit_insn (gen_pic_load_addr_thumb (address, orig)); 3273 3274 if ((GET_CODE (orig) == LABEL_REF 3275 || (GET_CODE (orig) == SYMBOL_REF && 3276 SYMBOL_REF_LOCAL_P (orig))) 3277 && NEED_GOT_RELOC) 3278 pic_ref = gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, address); 3279 else 3280 { 3281 pic_ref = gen_const_mem (Pmode, 3282 gen_rtx_PLUS (Pmode, cfun->machine->pic_reg, 3283 address)); 3284 } 3285 3286 insn = emit_move_insn (reg, pic_ref); 3287#endif 3288 /* Put a REG_EQUAL note on this insn, so that it can be optimized 3289 by loop. */ 3290 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, 3291 REG_NOTES (insn)); 3292 return reg; 3293 } 3294 else if (GET_CODE (orig) == CONST) 3295 { 3296 rtx base, offset; 3297 3298 if (GET_CODE (XEXP (orig, 0)) == PLUS 3299 && XEXP (XEXP (orig, 0), 0) == cfun->machine->pic_reg) 3300 return orig; 3301 3302 if (GET_CODE (XEXP (orig, 0)) == UNSPEC 3303 && XINT (XEXP (orig, 0), 1) == UNSPEC_TLS) 3304 return orig; 3305 3306 if (reg == 0) 3307 { 3308 gcc_assert (!no_new_pseudos); 3309 reg = gen_reg_rtx (Pmode); 3310 } 3311 3312 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); 3313 3314 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); 3315 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, 3316 base == reg ? 0 : reg); 3317 3318 if (GET_CODE (offset) == CONST_INT) 3319 { 3320 /* The base register doesn't really matter, we only want to 3321 test the index for the appropriate mode. */ 3322 if (!arm_legitimate_index_p (mode, offset, SET, 0)) 3323 { 3324 gcc_assert (!no_new_pseudos); 3325 offset = force_reg (Pmode, offset); 3326 } 3327 3328 if (GET_CODE (offset) == CONST_INT) 3329 return plus_constant (base, INTVAL (offset)); 3330 } 3331 3332 if (GET_MODE_SIZE (mode) > 4 3333 && (GET_MODE_CLASS (mode) == MODE_INT 3334 || TARGET_SOFT_FLOAT)) 3335 { 3336 emit_insn (gen_addsi3 (reg, base, offset)); 3337 return reg; 3338 } 3339 3340 return gen_rtx_PLUS (Pmode, base, offset); 3341 } 3342 3343 return orig; 3344} 3345 3346 3347/* Find a spare low register to use during the prolog of a function. */ 3348 3349static int 3350thumb_find_work_register (unsigned long pushed_regs_mask) 3351{ 3352 int reg; 3353 3354 /* Check the argument registers first as these are call-used. The 3355 register allocation order means that sometimes r3 might be used 3356 but earlier argument registers might not, so check them all. */ 3357 for (reg = LAST_ARG_REGNUM; reg >= 0; reg --) 3358 if (!regs_ever_live[reg]) 3359 return reg; 3360 3361 /* Before going on to check the call-saved registers we can try a couple 3362 more ways of deducing that r3 is available. The first is when we are 3363 pushing anonymous arguments onto the stack and we have less than 4 3364 registers worth of fixed arguments(*). In this case r3 will be part of 3365 the variable argument list and so we can be sure that it will be 3366 pushed right at the start of the function. Hence it will be available 3367 for the rest of the prologue. 3368 (*): ie current_function_pretend_args_size is greater than 0. */ 3369 if (cfun->machine->uses_anonymous_args 3370 && current_function_pretend_args_size > 0) 3371 return LAST_ARG_REGNUM; 3372 3373 /* The other case is when we have fixed arguments but less than 4 registers 3374 worth. In this case r3 might be used in the body of the function, but 3375 it is not being used to convey an argument into the function. In theory 3376 we could just check current_function_args_size to see how many bytes are 3377 being passed in argument registers, but it seems that it is unreliable. 3378 Sometimes it will have the value 0 when in fact arguments are being 3379 passed. (See testcase execute/20021111-1.c for an example). So we also 3380 check the args_info.nregs field as well. The problem with this field is 3381 that it makes no allowances for arguments that are passed to the 3382 function but which are not used. Hence we could miss an opportunity 3383 when a function has an unused argument in r3. But it is better to be 3384 safe than to be sorry. */ 3385 if (! cfun->machine->uses_anonymous_args 3386 && current_function_args_size >= 0 3387 && current_function_args_size <= (LAST_ARG_REGNUM * UNITS_PER_WORD) 3388 && cfun->args_info.nregs < 4) 3389 return LAST_ARG_REGNUM; 3390 3391 /* Otherwise look for a call-saved register that is going to be pushed. */ 3392 for (reg = LAST_LO_REGNUM; reg > LAST_ARG_REGNUM; reg --) 3393 if (pushed_regs_mask & (1 << reg)) 3394 return reg; 3395 3396 /* Something went wrong - thumb_compute_save_reg_mask() 3397 should have arranged for a suitable register to be pushed. */ 3398 gcc_unreachable (); 3399} 3400 3401static GTY(()) int pic_labelno; 3402 3403/* Generate code to load the PIC register. In thumb mode SCRATCH is a 3404 low register. */ 3405 3406void 3407arm_load_pic_register (unsigned long saved_regs ATTRIBUTE_UNUSED) 3408{ 3409#ifndef AOF_ASSEMBLER 3410 rtx l1, labelno, pic_tmp, pic_tmp2, pic_rtx; 3411 rtx global_offset_table; 3412 3413 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) 3414 return; 3415 3416 gcc_assert (flag_pic); 3417 3418 /* We use an UNSPEC rather than a LABEL_REF because this label never appears 3419 in the code stream. */ 3420 3421 labelno = GEN_INT (pic_labelno++); 3422 l1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); 3423 l1 = gen_rtx_CONST (VOIDmode, l1); 3424 3425 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 3426 /* On the ARM the PC register contains 'dot + 8' at the time of the 3427 addition, on the Thumb it is 'dot + 4'. */ 3428 pic_tmp = plus_constant (l1, TARGET_ARM ? 8 : 4); 3429 if (GOT_PCREL) 3430 pic_tmp2 = gen_rtx_CONST (VOIDmode, 3431 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx)); 3432 else 3433 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table); 3434 3435 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp)); 3436 3437 if (TARGET_ARM) 3438 { 3439 emit_insn (gen_pic_load_addr_arm (cfun->machine->pic_reg, pic_rtx)); 3440 emit_insn (gen_pic_add_dot_plus_eight (cfun->machine->pic_reg, 3441 cfun->machine->pic_reg, labelno)); 3442 } 3443 else 3444 { 3445 if (arm_pic_register != INVALID_REGNUM 3446 && REGNO (cfun->machine->pic_reg) > LAST_LO_REGNUM) 3447 { 3448 /* We will have pushed the pic register, so we should always be 3449 able to find a work register. */ 3450 pic_tmp = gen_rtx_REG (SImode, 3451 thumb_find_work_register (saved_regs)); 3452 emit_insn (gen_pic_load_addr_thumb (pic_tmp, pic_rtx)); 3453 emit_insn (gen_movsi (pic_offset_table_rtx, pic_tmp)); 3454 } 3455 else 3456 emit_insn (gen_pic_load_addr_thumb (cfun->machine->pic_reg, pic_rtx)); 3457 emit_insn (gen_pic_add_dot_plus_four (cfun->machine->pic_reg, 3458 cfun->machine->pic_reg, labelno)); 3459 } 3460 3461 /* Need to emit this whether or not we obey regdecls, 3462 since setjmp/longjmp can cause life info to screw up. */ 3463 emit_insn (gen_rtx_USE (VOIDmode, cfun->machine->pic_reg)); 3464#endif /* AOF_ASSEMBLER */ 3465} 3466 3467 3468/* Return nonzero if X is valid as an ARM state addressing register. */ 3469static int 3470arm_address_register_rtx_p (rtx x, int strict_p) 3471{ 3472 int regno; 3473 3474 if (GET_CODE (x) != REG) 3475 return 0; 3476 3477 regno = REGNO (x); 3478 3479 if (strict_p) 3480 return ARM_REGNO_OK_FOR_BASE_P (regno); 3481 3482 return (regno <= LAST_ARM_REGNUM 3483 || regno >= FIRST_PSEUDO_REGISTER 3484 || regno == FRAME_POINTER_REGNUM 3485 || regno == ARG_POINTER_REGNUM); 3486} 3487 3488/* Return TRUE if this rtx is the difference of a symbol and a label, 3489 and will reduce to a PC-relative relocation in the object file. 3490 Expressions like this can be left alone when generating PIC, rather 3491 than forced through the GOT. */ 3492static int 3493pcrel_constant_p (rtx x) 3494{ 3495 if (GET_CODE (x) == MINUS) 3496 return symbol_mentioned_p (XEXP (x, 0)) && label_mentioned_p (XEXP (x, 1)); 3497 3498 return FALSE; 3499} 3500 3501/* Return nonzero if X is a valid ARM state address operand. */ 3502int 3503arm_legitimate_address_p (enum machine_mode mode, rtx x, RTX_CODE outer, 3504 int strict_p) 3505{ 3506 bool use_ldrd; 3507 enum rtx_code code = GET_CODE (x); 3508 3509 if (arm_address_register_rtx_p (x, strict_p)) 3510 return 1; 3511 3512 use_ldrd = (TARGET_LDRD 3513 && (mode == DImode 3514 || (mode == DFmode && (TARGET_SOFT_FLOAT || TARGET_VFP)))); 3515 3516 if (code == POST_INC || code == PRE_DEC 3517 || ((code == PRE_INC || code == POST_DEC) 3518 && (use_ldrd || GET_MODE_SIZE (mode) <= 4))) 3519 return arm_address_register_rtx_p (XEXP (x, 0), strict_p); 3520 3521 else if ((code == POST_MODIFY || code == PRE_MODIFY) 3522 && arm_address_register_rtx_p (XEXP (x, 0), strict_p) 3523 && GET_CODE (XEXP (x, 1)) == PLUS 3524 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) 3525 { 3526 rtx addend = XEXP (XEXP (x, 1), 1); 3527 3528 /* Don't allow ldrd post increment by register because it's hard 3529 to fixup invalid register choices. */ 3530 if (use_ldrd 3531 && GET_CODE (x) == POST_MODIFY 3532 && GET_CODE (addend) == REG) 3533 return 0; 3534 3535 return ((use_ldrd || GET_MODE_SIZE (mode) <= 4) 3536 && arm_legitimate_index_p (mode, addend, outer, strict_p)); 3537 } 3538 3539 /* After reload constants split into minipools will have addresses 3540 from a LABEL_REF. */ 3541 else if (reload_completed 3542 && (code == LABEL_REF 3543 || (code == CONST 3544 && GET_CODE (XEXP (x, 0)) == PLUS 3545 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF 3546 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) 3547 return 1; 3548 3549 else if (mode == TImode) 3550 return 0; 3551 3552 else if (code == PLUS) 3553 { 3554 rtx xop0 = XEXP (x, 0); 3555 rtx xop1 = XEXP (x, 1); 3556 3557 return ((arm_address_register_rtx_p (xop0, strict_p) 3558 && arm_legitimate_index_p (mode, xop1, outer, strict_p)) 3559 || (arm_address_register_rtx_p (xop1, strict_p) 3560 && arm_legitimate_index_p (mode, xop0, outer, strict_p))); 3561 } 3562 3563#if 0 3564 /* Reload currently can't handle MINUS, so disable this for now */ 3565 else if (GET_CODE (x) == MINUS) 3566 { 3567 rtx xop0 = XEXP (x, 0); 3568 rtx xop1 = XEXP (x, 1); 3569 3570 return (arm_address_register_rtx_p (xop0, strict_p) 3571 && arm_legitimate_index_p (mode, xop1, outer, strict_p)); 3572 } 3573#endif 3574 3575 else if (GET_MODE_CLASS (mode) != MODE_FLOAT 3576 && code == SYMBOL_REF 3577 && CONSTANT_POOL_ADDRESS_P (x) 3578 && ! (flag_pic 3579 && symbol_mentioned_p (get_pool_constant (x)) 3580 && ! pcrel_constant_p (get_pool_constant (x)))) 3581 return 1; 3582 3583 return 0; 3584} 3585 3586/* Return nonzero if INDEX is valid for an address index operand in 3587 ARM state. */ 3588static int 3589arm_legitimate_index_p (enum machine_mode mode, rtx index, RTX_CODE outer, 3590 int strict_p) 3591{ 3592 HOST_WIDE_INT range; 3593 enum rtx_code code = GET_CODE (index); 3594 3595 /* Standard coprocessor addressing modes. */ 3596 if (TARGET_HARD_FLOAT 3597 && (TARGET_FPA || TARGET_MAVERICK) 3598 && (GET_MODE_CLASS (mode) == MODE_FLOAT 3599 || (TARGET_MAVERICK && mode == DImode))) 3600 return (code == CONST_INT && INTVAL (index) < 1024 3601 && INTVAL (index) > -1024 3602 && (INTVAL (index) & 3) == 0); 3603 3604 if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) 3605 { 3606 /* For DImode assume values will usually live in core regs 3607 and only allow LDRD addressing modes. */ 3608 if (!TARGET_LDRD || mode != DImode) 3609 return (code == CONST_INT 3610 && INTVAL (index) < 1024 3611 && INTVAL (index) > -1024 3612 && (INTVAL (index) & 3) == 0); 3613 } 3614 3615 if (arm_address_register_rtx_p (index, strict_p) 3616 && (GET_MODE_SIZE (mode) <= 4)) 3617 return 1; 3618 3619 if (mode == DImode || mode == DFmode) 3620 { 3621 if (code == CONST_INT) 3622 { 3623 HOST_WIDE_INT val = INTVAL (index); 3624 3625 if (TARGET_LDRD) 3626 return val > -256 && val < 256; 3627 else 3628 return val > -4096 && val < 4092; 3629 } 3630 3631 return TARGET_LDRD && arm_address_register_rtx_p (index, strict_p); 3632 } 3633 3634 if (GET_MODE_SIZE (mode) <= 4 3635 && ! (arm_arch4 3636 && (mode == HImode 3637 || (mode == QImode && outer == SIGN_EXTEND)))) 3638 { 3639 if (code == MULT) 3640 { 3641 rtx xiop0 = XEXP (index, 0); 3642 rtx xiop1 = XEXP (index, 1); 3643 3644 return ((arm_address_register_rtx_p (xiop0, strict_p) 3645 && power_of_two_operand (xiop1, SImode)) 3646 || (arm_address_register_rtx_p (xiop1, strict_p) 3647 && power_of_two_operand (xiop0, SImode))); 3648 } 3649 else if (code == LSHIFTRT || code == ASHIFTRT 3650 || code == ASHIFT || code == ROTATERT) 3651 { 3652 rtx op = XEXP (index, 1); 3653 3654 return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) 3655 && GET_CODE (op) == CONST_INT 3656 && INTVAL (op) > 0 3657 && INTVAL (op) <= 31); 3658 } 3659 } 3660 3661 /* For ARM v4 we may be doing a sign-extend operation during the 3662 load. */ 3663 if (arm_arch4) 3664 { 3665 if (mode == HImode || (outer == SIGN_EXTEND && mode == QImode)) 3666 range = 256; 3667 else 3668 range = 4096; 3669 } 3670 else 3671 range = (mode == HImode) ? 4095 : 4096; 3672 3673 return (code == CONST_INT 3674 && INTVAL (index) < range 3675 && INTVAL (index) > -range); 3676} 3677 3678/* Return nonzero if X is valid as a Thumb state base register. */ 3679static int 3680thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) 3681{ 3682 int regno; 3683 3684 if (GET_CODE (x) != REG) 3685 return 0; 3686 3687 regno = REGNO (x); 3688 3689 if (strict_p) 3690 return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode); 3691 3692 return (regno <= LAST_LO_REGNUM 3693 || regno > LAST_VIRTUAL_REGISTER 3694 || regno == FRAME_POINTER_REGNUM 3695 || (GET_MODE_SIZE (mode) >= 4 3696 && (regno == STACK_POINTER_REGNUM 3697 || regno >= FIRST_PSEUDO_REGISTER 3698 || x == hard_frame_pointer_rtx 3699 || x == arg_pointer_rtx))); 3700} 3701 3702/* Return nonzero if x is a legitimate index register. This is the case 3703 for any base register that can access a QImode object. */ 3704inline static int 3705thumb_index_register_rtx_p (rtx x, int strict_p) 3706{ 3707 return thumb_base_register_rtx_p (x, QImode, strict_p); 3708} 3709 3710/* Return nonzero if x is a legitimate Thumb-state address. 3711 3712 The AP may be eliminated to either the SP or the FP, so we use the 3713 least common denominator, e.g. SImode, and offsets from 0 to 64. 3714 3715 ??? Verify whether the above is the right approach. 3716 3717 ??? Also, the FP may be eliminated to the SP, so perhaps that 3718 needs special handling also. 3719 3720 ??? Look at how the mips16 port solves this problem. It probably uses 3721 better ways to solve some of these problems. 3722 3723 Although it is not incorrect, we don't accept QImode and HImode 3724 addresses based on the frame pointer or arg pointer until the 3725 reload pass starts. This is so that eliminating such addresses 3726 into stack based ones won't produce impossible code. */ 3727int 3728thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) 3729{ 3730 /* ??? Not clear if this is right. Experiment. */ 3731 if (GET_MODE_SIZE (mode) < 4 3732 && !(reload_in_progress || reload_completed) 3733 && (reg_mentioned_p (frame_pointer_rtx, x) 3734 || reg_mentioned_p (arg_pointer_rtx, x) 3735 || reg_mentioned_p (virtual_incoming_args_rtx, x) 3736 || reg_mentioned_p (virtual_outgoing_args_rtx, x) 3737 || reg_mentioned_p (virtual_stack_dynamic_rtx, x) 3738 || reg_mentioned_p (virtual_stack_vars_rtx, x))) 3739 return 0; 3740 3741 /* Accept any base register. SP only in SImode or larger. */ 3742 else if (thumb_base_register_rtx_p (x, mode, strict_p)) 3743 return 1; 3744 3745 /* This is PC relative data before arm_reorg runs. */ 3746 else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) 3747 && GET_CODE (x) == SYMBOL_REF 3748 && CONSTANT_POOL_ADDRESS_P (x) && !flag_pic) 3749 return 1; 3750 3751 /* This is PC relative data after arm_reorg runs. */ 3752 else if (GET_MODE_SIZE (mode) >= 4 && reload_completed 3753 && (GET_CODE (x) == LABEL_REF 3754 || (GET_CODE (x) == CONST 3755 && GET_CODE (XEXP (x, 0)) == PLUS 3756 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF 3757 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) 3758 return 1; 3759 3760 /* Post-inc indexing only supported for SImode and larger. */ 3761 else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 3762 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)) 3763 return 1; 3764 3765 else if (GET_CODE (x) == PLUS) 3766 { 3767 /* REG+REG address can be any two index registers. */ 3768 /* We disallow FRAME+REG addressing since we know that FRAME 3769 will be replaced with STACK, and SP relative addressing only 3770 permits SP+OFFSET. */ 3771 if (GET_MODE_SIZE (mode) <= 4 3772 && XEXP (x, 0) != frame_pointer_rtx 3773 && XEXP (x, 1) != frame_pointer_rtx 3774 && thumb_index_register_rtx_p (XEXP (x, 0), strict_p) 3775 && thumb_index_register_rtx_p (XEXP (x, 1), strict_p)) 3776 return 1; 3777 3778 /* REG+const has 5-7 bit offset for non-SP registers. */ 3779 else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p) 3780 || XEXP (x, 0) == arg_pointer_rtx) 3781 && GET_CODE (XEXP (x, 1)) == CONST_INT 3782 && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) 3783 return 1; 3784 3785 /* REG+const has 10 bit offset for SP, but only SImode and 3786 larger is supported. */ 3787 /* ??? Should probably check for DI/DFmode overflow here 3788 just like GO_IF_LEGITIMATE_OFFSET does. */ 3789 else if (GET_CODE (XEXP (x, 0)) == REG 3790 && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM 3791 && GET_MODE_SIZE (mode) >= 4 3792 && GET_CODE (XEXP (x, 1)) == CONST_INT 3793 && INTVAL (XEXP (x, 1)) >= 0 3794 && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 3795 && (INTVAL (XEXP (x, 1)) & 3) == 0) 3796 return 1; 3797 3798 else if (GET_CODE (XEXP (x, 0)) == REG 3799 && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM 3800 && GET_MODE_SIZE (mode) >= 4 3801 && GET_CODE (XEXP (x, 1)) == CONST_INT 3802 && (INTVAL (XEXP (x, 1)) & 3) == 0) 3803 return 1; 3804 } 3805 3806 else if (GET_MODE_CLASS (mode) != MODE_FLOAT 3807 && GET_MODE_SIZE (mode) == 4 3808 && GET_CODE (x) == SYMBOL_REF 3809 && CONSTANT_POOL_ADDRESS_P (x) 3810 && ! (flag_pic 3811 && symbol_mentioned_p (get_pool_constant (x)) 3812 && ! pcrel_constant_p (get_pool_constant (x)))) 3813 return 1; 3814 3815 return 0; 3816} 3817 3818/* Return nonzero if VAL can be used as an offset in a Thumb-state address 3819 instruction of mode MODE. */ 3820int 3821thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) 3822{ 3823 switch (GET_MODE_SIZE (mode)) 3824 { 3825 case 1: 3826 return val >= 0 && val < 32; 3827 3828 case 2: 3829 return val >= 0 && val < 64 && (val & 1) == 0; 3830 3831 default: 3832 return (val >= 0 3833 && (val + GET_MODE_SIZE (mode)) <= 128 3834 && (val & 3) == 0); 3835 } 3836} 3837 3838/* Build the SYMBOL_REF for __tls_get_addr. */ 3839 3840static GTY(()) rtx tls_get_addr_libfunc; 3841 3842static rtx 3843get_tls_get_addr (void) 3844{ 3845 if (!tls_get_addr_libfunc) 3846 tls_get_addr_libfunc = init_one_libfunc ("__tls_get_addr"); 3847 return tls_get_addr_libfunc; 3848} 3849 3850static rtx 3851arm_load_tp (rtx target) 3852{ 3853 if (!target) 3854 target = gen_reg_rtx (SImode); 3855 3856 if (TARGET_HARD_TP) 3857 { 3858 /* Can return in any reg. */ 3859 emit_insn (gen_load_tp_hard (target)); 3860 } 3861 else 3862 { 3863 /* Always returned in r0. Immediately copy the result into a pseudo, 3864 otherwise other uses of r0 (e.g. setting up function arguments) may 3865 clobber the value. */ 3866 3867 rtx tmp; 3868 3869 emit_insn (gen_load_tp_soft ()); 3870 3871 tmp = gen_rtx_REG (SImode, 0); 3872 emit_move_insn (target, tmp); 3873 } 3874 return target; 3875} 3876 3877static rtx 3878load_tls_operand (rtx x, rtx reg) 3879{ 3880 rtx tmp; 3881 3882 if (reg == NULL_RTX) 3883 reg = gen_reg_rtx (SImode); 3884 3885 tmp = gen_rtx_CONST (SImode, x); 3886 3887 emit_move_insn (reg, tmp); 3888 3889 return reg; 3890} 3891 3892static rtx 3893arm_call_tls_get_addr (rtx x, rtx reg, rtx *valuep, int reloc) 3894{ 3895 rtx insns, label, labelno, sum; 3896 3897 start_sequence (); 3898 3899 labelno = GEN_INT (pic_labelno++); 3900 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); 3901 label = gen_rtx_CONST (VOIDmode, label); 3902 3903 sum = gen_rtx_UNSPEC (Pmode, 3904 gen_rtvec (4, x, GEN_INT (reloc), label, 3905 GEN_INT (TARGET_ARM ? 8 : 4)), 3906 UNSPEC_TLS); 3907 reg = load_tls_operand (sum, reg); 3908 3909 if (TARGET_ARM) 3910 emit_insn (gen_pic_add_dot_plus_eight (reg, reg, labelno)); 3911 else 3912 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); 3913 3914 *valuep = emit_library_call_value (get_tls_get_addr (), NULL_RTX, LCT_PURE, /* LCT_CONST? */ 3915 Pmode, 1, reg, Pmode); 3916 3917 insns = get_insns (); 3918 end_sequence (); 3919 3920 return insns; 3921} 3922 3923rtx 3924legitimize_tls_address (rtx x, rtx reg) 3925{ 3926 rtx dest, tp, label, labelno, sum, insns, ret, eqv, addend; 3927 unsigned int model = SYMBOL_REF_TLS_MODEL (x); 3928 3929 switch (model) 3930 { 3931 case TLS_MODEL_GLOBAL_DYNAMIC: 3932 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_GD32); 3933 dest = gen_reg_rtx (Pmode); 3934 emit_libcall_block (insns, dest, ret, x); 3935 return dest; 3936 3937 case TLS_MODEL_LOCAL_DYNAMIC: 3938 insns = arm_call_tls_get_addr (x, reg, &ret, TLS_LDM32); 3939 3940 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to 3941 share the LDM result with other LD model accesses. */ 3942 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), 3943 UNSPEC_TLS); 3944 dest = gen_reg_rtx (Pmode); 3945 emit_libcall_block (insns, dest, ret, eqv); 3946 3947 /* Load the addend. */ 3948 addend = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (TLS_LDO32)), 3949 UNSPEC_TLS); 3950 addend = force_reg (SImode, gen_rtx_CONST (SImode, addend)); 3951 return gen_rtx_PLUS (Pmode, dest, addend); 3952 3953 case TLS_MODEL_INITIAL_EXEC: 3954 labelno = GEN_INT (pic_labelno++); 3955 label = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, labelno), UNSPEC_PIC_LABEL); 3956 label = gen_rtx_CONST (VOIDmode, label); 3957 sum = gen_rtx_UNSPEC (Pmode, 3958 gen_rtvec (4, x, GEN_INT (TLS_IE32), label, 3959 GEN_INT (TARGET_ARM ? 8 : 4)), 3960 UNSPEC_TLS); 3961 reg = load_tls_operand (sum, reg); 3962 3963 if (TARGET_ARM) 3964 emit_insn (gen_tls_load_dot_plus_eight (reg, reg, labelno)); 3965 else 3966 { 3967 emit_insn (gen_pic_add_dot_plus_four (reg, reg, labelno)); 3968 emit_move_insn (reg, gen_const_mem (SImode, reg)); 3969 } 3970 3971 tp = arm_load_tp (NULL_RTX); 3972 3973 return gen_rtx_PLUS (Pmode, tp, reg); 3974 3975 case TLS_MODEL_LOCAL_EXEC: 3976 tp = arm_load_tp (NULL_RTX); 3977 3978 reg = gen_rtx_UNSPEC (Pmode, 3979 gen_rtvec (2, x, GEN_INT (TLS_LE32)), 3980 UNSPEC_TLS); 3981 reg = force_reg (SImode, gen_rtx_CONST (SImode, reg)); 3982 3983 return gen_rtx_PLUS (Pmode, tp, reg); 3984 3985 default: 3986 abort (); 3987 } 3988} 3989 3990/* Try machine-dependent ways of modifying an illegitimate address 3991 to be legitimate. If we find one, return the new, valid address. */ 3992rtx 3993arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) 3994{ 3995 if (arm_tls_symbol_p (x)) 3996 return legitimize_tls_address (x, NULL_RTX); 3997 3998 if (GET_CODE (x) == PLUS) 3999 { 4000 rtx xop0 = XEXP (x, 0); 4001 rtx xop1 = XEXP (x, 1); 4002 4003 if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) 4004 xop0 = force_reg (SImode, xop0); 4005 4006 if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) 4007 xop1 = force_reg (SImode, xop1); 4008 4009 if (ARM_BASE_REGISTER_RTX_P (xop0) 4010 && GET_CODE (xop1) == CONST_INT) 4011 { 4012 HOST_WIDE_INT n, low_n; 4013 rtx base_reg, val; 4014 n = INTVAL (xop1); 4015 4016 /* VFP addressing modes actually allow greater offsets, but for 4017 now we just stick with the lowest common denominator. */ 4018 if (mode == DImode 4019 || ((TARGET_SOFT_FLOAT || TARGET_VFP) && mode == DFmode)) 4020 { 4021 low_n = n & 0x0f; 4022 n &= ~0x0f; 4023 if (low_n > 4) 4024 { 4025 n += 16; 4026 low_n -= 16; 4027 } 4028 } 4029 else 4030 { 4031 low_n = ((mode) == TImode ? 0 4032 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); 4033 n -= low_n; 4034 } 4035 4036 base_reg = gen_reg_rtx (SImode); 4037 val = force_operand (plus_constant (xop0, n), NULL_RTX); 4038 emit_move_insn (base_reg, val); 4039 x = plus_constant (base_reg, low_n); 4040 } 4041 else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) 4042 x = gen_rtx_PLUS (SImode, xop0, xop1); 4043 } 4044 4045 /* XXX We don't allow MINUS any more -- see comment in 4046 arm_legitimate_address_p (). */ 4047 else if (GET_CODE (x) == MINUS) 4048 { 4049 rtx xop0 = XEXP (x, 0); 4050 rtx xop1 = XEXP (x, 1); 4051 4052 if (CONSTANT_P (xop0)) 4053 xop0 = force_reg (SImode, xop0); 4054 4055 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) 4056 xop1 = force_reg (SImode, xop1); 4057 4058 if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) 4059 x = gen_rtx_MINUS (SImode, xop0, xop1); 4060 } 4061 4062 /* Make sure to take full advantage of the pre-indexed addressing mode 4063 with absolute addresses which often allows for the base register to 4064 be factorized for multiple adjacent memory references, and it might 4065 even allows for the mini pool to be avoided entirely. */ 4066 else if (GET_CODE (x) == CONST_INT && optimize > 0) 4067 { 4068 unsigned int bits; 4069 HOST_WIDE_INT mask, base, index; 4070 rtx base_reg; 4071 4072 /* ldr and ldrb can use a 12 bit index, ldrsb and the rest can only 4073 use a 8 bit index. So let's use a 12 bit index for SImode only and 4074 hope that arm_gen_constant will enable ldrb to use more bits. */ 4075 bits = (mode == SImode) ? 12 : 8; 4076 mask = (1 << bits) - 1; 4077 base = INTVAL (x) & ~mask; 4078 index = INTVAL (x) & mask; 4079 if (bit_count (base & 0xffffffff) > (32 - bits)/2) 4080 { 4081 /* It'll most probably be more efficient to generate the base 4082 with more bits set and use a negative index instead. */ 4083 base |= mask; 4084 index -= mask; 4085 } 4086 base_reg = force_reg (SImode, GEN_INT (base)); 4087 x = plus_constant (base_reg, index); 4088 } 4089 4090 if (flag_pic) 4091 { 4092 /* We need to find and carefully transform any SYMBOL and LABEL 4093 references; so go back to the original address expression. */ 4094 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); 4095 4096 if (new_x != orig_x) 4097 x = new_x; 4098 } 4099 4100 return x; 4101} 4102 4103 4104/* Try machine-dependent ways of modifying an illegitimate Thumb address 4105 to be legitimate. If we find one, return the new, valid address. */ 4106rtx 4107thumb_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) 4108{ 4109 if (arm_tls_symbol_p (x)) 4110 return legitimize_tls_address (x, NULL_RTX); 4111 4112 if (GET_CODE (x) == PLUS 4113 && GET_CODE (XEXP (x, 1)) == CONST_INT 4114 && (INTVAL (XEXP (x, 1)) >= 32 * GET_MODE_SIZE (mode) 4115 || INTVAL (XEXP (x, 1)) < 0)) 4116 { 4117 rtx xop0 = XEXP (x, 0); 4118 rtx xop1 = XEXP (x, 1); 4119 HOST_WIDE_INT offset = INTVAL (xop1); 4120 4121 /* Try and fold the offset into a biasing of the base register and 4122 then offsetting that. Don't do this when optimizing for space 4123 since it can cause too many CSEs. */ 4124 if (optimize_size && offset >= 0 4125 && offset < 256 + 31 * GET_MODE_SIZE (mode)) 4126 { 4127 HOST_WIDE_INT delta; 4128 4129 if (offset >= 256) 4130 delta = offset - (256 - GET_MODE_SIZE (mode)); 4131 else if (offset < 32 * GET_MODE_SIZE (mode) + 8) 4132 delta = 31 * GET_MODE_SIZE (mode); 4133 else 4134 delta = offset & (~31 * GET_MODE_SIZE (mode)); 4135 4136 xop0 = force_operand (plus_constant (xop0, offset - delta), 4137 NULL_RTX); 4138 x = plus_constant (xop0, delta); 4139 } 4140 else if (offset < 0 && offset > -256) 4141 /* Small negative offsets are best done with a subtract before the 4142 dereference, forcing these into a register normally takes two 4143 instructions. */ 4144 x = force_operand (x, NULL_RTX); 4145 else 4146 { 4147 /* For the remaining cases, force the constant into a register. */ 4148 xop1 = force_reg (SImode, xop1); 4149 x = gen_rtx_PLUS (SImode, xop0, xop1); 4150 } 4151 } 4152 else if (GET_CODE (x) == PLUS 4153 && s_register_operand (XEXP (x, 1), SImode) 4154 && !s_register_operand (XEXP (x, 0), SImode)) 4155 { 4156 rtx xop0 = force_operand (XEXP (x, 0), NULL_RTX); 4157 4158 x = gen_rtx_PLUS (SImode, xop0, XEXP (x, 1)); 4159 } 4160 4161 if (flag_pic) 4162 { 4163 /* We need to find and carefully transform any SYMBOL and LABEL 4164 references; so go back to the original address expression. */ 4165 rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); 4166 4167 if (new_x != orig_x) 4168 x = new_x; 4169 } 4170 4171 return x; 4172} 4173 4174rtx 4175thumb_legitimize_reload_address (rtx *x_p, 4176 enum machine_mode mode, 4177 int opnum, int type, 4178 int ind_levels ATTRIBUTE_UNUSED) 4179{ 4180 rtx x = *x_p; 4181 4182 if (GET_CODE (x) == PLUS 4183 && GET_MODE_SIZE (mode) < 4 4184 && REG_P (XEXP (x, 0)) 4185 && XEXP (x, 0) == stack_pointer_rtx 4186 && GET_CODE (XEXP (x, 1)) == CONST_INT 4187 && !thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) 4188 { 4189 rtx orig_x = x; 4190 4191 x = copy_rtx (x); 4192 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), 4193 Pmode, VOIDmode, 0, 0, opnum, type); 4194 return x; 4195 } 4196 4197 /* If both registers are hi-regs, then it's better to reload the 4198 entire expression rather than each register individually. That 4199 only requires one reload register rather than two. */ 4200 if (GET_CODE (x) == PLUS 4201 && REG_P (XEXP (x, 0)) 4202 && REG_P (XEXP (x, 1)) 4203 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 0), mode) 4204 && !REG_MODE_OK_FOR_REG_BASE_P (XEXP (x, 1), mode)) 4205 { 4206 rtx orig_x = x; 4207 4208 x = copy_rtx (x); 4209 push_reload (orig_x, NULL_RTX, x_p, NULL, MODE_BASE_REG_CLASS (mode), 4210 Pmode, VOIDmode, 0, 0, opnum, type); 4211 return x; 4212 } 4213 4214 return NULL; 4215} 4216 4217/* Test for various thread-local symbols. */ 4218 4219/* Return TRUE if X is a thread-local symbol. */ 4220 4221static bool 4222arm_tls_symbol_p (rtx x) 4223{ 4224 if (! TARGET_HAVE_TLS) 4225 return false; 4226 4227 if (GET_CODE (x) != SYMBOL_REF) 4228 return false; 4229 4230 return SYMBOL_REF_TLS_MODEL (x) != 0; 4231} 4232 4233/* Helper for arm_tls_referenced_p. */ 4234 4235static int 4236arm_tls_operand_p_1 (rtx *x, void *data ATTRIBUTE_UNUSED) 4237{ 4238 if (GET_CODE (*x) == SYMBOL_REF) 4239 return SYMBOL_REF_TLS_MODEL (*x) != 0; 4240 4241 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are 4242 TLS offsets, not real symbol references. */ 4243 if (GET_CODE (*x) == UNSPEC 4244 && XINT (*x, 1) == UNSPEC_TLS) 4245 return -1; 4246 4247 return 0; 4248} 4249 4250/* Return TRUE if X contains any TLS symbol references. */ 4251 4252bool 4253arm_tls_referenced_p (rtx x) 4254{ 4255 if (! TARGET_HAVE_TLS) 4256 return false; 4257 4258 return for_each_rtx (&x, arm_tls_operand_p_1, NULL); 4259} 4260 4261#define REG_OR_SUBREG_REG(X) \ 4262 (GET_CODE (X) == REG \ 4263 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) 4264 4265#define REG_OR_SUBREG_RTX(X) \ 4266 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) 4267 4268#ifndef COSTS_N_INSNS 4269#define COSTS_N_INSNS(N) ((N) * 4 - 2) 4270#endif 4271static inline int 4272thumb_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer) 4273{ 4274 enum machine_mode mode = GET_MODE (x); 4275 4276 switch (code) 4277 { 4278 case ASHIFT: 4279 case ASHIFTRT: 4280 case LSHIFTRT: 4281 case ROTATERT: 4282 case PLUS: 4283 case MINUS: 4284 case COMPARE: 4285 case NEG: 4286 case NOT: 4287 return COSTS_N_INSNS (1); 4288 4289 case MULT: 4290 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 4291 { 4292 int cycles = 0; 4293 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); 4294 4295 while (i) 4296 { 4297 i >>= 2; 4298 cycles++; 4299 } 4300 return COSTS_N_INSNS (2) + cycles; 4301 } 4302 return COSTS_N_INSNS (1) + 16; 4303 4304 case SET: 4305 return (COSTS_N_INSNS (1) 4306 + 4 * ((GET_CODE (SET_SRC (x)) == MEM) 4307 + GET_CODE (SET_DEST (x)) == MEM)); 4308 4309 case CONST_INT: 4310 if (outer == SET) 4311 { 4312 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) 4313 return 0; 4314 if (thumb_shiftable_const (INTVAL (x))) 4315 return COSTS_N_INSNS (2); 4316 return COSTS_N_INSNS (3); 4317 } 4318 else if ((outer == PLUS || outer == COMPARE) 4319 && INTVAL (x) < 256 && INTVAL (x) > -256) 4320 return 0; 4321 else if (outer == AND 4322 && INTVAL (x) < 256 && INTVAL (x) >= -256) 4323 return COSTS_N_INSNS (1); 4324 else if (outer == ASHIFT || outer == ASHIFTRT 4325 || outer == LSHIFTRT) 4326 return 0; 4327 return COSTS_N_INSNS (2); 4328 4329 case CONST: 4330 case CONST_DOUBLE: 4331 case LABEL_REF: 4332 case SYMBOL_REF: 4333 return COSTS_N_INSNS (3); 4334 4335 case UDIV: 4336 case UMOD: 4337 case DIV: 4338 case MOD: 4339 return 100; 4340 4341 case TRUNCATE: 4342 return 99; 4343 4344 case AND: 4345 case XOR: 4346 case IOR: 4347 /* XXX guess. */ 4348 return 8; 4349 4350 case MEM: 4351 /* XXX another guess. */ 4352 /* Memory costs quite a lot for the first word, but subsequent words 4353 load at the equivalent of a single insn each. */ 4354 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) 4355 + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) 4356 ? 4 : 0)); 4357 4358 case IF_THEN_ELSE: 4359 /* XXX a guess. */ 4360 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) 4361 return 14; 4362 return 2; 4363 4364 case ZERO_EXTEND: 4365 /* XXX still guessing. */ 4366 switch (GET_MODE (XEXP (x, 0))) 4367 { 4368 case QImode: 4369 return (1 + (mode == DImode ? 4 : 0) 4370 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 4371 4372 case HImode: 4373 return (4 + (mode == DImode ? 4 : 0) 4374 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 4375 4376 case SImode: 4377 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 4378 4379 default: 4380 return 99; 4381 } 4382 4383 default: 4384 return 99; 4385 } 4386} 4387 4388 4389/* Worker routine for arm_rtx_costs. */ 4390static inline int 4391arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) 4392{ 4393 enum machine_mode mode = GET_MODE (x); 4394 enum rtx_code subcode; 4395 int extra_cost; 4396 4397 switch (code) 4398 { 4399 case MEM: 4400 /* Memory costs quite a lot for the first word, but subsequent words 4401 load at the equivalent of a single insn each. */ 4402 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) 4403 + (GET_CODE (x) == SYMBOL_REF 4404 && CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); 4405 4406 case DIV: 4407 case MOD: 4408 case UDIV: 4409 case UMOD: 4410 return optimize_size ? COSTS_N_INSNS (2) : 100; 4411 4412 case ROTATE: 4413 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) 4414 return 4; 4415 /* Fall through */ 4416 case ROTATERT: 4417 if (mode != SImode) 4418 return 8; 4419 /* Fall through */ 4420 case ASHIFT: case LSHIFTRT: case ASHIFTRT: 4421 if (mode == DImode) 4422 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8) 4423 + ((GET_CODE (XEXP (x, 0)) == REG 4424 || (GET_CODE (XEXP (x, 0)) == SUBREG 4425 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) 4426 ? 0 : 8)); 4427 return (1 + ((GET_CODE (XEXP (x, 0)) == REG 4428 || (GET_CODE (XEXP (x, 0)) == SUBREG 4429 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) 4430 ? 0 : 4) 4431 + ((GET_CODE (XEXP (x, 1)) == REG 4432 || (GET_CODE (XEXP (x, 1)) == SUBREG 4433 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG) 4434 || (GET_CODE (XEXP (x, 1)) == CONST_INT)) 4435 ? 0 : 4)); 4436 4437 case MINUS: 4438 if (mode == DImode) 4439 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8) 4440 + ((REG_OR_SUBREG_REG (XEXP (x, 0)) 4441 || (GET_CODE (XEXP (x, 0)) == CONST_INT 4442 && const_ok_for_arm (INTVAL (XEXP (x, 0))))) 4443 ? 0 : 8)); 4444 4445 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 4446 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 4447 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE 4448 && arm_const_double_rtx (XEXP (x, 1)))) 4449 ? 0 : 8) 4450 + ((REG_OR_SUBREG_REG (XEXP (x, 0)) 4451 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE 4452 && arm_const_double_rtx (XEXP (x, 0)))) 4453 ? 0 : 8)); 4454 4455 if (((GET_CODE (XEXP (x, 0)) == CONST_INT 4456 && const_ok_for_arm (INTVAL (XEXP (x, 0))) 4457 && REG_OR_SUBREG_REG (XEXP (x, 1)))) 4458 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT 4459 || subcode == ASHIFTRT || subcode == LSHIFTRT 4460 || subcode == ROTATE || subcode == ROTATERT 4461 || (subcode == MULT 4462 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 4463 && ((INTVAL (XEXP (XEXP (x, 1), 1)) & 4464 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) 4465 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0)) 4466 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1)) 4467 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) 4468 && REG_OR_SUBREG_REG (XEXP (x, 0)))) 4469 return 1; 4470 /* Fall through */ 4471 4472 case PLUS: 4473 if (GET_CODE (XEXP (x, 0)) == MULT) 4474 { 4475 extra_cost = rtx_cost (XEXP (x, 0), code); 4476 if (!REG_OR_SUBREG_REG (XEXP (x, 1))) 4477 extra_cost += 4 * ARM_NUM_REGS (mode); 4478 return extra_cost; 4479 } 4480 4481 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 4482 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) 4483 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 4484 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE 4485 && arm_const_double_rtx (XEXP (x, 1)))) 4486 ? 0 : 8)); 4487 4488 /* Fall through */ 4489 case AND: case XOR: case IOR: 4490 extra_cost = 0; 4491 4492 /* Normally the frame registers will be spilt into reg+const during 4493 reload, so it is a bad idea to combine them with other instructions, 4494 since then they might not be moved outside of loops. As a compromise 4495 we allow integration with ops that have a constant as their second 4496 operand. */ 4497 if ((REG_OR_SUBREG_REG (XEXP (x, 0)) 4498 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) 4499 && GET_CODE (XEXP (x, 1)) != CONST_INT) 4500 || (REG_OR_SUBREG_REG (XEXP (x, 0)) 4501 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) 4502 extra_cost = 4; 4503 4504 if (mode == DImode) 4505 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) 4506 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 4507 || (GET_CODE (XEXP (x, 1)) == CONST_INT 4508 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) 4509 ? 0 : 8)); 4510 4511 if (REG_OR_SUBREG_REG (XEXP (x, 0))) 4512 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost) 4513 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 4514 || (GET_CODE (XEXP (x, 1)) == CONST_INT 4515 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) 4516 ? 0 : 4)); 4517 4518 else if (REG_OR_SUBREG_REG (XEXP (x, 1))) 4519 return (1 + extra_cost 4520 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT 4521 || subcode == LSHIFTRT || subcode == ASHIFTRT 4522 || subcode == ROTATE || subcode == ROTATERT 4523 || (subcode == MULT 4524 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 4525 && ((INTVAL (XEXP (XEXP (x, 0), 1)) & 4526 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) 4527 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0))) 4528 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1))) 4529 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) 4530 ? 0 : 4)); 4531 4532 return 8; 4533 4534 case MULT: 4535 /* This should have been handled by the CPU specific routines. */ 4536 gcc_unreachable (); 4537 4538 case TRUNCATE: 4539 if (arm_arch3m && mode == SImode 4540 && GET_CODE (XEXP (x, 0)) == LSHIFTRT 4541 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT 4542 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) 4543 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) 4544 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND 4545 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) 4546 return 8; 4547 return 99; 4548 4549 case NEG: 4550 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 4551 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6); 4552 /* Fall through */ 4553 case NOT: 4554 if (mode == DImode) 4555 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); 4556 4557 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); 4558 4559 case IF_THEN_ELSE: 4560 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) 4561 return 14; 4562 return 2; 4563 4564 case COMPARE: 4565 return 1; 4566 4567 case ABS: 4568 return 4 + (mode == DImode ? 4 : 0); 4569 4570 case SIGN_EXTEND: 4571 if (GET_MODE (XEXP (x, 0)) == QImode) 4572 return (4 + (mode == DImode ? 4 : 0) 4573 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 4574 /* Fall through */ 4575 case ZERO_EXTEND: 4576 switch (GET_MODE (XEXP (x, 0))) 4577 { 4578 case QImode: 4579 return (1 + (mode == DImode ? 4 : 0) 4580 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 4581 4582 case HImode: 4583 return (4 + (mode == DImode ? 4 : 0) 4584 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 4585 4586 case SImode: 4587 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 4588 4589 case V8QImode: 4590 case V4HImode: 4591 case V2SImode: 4592 case V4QImode: 4593 case V2HImode: 4594 return 1; 4595 4596 default: 4597 gcc_unreachable (); 4598 } 4599 gcc_unreachable (); 4600 4601 case CONST_INT: 4602 if (const_ok_for_arm (INTVAL (x))) 4603 return outer == SET ? 2 : -1; 4604 else if (outer == AND 4605 && const_ok_for_arm (~INTVAL (x))) 4606 return -1; 4607 else if ((outer == COMPARE 4608 || outer == PLUS || outer == MINUS) 4609 && const_ok_for_arm (-INTVAL (x))) 4610 return -1; 4611 else 4612 return 5; 4613 4614 case CONST: 4615 case LABEL_REF: 4616 case SYMBOL_REF: 4617 return 6; 4618 4619 case CONST_DOUBLE: 4620 if (arm_const_double_rtx (x)) 4621 return outer == SET ? 2 : -1; 4622 else if ((outer == COMPARE || outer == PLUS) 4623 && neg_const_double_rtx_ok_for_fpa (x)) 4624 return -1; 4625 return 7; 4626 4627 default: 4628 return 99; 4629 } 4630} 4631 4632/* RTX costs when optimizing for size. */ 4633static bool 4634arm_size_rtx_costs (rtx x, int code, int outer_code, int *total) 4635{ 4636 enum machine_mode mode = GET_MODE (x); 4637 4638 if (TARGET_THUMB) 4639 { 4640 /* XXX TBD. For now, use the standard costs. */ 4641 *total = thumb_rtx_costs (x, code, outer_code); 4642 return true; 4643 } 4644 4645 switch (code) 4646 { 4647 case MEM: 4648 /* A memory access costs 1 insn if the mode is small, or the address is 4649 a single register, otherwise it costs one insn per word. */ 4650 if (REG_P (XEXP (x, 0))) 4651 *total = COSTS_N_INSNS (1); 4652 else 4653 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); 4654 return true; 4655 4656 case DIV: 4657 case MOD: 4658 case UDIV: 4659 case UMOD: 4660 /* Needs a libcall, so it costs about this. */ 4661 *total = COSTS_N_INSNS (2); 4662 return false; 4663 4664 case ROTATE: 4665 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) 4666 { 4667 *total = COSTS_N_INSNS (2) + rtx_cost (XEXP (x, 0), code); 4668 return true; 4669 } 4670 /* Fall through */ 4671 case ROTATERT: 4672 case ASHIFT: 4673 case LSHIFTRT: 4674 case ASHIFTRT: 4675 if (mode == DImode && GET_CODE (XEXP (x, 1)) == CONST_INT) 4676 { 4677 *total = COSTS_N_INSNS (3) + rtx_cost (XEXP (x, 0), code); 4678 return true; 4679 } 4680 else if (mode == SImode) 4681 { 4682 *total = COSTS_N_INSNS (1) + rtx_cost (XEXP (x, 0), code); 4683 /* Slightly disparage register shifts, but not by much. */ 4684 if (GET_CODE (XEXP (x, 1)) != CONST_INT) 4685 *total += 1 + rtx_cost (XEXP (x, 1), code); 4686 return true; 4687 } 4688 4689 /* Needs a libcall. */ 4690 *total = COSTS_N_INSNS (2); 4691 return false; 4692 4693 case MINUS: 4694 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) 4695 { 4696 *total = COSTS_N_INSNS (1); 4697 return false; 4698 } 4699 4700 if (mode == SImode) 4701 { 4702 enum rtx_code subcode0 = GET_CODE (XEXP (x, 0)); 4703 enum rtx_code subcode1 = GET_CODE (XEXP (x, 1)); 4704 4705 if (subcode0 == ROTATE || subcode0 == ROTATERT || subcode0 == ASHIFT 4706 || subcode0 == LSHIFTRT || subcode0 == ASHIFTRT 4707 || subcode1 == ROTATE || subcode1 == ROTATERT 4708 || subcode1 == ASHIFT || subcode1 == LSHIFTRT 4709 || subcode1 == ASHIFTRT) 4710 { 4711 /* It's just the cost of the two operands. */ 4712 *total = 0; 4713 return false; 4714 } 4715 4716 *total = COSTS_N_INSNS (1); 4717 return false; 4718 } 4719 4720 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); 4721 return false; 4722 4723 case PLUS: 4724 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) 4725 { 4726 *total = COSTS_N_INSNS (1); 4727 return false; 4728 } 4729 4730 /* Fall through */ 4731 case AND: case XOR: case IOR: 4732 if (mode == SImode) 4733 { 4734 enum rtx_code subcode = GET_CODE (XEXP (x, 0)); 4735 4736 if (subcode == ROTATE || subcode == ROTATERT || subcode == ASHIFT 4737 || subcode == LSHIFTRT || subcode == ASHIFTRT 4738 || (code == AND && subcode == NOT)) 4739 { 4740 /* It's just the cost of the two operands. */ 4741 *total = 0; 4742 return false; 4743 } 4744 } 4745 4746 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); 4747 return false; 4748 4749 case MULT: 4750 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); 4751 return false; 4752 4753 case NEG: 4754 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) 4755 *total = COSTS_N_INSNS (1); 4756 /* Fall through */ 4757 case NOT: 4758 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); 4759 4760 return false; 4761 4762 case IF_THEN_ELSE: 4763 *total = 0; 4764 return false; 4765 4766 case COMPARE: 4767 if (cc_register (XEXP (x, 0), VOIDmode)) 4768 * total = 0; 4769 else 4770 *total = COSTS_N_INSNS (1); 4771 return false; 4772 4773 case ABS: 4774 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) 4775 *total = COSTS_N_INSNS (1); 4776 else 4777 *total = COSTS_N_INSNS (1 + ARM_NUM_REGS (mode)); 4778 return false; 4779 4780 case SIGN_EXTEND: 4781 *total = 0; 4782 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) < 4) 4783 { 4784 if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) 4785 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); 4786 } 4787 if (mode == DImode) 4788 *total += COSTS_N_INSNS (1); 4789 return false; 4790 4791 case ZERO_EXTEND: 4792 *total = 0; 4793 if (!(arm_arch4 && MEM_P (XEXP (x, 0)))) 4794 { 4795 switch (GET_MODE (XEXP (x, 0))) 4796 { 4797 case QImode: 4798 *total += COSTS_N_INSNS (1); 4799 break; 4800 4801 case HImode: 4802 *total += COSTS_N_INSNS (arm_arch6 ? 1 : 2); 4803 4804 case SImode: 4805 break; 4806 4807 default: 4808 *total += COSTS_N_INSNS (2); 4809 } 4810 } 4811 4812 if (mode == DImode) 4813 *total += COSTS_N_INSNS (1); 4814 4815 return false; 4816 4817 case CONST_INT: 4818 if (const_ok_for_arm (INTVAL (x))) 4819 *total = COSTS_N_INSNS (outer_code == SET ? 1 : 0); 4820 else if (const_ok_for_arm (~INTVAL (x))) 4821 *total = COSTS_N_INSNS (outer_code == AND ? 0 : 1); 4822 else if (const_ok_for_arm (-INTVAL (x))) 4823 { 4824 if (outer_code == COMPARE || outer_code == PLUS 4825 || outer_code == MINUS) 4826 *total = 0; 4827 else 4828 *total = COSTS_N_INSNS (1); 4829 } 4830 else 4831 *total = COSTS_N_INSNS (2); 4832 return true; 4833 4834 case CONST: 4835 case LABEL_REF: 4836 case SYMBOL_REF: 4837 *total = COSTS_N_INSNS (2); 4838 return true; 4839 4840 case CONST_DOUBLE: 4841 *total = COSTS_N_INSNS (4); 4842 return true; 4843 4844 default: 4845 if (mode != VOIDmode) 4846 *total = COSTS_N_INSNS (ARM_NUM_REGS (mode)); 4847 else 4848 *total = COSTS_N_INSNS (4); /* How knows? */ 4849 return false; 4850 } 4851} 4852 4853/* RTX costs for cores with a slow MUL implementation. */ 4854 4855static bool 4856arm_slowmul_rtx_costs (rtx x, int code, int outer_code, int *total) 4857{ 4858 enum machine_mode mode = GET_MODE (x); 4859 4860 if (TARGET_THUMB) 4861 { 4862 *total = thumb_rtx_costs (x, code, outer_code); 4863 return true; 4864 } 4865 4866 switch (code) 4867 { 4868 case MULT: 4869 if (GET_MODE_CLASS (mode) == MODE_FLOAT 4870 || mode == DImode) 4871 { 4872 *total = 30; 4873 return true; 4874 } 4875 4876 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 4877 { 4878 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) 4879 & (unsigned HOST_WIDE_INT) 0xffffffff); 4880 int cost, const_ok = const_ok_for_arm (i); 4881 int j, booth_unit_size; 4882 4883 /* Tune as appropriate. */ 4884 cost = const_ok ? 4 : 8; 4885 booth_unit_size = 2; 4886 for (j = 0; i && j < 32; j += booth_unit_size) 4887 { 4888 i >>= booth_unit_size; 4889 cost += 2; 4890 } 4891 4892 *total = cost; 4893 return true; 4894 } 4895 4896 *total = 30 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) 4897 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); 4898 return true; 4899 4900 default: 4901 *total = arm_rtx_costs_1 (x, code, outer_code); 4902 return true; 4903 } 4904} 4905 4906 4907/* RTX cost for cores with a fast multiply unit (M variants). */ 4908 4909static bool 4910arm_fastmul_rtx_costs (rtx x, int code, int outer_code, int *total) 4911{ 4912 enum machine_mode mode = GET_MODE (x); 4913 4914 if (TARGET_THUMB) 4915 { 4916 *total = thumb_rtx_costs (x, code, outer_code); 4917 return true; 4918 } 4919 4920 switch (code) 4921 { 4922 case MULT: 4923 /* There is no point basing this on the tuning, since it is always the 4924 fast variant if it exists at all. */ 4925 if (mode == DImode 4926 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) 4927 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 4928 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) 4929 { 4930 *total = 8; 4931 return true; 4932 } 4933 4934 4935 if (GET_MODE_CLASS (mode) == MODE_FLOAT 4936 || mode == DImode) 4937 { 4938 *total = 30; 4939 return true; 4940 } 4941 4942 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 4943 { 4944 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) 4945 & (unsigned HOST_WIDE_INT) 0xffffffff); 4946 int cost, const_ok = const_ok_for_arm (i); 4947 int j, booth_unit_size; 4948 4949 /* Tune as appropriate. */ 4950 cost = const_ok ? 4 : 8; 4951 booth_unit_size = 8; 4952 for (j = 0; i && j < 32; j += booth_unit_size) 4953 { 4954 i >>= booth_unit_size; 4955 cost += 2; 4956 } 4957 4958 *total = cost; 4959 return true; 4960 } 4961 4962 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) 4963 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); 4964 return true; 4965 4966 default: 4967 *total = arm_rtx_costs_1 (x, code, outer_code); 4968 return true; 4969 } 4970} 4971 4972 4973/* RTX cost for XScale CPUs. */ 4974 4975static bool 4976arm_xscale_rtx_costs (rtx x, int code, int outer_code, int *total) 4977{ 4978 enum machine_mode mode = GET_MODE (x); 4979 4980 if (TARGET_THUMB) 4981 { 4982 *total = thumb_rtx_costs (x, code, outer_code); 4983 return true; 4984 } 4985 4986 switch (code) 4987 { 4988 case MULT: 4989 /* There is no point basing this on the tuning, since it is always the 4990 fast variant if it exists at all. */ 4991 if (mode == DImode 4992 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) 4993 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 4994 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) 4995 { 4996 *total = 8; 4997 return true; 4998 } 4999 5000 5001 if (GET_MODE_CLASS (mode) == MODE_FLOAT 5002 || mode == DImode) 5003 { 5004 *total = 30; 5005 return true; 5006 } 5007 5008 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 5009 { 5010 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) 5011 & (unsigned HOST_WIDE_INT) 0xffffffff); 5012 int cost, const_ok = const_ok_for_arm (i); 5013 unsigned HOST_WIDE_INT masked_const; 5014 5015 /* The cost will be related to two insns. 5016 First a load of the constant (MOV or LDR), then a multiply. */ 5017 cost = 2; 5018 if (! const_ok) 5019 cost += 1; /* LDR is probably more expensive because 5020 of longer result latency. */ 5021 masked_const = i & 0xffff8000; 5022 if (masked_const != 0 && masked_const != 0xffff8000) 5023 { 5024 masked_const = i & 0xf8000000; 5025 if (masked_const == 0 || masked_const == 0xf8000000) 5026 cost += 1; 5027 else 5028 cost += 2; 5029 } 5030 *total = cost; 5031 return true; 5032 } 5033 5034 *total = 8 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) 5035 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4); 5036 return true; 5037 5038 case COMPARE: 5039 /* A COMPARE of a MULT is slow on XScale; the muls instruction 5040 will stall until the multiplication is complete. */ 5041 if (GET_CODE (XEXP (x, 0)) == MULT) 5042 *total = 4 + rtx_cost (XEXP (x, 0), code); 5043 else 5044 *total = arm_rtx_costs_1 (x, code, outer_code); 5045 return true; 5046 5047 default: 5048 *total = arm_rtx_costs_1 (x, code, outer_code); 5049 return true; 5050 } 5051} 5052 5053 5054/* RTX costs for 9e (and later) cores. */ 5055 5056static bool 5057arm_9e_rtx_costs (rtx x, int code, int outer_code, int *total) 5058{ 5059 enum machine_mode mode = GET_MODE (x); 5060 int nonreg_cost; 5061 int cost; 5062 5063 if (TARGET_THUMB) 5064 { 5065 switch (code) 5066 { 5067 case MULT: 5068 *total = COSTS_N_INSNS (3); 5069 return true; 5070 5071 default: 5072 *total = thumb_rtx_costs (x, code, outer_code); 5073 return true; 5074 } 5075 } 5076 5077 switch (code) 5078 { 5079 case MULT: 5080 /* There is no point basing this on the tuning, since it is always the 5081 fast variant if it exists at all. */ 5082 if (mode == DImode 5083 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) 5084 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 5085 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) 5086 { 5087 *total = 3; 5088 return true; 5089 } 5090 5091 5092 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 5093 { 5094 *total = 30; 5095 return true; 5096 } 5097 if (mode == DImode) 5098 { 5099 cost = 7; 5100 nonreg_cost = 8; 5101 } 5102 else 5103 { 5104 cost = 2; 5105 nonreg_cost = 4; 5106 } 5107 5108 5109 *total = cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : nonreg_cost) 5110 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : nonreg_cost); 5111 return true; 5112 5113 default: 5114 *total = arm_rtx_costs_1 (x, code, outer_code); 5115 return true; 5116 } 5117} 5118/* All address computations that can be done are free, but rtx cost returns 5119 the same for practically all of them. So we weight the different types 5120 of address here in the order (most pref first): 5121 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ 5122static inline int 5123arm_arm_address_cost (rtx x) 5124{ 5125 enum rtx_code c = GET_CODE (x); 5126 5127 if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC) 5128 return 0; 5129 if (c == MEM || c == LABEL_REF || c == SYMBOL_REF) 5130 return 10; 5131 5132 if (c == PLUS || c == MINUS) 5133 { 5134 if (GET_CODE (XEXP (x, 0)) == CONST_INT) 5135 return 2; 5136 5137 if (ARITHMETIC_P (XEXP (x, 0)) || ARITHMETIC_P (XEXP (x, 1))) 5138 return 3; 5139 5140 return 4; 5141 } 5142 5143 return 6; 5144} 5145 5146static inline int 5147arm_thumb_address_cost (rtx x) 5148{ 5149 enum rtx_code c = GET_CODE (x); 5150 5151 if (c == REG) 5152 return 1; 5153 if (c == PLUS 5154 && GET_CODE (XEXP (x, 0)) == REG 5155 && GET_CODE (XEXP (x, 1)) == CONST_INT) 5156 return 1; 5157 5158 return 2; 5159} 5160 5161static int 5162arm_address_cost (rtx x) 5163{ 5164 return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); 5165} 5166 5167static int 5168arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) 5169{ 5170 rtx i_pat, d_pat; 5171 5172 /* Some true dependencies can have a higher cost depending 5173 on precisely how certain input operands are used. */ 5174 if (arm_tune_xscale 5175 && REG_NOTE_KIND (link) == 0 5176 && recog_memoized (insn) >= 0 5177 && recog_memoized (dep) >= 0) 5178 { 5179 int shift_opnum = get_attr_shift (insn); 5180 enum attr_type attr_type = get_attr_type (dep); 5181 5182 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted 5183 operand for INSN. If we have a shifted input operand and the 5184 instruction we depend on is another ALU instruction, then we may 5185 have to account for an additional stall. */ 5186 if (shift_opnum != 0 5187 && (attr_type == TYPE_ALU_SHIFT || attr_type == TYPE_ALU_SHIFT_REG)) 5188 { 5189 rtx shifted_operand; 5190 int opno; 5191 5192 /* Get the shifted operand. */ 5193 extract_insn (insn); 5194 shifted_operand = recog_data.operand[shift_opnum]; 5195 5196 /* Iterate over all the operands in DEP. If we write an operand 5197 that overlaps with SHIFTED_OPERAND, then we have increase the 5198 cost of this dependency. */ 5199 extract_insn (dep); 5200 preprocess_constraints (); 5201 for (opno = 0; opno < recog_data.n_operands; opno++) 5202 { 5203 /* We can ignore strict inputs. */ 5204 if (recog_data.operand_type[opno] == OP_IN) 5205 continue; 5206 5207 if (reg_overlap_mentioned_p (recog_data.operand[opno], 5208 shifted_operand)) 5209 return 2; 5210 } 5211 } 5212 } 5213 5214 /* XXX This is not strictly true for the FPA. */ 5215 if (REG_NOTE_KIND (link) == REG_DEP_ANTI 5216 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) 5217 return 0; 5218 5219 /* Call insns don't incur a stall, even if they follow a load. */ 5220 if (REG_NOTE_KIND (link) == 0 5221 && GET_CODE (insn) == CALL_INSN) 5222 return 1; 5223 5224 if ((i_pat = single_set (insn)) != NULL 5225 && GET_CODE (SET_SRC (i_pat)) == MEM 5226 && (d_pat = single_set (dep)) != NULL 5227 && GET_CODE (SET_DEST (d_pat)) == MEM) 5228 { 5229 rtx src_mem = XEXP (SET_SRC (i_pat), 0); 5230 /* This is a load after a store, there is no conflict if the load reads 5231 from a cached area. Assume that loads from the stack, and from the 5232 constant pool are cached, and that others will miss. This is a 5233 hack. */ 5234 5235 if ((GET_CODE (src_mem) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (src_mem)) 5236 || reg_mentioned_p (stack_pointer_rtx, src_mem) 5237 || reg_mentioned_p (frame_pointer_rtx, src_mem) 5238 || reg_mentioned_p (hard_frame_pointer_rtx, src_mem)) 5239 return 1; 5240 } 5241 5242 return cost; 5243} 5244 5245static int fp_consts_inited = 0; 5246 5247/* Only zero is valid for VFP. Other values are also valid for FPA. */ 5248static const char * const strings_fp[8] = 5249{ 5250 "0", "1", "2", "3", 5251 "4", "5", "0.5", "10" 5252}; 5253 5254static REAL_VALUE_TYPE values_fp[8]; 5255 5256static void 5257init_fp_table (void) 5258{ 5259 int i; 5260 REAL_VALUE_TYPE r; 5261 5262 if (TARGET_VFP) 5263 fp_consts_inited = 1; 5264 else 5265 fp_consts_inited = 8; 5266 5267 for (i = 0; i < fp_consts_inited; i++) 5268 { 5269 r = REAL_VALUE_ATOF (strings_fp[i], DFmode); 5270 values_fp[i] = r; 5271 } 5272} 5273 5274/* Return TRUE if rtx X is a valid immediate FP constant. */ 5275int 5276arm_const_double_rtx (rtx x) 5277{ 5278 REAL_VALUE_TYPE r; 5279 int i; 5280 5281 if (!fp_consts_inited) 5282 init_fp_table (); 5283 5284 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 5285 if (REAL_VALUE_MINUS_ZERO (r)) 5286 return 0; 5287 5288 for (i = 0; i < fp_consts_inited; i++) 5289 if (REAL_VALUES_EQUAL (r, values_fp[i])) 5290 return 1; 5291 5292 return 0; 5293} 5294 5295/* Return TRUE if rtx X is a valid immediate FPA constant. */ 5296int 5297neg_const_double_rtx_ok_for_fpa (rtx x) 5298{ 5299 REAL_VALUE_TYPE r; 5300 int i; 5301 5302 if (!fp_consts_inited) 5303 init_fp_table (); 5304 5305 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 5306 r = REAL_VALUE_NEGATE (r); 5307 if (REAL_VALUE_MINUS_ZERO (r)) 5308 return 0; 5309 5310 for (i = 0; i < 8; i++) 5311 if (REAL_VALUES_EQUAL (r, values_fp[i])) 5312 return 1; 5313 5314 return 0; 5315} 5316 5317/* Predicates for `match_operand' and `match_operator'. */ 5318 5319/* Return nonzero if OP is a valid Cirrus memory address pattern. */ 5320int 5321cirrus_memory_offset (rtx op) 5322{ 5323 /* Reject eliminable registers. */ 5324 if (! (reload_in_progress || reload_completed) 5325 && ( reg_mentioned_p (frame_pointer_rtx, op) 5326 || reg_mentioned_p (arg_pointer_rtx, op) 5327 || reg_mentioned_p (virtual_incoming_args_rtx, op) 5328 || reg_mentioned_p (virtual_outgoing_args_rtx, op) 5329 || reg_mentioned_p (virtual_stack_dynamic_rtx, op) 5330 || reg_mentioned_p (virtual_stack_vars_rtx, op))) 5331 return 0; 5332 5333 if (GET_CODE (op) == MEM) 5334 { 5335 rtx ind; 5336 5337 ind = XEXP (op, 0); 5338 5339 /* Match: (mem (reg)). */ 5340 if (GET_CODE (ind) == REG) 5341 return 1; 5342 5343 /* Match: 5344 (mem (plus (reg) 5345 (const))). */ 5346 if (GET_CODE (ind) == PLUS 5347 && GET_CODE (XEXP (ind, 0)) == REG 5348 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) 5349 && GET_CODE (XEXP (ind, 1)) == CONST_INT) 5350 return 1; 5351 } 5352 5353 return 0; 5354} 5355 5356/* Return TRUE if OP is a valid coprocessor memory address pattern. 5357 WB if true if writeback address modes are allowed. */ 5358 5359int 5360arm_coproc_mem_operand (rtx op, bool wb) 5361{ 5362 rtx ind; 5363 5364 /* Reject eliminable registers. */ 5365 if (! (reload_in_progress || reload_completed) 5366 && ( reg_mentioned_p (frame_pointer_rtx, op) 5367 || reg_mentioned_p (arg_pointer_rtx, op) 5368 || reg_mentioned_p (virtual_incoming_args_rtx, op) 5369 || reg_mentioned_p (virtual_outgoing_args_rtx, op) 5370 || reg_mentioned_p (virtual_stack_dynamic_rtx, op) 5371 || reg_mentioned_p (virtual_stack_vars_rtx, op))) 5372 return FALSE; 5373 5374 /* Constants are converted into offsets from labels. */ 5375 if (GET_CODE (op) != MEM) 5376 return FALSE; 5377 5378 ind = XEXP (op, 0); 5379 5380 if (reload_completed 5381 && (GET_CODE (ind) == LABEL_REF 5382 || (GET_CODE (ind) == CONST 5383 && GET_CODE (XEXP (ind, 0)) == PLUS 5384 && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF 5385 && GET_CODE (XEXP (XEXP (ind, 0), 1)) == CONST_INT))) 5386 return TRUE; 5387 5388 /* Match: (mem (reg)). */ 5389 if (GET_CODE (ind) == REG) 5390 return arm_address_register_rtx_p (ind, 0); 5391 5392 /* Autoincremment addressing modes. */ 5393 if (wb 5394 && (GET_CODE (ind) == PRE_INC 5395 || GET_CODE (ind) == POST_INC 5396 || GET_CODE (ind) == PRE_DEC 5397 || GET_CODE (ind) == POST_DEC)) 5398 return arm_address_register_rtx_p (XEXP (ind, 0), 0); 5399 5400 if (wb 5401 && (GET_CODE (ind) == POST_MODIFY || GET_CODE (ind) == PRE_MODIFY) 5402 && arm_address_register_rtx_p (XEXP (ind, 0), 0) 5403 && GET_CODE (XEXP (ind, 1)) == PLUS 5404 && rtx_equal_p (XEXP (XEXP (ind, 1), 0), XEXP (ind, 0))) 5405 ind = XEXP (ind, 1); 5406 5407 /* Match: 5408 (plus (reg) 5409 (const)). */ 5410 if (GET_CODE (ind) == PLUS 5411 && GET_CODE (XEXP (ind, 0)) == REG 5412 && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) 5413 && GET_CODE (XEXP (ind, 1)) == CONST_INT 5414 && INTVAL (XEXP (ind, 1)) > -1024 5415 && INTVAL (XEXP (ind, 1)) < 1024 5416 && (INTVAL (XEXP (ind, 1)) & 3) == 0) 5417 return TRUE; 5418 5419 return FALSE; 5420} 5421 5422/* Return true if X is a register that will be eliminated later on. */ 5423int 5424arm_eliminable_register (rtx x) 5425{ 5426 return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM 5427 || REGNO (x) == ARG_POINTER_REGNUM 5428 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER 5429 && REGNO (x) <= LAST_VIRTUAL_REGISTER)); 5430} 5431 5432/* Return GENERAL_REGS if a scratch register required to reload x to/from 5433 coprocessor registers. Otherwise return NO_REGS. */ 5434 5435enum reg_class 5436coproc_secondary_reload_class (enum machine_mode mode, rtx x, bool wb) 5437{ 5438 if (arm_coproc_mem_operand (x, wb) || s_register_operand (x, mode)) 5439 return NO_REGS; 5440 5441 return GENERAL_REGS; 5442} 5443 5444/* Values which must be returned in the most-significant end of the return 5445 register. */ 5446 5447static bool 5448arm_return_in_msb (tree valtype) 5449{ 5450 return (TARGET_AAPCS_BASED 5451 && BYTES_BIG_ENDIAN 5452 && (AGGREGATE_TYPE_P (valtype) 5453 || TREE_CODE (valtype) == COMPLEX_TYPE)); 5454} 5455 5456/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. 5457 Use by the Cirrus Maverick code which has to workaround 5458 a hardware bug triggered by such instructions. */ 5459static bool 5460arm_memory_load_p (rtx insn) 5461{ 5462 rtx body, lhs, rhs;; 5463 5464 if (insn == NULL_RTX || GET_CODE (insn) != INSN) 5465 return false; 5466 5467 body = PATTERN (insn); 5468 5469 if (GET_CODE (body) != SET) 5470 return false; 5471 5472 lhs = XEXP (body, 0); 5473 rhs = XEXP (body, 1); 5474 5475 lhs = REG_OR_SUBREG_RTX (lhs); 5476 5477 /* If the destination is not a general purpose 5478 register we do not have to worry. */ 5479 if (GET_CODE (lhs) != REG 5480 || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) 5481 return false; 5482 5483 /* As well as loads from memory we also have to react 5484 to loads of invalid constants which will be turned 5485 into loads from the minipool. */ 5486 return (GET_CODE (rhs) == MEM 5487 || GET_CODE (rhs) == SYMBOL_REF 5488 || note_invalid_constants (insn, -1, false)); 5489} 5490 5491/* Return TRUE if INSN is a Cirrus instruction. */ 5492static bool 5493arm_cirrus_insn_p (rtx insn) 5494{ 5495 enum attr_cirrus attr; 5496 5497 /* get_attr cannot accept USE or CLOBBER. */ 5498 if (!insn 5499 || GET_CODE (insn) != INSN 5500 || GET_CODE (PATTERN (insn)) == USE 5501 || GET_CODE (PATTERN (insn)) == CLOBBER) 5502 return 0; 5503 5504 attr = get_attr_cirrus (insn); 5505 5506 return attr != CIRRUS_NOT; 5507} 5508 5509/* Cirrus reorg for invalid instruction combinations. */ 5510static void 5511cirrus_reorg (rtx first) 5512{ 5513 enum attr_cirrus attr; 5514 rtx body = PATTERN (first); 5515 rtx t; 5516 int nops; 5517 5518 /* Any branch must be followed by 2 non Cirrus instructions. */ 5519 if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) 5520 { 5521 nops = 0; 5522 t = next_nonnote_insn (first); 5523 5524 if (arm_cirrus_insn_p (t)) 5525 ++ nops; 5526 5527 if (arm_cirrus_insn_p (next_nonnote_insn (t))) 5528 ++ nops; 5529 5530 while (nops --) 5531 emit_insn_after (gen_nop (), first); 5532 5533 return; 5534 } 5535 5536 /* (float (blah)) is in parallel with a clobber. */ 5537 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) 5538 body = XVECEXP (body, 0, 0); 5539 5540 if (GET_CODE (body) == SET) 5541 { 5542 rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); 5543 5544 /* cfldrd, cfldr64, cfstrd, cfstr64 must 5545 be followed by a non Cirrus insn. */ 5546 if (get_attr_cirrus (first) == CIRRUS_DOUBLE) 5547 { 5548 if (arm_cirrus_insn_p (next_nonnote_insn (first))) 5549 emit_insn_after (gen_nop (), first); 5550 5551 return; 5552 } 5553 else if (arm_memory_load_p (first)) 5554 { 5555 unsigned int arm_regno; 5556 5557 /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, 5558 ldr/cfmv64hr combination where the Rd field is the same 5559 in both instructions must be split with a non Cirrus 5560 insn. Example: 5561 5562 ldr r0, blah 5563 nop 5564 cfmvsr mvf0, r0. */ 5565 5566 /* Get Arm register number for ldr insn. */ 5567 if (GET_CODE (lhs) == REG) 5568 arm_regno = REGNO (lhs); 5569 else 5570 { 5571 gcc_assert (GET_CODE (rhs) == REG); 5572 arm_regno = REGNO (rhs); 5573 } 5574 5575 /* Next insn. */ 5576 first = next_nonnote_insn (first); 5577 5578 if (! arm_cirrus_insn_p (first)) 5579 return; 5580 5581 body = PATTERN (first); 5582 5583 /* (float (blah)) is in parallel with a clobber. */ 5584 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) 5585 body = XVECEXP (body, 0, 0); 5586 5587 if (GET_CODE (body) == FLOAT) 5588 body = XEXP (body, 0); 5589 5590 if (get_attr_cirrus (first) == CIRRUS_MOVE 5591 && GET_CODE (XEXP (body, 1)) == REG 5592 && arm_regno == REGNO (XEXP (body, 1))) 5593 emit_insn_after (gen_nop (), first); 5594 5595 return; 5596 } 5597 } 5598 5599 /* get_attr cannot accept USE or CLOBBER. */ 5600 if (!first 5601 || GET_CODE (first) != INSN 5602 || GET_CODE (PATTERN (first)) == USE 5603 || GET_CODE (PATTERN (first)) == CLOBBER) 5604 return; 5605 5606 attr = get_attr_cirrus (first); 5607 5608 /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) 5609 must be followed by a non-coprocessor instruction. */ 5610 if (attr == CIRRUS_COMPARE) 5611 { 5612 nops = 0; 5613 5614 t = next_nonnote_insn (first); 5615 5616 if (arm_cirrus_insn_p (t)) 5617 ++ nops; 5618 5619 if (arm_cirrus_insn_p (next_nonnote_insn (t))) 5620 ++ nops; 5621 5622 while (nops --) 5623 emit_insn_after (gen_nop (), first); 5624 5625 return; 5626 } 5627} 5628 5629/* Return TRUE if X references a SYMBOL_REF. */ 5630int 5631symbol_mentioned_p (rtx x) 5632{ 5633 const char * fmt; 5634 int i; 5635 5636 if (GET_CODE (x) == SYMBOL_REF) 5637 return 1; 5638 5639 /* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they 5640 are constant offsets, not symbols. */ 5641 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) 5642 return 0; 5643 5644 fmt = GET_RTX_FORMAT (GET_CODE (x)); 5645 5646 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 5647 { 5648 if (fmt[i] == 'E') 5649 { 5650 int j; 5651 5652 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 5653 if (symbol_mentioned_p (XVECEXP (x, i, j))) 5654 return 1; 5655 } 5656 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) 5657 return 1; 5658 } 5659 5660 return 0; 5661} 5662 5663/* Return TRUE if X references a LABEL_REF. */ 5664int 5665label_mentioned_p (rtx x) 5666{ 5667 const char * fmt; 5668 int i; 5669 5670 if (GET_CODE (x) == LABEL_REF) 5671 return 1; 5672 5673 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing 5674 instruction, but they are constant offsets, not symbols. */ 5675 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) 5676 return 0; 5677 5678 fmt = GET_RTX_FORMAT (GET_CODE (x)); 5679 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 5680 { 5681 if (fmt[i] == 'E') 5682 { 5683 int j; 5684 5685 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 5686 if (label_mentioned_p (XVECEXP (x, i, j))) 5687 return 1; 5688 } 5689 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) 5690 return 1; 5691 } 5692 5693 return 0; 5694} 5695 5696int 5697tls_mentioned_p (rtx x) 5698{ 5699 switch (GET_CODE (x)) 5700 { 5701 case CONST: 5702 return tls_mentioned_p (XEXP (x, 0)); 5703 5704 case UNSPEC: 5705 if (XINT (x, 1) == UNSPEC_TLS) 5706 return 1; 5707 5708 default: 5709 return 0; 5710 } 5711} 5712 5713/* Must not copy a SET whose source operand is PC-relative. */ 5714 5715static bool 5716arm_cannot_copy_insn_p (rtx insn) 5717{ 5718 rtx pat = PATTERN (insn); 5719 5720 if (GET_CODE (pat) == PARALLEL 5721 && GET_CODE (XVECEXP (pat, 0, 0)) == SET) 5722 { 5723 rtx rhs = SET_SRC (XVECEXP (pat, 0, 0)); 5724 5725 if (GET_CODE (rhs) == UNSPEC 5726 && XINT (rhs, 1) == UNSPEC_PIC_BASE) 5727 return TRUE; 5728 5729 if (GET_CODE (rhs) == MEM 5730 && GET_CODE (XEXP (rhs, 0)) == UNSPEC 5731 && XINT (XEXP (rhs, 0), 1) == UNSPEC_PIC_BASE) 5732 return TRUE; 5733 } 5734 5735 return FALSE; 5736} 5737 5738enum rtx_code 5739minmax_code (rtx x) 5740{ 5741 enum rtx_code code = GET_CODE (x); 5742 5743 switch (code) 5744 { 5745 case SMAX: 5746 return GE; 5747 case SMIN: 5748 return LE; 5749 case UMIN: 5750 return LEU; 5751 case UMAX: 5752 return GEU; 5753 default: 5754 gcc_unreachable (); 5755 } 5756} 5757 5758/* Return 1 if memory locations are adjacent. */ 5759int 5760adjacent_mem_locations (rtx a, rtx b) 5761{ 5762 /* We don't guarantee to preserve the order of these memory refs. */ 5763 if (volatile_refs_p (a) || volatile_refs_p (b)) 5764 return 0; 5765 5766 if ((GET_CODE (XEXP (a, 0)) == REG 5767 || (GET_CODE (XEXP (a, 0)) == PLUS 5768 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) 5769 && (GET_CODE (XEXP (b, 0)) == REG 5770 || (GET_CODE (XEXP (b, 0)) == PLUS 5771 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) 5772 { 5773 HOST_WIDE_INT val0 = 0, val1 = 0; 5774 rtx reg0, reg1; 5775 int val_diff; 5776 5777 if (GET_CODE (XEXP (a, 0)) == PLUS) 5778 { 5779 reg0 = XEXP (XEXP (a, 0), 0); 5780 val0 = INTVAL (XEXP (XEXP (a, 0), 1)); 5781 } 5782 else 5783 reg0 = XEXP (a, 0); 5784 5785 if (GET_CODE (XEXP (b, 0)) == PLUS) 5786 { 5787 reg1 = XEXP (XEXP (b, 0), 0); 5788 val1 = INTVAL (XEXP (XEXP (b, 0), 1)); 5789 } 5790 else 5791 reg1 = XEXP (b, 0); 5792 5793 /* Don't accept any offset that will require multiple 5794 instructions to handle, since this would cause the 5795 arith_adjacentmem pattern to output an overlong sequence. */ 5796 if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1)) 5797 return 0; 5798 5799 /* Don't allow an eliminable register: register elimination can make 5800 the offset too large. */ 5801 if (arm_eliminable_register (reg0)) 5802 return 0; 5803 5804 val_diff = val1 - val0; 5805 5806 if (arm_ld_sched) 5807 { 5808 /* If the target has load delay slots, then there's no benefit 5809 to using an ldm instruction unless the offset is zero and 5810 we are optimizing for size. */ 5811 return (optimize_size && (REGNO (reg0) == REGNO (reg1)) 5812 && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4) 5813 && (val_diff == 4 || val_diff == -4)); 5814 } 5815 5816 return ((REGNO (reg0) == REGNO (reg1)) 5817 && (val_diff == 4 || val_diff == -4)); 5818 } 5819 5820 return 0; 5821} 5822 5823int 5824load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, 5825 HOST_WIDE_INT *load_offset) 5826{ 5827 int unsorted_regs[4]; 5828 HOST_WIDE_INT unsorted_offsets[4]; 5829 int order[4]; 5830 int base_reg = -1; 5831 int i; 5832 5833 /* Can only handle 2, 3, or 4 insns at present, 5834 though could be easily extended if required. */ 5835 gcc_assert (nops >= 2 && nops <= 4); 5836 5837 /* Loop over the operands and check that the memory references are 5838 suitable (i.e. immediate offsets from the same base register). At 5839 the same time, extract the target register, and the memory 5840 offsets. */ 5841 for (i = 0; i < nops; i++) 5842 { 5843 rtx reg; 5844 rtx offset; 5845 5846 /* Convert a subreg of a mem into the mem itself. */ 5847 if (GET_CODE (operands[nops + i]) == SUBREG) 5848 operands[nops + i] = alter_subreg (operands + (nops + i)); 5849 5850 gcc_assert (GET_CODE (operands[nops + i]) == MEM); 5851 5852 /* Don't reorder volatile memory references; it doesn't seem worth 5853 looking for the case where the order is ok anyway. */ 5854 if (MEM_VOLATILE_P (operands[nops + i])) 5855 return 0; 5856 5857 offset = const0_rtx; 5858 5859 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG 5860 || (GET_CODE (reg) == SUBREG 5861 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 5862 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS 5863 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) 5864 == REG) 5865 || (GET_CODE (reg) == SUBREG 5866 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 5867 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) 5868 == CONST_INT))) 5869 { 5870 if (i == 0) 5871 { 5872 base_reg = REGNO (reg); 5873 unsorted_regs[0] = (GET_CODE (operands[i]) == REG 5874 ? REGNO (operands[i]) 5875 : REGNO (SUBREG_REG (operands[i]))); 5876 order[0] = 0; 5877 } 5878 else 5879 { 5880 if (base_reg != (int) REGNO (reg)) 5881 /* Not addressed from the same base register. */ 5882 return 0; 5883 5884 unsorted_regs[i] = (GET_CODE (operands[i]) == REG 5885 ? REGNO (operands[i]) 5886 : REGNO (SUBREG_REG (operands[i]))); 5887 if (unsorted_regs[i] < unsorted_regs[order[0]]) 5888 order[0] = i; 5889 } 5890 5891 /* If it isn't an integer register, or if it overwrites the 5892 base register but isn't the last insn in the list, then 5893 we can't do this. */ 5894 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 5895 || (i != nops - 1 && unsorted_regs[i] == base_reg)) 5896 return 0; 5897 5898 unsorted_offsets[i] = INTVAL (offset); 5899 } 5900 else 5901 /* Not a suitable memory address. */ 5902 return 0; 5903 } 5904 5905 /* All the useful information has now been extracted from the 5906 operands into unsorted_regs and unsorted_offsets; additionally, 5907 order[0] has been set to the lowest numbered register in the 5908 list. Sort the registers into order, and check that the memory 5909 offsets are ascending and adjacent. */ 5910 5911 for (i = 1; i < nops; i++) 5912 { 5913 int j; 5914 5915 order[i] = order[i - 1]; 5916 for (j = 0; j < nops; j++) 5917 if (unsorted_regs[j] > unsorted_regs[order[i - 1]] 5918 && (order[i] == order[i - 1] 5919 || unsorted_regs[j] < unsorted_regs[order[i]])) 5920 order[i] = j; 5921 5922 /* Have we found a suitable register? if not, one must be used more 5923 than once. */ 5924 if (order[i] == order[i - 1]) 5925 return 0; 5926 5927 /* Is the memory address adjacent and ascending? */ 5928 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) 5929 return 0; 5930 } 5931 5932 if (base) 5933 { 5934 *base = base_reg; 5935 5936 for (i = 0; i < nops; i++) 5937 regs[i] = unsorted_regs[order[i]]; 5938 5939 *load_offset = unsorted_offsets[order[0]]; 5940 } 5941 5942 if (unsorted_offsets[order[0]] == 0) 5943 return 1; /* ldmia */ 5944 5945 if (unsorted_offsets[order[0]] == 4) 5946 return 2; /* ldmib */ 5947 5948 if (unsorted_offsets[order[nops - 1]] == 0) 5949 return 3; /* ldmda */ 5950 5951 if (unsorted_offsets[order[nops - 1]] == -4) 5952 return 4; /* ldmdb */ 5953 5954 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm 5955 if the offset isn't small enough. The reason 2 ldrs are faster 5956 is because these ARMs are able to do more than one cache access 5957 in a single cycle. The ARM9 and StrongARM have Harvard caches, 5958 whilst the ARM8 has a double bandwidth cache. This means that 5959 these cores can do both an instruction fetch and a data fetch in 5960 a single cycle, so the trick of calculating the address into a 5961 scratch register (one of the result regs) and then doing a load 5962 multiple actually becomes slower (and no smaller in code size). 5963 That is the transformation 5964 5965 ldr rd1, [rbase + offset] 5966 ldr rd2, [rbase + offset + 4] 5967 5968 to 5969 5970 add rd1, rbase, offset 5971 ldmia rd1, {rd1, rd2} 5972 5973 produces worse code -- '3 cycles + any stalls on rd2' instead of 5974 '2 cycles + any stalls on rd2'. On ARMs with only one cache 5975 access per cycle, the first sequence could never complete in less 5976 than 6 cycles, whereas the ldm sequence would only take 5 and 5977 would make better use of sequential accesses if not hitting the 5978 cache. 5979 5980 We cheat here and test 'arm_ld_sched' which we currently know to 5981 only be true for the ARM8, ARM9 and StrongARM. If this ever 5982 changes, then the test below needs to be reworked. */ 5983 if (nops == 2 && arm_ld_sched) 5984 return 0; 5985 5986 /* Can't do it without setting up the offset, only do this if it takes 5987 no more than one insn. */ 5988 return (const_ok_for_arm (unsorted_offsets[order[0]]) 5989 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; 5990} 5991 5992const char * 5993emit_ldm_seq (rtx *operands, int nops) 5994{ 5995 int regs[4]; 5996 int base_reg; 5997 HOST_WIDE_INT offset; 5998 char buf[100]; 5999 int i; 6000 6001 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) 6002 { 6003 case 1: 6004 strcpy (buf, "ldm%?ia\t"); 6005 break; 6006 6007 case 2: 6008 strcpy (buf, "ldm%?ib\t"); 6009 break; 6010 6011 case 3: 6012 strcpy (buf, "ldm%?da\t"); 6013 break; 6014 6015 case 4: 6016 strcpy (buf, "ldm%?db\t"); 6017 break; 6018 6019 case 5: 6020 if (offset >= 0) 6021 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, 6022 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], 6023 (long) offset); 6024 else 6025 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, 6026 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], 6027 (long) -offset); 6028 output_asm_insn (buf, operands); 6029 base_reg = regs[0]; 6030 strcpy (buf, "ldm%?ia\t"); 6031 break; 6032 6033 default: 6034 gcc_unreachable (); 6035 } 6036 6037 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, 6038 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); 6039 6040 for (i = 1; i < nops; i++) 6041 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, 6042 reg_names[regs[i]]); 6043 6044 strcat (buf, "}\t%@ phole ldm"); 6045 6046 output_asm_insn (buf, operands); 6047 return ""; 6048} 6049 6050int 6051store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, 6052 HOST_WIDE_INT * load_offset) 6053{ 6054 int unsorted_regs[4]; 6055 HOST_WIDE_INT unsorted_offsets[4]; 6056 int order[4]; 6057 int base_reg = -1; 6058 int i; 6059 6060 /* Can only handle 2, 3, or 4 insns at present, though could be easily 6061 extended if required. */ 6062 gcc_assert (nops >= 2 && nops <= 4); 6063 6064 /* Loop over the operands and check that the memory references are 6065 suitable (i.e. immediate offsets from the same base register). At 6066 the same time, extract the target register, and the memory 6067 offsets. */ 6068 for (i = 0; i < nops; i++) 6069 { 6070 rtx reg; 6071 rtx offset; 6072 6073 /* Convert a subreg of a mem into the mem itself. */ 6074 if (GET_CODE (operands[nops + i]) == SUBREG) 6075 operands[nops + i] = alter_subreg (operands + (nops + i)); 6076 6077 gcc_assert (GET_CODE (operands[nops + i]) == MEM); 6078 6079 /* Don't reorder volatile memory references; it doesn't seem worth 6080 looking for the case where the order is ok anyway. */ 6081 if (MEM_VOLATILE_P (operands[nops + i])) 6082 return 0; 6083 6084 offset = const0_rtx; 6085 6086 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG 6087 || (GET_CODE (reg) == SUBREG 6088 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 6089 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS 6090 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) 6091 == REG) 6092 || (GET_CODE (reg) == SUBREG 6093 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 6094 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) 6095 == CONST_INT))) 6096 { 6097 if (i == 0) 6098 { 6099 base_reg = REGNO (reg); 6100 unsorted_regs[0] = (GET_CODE (operands[i]) == REG 6101 ? REGNO (operands[i]) 6102 : REGNO (SUBREG_REG (operands[i]))); 6103 order[0] = 0; 6104 } 6105 else 6106 { 6107 if (base_reg != (int) REGNO (reg)) 6108 /* Not addressed from the same base register. */ 6109 return 0; 6110 6111 unsorted_regs[i] = (GET_CODE (operands[i]) == REG 6112 ? REGNO (operands[i]) 6113 : REGNO (SUBREG_REG (operands[i]))); 6114 if (unsorted_regs[i] < unsorted_regs[order[0]]) 6115 order[0] = i; 6116 } 6117 6118 /* If it isn't an integer register, then we can't do this. */ 6119 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) 6120 return 0; 6121 6122 unsorted_offsets[i] = INTVAL (offset); 6123 } 6124 else 6125 /* Not a suitable memory address. */ 6126 return 0; 6127 } 6128 6129 /* All the useful information has now been extracted from the 6130 operands into unsorted_regs and unsorted_offsets; additionally, 6131 order[0] has been set to the lowest numbered register in the 6132 list. Sort the registers into order, and check that the memory 6133 offsets are ascending and adjacent. */ 6134 6135 for (i = 1; i < nops; i++) 6136 { 6137 int j; 6138 6139 order[i] = order[i - 1]; 6140 for (j = 0; j < nops; j++) 6141 if (unsorted_regs[j] > unsorted_regs[order[i - 1]] 6142 && (order[i] == order[i - 1] 6143 || unsorted_regs[j] < unsorted_regs[order[i]])) 6144 order[i] = j; 6145 6146 /* Have we found a suitable register? if not, one must be used more 6147 than once. */ 6148 if (order[i] == order[i - 1]) 6149 return 0; 6150 6151 /* Is the memory address adjacent and ascending? */ 6152 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) 6153 return 0; 6154 } 6155 6156 if (base) 6157 { 6158 *base = base_reg; 6159 6160 for (i = 0; i < nops; i++) 6161 regs[i] = unsorted_regs[order[i]]; 6162 6163 *load_offset = unsorted_offsets[order[0]]; 6164 } 6165 6166 if (unsorted_offsets[order[0]] == 0) 6167 return 1; /* stmia */ 6168 6169 if (unsorted_offsets[order[0]] == 4) 6170 return 2; /* stmib */ 6171 6172 if (unsorted_offsets[order[nops - 1]] == 0) 6173 return 3; /* stmda */ 6174 6175 if (unsorted_offsets[order[nops - 1]] == -4) 6176 return 4; /* stmdb */ 6177 6178 return 0; 6179} 6180 6181const char * 6182emit_stm_seq (rtx *operands, int nops) 6183{ 6184 int regs[4]; 6185 int base_reg; 6186 HOST_WIDE_INT offset; 6187 char buf[100]; 6188 int i; 6189 6190 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) 6191 { 6192 case 1: 6193 strcpy (buf, "stm%?ia\t"); 6194 break; 6195 6196 case 2: 6197 strcpy (buf, "stm%?ib\t"); 6198 break; 6199 6200 case 3: 6201 strcpy (buf, "stm%?da\t"); 6202 break; 6203 6204 case 4: 6205 strcpy (buf, "stm%?db\t"); 6206 break; 6207 6208 default: 6209 gcc_unreachable (); 6210 } 6211 6212 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, 6213 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); 6214 6215 for (i = 1; i < nops; i++) 6216 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, 6217 reg_names[regs[i]]); 6218 6219 strcat (buf, "}\t%@ phole stm"); 6220 6221 output_asm_insn (buf, operands); 6222 return ""; 6223} 6224 6225/* Routines for use in generating RTL. */ 6226 6227rtx 6228arm_gen_load_multiple (int base_regno, int count, rtx from, int up, 6229 int write_back, rtx basemem, HOST_WIDE_INT *offsetp) 6230{ 6231 HOST_WIDE_INT offset = *offsetp; 6232 int i = 0, j; 6233 rtx result; 6234 int sign = up ? 1 : -1; 6235 rtx mem, addr; 6236 6237 /* XScale has load-store double instructions, but they have stricter 6238 alignment requirements than load-store multiple, so we cannot 6239 use them. 6240 6241 For XScale ldm requires 2 + NREGS cycles to complete and blocks 6242 the pipeline until completion. 6243 6244 NREGS CYCLES 6245 1 3 6246 2 4 6247 3 5 6248 4 6 6249 6250 An ldr instruction takes 1-3 cycles, but does not block the 6251 pipeline. 6252 6253 NREGS CYCLES 6254 1 1-3 6255 2 2-6 6256 3 3-9 6257 4 4-12 6258 6259 Best case ldr will always win. However, the more ldr instructions 6260 we issue, the less likely we are to be able to schedule them well. 6261 Using ldr instructions also increases code size. 6262 6263 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm 6264 for counts of 3 or 4 regs. */ 6265 if (arm_tune_xscale && count <= 2 && ! optimize_size) 6266 { 6267 rtx seq; 6268 6269 start_sequence (); 6270 6271 for (i = 0; i < count; i++) 6272 { 6273 addr = plus_constant (from, i * 4 * sign); 6274 mem = adjust_automodify_address (basemem, SImode, addr, offset); 6275 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); 6276 offset += 4 * sign; 6277 } 6278 6279 if (write_back) 6280 { 6281 emit_move_insn (from, plus_constant (from, count * 4 * sign)); 6282 *offsetp = offset; 6283 } 6284 6285 seq = get_insns (); 6286 end_sequence (); 6287 6288 return seq; 6289 } 6290 6291 result = gen_rtx_PARALLEL (VOIDmode, 6292 rtvec_alloc (count + (write_back ? 1 : 0))); 6293 if (write_back) 6294 { 6295 XVECEXP (result, 0, 0) 6296 = gen_rtx_SET (VOIDmode, from, plus_constant (from, count * 4 * sign)); 6297 i = 1; 6298 count++; 6299 } 6300 6301 for (j = 0; i < count; i++, j++) 6302 { 6303 addr = plus_constant (from, j * 4 * sign); 6304 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); 6305 XVECEXP (result, 0, i) 6306 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); 6307 offset += 4 * sign; 6308 } 6309 6310 if (write_back) 6311 *offsetp = offset; 6312 6313 return result; 6314} 6315 6316rtx 6317arm_gen_store_multiple (int base_regno, int count, rtx to, int up, 6318 int write_back, rtx basemem, HOST_WIDE_INT *offsetp) 6319{ 6320 HOST_WIDE_INT offset = *offsetp; 6321 int i = 0, j; 6322 rtx result; 6323 int sign = up ? 1 : -1; 6324 rtx mem, addr; 6325 6326 /* See arm_gen_load_multiple for discussion of 6327 the pros/cons of ldm/stm usage for XScale. */ 6328 if (arm_tune_xscale && count <= 2 && ! optimize_size) 6329 { 6330 rtx seq; 6331 6332 start_sequence (); 6333 6334 for (i = 0; i < count; i++) 6335 { 6336 addr = plus_constant (to, i * 4 * sign); 6337 mem = adjust_automodify_address (basemem, SImode, addr, offset); 6338 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); 6339 offset += 4 * sign; 6340 } 6341 6342 if (write_back) 6343 { 6344 emit_move_insn (to, plus_constant (to, count * 4 * sign)); 6345 *offsetp = offset; 6346 } 6347 6348 seq = get_insns (); 6349 end_sequence (); 6350 6351 return seq; 6352 } 6353 6354 result = gen_rtx_PARALLEL (VOIDmode, 6355 rtvec_alloc (count + (write_back ? 1 : 0))); 6356 if (write_back) 6357 { 6358 XVECEXP (result, 0, 0) 6359 = gen_rtx_SET (VOIDmode, to, 6360 plus_constant (to, count * 4 * sign)); 6361 i = 1; 6362 count++; 6363 } 6364 6365 for (j = 0; i < count; i++, j++) 6366 { 6367 addr = plus_constant (to, j * 4 * sign); 6368 mem = adjust_automodify_address_nv (basemem, SImode, addr, offset); 6369 XVECEXP (result, 0, i) 6370 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); 6371 offset += 4 * sign; 6372 } 6373 6374 if (write_back) 6375 *offsetp = offset; 6376 6377 return result; 6378} 6379 6380int 6381arm_gen_movmemqi (rtx *operands) 6382{ 6383 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; 6384 HOST_WIDE_INT srcoffset, dstoffset; 6385 int i; 6386 rtx src, dst, srcbase, dstbase; 6387 rtx part_bytes_reg = NULL; 6388 rtx mem; 6389 6390 if (GET_CODE (operands[2]) != CONST_INT 6391 || GET_CODE (operands[3]) != CONST_INT 6392 || INTVAL (operands[2]) > 64 6393 || INTVAL (operands[3]) & 3) 6394 return 0; 6395 6396 dstbase = operands[0]; 6397 srcbase = operands[1]; 6398 6399 dst = copy_to_mode_reg (SImode, XEXP (dstbase, 0)); 6400 src = copy_to_mode_reg (SImode, XEXP (srcbase, 0)); 6401 6402 in_words_to_go = ARM_NUM_INTS (INTVAL (operands[2])); 6403 out_words_to_go = INTVAL (operands[2]) / 4; 6404 last_bytes = INTVAL (operands[2]) & 3; 6405 dstoffset = srcoffset = 0; 6406 6407 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) 6408 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); 6409 6410 for (i = 0; in_words_to_go >= 2; i+=4) 6411 { 6412 if (in_words_to_go > 4) 6413 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, 6414 srcbase, &srcoffset)); 6415 else 6416 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, 6417 FALSE, srcbase, &srcoffset)); 6418 6419 if (out_words_to_go) 6420 { 6421 if (out_words_to_go > 4) 6422 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, 6423 dstbase, &dstoffset)); 6424 else if (out_words_to_go != 1) 6425 emit_insn (arm_gen_store_multiple (0, out_words_to_go, 6426 dst, TRUE, 6427 (last_bytes == 0 6428 ? FALSE : TRUE), 6429 dstbase, &dstoffset)); 6430 else 6431 { 6432 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); 6433 emit_move_insn (mem, gen_rtx_REG (SImode, 0)); 6434 if (last_bytes != 0) 6435 { 6436 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); 6437 dstoffset += 4; 6438 } 6439 } 6440 } 6441 6442 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; 6443 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; 6444 } 6445 6446 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ 6447 if (out_words_to_go) 6448 { 6449 rtx sreg; 6450 6451 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); 6452 sreg = copy_to_reg (mem); 6453 6454 mem = adjust_automodify_address (dstbase, SImode, dst, dstoffset); 6455 emit_move_insn (mem, sreg); 6456 in_words_to_go--; 6457 6458 gcc_assert (!in_words_to_go); /* Sanity check */ 6459 } 6460 6461 if (in_words_to_go) 6462 { 6463 gcc_assert (in_words_to_go > 0); 6464 6465 mem = adjust_automodify_address (srcbase, SImode, src, srcoffset); 6466 part_bytes_reg = copy_to_mode_reg (SImode, mem); 6467 } 6468 6469 gcc_assert (!last_bytes || part_bytes_reg); 6470 6471 if (BYTES_BIG_ENDIAN && last_bytes) 6472 { 6473 rtx tmp = gen_reg_rtx (SImode); 6474 6475 /* The bytes we want are in the top end of the word. */ 6476 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, 6477 GEN_INT (8 * (4 - last_bytes)))); 6478 part_bytes_reg = tmp; 6479 6480 while (last_bytes) 6481 { 6482 mem = adjust_automodify_address (dstbase, QImode, 6483 plus_constant (dst, last_bytes - 1), 6484 dstoffset + last_bytes - 1); 6485 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); 6486 6487 if (--last_bytes) 6488 { 6489 tmp = gen_reg_rtx (SImode); 6490 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); 6491 part_bytes_reg = tmp; 6492 } 6493 } 6494 6495 } 6496 else 6497 { 6498 if (last_bytes > 1) 6499 { 6500 mem = adjust_automodify_address (dstbase, HImode, dst, dstoffset); 6501 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); 6502 last_bytes -= 2; 6503 if (last_bytes) 6504 { 6505 rtx tmp = gen_reg_rtx (SImode); 6506 emit_insn (gen_addsi3 (dst, dst, const2_rtx)); 6507 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); 6508 part_bytes_reg = tmp; 6509 dstoffset += 2; 6510 } 6511 } 6512 6513 if (last_bytes) 6514 { 6515 mem = adjust_automodify_address (dstbase, QImode, dst, dstoffset); 6516 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); 6517 } 6518 } 6519 6520 return 1; 6521} 6522 6523/* Select a dominance comparison mode if possible for a test of the general 6524 form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. 6525 COND_OR == DOM_CC_X_AND_Y => (X && Y) 6526 COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) 6527 COND_OR == DOM_CC_X_OR_Y => (X || Y) 6528 In all cases OP will be either EQ or NE, but we don't need to know which 6529 here. If we are unable to support a dominance comparison we return 6530 CC mode. This will then fail to match for the RTL expressions that 6531 generate this call. */ 6532enum machine_mode 6533arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) 6534{ 6535 enum rtx_code cond1, cond2; 6536 int swapped = 0; 6537 6538 /* Currently we will probably get the wrong result if the individual 6539 comparisons are not simple. This also ensures that it is safe to 6540 reverse a comparison if necessary. */ 6541 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) 6542 != CCmode) 6543 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) 6544 != CCmode)) 6545 return CCmode; 6546 6547 /* The if_then_else variant of this tests the second condition if the 6548 first passes, but is true if the first fails. Reverse the first 6549 condition to get a true "inclusive-or" expression. */ 6550 if (cond_or == DOM_CC_NX_OR_Y) 6551 cond1 = reverse_condition (cond1); 6552 6553 /* If the comparisons are not equal, and one doesn't dominate the other, 6554 then we can't do this. */ 6555 if (cond1 != cond2 6556 && !comparison_dominates_p (cond1, cond2) 6557 && (swapped = 1, !comparison_dominates_p (cond2, cond1))) 6558 return CCmode; 6559 6560 if (swapped) 6561 { 6562 enum rtx_code temp = cond1; 6563 cond1 = cond2; 6564 cond2 = temp; 6565 } 6566 6567 switch (cond1) 6568 { 6569 case EQ: 6570 if (cond_or == DOM_CC_X_AND_Y) 6571 return CC_DEQmode; 6572 6573 switch (cond2) 6574 { 6575 case EQ: return CC_DEQmode; 6576 case LE: return CC_DLEmode; 6577 case LEU: return CC_DLEUmode; 6578 case GE: return CC_DGEmode; 6579 case GEU: return CC_DGEUmode; 6580 default: gcc_unreachable (); 6581 } 6582 6583 case LT: 6584 if (cond_or == DOM_CC_X_AND_Y) 6585 return CC_DLTmode; 6586 6587 switch (cond2) 6588 { 6589 case LT: 6590 return CC_DLTmode; 6591 case LE: 6592 return CC_DLEmode; 6593 case NE: 6594 return CC_DNEmode; 6595 default: 6596 gcc_unreachable (); 6597 } 6598 6599 case GT: 6600 if (cond_or == DOM_CC_X_AND_Y) 6601 return CC_DGTmode; 6602 6603 switch (cond2) 6604 { 6605 case GT: 6606 return CC_DGTmode; 6607 case GE: 6608 return CC_DGEmode; 6609 case NE: 6610 return CC_DNEmode; 6611 default: 6612 gcc_unreachable (); 6613 } 6614 6615 case LTU: 6616 if (cond_or == DOM_CC_X_AND_Y) 6617 return CC_DLTUmode; 6618 6619 switch (cond2) 6620 { 6621 case LTU: 6622 return CC_DLTUmode; 6623 case LEU: 6624 return CC_DLEUmode; 6625 case NE: 6626 return CC_DNEmode; 6627 default: 6628 gcc_unreachable (); 6629 } 6630 6631 case GTU: 6632 if (cond_or == DOM_CC_X_AND_Y) 6633 return CC_DGTUmode; 6634 6635 switch (cond2) 6636 { 6637 case GTU: 6638 return CC_DGTUmode; 6639 case GEU: 6640 return CC_DGEUmode; 6641 case NE: 6642 return CC_DNEmode; 6643 default: 6644 gcc_unreachable (); 6645 } 6646 6647 /* The remaining cases only occur when both comparisons are the 6648 same. */ 6649 case NE: 6650 gcc_assert (cond1 == cond2); 6651 return CC_DNEmode; 6652 6653 case LE: 6654 gcc_assert (cond1 == cond2); 6655 return CC_DLEmode; 6656 6657 case GE: 6658 gcc_assert (cond1 == cond2); 6659 return CC_DGEmode; 6660 6661 case LEU: 6662 gcc_assert (cond1 == cond2); 6663 return CC_DLEUmode; 6664 6665 case GEU: 6666 gcc_assert (cond1 == cond2); 6667 return CC_DGEUmode; 6668 6669 default: 6670 gcc_unreachable (); 6671 } 6672} 6673 6674enum machine_mode 6675arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) 6676{ 6677 /* All floating point compares return CCFP if it is an equality 6678 comparison, and CCFPE otherwise. */ 6679 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 6680 { 6681 switch (op) 6682 { 6683 case EQ: 6684 case NE: 6685 case UNORDERED: 6686 case ORDERED: 6687 case UNLT: 6688 case UNLE: 6689 case UNGT: 6690 case UNGE: 6691 case UNEQ: 6692 case LTGT: 6693 return CCFPmode; 6694 6695 case LT: 6696 case LE: 6697 case GT: 6698 case GE: 6699 if (TARGET_HARD_FLOAT && TARGET_MAVERICK) 6700 return CCFPmode; 6701 return CCFPEmode; 6702 6703 default: 6704 gcc_unreachable (); 6705 } 6706 } 6707 6708 /* A compare with a shifted operand. Because of canonicalization, the 6709 comparison will have to be swapped when we emit the assembler. */ 6710 if (GET_MODE (y) == SImode && GET_CODE (y) == REG 6711 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT 6712 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE 6713 || GET_CODE (x) == ROTATERT)) 6714 return CC_SWPmode; 6715 6716 /* This operation is performed swapped, but since we only rely on the Z 6717 flag we don't need an additional mode. */ 6718 if (GET_MODE (y) == SImode && REG_P (y) 6719 && GET_CODE (x) == NEG 6720 && (op == EQ || op == NE)) 6721 return CC_Zmode; 6722 6723 /* This is a special case that is used by combine to allow a 6724 comparison of a shifted byte load to be split into a zero-extend 6725 followed by a comparison of the shifted integer (only valid for 6726 equalities and unsigned inequalities). */ 6727 if (GET_MODE (x) == SImode 6728 && GET_CODE (x) == ASHIFT 6729 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 6730 && GET_CODE (XEXP (x, 0)) == SUBREG 6731 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM 6732 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode 6733 && (op == EQ || op == NE 6734 || op == GEU || op == GTU || op == LTU || op == LEU) 6735 && GET_CODE (y) == CONST_INT) 6736 return CC_Zmode; 6737 6738 /* A construct for a conditional compare, if the false arm contains 6739 0, then both conditions must be true, otherwise either condition 6740 must be true. Not all conditions are possible, so CCmode is 6741 returned if it can't be done. */ 6742 if (GET_CODE (x) == IF_THEN_ELSE 6743 && (XEXP (x, 2) == const0_rtx 6744 || XEXP (x, 2) == const1_rtx) 6745 && COMPARISON_P (XEXP (x, 0)) 6746 && COMPARISON_P (XEXP (x, 1))) 6747 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 6748 INTVAL (XEXP (x, 2))); 6749 6750 /* Alternate canonicalizations of the above. These are somewhat cleaner. */ 6751 if (GET_CODE (x) == AND 6752 && COMPARISON_P (XEXP (x, 0)) 6753 && COMPARISON_P (XEXP (x, 1))) 6754 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 6755 DOM_CC_X_AND_Y); 6756 6757 if (GET_CODE (x) == IOR 6758 && COMPARISON_P (XEXP (x, 0)) 6759 && COMPARISON_P (XEXP (x, 1))) 6760 return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 6761 DOM_CC_X_OR_Y); 6762 6763 /* An operation (on Thumb) where we want to test for a single bit. 6764 This is done by shifting that bit up into the top bit of a 6765 scratch register; we can then branch on the sign bit. */ 6766 if (TARGET_THUMB 6767 && GET_MODE (x) == SImode 6768 && (op == EQ || op == NE) 6769 && GET_CODE (x) == ZERO_EXTRACT 6770 && XEXP (x, 1) == const1_rtx) 6771 return CC_Nmode; 6772 6773 /* An operation that sets the condition codes as a side-effect, the 6774 V flag is not set correctly, so we can only use comparisons where 6775 this doesn't matter. (For LT and GE we can use "mi" and "pl" 6776 instead.) */ 6777 if (GET_MODE (x) == SImode 6778 && y == const0_rtx 6779 && (op == EQ || op == NE || op == LT || op == GE) 6780 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS 6781 || GET_CODE (x) == AND || GET_CODE (x) == IOR 6782 || GET_CODE (x) == XOR || GET_CODE (x) == MULT 6783 || GET_CODE (x) == NOT || GET_CODE (x) == NEG 6784 || GET_CODE (x) == LSHIFTRT 6785 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT 6786 || GET_CODE (x) == ROTATERT 6787 || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT))) 6788 return CC_NOOVmode; 6789 6790 if (GET_MODE (x) == QImode && (op == EQ || op == NE)) 6791 return CC_Zmode; 6792 6793 if (GET_MODE (x) == SImode && (op == LTU || op == GEU) 6794 && GET_CODE (x) == PLUS 6795 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) 6796 return CC_Cmode; 6797 6798 return CCmode; 6799} 6800 6801/* X and Y are two things to compare using CODE. Emit the compare insn and 6802 return the rtx for register 0 in the proper mode. FP means this is a 6803 floating point compare: I don't think that it is needed on the arm. */ 6804rtx 6805arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) 6806{ 6807 enum machine_mode mode = SELECT_CC_MODE (code, x, y); 6808 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); 6809 6810 emit_set_insn (cc_reg, gen_rtx_COMPARE (mode, x, y)); 6811 6812 return cc_reg; 6813} 6814 6815/* Generate a sequence of insns that will generate the correct return 6816 address mask depending on the physical architecture that the program 6817 is running on. */ 6818rtx 6819arm_gen_return_addr_mask (void) 6820{ 6821 rtx reg = gen_reg_rtx (Pmode); 6822 6823 emit_insn (gen_return_addr_mask (reg)); 6824 return reg; 6825} 6826 6827void 6828arm_reload_in_hi (rtx *operands) 6829{ 6830 rtx ref = operands[1]; 6831 rtx base, scratch; 6832 HOST_WIDE_INT offset = 0; 6833 6834 if (GET_CODE (ref) == SUBREG) 6835 { 6836 offset = SUBREG_BYTE (ref); 6837 ref = SUBREG_REG (ref); 6838 } 6839 6840 if (GET_CODE (ref) == REG) 6841 { 6842 /* We have a pseudo which has been spilt onto the stack; there 6843 are two cases here: the first where there is a simple 6844 stack-slot replacement and a second where the stack-slot is 6845 out of range, or is used as a subreg. */ 6846 if (reg_equiv_mem[REGNO (ref)]) 6847 { 6848 ref = reg_equiv_mem[REGNO (ref)]; 6849 base = find_replacement (&XEXP (ref, 0)); 6850 } 6851 else 6852 /* The slot is out of range, or was dressed up in a SUBREG. */ 6853 base = reg_equiv_address[REGNO (ref)]; 6854 } 6855 else 6856 base = find_replacement (&XEXP (ref, 0)); 6857 6858 /* Handle the case where the address is too complex to be offset by 1. */ 6859 if (GET_CODE (base) == MINUS 6860 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) 6861 { 6862 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 6863 6864 emit_set_insn (base_plus, base); 6865 base = base_plus; 6866 } 6867 else if (GET_CODE (base) == PLUS) 6868 { 6869 /* The addend must be CONST_INT, or we would have dealt with it above. */ 6870 HOST_WIDE_INT hi, lo; 6871 6872 offset += INTVAL (XEXP (base, 1)); 6873 base = XEXP (base, 0); 6874 6875 /* Rework the address into a legal sequence of insns. */ 6876 /* Valid range for lo is -4095 -> 4095 */ 6877 lo = (offset >= 0 6878 ? (offset & 0xfff) 6879 : -((-offset) & 0xfff)); 6880 6881 /* Corner case, if lo is the max offset then we would be out of range 6882 once we have added the additional 1 below, so bump the msb into the 6883 pre-loading insn(s). */ 6884 if (lo == 4095) 6885 lo &= 0x7ff; 6886 6887 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) 6888 ^ (HOST_WIDE_INT) 0x80000000) 6889 - (HOST_WIDE_INT) 0x80000000); 6890 6891 gcc_assert (hi + lo == offset); 6892 6893 if (hi != 0) 6894 { 6895 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 6896 6897 /* Get the base address; addsi3 knows how to handle constants 6898 that require more than one insn. */ 6899 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); 6900 base = base_plus; 6901 offset = lo; 6902 } 6903 } 6904 6905 /* Operands[2] may overlap operands[0] (though it won't overlap 6906 operands[1]), that's why we asked for a DImode reg -- so we can 6907 use the bit that does not overlap. */ 6908 if (REGNO (operands[2]) == REGNO (operands[0])) 6909 scratch = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 6910 else 6911 scratch = gen_rtx_REG (SImode, REGNO (operands[2])); 6912 6913 emit_insn (gen_zero_extendqisi2 (scratch, 6914 gen_rtx_MEM (QImode, 6915 plus_constant (base, 6916 offset)))); 6917 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), 6918 gen_rtx_MEM (QImode, 6919 plus_constant (base, 6920 offset + 1)))); 6921 if (!BYTES_BIG_ENDIAN) 6922 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), 6923 gen_rtx_IOR (SImode, 6924 gen_rtx_ASHIFT 6925 (SImode, 6926 gen_rtx_SUBREG (SImode, operands[0], 0), 6927 GEN_INT (8)), 6928 scratch)); 6929 else 6930 emit_set_insn (gen_rtx_SUBREG (SImode, operands[0], 0), 6931 gen_rtx_IOR (SImode, 6932 gen_rtx_ASHIFT (SImode, scratch, 6933 GEN_INT (8)), 6934 gen_rtx_SUBREG (SImode, operands[0], 0))); 6935} 6936 6937/* Handle storing a half-word to memory during reload by synthesizing as two 6938 byte stores. Take care not to clobber the input values until after we 6939 have moved them somewhere safe. This code assumes that if the DImode 6940 scratch in operands[2] overlaps either the input value or output address 6941 in some way, then that value must die in this insn (we absolutely need 6942 two scratch registers for some corner cases). */ 6943void 6944arm_reload_out_hi (rtx *operands) 6945{ 6946 rtx ref = operands[0]; 6947 rtx outval = operands[1]; 6948 rtx base, scratch; 6949 HOST_WIDE_INT offset = 0; 6950 6951 if (GET_CODE (ref) == SUBREG) 6952 { 6953 offset = SUBREG_BYTE (ref); 6954 ref = SUBREG_REG (ref); 6955 } 6956 6957 if (GET_CODE (ref) == REG) 6958 { 6959 /* We have a pseudo which has been spilt onto the stack; there 6960 are two cases here: the first where there is a simple 6961 stack-slot replacement and a second where the stack-slot is 6962 out of range, or is used as a subreg. */ 6963 if (reg_equiv_mem[REGNO (ref)]) 6964 { 6965 ref = reg_equiv_mem[REGNO (ref)]; 6966 base = find_replacement (&XEXP (ref, 0)); 6967 } 6968 else 6969 /* The slot is out of range, or was dressed up in a SUBREG. */ 6970 base = reg_equiv_address[REGNO (ref)]; 6971 } 6972 else 6973 base = find_replacement (&XEXP (ref, 0)); 6974 6975 scratch = gen_rtx_REG (SImode, REGNO (operands[2])); 6976 6977 /* Handle the case where the address is too complex to be offset by 1. */ 6978 if (GET_CODE (base) == MINUS 6979 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) 6980 { 6981 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 6982 6983 /* Be careful not to destroy OUTVAL. */ 6984 if (reg_overlap_mentioned_p (base_plus, outval)) 6985 { 6986 /* Updating base_plus might destroy outval, see if we can 6987 swap the scratch and base_plus. */ 6988 if (!reg_overlap_mentioned_p (scratch, outval)) 6989 { 6990 rtx tmp = scratch; 6991 scratch = base_plus; 6992 base_plus = tmp; 6993 } 6994 else 6995 { 6996 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); 6997 6998 /* Be conservative and copy OUTVAL into the scratch now, 6999 this should only be necessary if outval is a subreg 7000 of something larger than a word. */ 7001 /* XXX Might this clobber base? I can't see how it can, 7002 since scratch is known to overlap with OUTVAL, and 7003 must be wider than a word. */ 7004 emit_insn (gen_movhi (scratch_hi, outval)); 7005 outval = scratch_hi; 7006 } 7007 } 7008 7009 emit_set_insn (base_plus, base); 7010 base = base_plus; 7011 } 7012 else if (GET_CODE (base) == PLUS) 7013 { 7014 /* The addend must be CONST_INT, or we would have dealt with it above. */ 7015 HOST_WIDE_INT hi, lo; 7016 7017 offset += INTVAL (XEXP (base, 1)); 7018 base = XEXP (base, 0); 7019 7020 /* Rework the address into a legal sequence of insns. */ 7021 /* Valid range for lo is -4095 -> 4095 */ 7022 lo = (offset >= 0 7023 ? (offset & 0xfff) 7024 : -((-offset) & 0xfff)); 7025 7026 /* Corner case, if lo is the max offset then we would be out of range 7027 once we have added the additional 1 below, so bump the msb into the 7028 pre-loading insn(s). */ 7029 if (lo == 4095) 7030 lo &= 0x7ff; 7031 7032 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) 7033 ^ (HOST_WIDE_INT) 0x80000000) 7034 - (HOST_WIDE_INT) 0x80000000); 7035 7036 gcc_assert (hi + lo == offset); 7037 7038 if (hi != 0) 7039 { 7040 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 7041 7042 /* Be careful not to destroy OUTVAL. */ 7043 if (reg_overlap_mentioned_p (base_plus, outval)) 7044 { 7045 /* Updating base_plus might destroy outval, see if we 7046 can swap the scratch and base_plus. */ 7047 if (!reg_overlap_mentioned_p (scratch, outval)) 7048 { 7049 rtx tmp = scratch; 7050 scratch = base_plus; 7051 base_plus = tmp; 7052 } 7053 else 7054 { 7055 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); 7056 7057 /* Be conservative and copy outval into scratch now, 7058 this should only be necessary if outval is a 7059 subreg of something larger than a word. */ 7060 /* XXX Might this clobber base? I can't see how it 7061 can, since scratch is known to overlap with 7062 outval. */ 7063 emit_insn (gen_movhi (scratch_hi, outval)); 7064 outval = scratch_hi; 7065 } 7066 } 7067 7068 /* Get the base address; addsi3 knows how to handle constants 7069 that require more than one insn. */ 7070 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); 7071 base = base_plus; 7072 offset = lo; 7073 } 7074 } 7075 7076 if (BYTES_BIG_ENDIAN) 7077 { 7078 emit_insn (gen_movqi (gen_rtx_MEM (QImode, 7079 plus_constant (base, offset + 1)), 7080 gen_lowpart (QImode, outval))); 7081 emit_insn (gen_lshrsi3 (scratch, 7082 gen_rtx_SUBREG (SImode, outval, 0), 7083 GEN_INT (8))); 7084 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), 7085 gen_lowpart (QImode, scratch))); 7086 } 7087 else 7088 { 7089 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), 7090 gen_lowpart (QImode, outval))); 7091 emit_insn (gen_lshrsi3 (scratch, 7092 gen_rtx_SUBREG (SImode, outval, 0), 7093 GEN_INT (8))); 7094 emit_insn (gen_movqi (gen_rtx_MEM (QImode, 7095 plus_constant (base, offset + 1)), 7096 gen_lowpart (QImode, scratch))); 7097 } 7098} 7099 7100/* Return true if a type must be passed in memory. For AAPCS, small aggregates 7101 (padded to the size of a word) should be passed in a register. */ 7102 7103static bool 7104arm_must_pass_in_stack (enum machine_mode mode, tree type) 7105{ 7106 if (TARGET_AAPCS_BASED) 7107 return must_pass_in_stack_var_size (mode, type); 7108 else 7109 return must_pass_in_stack_var_size_or_pad (mode, type); 7110} 7111 7112 7113/* For use by FUNCTION_ARG_PADDING (MODE, TYPE). 7114 Return true if an argument passed on the stack should be padded upwards, 7115 i.e. if the least-significant byte has useful data. 7116 For legacy APCS ABIs we use the default. For AAPCS based ABIs small 7117 aggregate types are placed in the lowest memory address. */ 7118 7119bool 7120arm_pad_arg_upward (enum machine_mode mode, tree type) 7121{ 7122 if (!TARGET_AAPCS_BASED) 7123 return DEFAULT_FUNCTION_ARG_PADDING(mode, type) == upward; 7124 7125 if (type && BYTES_BIG_ENDIAN && INTEGRAL_TYPE_P (type)) 7126 return false; 7127 7128 return true; 7129} 7130 7131 7132/* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST). 7133 For non-AAPCS, return !BYTES_BIG_ENDIAN if the least significant 7134 byte of the register has useful data, and return the opposite if the 7135 most significant byte does. 7136 For AAPCS, small aggregates and small complex types are always padded 7137 upwards. */ 7138 7139bool 7140arm_pad_reg_upward (enum machine_mode mode ATTRIBUTE_UNUSED, 7141 tree type, int first ATTRIBUTE_UNUSED) 7142{ 7143 if (TARGET_AAPCS_BASED 7144 && BYTES_BIG_ENDIAN 7145 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == COMPLEX_TYPE) 7146 && int_size_in_bytes (type) <= 4) 7147 return true; 7148 7149 /* Otherwise, use default padding. */ 7150 return !BYTES_BIG_ENDIAN; 7151} 7152 7153 7154/* Print a symbolic form of X to the debug file, F. */ 7155static void 7156arm_print_value (FILE *f, rtx x) 7157{ 7158 switch (GET_CODE (x)) 7159 { 7160 case CONST_INT: 7161 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); 7162 return; 7163 7164 case CONST_DOUBLE: 7165 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); 7166 return; 7167 7168 case CONST_VECTOR: 7169 { 7170 int i; 7171 7172 fprintf (f, "<"); 7173 for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) 7174 { 7175 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i))); 7176 if (i < (CONST_VECTOR_NUNITS (x) - 1)) 7177 fputc (',', f); 7178 } 7179 fprintf (f, ">"); 7180 } 7181 return; 7182 7183 case CONST_STRING: 7184 fprintf (f, "\"%s\"", XSTR (x, 0)); 7185 return; 7186 7187 case SYMBOL_REF: 7188 fprintf (f, "`%s'", XSTR (x, 0)); 7189 return; 7190 7191 case LABEL_REF: 7192 fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); 7193 return; 7194 7195 case CONST: 7196 arm_print_value (f, XEXP (x, 0)); 7197 return; 7198 7199 case PLUS: 7200 arm_print_value (f, XEXP (x, 0)); 7201 fprintf (f, "+"); 7202 arm_print_value (f, XEXP (x, 1)); 7203 return; 7204 7205 case PC: 7206 fprintf (f, "pc"); 7207 return; 7208 7209 default: 7210 fprintf (f, "????"); 7211 return; 7212 } 7213} 7214 7215/* Routines for manipulation of the constant pool. */ 7216 7217/* Arm instructions cannot load a large constant directly into a 7218 register; they have to come from a pc relative load. The constant 7219 must therefore be placed in the addressable range of the pc 7220 relative load. Depending on the precise pc relative load 7221 instruction the range is somewhere between 256 bytes and 4k. This 7222 means that we often have to dump a constant inside a function, and 7223 generate code to branch around it. 7224 7225 It is important to minimize this, since the branches will slow 7226 things down and make the code larger. 7227 7228 Normally we can hide the table after an existing unconditional 7229 branch so that there is no interruption of the flow, but in the 7230 worst case the code looks like this: 7231 7232 ldr rn, L1 7233 ... 7234 b L2 7235 align 7236 L1: .long value 7237 L2: 7238 ... 7239 7240 ldr rn, L3 7241 ... 7242 b L4 7243 align 7244 L3: .long value 7245 L4: 7246 ... 7247 7248 We fix this by performing a scan after scheduling, which notices 7249 which instructions need to have their operands fetched from the 7250 constant table and builds the table. 7251 7252 The algorithm starts by building a table of all the constants that 7253 need fixing up and all the natural barriers in the function (places 7254 where a constant table can be dropped without breaking the flow). 7255 For each fixup we note how far the pc-relative replacement will be 7256 able to reach and the offset of the instruction into the function. 7257 7258 Having built the table we then group the fixes together to form 7259 tables that are as large as possible (subject to addressing 7260 constraints) and emit each table of constants after the last 7261 barrier that is within range of all the instructions in the group. 7262 If a group does not contain a barrier, then we forcibly create one 7263 by inserting a jump instruction into the flow. Once the table has 7264 been inserted, the insns are then modified to reference the 7265 relevant entry in the pool. 7266 7267 Possible enhancements to the algorithm (not implemented) are: 7268 7269 1) For some processors and object formats, there may be benefit in 7270 aligning the pools to the start of cache lines; this alignment 7271 would need to be taken into account when calculating addressability 7272 of a pool. */ 7273 7274/* These typedefs are located at the start of this file, so that 7275 they can be used in the prototypes there. This comment is to 7276 remind readers of that fact so that the following structures 7277 can be understood more easily. 7278 7279 typedef struct minipool_node Mnode; 7280 typedef struct minipool_fixup Mfix; */ 7281 7282struct minipool_node 7283{ 7284 /* Doubly linked chain of entries. */ 7285 Mnode * next; 7286 Mnode * prev; 7287 /* The maximum offset into the code that this entry can be placed. While 7288 pushing fixes for forward references, all entries are sorted in order 7289 of increasing max_address. */ 7290 HOST_WIDE_INT max_address; 7291 /* Similarly for an entry inserted for a backwards ref. */ 7292 HOST_WIDE_INT min_address; 7293 /* The number of fixes referencing this entry. This can become zero 7294 if we "unpush" an entry. In this case we ignore the entry when we 7295 come to emit the code. */ 7296 int refcount; 7297 /* The offset from the start of the minipool. */ 7298 HOST_WIDE_INT offset; 7299 /* The value in table. */ 7300 rtx value; 7301 /* The mode of value. */ 7302 enum machine_mode mode; 7303 /* The size of the value. With iWMMXt enabled 7304 sizes > 4 also imply an alignment of 8-bytes. */ 7305 int fix_size; 7306}; 7307 7308struct minipool_fixup 7309{ 7310 Mfix * next; 7311 rtx insn; 7312 HOST_WIDE_INT address; 7313 rtx * loc; 7314 enum machine_mode mode; 7315 int fix_size; 7316 rtx value; 7317 Mnode * minipool; 7318 HOST_WIDE_INT forwards; 7319 HOST_WIDE_INT backwards; 7320}; 7321 7322/* Fixes less than a word need padding out to a word boundary. */ 7323#define MINIPOOL_FIX_SIZE(mode) \ 7324 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) 7325 7326static Mnode * minipool_vector_head; 7327static Mnode * minipool_vector_tail; 7328static rtx minipool_vector_label; 7329static int minipool_pad; 7330 7331/* The linked list of all minipool fixes required for this function. */ 7332Mfix * minipool_fix_head; 7333Mfix * minipool_fix_tail; 7334/* The fix entry for the current minipool, once it has been placed. */ 7335Mfix * minipool_barrier; 7336 7337/* Determines if INSN is the start of a jump table. Returns the end 7338 of the TABLE or NULL_RTX. */ 7339static rtx 7340is_jump_table (rtx insn) 7341{ 7342 rtx table; 7343 7344 if (GET_CODE (insn) == JUMP_INSN 7345 && JUMP_LABEL (insn) != NULL 7346 && ((table = next_real_insn (JUMP_LABEL (insn))) 7347 == next_real_insn (insn)) 7348 && table != NULL 7349 && GET_CODE (table) == JUMP_INSN 7350 && (GET_CODE (PATTERN (table)) == ADDR_VEC 7351 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) 7352 return table; 7353 7354 return NULL_RTX; 7355} 7356 7357#ifndef JUMP_TABLES_IN_TEXT_SECTION 7358#define JUMP_TABLES_IN_TEXT_SECTION 0 7359#endif 7360 7361static HOST_WIDE_INT 7362get_jump_table_size (rtx insn) 7363{ 7364 /* ADDR_VECs only take room if read-only data does into the text 7365 section. */ 7366 if (JUMP_TABLES_IN_TEXT_SECTION || readonly_data_section == text_section) 7367 { 7368 rtx body = PATTERN (insn); 7369 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; 7370 7371 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt); 7372 } 7373 7374 return 0; 7375} 7376 7377/* Move a minipool fix MP from its current location to before MAX_MP. 7378 If MAX_MP is NULL, then MP doesn't need moving, but the addressing 7379 constraints may need updating. */ 7380static Mnode * 7381move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, 7382 HOST_WIDE_INT max_address) 7383{ 7384 /* The code below assumes these are different. */ 7385 gcc_assert (mp != max_mp); 7386 7387 if (max_mp == NULL) 7388 { 7389 if (max_address < mp->max_address) 7390 mp->max_address = max_address; 7391 } 7392 else 7393 { 7394 if (max_address > max_mp->max_address - mp->fix_size) 7395 mp->max_address = max_mp->max_address - mp->fix_size; 7396 else 7397 mp->max_address = max_address; 7398 7399 /* Unlink MP from its current position. Since max_mp is non-null, 7400 mp->prev must be non-null. */ 7401 mp->prev->next = mp->next; 7402 if (mp->next != NULL) 7403 mp->next->prev = mp->prev; 7404 else 7405 minipool_vector_tail = mp->prev; 7406 7407 /* Re-insert it before MAX_MP. */ 7408 mp->next = max_mp; 7409 mp->prev = max_mp->prev; 7410 max_mp->prev = mp; 7411 7412 if (mp->prev != NULL) 7413 mp->prev->next = mp; 7414 else 7415 minipool_vector_head = mp; 7416 } 7417 7418 /* Save the new entry. */ 7419 max_mp = mp; 7420 7421 /* Scan over the preceding entries and adjust their addresses as 7422 required. */ 7423 while (mp->prev != NULL 7424 && mp->prev->max_address > mp->max_address - mp->prev->fix_size) 7425 { 7426 mp->prev->max_address = mp->max_address - mp->prev->fix_size; 7427 mp = mp->prev; 7428 } 7429 7430 return max_mp; 7431} 7432 7433/* Add a constant to the minipool for a forward reference. Returns the 7434 node added or NULL if the constant will not fit in this pool. */ 7435static Mnode * 7436add_minipool_forward_ref (Mfix *fix) 7437{ 7438 /* If set, max_mp is the first pool_entry that has a lower 7439 constraint than the one we are trying to add. */ 7440 Mnode * max_mp = NULL; 7441 HOST_WIDE_INT max_address = fix->address + fix->forwards - minipool_pad; 7442 Mnode * mp; 7443 7444 /* If the minipool starts before the end of FIX->INSN then this FIX 7445 can not be placed into the current pool. Furthermore, adding the 7446 new constant pool entry may cause the pool to start FIX_SIZE bytes 7447 earlier. */ 7448 if (minipool_vector_head && 7449 (fix->address + get_attr_length (fix->insn) 7450 >= minipool_vector_head->max_address - fix->fix_size)) 7451 return NULL; 7452 7453 /* Scan the pool to see if a constant with the same value has 7454 already been added. While we are doing this, also note the 7455 location where we must insert the constant if it doesn't already 7456 exist. */ 7457 for (mp = minipool_vector_head; mp != NULL; mp = mp->next) 7458 { 7459 if (GET_CODE (fix->value) == GET_CODE (mp->value) 7460 && fix->mode == mp->mode 7461 && (GET_CODE (fix->value) != CODE_LABEL 7462 || (CODE_LABEL_NUMBER (fix->value) 7463 == CODE_LABEL_NUMBER (mp->value))) 7464 && rtx_equal_p (fix->value, mp->value)) 7465 { 7466 /* More than one fix references this entry. */ 7467 mp->refcount++; 7468 return move_minipool_fix_forward_ref (mp, max_mp, max_address); 7469 } 7470 7471 /* Note the insertion point if necessary. */ 7472 if (max_mp == NULL 7473 && mp->max_address > max_address) 7474 max_mp = mp; 7475 7476 /* If we are inserting an 8-bytes aligned quantity and 7477 we have not already found an insertion point, then 7478 make sure that all such 8-byte aligned quantities are 7479 placed at the start of the pool. */ 7480 if (ARM_DOUBLEWORD_ALIGN 7481 && max_mp == NULL 7482 && fix->fix_size == 8 7483 && mp->fix_size != 8) 7484 { 7485 max_mp = mp; 7486 max_address = mp->max_address; 7487 } 7488 } 7489 7490 /* The value is not currently in the minipool, so we need to create 7491 a new entry for it. If MAX_MP is NULL, the entry will be put on 7492 the end of the list since the placement is less constrained than 7493 any existing entry. Otherwise, we insert the new fix before 7494 MAX_MP and, if necessary, adjust the constraints on the other 7495 entries. */ 7496 mp = XNEW (Mnode); 7497 mp->fix_size = fix->fix_size; 7498 mp->mode = fix->mode; 7499 mp->value = fix->value; 7500 mp->refcount = 1; 7501 /* Not yet required for a backwards ref. */ 7502 mp->min_address = -65536; 7503 7504 if (max_mp == NULL) 7505 { 7506 mp->max_address = max_address; 7507 mp->next = NULL; 7508 mp->prev = minipool_vector_tail; 7509 7510 if (mp->prev == NULL) 7511 { 7512 minipool_vector_head = mp; 7513 minipool_vector_label = gen_label_rtx (); 7514 } 7515 else 7516 mp->prev->next = mp; 7517 7518 minipool_vector_tail = mp; 7519 } 7520 else 7521 { 7522 if (max_address > max_mp->max_address - mp->fix_size) 7523 mp->max_address = max_mp->max_address - mp->fix_size; 7524 else 7525 mp->max_address = max_address; 7526 7527 mp->next = max_mp; 7528 mp->prev = max_mp->prev; 7529 max_mp->prev = mp; 7530 if (mp->prev != NULL) 7531 mp->prev->next = mp; 7532 else 7533 minipool_vector_head = mp; 7534 } 7535 7536 /* Save the new entry. */ 7537 max_mp = mp; 7538 7539 /* Scan over the preceding entries and adjust their addresses as 7540 required. */ 7541 while (mp->prev != NULL 7542 && mp->prev->max_address > mp->max_address - mp->prev->fix_size) 7543 { 7544 mp->prev->max_address = mp->max_address - mp->prev->fix_size; 7545 mp = mp->prev; 7546 } 7547 7548 return max_mp; 7549} 7550 7551static Mnode * 7552move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, 7553 HOST_WIDE_INT min_address) 7554{ 7555 HOST_WIDE_INT offset; 7556 7557 /* The code below assumes these are different. */ 7558 gcc_assert (mp != min_mp); 7559 7560 if (min_mp == NULL) 7561 { 7562 if (min_address > mp->min_address) 7563 mp->min_address = min_address; 7564 } 7565 else 7566 { 7567 /* We will adjust this below if it is too loose. */ 7568 mp->min_address = min_address; 7569 7570 /* Unlink MP from its current position. Since min_mp is non-null, 7571 mp->next must be non-null. */ 7572 mp->next->prev = mp->prev; 7573 if (mp->prev != NULL) 7574 mp->prev->next = mp->next; 7575 else 7576 minipool_vector_head = mp->next; 7577 7578 /* Reinsert it after MIN_MP. */ 7579 mp->prev = min_mp; 7580 mp->next = min_mp->next; 7581 min_mp->next = mp; 7582 if (mp->next != NULL) 7583 mp->next->prev = mp; 7584 else 7585 minipool_vector_tail = mp; 7586 } 7587 7588 min_mp = mp; 7589 7590 offset = 0; 7591 for (mp = minipool_vector_head; mp != NULL; mp = mp->next) 7592 { 7593 mp->offset = offset; 7594 if (mp->refcount > 0) 7595 offset += mp->fix_size; 7596 7597 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) 7598 mp->next->min_address = mp->min_address + mp->fix_size; 7599 } 7600 7601 return min_mp; 7602} 7603 7604/* Add a constant to the minipool for a backward reference. Returns the 7605 node added or NULL if the constant will not fit in this pool. 7606 7607 Note that the code for insertion for a backwards reference can be 7608 somewhat confusing because the calculated offsets for each fix do 7609 not take into account the size of the pool (which is still under 7610 construction. */ 7611static Mnode * 7612add_minipool_backward_ref (Mfix *fix) 7613{ 7614 /* If set, min_mp is the last pool_entry that has a lower constraint 7615 than the one we are trying to add. */ 7616 Mnode *min_mp = NULL; 7617 /* This can be negative, since it is only a constraint. */ 7618 HOST_WIDE_INT min_address = fix->address - fix->backwards; 7619 Mnode *mp; 7620 7621 /* If we can't reach the current pool from this insn, or if we can't 7622 insert this entry at the end of the pool without pushing other 7623 fixes out of range, then we don't try. This ensures that we 7624 can't fail later on. */ 7625 if (min_address >= minipool_barrier->address 7626 || (minipool_vector_tail->min_address + fix->fix_size 7627 >= minipool_barrier->address)) 7628 return NULL; 7629 7630 /* Scan the pool to see if a constant with the same value has 7631 already been added. While we are doing this, also note the 7632 location where we must insert the constant if it doesn't already 7633 exist. */ 7634 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) 7635 { 7636 if (GET_CODE (fix->value) == GET_CODE (mp->value) 7637 && fix->mode == mp->mode 7638 && (GET_CODE (fix->value) != CODE_LABEL 7639 || (CODE_LABEL_NUMBER (fix->value) 7640 == CODE_LABEL_NUMBER (mp->value))) 7641 && rtx_equal_p (fix->value, mp->value) 7642 /* Check that there is enough slack to move this entry to the 7643 end of the table (this is conservative). */ 7644 && (mp->max_address 7645 > (minipool_barrier->address 7646 + minipool_vector_tail->offset 7647 + minipool_vector_tail->fix_size))) 7648 { 7649 mp->refcount++; 7650 return move_minipool_fix_backward_ref (mp, min_mp, min_address); 7651 } 7652 7653 if (min_mp != NULL) 7654 mp->min_address += fix->fix_size; 7655 else 7656 { 7657 /* Note the insertion point if necessary. */ 7658 if (mp->min_address < min_address) 7659 { 7660 /* For now, we do not allow the insertion of 8-byte alignment 7661 requiring nodes anywhere but at the start of the pool. */ 7662 if (ARM_DOUBLEWORD_ALIGN 7663 && fix->fix_size == 8 && mp->fix_size != 8) 7664 return NULL; 7665 else 7666 min_mp = mp; 7667 } 7668 else if (mp->max_address 7669 < minipool_barrier->address + mp->offset + fix->fix_size) 7670 { 7671 /* Inserting before this entry would push the fix beyond 7672 its maximum address (which can happen if we have 7673 re-located a forwards fix); force the new fix to come 7674 after it. */ 7675 min_mp = mp; 7676 min_address = mp->min_address + fix->fix_size; 7677 } 7678 /* If we are inserting an 8-bytes aligned quantity and 7679 we have not already found an insertion point, then 7680 make sure that all such 8-byte aligned quantities are 7681 placed at the start of the pool. */ 7682 else if (ARM_DOUBLEWORD_ALIGN 7683 && min_mp == NULL 7684 && fix->fix_size == 8 7685 && mp->fix_size < 8) 7686 { 7687 min_mp = mp; 7688 min_address = mp->min_address + fix->fix_size; 7689 } 7690 } 7691 } 7692 7693 /* We need to create a new entry. */ 7694 mp = XNEW (Mnode); 7695 mp->fix_size = fix->fix_size; 7696 mp->mode = fix->mode; 7697 mp->value = fix->value; 7698 mp->refcount = 1; 7699 mp->max_address = minipool_barrier->address + 65536; 7700 7701 mp->min_address = min_address; 7702 7703 if (min_mp == NULL) 7704 { 7705 mp->prev = NULL; 7706 mp->next = minipool_vector_head; 7707 7708 if (mp->next == NULL) 7709 { 7710 minipool_vector_tail = mp; 7711 minipool_vector_label = gen_label_rtx (); 7712 } 7713 else 7714 mp->next->prev = mp; 7715 7716 minipool_vector_head = mp; 7717 } 7718 else 7719 { 7720 mp->next = min_mp->next; 7721 mp->prev = min_mp; 7722 min_mp->next = mp; 7723 7724 if (mp->next != NULL) 7725 mp->next->prev = mp; 7726 else 7727 minipool_vector_tail = mp; 7728 } 7729 7730 /* Save the new entry. */ 7731 min_mp = mp; 7732 7733 if (mp->prev) 7734 mp = mp->prev; 7735 else 7736 mp->offset = 0; 7737 7738 /* Scan over the following entries and adjust their offsets. */ 7739 while (mp->next != NULL) 7740 { 7741 if (mp->next->min_address < mp->min_address + mp->fix_size) 7742 mp->next->min_address = mp->min_address + mp->fix_size; 7743 7744 if (mp->refcount) 7745 mp->next->offset = mp->offset + mp->fix_size; 7746 else 7747 mp->next->offset = mp->offset; 7748 7749 mp = mp->next; 7750 } 7751 7752 return min_mp; 7753} 7754 7755static void 7756assign_minipool_offsets (Mfix *barrier) 7757{ 7758 HOST_WIDE_INT offset = 0; 7759 Mnode *mp; 7760 7761 minipool_barrier = barrier; 7762 7763 for (mp = minipool_vector_head; mp != NULL; mp = mp->next) 7764 { 7765 mp->offset = offset; 7766 7767 if (mp->refcount > 0) 7768 offset += mp->fix_size; 7769 } 7770} 7771 7772/* Output the literal table */ 7773static void 7774dump_minipool (rtx scan) 7775{ 7776 Mnode * mp; 7777 Mnode * nmp; 7778 int align64 = 0; 7779 7780 if (ARM_DOUBLEWORD_ALIGN) 7781 for (mp = minipool_vector_head; mp != NULL; mp = mp->next) 7782 if (mp->refcount > 0 && mp->fix_size == 8) 7783 { 7784 align64 = 1; 7785 break; 7786 } 7787 7788 if (dump_file) 7789 fprintf (dump_file, 7790 ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", 7791 INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); 7792 7793 scan = emit_label_after (gen_label_rtx (), scan); 7794 scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); 7795 scan = emit_label_after (minipool_vector_label, scan); 7796 7797 for (mp = minipool_vector_head; mp != NULL; mp = nmp) 7798 { 7799 if (mp->refcount > 0) 7800 { 7801 if (dump_file) 7802 { 7803 fprintf (dump_file, 7804 ";; Offset %u, min %ld, max %ld ", 7805 (unsigned) mp->offset, (unsigned long) mp->min_address, 7806 (unsigned long) mp->max_address); 7807 arm_print_value (dump_file, mp->value); 7808 fputc ('\n', dump_file); 7809 } 7810 7811 switch (mp->fix_size) 7812 { 7813#ifdef HAVE_consttable_1 7814 case 1: 7815 scan = emit_insn_after (gen_consttable_1 (mp->value), scan); 7816 break; 7817 7818#endif 7819#ifdef HAVE_consttable_2 7820 case 2: 7821 scan = emit_insn_after (gen_consttable_2 (mp->value), scan); 7822 break; 7823 7824#endif 7825#ifdef HAVE_consttable_4 7826 case 4: 7827 scan = emit_insn_after (gen_consttable_4 (mp->value), scan); 7828 break; 7829 7830#endif 7831#ifdef HAVE_consttable_8 7832 case 8: 7833 scan = emit_insn_after (gen_consttable_8 (mp->value), scan); 7834 break; 7835 7836#endif 7837 default: 7838 gcc_unreachable (); 7839 } 7840 } 7841 7842 nmp = mp->next; 7843 free (mp); 7844 } 7845 7846 minipool_vector_head = minipool_vector_tail = NULL; 7847 scan = emit_insn_after (gen_consttable_end (), scan); 7848 scan = emit_barrier_after (scan); 7849} 7850 7851/* Return the cost of forcibly inserting a barrier after INSN. */ 7852static int 7853arm_barrier_cost (rtx insn) 7854{ 7855 /* Basing the location of the pool on the loop depth is preferable, 7856 but at the moment, the basic block information seems to be 7857 corrupt by this stage of the compilation. */ 7858 int base_cost = 50; 7859 rtx next = next_nonnote_insn (insn); 7860 7861 if (next != NULL && GET_CODE (next) == CODE_LABEL) 7862 base_cost -= 20; 7863 7864 switch (GET_CODE (insn)) 7865 { 7866 case CODE_LABEL: 7867 /* It will always be better to place the table before the label, rather 7868 than after it. */ 7869 return 50; 7870 7871 case INSN: 7872 case CALL_INSN: 7873 return base_cost; 7874 7875 case JUMP_INSN: 7876 return base_cost - 10; 7877 7878 default: 7879 return base_cost + 10; 7880 } 7881} 7882 7883/* Find the best place in the insn stream in the range 7884 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. 7885 Create the barrier by inserting a jump and add a new fix entry for 7886 it. */ 7887static Mfix * 7888create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) 7889{ 7890 HOST_WIDE_INT count = 0; 7891 rtx barrier; 7892 rtx from = fix->insn; 7893 /* The instruction after which we will insert the jump. */ 7894 rtx selected = NULL; 7895 int selected_cost; 7896 /* The address at which the jump instruction will be placed. */ 7897 HOST_WIDE_INT selected_address; 7898 Mfix * new_fix; 7899 HOST_WIDE_INT max_count = max_address - fix->address; 7900 rtx label = gen_label_rtx (); 7901 7902 selected_cost = arm_barrier_cost (from); 7903 selected_address = fix->address; 7904 7905 while (from && count < max_count) 7906 { 7907 rtx tmp; 7908 int new_cost; 7909 7910 /* This code shouldn't have been called if there was a natural barrier 7911 within range. */ 7912 gcc_assert (GET_CODE (from) != BARRIER); 7913 7914 /* Count the length of this insn. */ 7915 count += get_attr_length (from); 7916 7917 /* If there is a jump table, add its length. */ 7918 tmp = is_jump_table (from); 7919 if (tmp != NULL) 7920 { 7921 count += get_jump_table_size (tmp); 7922 7923 /* Jump tables aren't in a basic block, so base the cost on 7924 the dispatch insn. If we select this location, we will 7925 still put the pool after the table. */ 7926 new_cost = arm_barrier_cost (from); 7927 7928 if (count < max_count 7929 && (!selected || new_cost <= selected_cost)) 7930 { 7931 selected = tmp; 7932 selected_cost = new_cost; 7933 selected_address = fix->address + count; 7934 } 7935 7936 /* Continue after the dispatch table. */ 7937 from = NEXT_INSN (tmp); 7938 continue; 7939 } 7940 7941 new_cost = arm_barrier_cost (from); 7942 7943 if (count < max_count 7944 && (!selected || new_cost <= selected_cost)) 7945 { 7946 selected = from; 7947 selected_cost = new_cost; 7948 selected_address = fix->address + count; 7949 } 7950 7951 from = NEXT_INSN (from); 7952 } 7953 7954 /* Make sure that we found a place to insert the jump. */ 7955 gcc_assert (selected); 7956 7957 /* Create a new JUMP_INSN that branches around a barrier. */ 7958 from = emit_jump_insn_after (gen_jump (label), selected); 7959 JUMP_LABEL (from) = label; 7960 barrier = emit_barrier_after (from); 7961 emit_label_after (label, barrier); 7962 7963 /* Create a minipool barrier entry for the new barrier. */ 7964 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); 7965 new_fix->insn = barrier; 7966 new_fix->address = selected_address; 7967 new_fix->next = fix->next; 7968 fix->next = new_fix; 7969 7970 return new_fix; 7971} 7972 7973/* Record that there is a natural barrier in the insn stream at 7974 ADDRESS. */ 7975static void 7976push_minipool_barrier (rtx insn, HOST_WIDE_INT address) 7977{ 7978 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); 7979 7980 fix->insn = insn; 7981 fix->address = address; 7982 7983 fix->next = NULL; 7984 if (minipool_fix_head != NULL) 7985 minipool_fix_tail->next = fix; 7986 else 7987 minipool_fix_head = fix; 7988 7989 minipool_fix_tail = fix; 7990} 7991 7992/* Record INSN, which will need fixing up to load a value from the 7993 minipool. ADDRESS is the offset of the insn since the start of the 7994 function; LOC is a pointer to the part of the insn which requires 7995 fixing; VALUE is the constant that must be loaded, which is of type 7996 MODE. */ 7997static void 7998push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, 7999 enum machine_mode mode, rtx value) 8000{ 8001 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); 8002 8003#ifdef AOF_ASSEMBLER 8004 /* PIC symbol references need to be converted into offsets into the 8005 based area. */ 8006 /* XXX This shouldn't be done here. */ 8007 if (flag_pic && GET_CODE (value) == SYMBOL_REF) 8008 value = aof_pic_entry (value); 8009#endif /* AOF_ASSEMBLER */ 8010 8011 fix->insn = insn; 8012 fix->address = address; 8013 fix->loc = loc; 8014 fix->mode = mode; 8015 fix->fix_size = MINIPOOL_FIX_SIZE (mode); 8016 fix->value = value; 8017 fix->forwards = get_attr_pool_range (insn); 8018 fix->backwards = get_attr_neg_pool_range (insn); 8019 fix->minipool = NULL; 8020 8021 /* If an insn doesn't have a range defined for it, then it isn't 8022 expecting to be reworked by this code. Better to stop now than 8023 to generate duff assembly code. */ 8024 gcc_assert (fix->forwards || fix->backwards); 8025 8026 /* If an entry requires 8-byte alignment then assume all constant pools 8027 require 4 bytes of padding. Trying to do this later on a per-pool 8028 basis is awkward because existing pool entries have to be modified. */ 8029 if (ARM_DOUBLEWORD_ALIGN && fix->fix_size == 8) 8030 minipool_pad = 4; 8031 8032 if (dump_file) 8033 { 8034 fprintf (dump_file, 8035 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", 8036 GET_MODE_NAME (mode), 8037 INSN_UID (insn), (unsigned long) address, 8038 -1 * (long)fix->backwards, (long)fix->forwards); 8039 arm_print_value (dump_file, fix->value); 8040 fprintf (dump_file, "\n"); 8041 } 8042 8043 /* Add it to the chain of fixes. */ 8044 fix->next = NULL; 8045 8046 if (minipool_fix_head != NULL) 8047 minipool_fix_tail->next = fix; 8048 else 8049 minipool_fix_head = fix; 8050 8051 minipool_fix_tail = fix; 8052} 8053 8054/* Return the cost of synthesizing a 64-bit constant VAL inline. 8055 Returns the number of insns needed, or 99 if we don't know how to 8056 do it. */ 8057int 8058arm_const_double_inline_cost (rtx val) 8059{ 8060 rtx lowpart, highpart; 8061 enum machine_mode mode; 8062 8063 mode = GET_MODE (val); 8064 8065 if (mode == VOIDmode) 8066 mode = DImode; 8067 8068 gcc_assert (GET_MODE_SIZE (mode) == 8); 8069 8070 lowpart = gen_lowpart (SImode, val); 8071 highpart = gen_highpart_mode (SImode, mode, val); 8072 8073 gcc_assert (GET_CODE (lowpart) == CONST_INT); 8074 gcc_assert (GET_CODE (highpart) == CONST_INT); 8075 8076 return (arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (lowpart), 8077 NULL_RTX, NULL_RTX, 0, 0) 8078 + arm_gen_constant (SET, SImode, NULL_RTX, INTVAL (highpart), 8079 NULL_RTX, NULL_RTX, 0, 0)); 8080} 8081 8082/* Return true if it is worthwhile to split a 64-bit constant into two 8083 32-bit operations. This is the case if optimizing for size, or 8084 if we have load delay slots, or if one 32-bit part can be done with 8085 a single data operation. */ 8086bool 8087arm_const_double_by_parts (rtx val) 8088{ 8089 enum machine_mode mode = GET_MODE (val); 8090 rtx part; 8091 8092 if (optimize_size || arm_ld_sched) 8093 return true; 8094 8095 if (mode == VOIDmode) 8096 mode = DImode; 8097 8098 part = gen_highpart_mode (SImode, mode, val); 8099 8100 gcc_assert (GET_CODE (part) == CONST_INT); 8101 8102 if (const_ok_for_arm (INTVAL (part)) 8103 || const_ok_for_arm (~INTVAL (part))) 8104 return true; 8105 8106 part = gen_lowpart (SImode, val); 8107 8108 gcc_assert (GET_CODE (part) == CONST_INT); 8109 8110 if (const_ok_for_arm (INTVAL (part)) 8111 || const_ok_for_arm (~INTVAL (part))) 8112 return true; 8113 8114 return false; 8115} 8116 8117/* Scan INSN and note any of its operands that need fixing. 8118 If DO_PUSHES is false we do not actually push any of the fixups 8119 needed. The function returns TRUE if any fixups were needed/pushed. 8120 This is used by arm_memory_load_p() which needs to know about loads 8121 of constants that will be converted into minipool loads. */ 8122static bool 8123note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) 8124{ 8125 bool result = false; 8126 int opno; 8127 8128 extract_insn (insn); 8129 8130 if (!constrain_operands (1)) 8131 fatal_insn_not_found (insn); 8132 8133 if (recog_data.n_alternatives == 0) 8134 return false; 8135 8136 /* Fill in recog_op_alt with information about the constraints of 8137 this insn. */ 8138 preprocess_constraints (); 8139 8140 for (opno = 0; opno < recog_data.n_operands; opno++) 8141 { 8142 /* Things we need to fix can only occur in inputs. */ 8143 if (recog_data.operand_type[opno] != OP_IN) 8144 continue; 8145 8146 /* If this alternative is a memory reference, then any mention 8147 of constants in this alternative is really to fool reload 8148 into allowing us to accept one there. We need to fix them up 8149 now so that we output the right code. */ 8150 if (recog_op_alt[opno][which_alternative].memory_ok) 8151 { 8152 rtx op = recog_data.operand[opno]; 8153 8154 if (CONSTANT_P (op)) 8155 { 8156 if (do_pushes) 8157 push_minipool_fix (insn, address, recog_data.operand_loc[opno], 8158 recog_data.operand_mode[opno], op); 8159 result = true; 8160 } 8161 else if (GET_CODE (op) == MEM 8162 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF 8163 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) 8164 { 8165 if (do_pushes) 8166 { 8167 rtx cop = avoid_constant_pool_reference (op); 8168 8169 /* Casting the address of something to a mode narrower 8170 than a word can cause avoid_constant_pool_reference() 8171 to return the pool reference itself. That's no good to 8172 us here. Lets just hope that we can use the 8173 constant pool value directly. */ 8174 if (op == cop) 8175 cop = get_pool_constant (XEXP (op, 0)); 8176 8177 push_minipool_fix (insn, address, 8178 recog_data.operand_loc[opno], 8179 recog_data.operand_mode[opno], cop); 8180 } 8181 8182 result = true; 8183 } 8184 } 8185 } 8186 8187 return result; 8188} 8189 8190/* Gcc puts the pool in the wrong place for ARM, since we can only 8191 load addresses a limited distance around the pc. We do some 8192 special munging to move the constant pool values to the correct 8193 point in the code. */ 8194static void 8195arm_reorg (void) 8196{ 8197 rtx insn; 8198 HOST_WIDE_INT address = 0; 8199 Mfix * fix; 8200 8201 minipool_fix_head = minipool_fix_tail = NULL; 8202 8203 /* The first insn must always be a note, or the code below won't 8204 scan it properly. */ 8205 insn = get_insns (); 8206 gcc_assert (GET_CODE (insn) == NOTE); 8207 minipool_pad = 0; 8208 8209 /* Scan all the insns and record the operands that will need fixing. */ 8210 for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) 8211 { 8212 if (TARGET_CIRRUS_FIX_INVALID_INSNS 8213 && (arm_cirrus_insn_p (insn) 8214 || GET_CODE (insn) == JUMP_INSN 8215 || arm_memory_load_p (insn))) 8216 cirrus_reorg (insn); 8217 8218 if (GET_CODE (insn) == BARRIER) 8219 push_minipool_barrier (insn, address); 8220 else if (INSN_P (insn)) 8221 { 8222 rtx table; 8223 8224 note_invalid_constants (insn, address, true); 8225 address += get_attr_length (insn); 8226 8227 /* If the insn is a vector jump, add the size of the table 8228 and skip the table. */ 8229 if ((table = is_jump_table (insn)) != NULL) 8230 { 8231 address += get_jump_table_size (table); 8232 insn = table; 8233 } 8234 } 8235 } 8236 8237 fix = minipool_fix_head; 8238 8239 /* Now scan the fixups and perform the required changes. */ 8240 while (fix) 8241 { 8242 Mfix * ftmp; 8243 Mfix * fdel; 8244 Mfix * last_added_fix; 8245 Mfix * last_barrier = NULL; 8246 Mfix * this_fix; 8247 8248 /* Skip any further barriers before the next fix. */ 8249 while (fix && GET_CODE (fix->insn) == BARRIER) 8250 fix = fix->next; 8251 8252 /* No more fixes. */ 8253 if (fix == NULL) 8254 break; 8255 8256 last_added_fix = NULL; 8257 8258 for (ftmp = fix; ftmp; ftmp = ftmp->next) 8259 { 8260 if (GET_CODE (ftmp->insn) == BARRIER) 8261 { 8262 if (ftmp->address >= minipool_vector_head->max_address) 8263 break; 8264 8265 last_barrier = ftmp; 8266 } 8267 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) 8268 break; 8269 8270 last_added_fix = ftmp; /* Keep track of the last fix added. */ 8271 } 8272 8273 /* If we found a barrier, drop back to that; any fixes that we 8274 could have reached but come after the barrier will now go in 8275 the next mini-pool. */ 8276 if (last_barrier != NULL) 8277 { 8278 /* Reduce the refcount for those fixes that won't go into this 8279 pool after all. */ 8280 for (fdel = last_barrier->next; 8281 fdel && fdel != ftmp; 8282 fdel = fdel->next) 8283 { 8284 fdel->minipool->refcount--; 8285 fdel->minipool = NULL; 8286 } 8287 8288 ftmp = last_barrier; 8289 } 8290 else 8291 { 8292 /* ftmp is first fix that we can't fit into this pool and 8293 there no natural barriers that we could use. Insert a 8294 new barrier in the code somewhere between the previous 8295 fix and this one, and arrange to jump around it. */ 8296 HOST_WIDE_INT max_address; 8297 8298 /* The last item on the list of fixes must be a barrier, so 8299 we can never run off the end of the list of fixes without 8300 last_barrier being set. */ 8301 gcc_assert (ftmp); 8302 8303 max_address = minipool_vector_head->max_address; 8304 /* Check that there isn't another fix that is in range that 8305 we couldn't fit into this pool because the pool was 8306 already too large: we need to put the pool before such an 8307 instruction. The pool itself may come just after the 8308 fix because create_fix_barrier also allows space for a 8309 jump instruction. */ 8310 if (ftmp->address < max_address) 8311 max_address = ftmp->address + 1; 8312 8313 last_barrier = create_fix_barrier (last_added_fix, max_address); 8314 } 8315 8316 assign_minipool_offsets (last_barrier); 8317 8318 while (ftmp) 8319 { 8320 if (GET_CODE (ftmp->insn) != BARRIER 8321 && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) 8322 == NULL)) 8323 break; 8324 8325 ftmp = ftmp->next; 8326 } 8327 8328 /* Scan over the fixes we have identified for this pool, fixing them 8329 up and adding the constants to the pool itself. */ 8330 for (this_fix = fix; this_fix && ftmp != this_fix; 8331 this_fix = this_fix->next) 8332 if (GET_CODE (this_fix->insn) != BARRIER) 8333 { 8334 rtx addr 8335 = plus_constant (gen_rtx_LABEL_REF (VOIDmode, 8336 minipool_vector_label), 8337 this_fix->minipool->offset); 8338 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); 8339 } 8340 8341 dump_minipool (last_barrier->insn); 8342 fix = ftmp; 8343 } 8344 8345 /* From now on we must synthesize any constants that we can't handle 8346 directly. This can happen if the RTL gets split during final 8347 instruction generation. */ 8348 after_arm_reorg = 1; 8349 8350 /* Free the minipool memory. */ 8351 obstack_free (&minipool_obstack, minipool_startobj); 8352} 8353 8354/* Routines to output assembly language. */ 8355 8356/* If the rtx is the correct value then return the string of the number. 8357 In this way we can ensure that valid double constants are generated even 8358 when cross compiling. */ 8359const char * 8360fp_immediate_constant (rtx x) 8361{ 8362 REAL_VALUE_TYPE r; 8363 int i; 8364 8365 if (!fp_consts_inited) 8366 init_fp_table (); 8367 8368 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 8369 for (i = 0; i < 8; i++) 8370 if (REAL_VALUES_EQUAL (r, values_fp[i])) 8371 return strings_fp[i]; 8372 8373 gcc_unreachable (); 8374} 8375 8376/* As for fp_immediate_constant, but value is passed directly, not in rtx. */ 8377static const char * 8378fp_const_from_val (REAL_VALUE_TYPE *r) 8379{ 8380 int i; 8381 8382 if (!fp_consts_inited) 8383 init_fp_table (); 8384 8385 for (i = 0; i < 8; i++) 8386 if (REAL_VALUES_EQUAL (*r, values_fp[i])) 8387 return strings_fp[i]; 8388 8389 gcc_unreachable (); 8390} 8391 8392/* Output the operands of a LDM/STM instruction to STREAM. 8393 MASK is the ARM register set mask of which only bits 0-15 are important. 8394 REG is the base register, either the frame pointer or the stack pointer, 8395 INSTR is the possibly suffixed load or store instruction. */ 8396 8397static void 8398print_multi_reg (FILE *stream, const char *instr, unsigned reg, 8399 unsigned long mask) 8400{ 8401 unsigned i; 8402 bool not_first = FALSE; 8403 8404 fputc ('\t', stream); 8405 asm_fprintf (stream, instr, reg); 8406 fputs (", {", stream); 8407 8408 for (i = 0; i <= LAST_ARM_REGNUM; i++) 8409 if (mask & (1 << i)) 8410 { 8411 if (not_first) 8412 fprintf (stream, ", "); 8413 8414 asm_fprintf (stream, "%r", i); 8415 not_first = TRUE; 8416 } 8417 8418 fprintf (stream, "}\n"); 8419} 8420 8421 8422/* Output a FLDMX instruction to STREAM. 8423 BASE if the register containing the address. 8424 REG and COUNT specify the register range. 8425 Extra registers may be added to avoid hardware bugs. */ 8426 8427static void 8428arm_output_fldmx (FILE * stream, unsigned int base, int reg, int count) 8429{ 8430 int i; 8431 8432 /* Workaround ARM10 VFPr1 bug. */ 8433 if (count == 2 && !arm_arch6) 8434 { 8435 if (reg == 15) 8436 reg--; 8437 count++; 8438 } 8439 8440 fputc ('\t', stream); 8441 asm_fprintf (stream, "fldmfdx\t%r!, {", base); 8442 8443 for (i = reg; i < reg + count; i++) 8444 { 8445 if (i > reg) 8446 fputs (", ", stream); 8447 asm_fprintf (stream, "d%d", i); 8448 } 8449 fputs ("}\n", stream); 8450 8451} 8452 8453 8454/* Output the assembly for a store multiple. */ 8455 8456const char * 8457vfp_output_fstmx (rtx * operands) 8458{ 8459 char pattern[100]; 8460 int p; 8461 int base; 8462 int i; 8463 8464 strcpy (pattern, "fstmfdx\t%m0!, {%P1"); 8465 p = strlen (pattern); 8466 8467 gcc_assert (GET_CODE (operands[1]) == REG); 8468 8469 base = (REGNO (operands[1]) - FIRST_VFP_REGNUM) / 2; 8470 for (i = 1; i < XVECLEN (operands[2], 0); i++) 8471 { 8472 p += sprintf (&pattern[p], ", d%d", base + i); 8473 } 8474 strcpy (&pattern[p], "}"); 8475 8476 output_asm_insn (pattern, operands); 8477 return ""; 8478} 8479 8480 8481/* Emit RTL to save block of VFP register pairs to the stack. Returns the 8482 number of bytes pushed. */ 8483 8484static int 8485vfp_emit_fstmx (int base_reg, int count) 8486{ 8487 rtx par; 8488 rtx dwarf; 8489 rtx tmp, reg; 8490 int i; 8491 8492 /* Workaround ARM10 VFPr1 bug. Data corruption can occur when exactly two 8493 register pairs are stored by a store multiple insn. We avoid this 8494 by pushing an extra pair. */ 8495 if (count == 2 && !arm_arch6) 8496 { 8497 if (base_reg == LAST_VFP_REGNUM - 3) 8498 base_reg -= 2; 8499 count++; 8500 } 8501 8502 /* ??? The frame layout is implementation defined. We describe 8503 standard format 1 (equivalent to a FSTMD insn and unused pad word). 8504 We really need some way of representing the whole block so that the 8505 unwinder can figure it out at runtime. */ 8506 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 8507 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); 8508 8509 reg = gen_rtx_REG (DFmode, base_reg); 8510 base_reg += 2; 8511 8512 XVECEXP (par, 0, 0) 8513 = gen_rtx_SET (VOIDmode, 8514 gen_frame_mem (BLKmode, 8515 gen_rtx_PRE_DEC (BLKmode, 8516 stack_pointer_rtx)), 8517 gen_rtx_UNSPEC (BLKmode, 8518 gen_rtvec (1, reg), 8519 UNSPEC_PUSH_MULT)); 8520 8521 tmp = gen_rtx_SET (VOIDmode, stack_pointer_rtx, 8522 plus_constant (stack_pointer_rtx, -(count * 8 + 4))); 8523 RTX_FRAME_RELATED_P (tmp) = 1; 8524 XVECEXP (dwarf, 0, 0) = tmp; 8525 8526 tmp = gen_rtx_SET (VOIDmode, 8527 gen_frame_mem (DFmode, stack_pointer_rtx), 8528 reg); 8529 RTX_FRAME_RELATED_P (tmp) = 1; 8530 XVECEXP (dwarf, 0, 1) = tmp; 8531 8532 for (i = 1; i < count; i++) 8533 { 8534 reg = gen_rtx_REG (DFmode, base_reg); 8535 base_reg += 2; 8536 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); 8537 8538 tmp = gen_rtx_SET (VOIDmode, 8539 gen_frame_mem (DFmode, 8540 plus_constant (stack_pointer_rtx, 8541 i * 8)), 8542 reg); 8543 RTX_FRAME_RELATED_P (tmp) = 1; 8544 XVECEXP (dwarf, 0, i + 1) = tmp; 8545 } 8546 8547 par = emit_insn (par); 8548 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, 8549 REG_NOTES (par)); 8550 RTX_FRAME_RELATED_P (par) = 1; 8551 8552 return count * 8 + 4; 8553} 8554 8555 8556/* Output a 'call' insn. */ 8557const char * 8558output_call (rtx *operands) 8559{ 8560 gcc_assert (!arm_arch5); /* Patterns should call blx <reg> directly. */ 8561 8562 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ 8563 if (REGNO (operands[0]) == LR_REGNUM) 8564 { 8565 operands[0] = gen_rtx_REG (SImode, IP_REGNUM); 8566 output_asm_insn ("mov%?\t%0, %|lr", operands); 8567 } 8568 8569 output_asm_insn ("mov%?\t%|lr, %|pc", operands); 8570 8571 if (TARGET_INTERWORK || arm_arch4t) 8572 output_asm_insn ("bx%?\t%0", operands); 8573 else 8574 output_asm_insn ("mov%?\t%|pc, %0", operands); 8575 8576 return ""; 8577} 8578 8579/* Output a 'call' insn that is a reference in memory. */ 8580const char * 8581output_call_mem (rtx *operands) 8582{ 8583 if (TARGET_INTERWORK && !arm_arch5) 8584 { 8585 output_asm_insn ("ldr%?\t%|ip, %0", operands); 8586 output_asm_insn ("mov%?\t%|lr, %|pc", operands); 8587 output_asm_insn ("bx%?\t%|ip", operands); 8588 } 8589 else if (regno_use_in (LR_REGNUM, operands[0])) 8590 { 8591 /* LR is used in the memory address. We load the address in the 8592 first instruction. It's safe to use IP as the target of the 8593 load since the call will kill it anyway. */ 8594 output_asm_insn ("ldr%?\t%|ip, %0", operands); 8595 if (arm_arch5) 8596 output_asm_insn ("blx%?\t%|ip", operands); 8597 else 8598 { 8599 output_asm_insn ("mov%?\t%|lr, %|pc", operands); 8600 if (arm_arch4t) 8601 output_asm_insn ("bx%?\t%|ip", operands); 8602 else 8603 output_asm_insn ("mov%?\t%|pc, %|ip", operands); 8604 } 8605 } 8606 else 8607 { 8608 output_asm_insn ("mov%?\t%|lr, %|pc", operands); 8609 output_asm_insn ("ldr%?\t%|pc, %0", operands); 8610 } 8611 8612 return ""; 8613} 8614 8615 8616/* Output a move from arm registers to an fpa registers. 8617 OPERANDS[0] is an fpa register. 8618 OPERANDS[1] is the first registers of an arm register pair. */ 8619const char * 8620output_mov_long_double_fpa_from_arm (rtx *operands) 8621{ 8622 int arm_reg0 = REGNO (operands[1]); 8623 rtx ops[3]; 8624 8625 gcc_assert (arm_reg0 != IP_REGNUM); 8626 8627 ops[0] = gen_rtx_REG (SImode, arm_reg0); 8628 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 8629 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); 8630 8631 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops); 8632 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); 8633 8634 return ""; 8635} 8636 8637/* Output a move from an fpa register to arm registers. 8638 OPERANDS[0] is the first registers of an arm register pair. 8639 OPERANDS[1] is an fpa register. */ 8640const char * 8641output_mov_long_double_arm_from_fpa (rtx *operands) 8642{ 8643 int arm_reg0 = REGNO (operands[0]); 8644 rtx ops[3]; 8645 8646 gcc_assert (arm_reg0 != IP_REGNUM); 8647 8648 ops[0] = gen_rtx_REG (SImode, arm_reg0); 8649 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 8650 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); 8651 8652 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); 8653 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops); 8654 return ""; 8655} 8656 8657/* Output a move from arm registers to arm registers of a long double 8658 OPERANDS[0] is the destination. 8659 OPERANDS[1] is the source. */ 8660const char * 8661output_mov_long_double_arm_from_arm (rtx *operands) 8662{ 8663 /* We have to be careful here because the two might overlap. */ 8664 int dest_start = REGNO (operands[0]); 8665 int src_start = REGNO (operands[1]); 8666 rtx ops[2]; 8667 int i; 8668 8669 if (dest_start < src_start) 8670 { 8671 for (i = 0; i < 3; i++) 8672 { 8673 ops[0] = gen_rtx_REG (SImode, dest_start + i); 8674 ops[1] = gen_rtx_REG (SImode, src_start + i); 8675 output_asm_insn ("mov%?\t%0, %1", ops); 8676 } 8677 } 8678 else 8679 { 8680 for (i = 2; i >= 0; i--) 8681 { 8682 ops[0] = gen_rtx_REG (SImode, dest_start + i); 8683 ops[1] = gen_rtx_REG (SImode, src_start + i); 8684 output_asm_insn ("mov%?\t%0, %1", ops); 8685 } 8686 } 8687 8688 return ""; 8689} 8690 8691 8692/* Output a move from arm registers to an fpa registers. 8693 OPERANDS[0] is an fpa register. 8694 OPERANDS[1] is the first registers of an arm register pair. */ 8695const char * 8696output_mov_double_fpa_from_arm (rtx *operands) 8697{ 8698 int arm_reg0 = REGNO (operands[1]); 8699 rtx ops[2]; 8700 8701 gcc_assert (arm_reg0 != IP_REGNUM); 8702 8703 ops[0] = gen_rtx_REG (SImode, arm_reg0); 8704 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 8705 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops); 8706 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); 8707 return ""; 8708} 8709 8710/* Output a move from an fpa register to arm registers. 8711 OPERANDS[0] is the first registers of an arm register pair. 8712 OPERANDS[1] is an fpa register. */ 8713const char * 8714output_mov_double_arm_from_fpa (rtx *operands) 8715{ 8716 int arm_reg0 = REGNO (operands[0]); 8717 rtx ops[2]; 8718 8719 gcc_assert (arm_reg0 != IP_REGNUM); 8720 8721 ops[0] = gen_rtx_REG (SImode, arm_reg0); 8722 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 8723 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); 8724 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops); 8725 return ""; 8726} 8727 8728/* Output a move between double words. 8729 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM 8730 or MEM<-REG and all MEMs must be offsettable addresses. */ 8731const char * 8732output_move_double (rtx *operands) 8733{ 8734 enum rtx_code code0 = GET_CODE (operands[0]); 8735 enum rtx_code code1 = GET_CODE (operands[1]); 8736 rtx otherops[3]; 8737 8738 if (code0 == REG) 8739 { 8740 int reg0 = REGNO (operands[0]); 8741 8742 otherops[0] = gen_rtx_REG (SImode, 1 + reg0); 8743 8744 gcc_assert (code1 == MEM); /* Constraints should ensure this. */ 8745 8746 switch (GET_CODE (XEXP (operands[1], 0))) 8747 { 8748 case REG: 8749 output_asm_insn ("ldm%?ia\t%m1, %M0", operands); 8750 break; 8751 8752 case PRE_INC: 8753 gcc_assert (TARGET_LDRD); 8754 output_asm_insn ("ldr%?d\t%0, [%m1, #8]!", operands); 8755 break; 8756 8757 case PRE_DEC: 8758 output_asm_insn ("ldm%?db\t%m1!, %M0", operands); 8759 break; 8760 8761 case POST_INC: 8762 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands); 8763 break; 8764 8765 case POST_DEC: 8766 gcc_assert (TARGET_LDRD); 8767 output_asm_insn ("ldr%?d\t%0, [%m1], #-8", operands); 8768 break; 8769 8770 case PRE_MODIFY: 8771 case POST_MODIFY: 8772 otherops[0] = operands[0]; 8773 otherops[1] = XEXP (XEXP (XEXP (operands[1], 0), 1), 0); 8774 otherops[2] = XEXP (XEXP (XEXP (operands[1], 0), 1), 1); 8775 8776 if (GET_CODE (XEXP (operands[1], 0)) == PRE_MODIFY) 8777 { 8778 if (reg_overlap_mentioned_p (otherops[0], otherops[2])) 8779 { 8780 /* Registers overlap so split out the increment. */ 8781 output_asm_insn ("add%?\t%1, %1, %2", otherops); 8782 output_asm_insn ("ldr%?d\t%0, [%1] @split", otherops); 8783 } 8784 else 8785 { 8786 /* IWMMXT allows offsets larger than ldrd can handle, 8787 fix these up with a pair of ldr. */ 8788 if (GET_CODE (otherops[2]) == CONST_INT 8789 && (INTVAL(otherops[2]) <= -256 8790 || INTVAL(otherops[2]) >= 256)) 8791 { 8792 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); 8793 otherops[0] = gen_rtx_REG (SImode, 1 + reg0); 8794 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); 8795 } 8796 else 8797 output_asm_insn ("ldr%?d\t%0, [%1, %2]!", otherops); 8798 } 8799 } 8800 else 8801 { 8802 /* IWMMXT allows offsets larger than ldrd can handle, 8803 fix these up with a pair of ldr. */ 8804 if (GET_CODE (otherops[2]) == CONST_INT 8805 && (INTVAL(otherops[2]) <= -256 8806 || INTVAL(otherops[2]) >= 256)) 8807 { 8808 otherops[0] = gen_rtx_REG (SImode, 1 + reg0); 8809 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); 8810 otherops[0] = operands[0]; 8811 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); 8812 } 8813 else 8814 /* We only allow constant increments, so this is safe. */ 8815 output_asm_insn ("ldr%?d\t%0, [%1], %2", otherops); 8816 } 8817 break; 8818 8819 case LABEL_REF: 8820 case CONST: 8821 output_asm_insn ("adr%?\t%0, %1", operands); 8822 output_asm_insn ("ldm%?ia\t%0, %M0", operands); 8823 break; 8824 8825 default: 8826 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), 8827 GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) 8828 { 8829 otherops[0] = operands[0]; 8830 otherops[1] = XEXP (XEXP (operands[1], 0), 0); 8831 otherops[2] = XEXP (XEXP (operands[1], 0), 1); 8832 8833 if (GET_CODE (XEXP (operands[1], 0)) == PLUS) 8834 { 8835 if (GET_CODE (otherops[2]) == CONST_INT) 8836 { 8837 switch ((int) INTVAL (otherops[2])) 8838 { 8839 case -8: 8840 output_asm_insn ("ldm%?db\t%1, %M0", otherops); 8841 return ""; 8842 case -4: 8843 output_asm_insn ("ldm%?da\t%1, %M0", otherops); 8844 return ""; 8845 case 4: 8846 output_asm_insn ("ldm%?ib\t%1, %M0", otherops); 8847 return ""; 8848 } 8849 } 8850 if (TARGET_LDRD 8851 && (GET_CODE (otherops[2]) == REG 8852 || (GET_CODE (otherops[2]) == CONST_INT 8853 && INTVAL (otherops[2]) > -256 8854 && INTVAL (otherops[2]) < 256))) 8855 { 8856 if (reg_overlap_mentioned_p (otherops[0], 8857 otherops[2])) 8858 { 8859 /* Swap base and index registers over to 8860 avoid a conflict. */ 8861 otherops[1] = XEXP (XEXP (operands[1], 0), 1); 8862 otherops[2] = XEXP (XEXP (operands[1], 0), 0); 8863 } 8864 /* If both registers conflict, it will usually 8865 have been fixed by a splitter. */ 8866 if (reg_overlap_mentioned_p (otherops[0], otherops[2])) 8867 { 8868 output_asm_insn ("add%?\t%1, %1, %2", otherops); 8869 output_asm_insn ("ldr%?d\t%0, [%1]", 8870 otherops); 8871 } 8872 else 8873 output_asm_insn ("ldr%?d\t%0, [%1, %2]", otherops); 8874 return ""; 8875 } 8876 8877 if (GET_CODE (otherops[2]) == CONST_INT) 8878 { 8879 if (!(const_ok_for_arm (INTVAL (otherops[2])))) 8880 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); 8881 else 8882 output_asm_insn ("add%?\t%0, %1, %2", otherops); 8883 } 8884 else 8885 output_asm_insn ("add%?\t%0, %1, %2", otherops); 8886 } 8887 else 8888 output_asm_insn ("sub%?\t%0, %1, %2", otherops); 8889 8890 return "ldm%?ia\t%0, %M0"; 8891 } 8892 else 8893 { 8894 otherops[1] = adjust_address (operands[1], SImode, 4); 8895 /* Take care of overlapping base/data reg. */ 8896 if (reg_mentioned_p (operands[0], operands[1])) 8897 { 8898 output_asm_insn ("ldr%?\t%0, %1", otherops); 8899 output_asm_insn ("ldr%?\t%0, %1", operands); 8900 } 8901 else 8902 { 8903 output_asm_insn ("ldr%?\t%0, %1", operands); 8904 output_asm_insn ("ldr%?\t%0, %1", otherops); 8905 } 8906 } 8907 } 8908 } 8909 else 8910 { 8911 /* Constraints should ensure this. */ 8912 gcc_assert (code0 == MEM && code1 == REG); 8913 gcc_assert (REGNO (operands[1]) != IP_REGNUM); 8914 8915 switch (GET_CODE (XEXP (operands[0], 0))) 8916 { 8917 case REG: 8918 output_asm_insn ("stm%?ia\t%m0, %M1", operands); 8919 break; 8920 8921 case PRE_INC: 8922 gcc_assert (TARGET_LDRD); 8923 output_asm_insn ("str%?d\t%1, [%m0, #8]!", operands); 8924 break; 8925 8926 case PRE_DEC: 8927 output_asm_insn ("stm%?db\t%m0!, %M1", operands); 8928 break; 8929 8930 case POST_INC: 8931 output_asm_insn ("stm%?ia\t%m0!, %M1", operands); 8932 break; 8933 8934 case POST_DEC: 8935 gcc_assert (TARGET_LDRD); 8936 output_asm_insn ("str%?d\t%1, [%m0], #-8", operands); 8937 break; 8938 8939 case PRE_MODIFY: 8940 case POST_MODIFY: 8941 otherops[0] = operands[1]; 8942 otherops[1] = XEXP (XEXP (XEXP (operands[0], 0), 1), 0); 8943 otherops[2] = XEXP (XEXP (XEXP (operands[0], 0), 1), 1); 8944 8945 /* IWMMXT allows offsets larger than ldrd can handle, 8946 fix these up with a pair of ldr. */ 8947 if (GET_CODE (otherops[2]) == CONST_INT 8948 && (INTVAL(otherops[2]) <= -256 8949 || INTVAL(otherops[2]) >= 256)) 8950 { 8951 rtx reg1; 8952 reg1 = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); 8953 if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) 8954 { 8955 output_asm_insn ("ldr%?\t%0, [%1, %2]!", otherops); 8956 otherops[0] = reg1; 8957 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); 8958 } 8959 else 8960 { 8961 otherops[0] = reg1; 8962 output_asm_insn ("ldr%?\t%0, [%1, #4]", otherops); 8963 otherops[0] = operands[1]; 8964 output_asm_insn ("ldr%?\t%0, [%1], %2", otherops); 8965 } 8966 } 8967 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY) 8968 output_asm_insn ("str%?d\t%0, [%1, %2]!", otherops); 8969 else 8970 output_asm_insn ("str%?d\t%0, [%1], %2", otherops); 8971 break; 8972 8973 case PLUS: 8974 otherops[2] = XEXP (XEXP (operands[0], 0), 1); 8975 if (GET_CODE (otherops[2]) == CONST_INT) 8976 { 8977 switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) 8978 { 8979 case -8: 8980 output_asm_insn ("stm%?db\t%m0, %M1", operands); 8981 return ""; 8982 8983 case -4: 8984 output_asm_insn ("stm%?da\t%m0, %M1", operands); 8985 return ""; 8986 8987 case 4: 8988 output_asm_insn ("stm%?ib\t%m0, %M1", operands); 8989 return ""; 8990 } 8991 } 8992 if (TARGET_LDRD 8993 && (GET_CODE (otherops[2]) == REG 8994 || (GET_CODE (otherops[2]) == CONST_INT 8995 && INTVAL (otherops[2]) > -256 8996 && INTVAL (otherops[2]) < 256))) 8997 { 8998 otherops[0] = operands[1]; 8999 otherops[1] = XEXP (XEXP (operands[0], 0), 0); 9000 output_asm_insn ("str%?d\t%0, [%1, %2]", otherops); 9001 return ""; 9002 } 9003 /* Fall through */ 9004 9005 default: 9006 otherops[0] = adjust_address (operands[0], SImode, 4); 9007 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); 9008 output_asm_insn ("str%?\t%1, %0", operands); 9009 output_asm_insn ("str%?\t%1, %0", otherops); 9010 } 9011 } 9012 9013 return ""; 9014} 9015 9016/* Output an ADD r, s, #n where n may be too big for one instruction. 9017 If adding zero to one register, output nothing. */ 9018const char * 9019output_add_immediate (rtx *operands) 9020{ 9021 HOST_WIDE_INT n = INTVAL (operands[2]); 9022 9023 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) 9024 { 9025 if (n < 0) 9026 output_multi_immediate (operands, 9027 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, 9028 -n); 9029 else 9030 output_multi_immediate (operands, 9031 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, 9032 n); 9033 } 9034 9035 return ""; 9036} 9037 9038/* Output a multiple immediate operation. 9039 OPERANDS is the vector of operands referred to in the output patterns. 9040 INSTR1 is the output pattern to use for the first constant. 9041 INSTR2 is the output pattern to use for subsequent constants. 9042 IMMED_OP is the index of the constant slot in OPERANDS. 9043 N is the constant value. */ 9044static const char * 9045output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, 9046 int immed_op, HOST_WIDE_INT n) 9047{ 9048#if HOST_BITS_PER_WIDE_INT > 32 9049 n &= 0xffffffff; 9050#endif 9051 9052 if (n == 0) 9053 { 9054 /* Quick and easy output. */ 9055 operands[immed_op] = const0_rtx; 9056 output_asm_insn (instr1, operands); 9057 } 9058 else 9059 { 9060 int i; 9061 const char * instr = instr1; 9062 9063 /* Note that n is never zero here (which would give no output). */ 9064 for (i = 0; i < 32; i += 2) 9065 { 9066 if (n & (3 << i)) 9067 { 9068 operands[immed_op] = GEN_INT (n & (255 << i)); 9069 output_asm_insn (instr, operands); 9070 instr = instr2; 9071 i += 6; 9072 } 9073 } 9074 } 9075 9076 return ""; 9077} 9078 9079/* Return the appropriate ARM instruction for the operation code. 9080 The returned result should not be overwritten. OP is the rtx of the 9081 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator 9082 was shifted. */ 9083const char * 9084arithmetic_instr (rtx op, int shift_first_arg) 9085{ 9086 switch (GET_CODE (op)) 9087 { 9088 case PLUS: 9089 return "add"; 9090 9091 case MINUS: 9092 return shift_first_arg ? "rsb" : "sub"; 9093 9094 case IOR: 9095 return "orr"; 9096 9097 case XOR: 9098 return "eor"; 9099 9100 case AND: 9101 return "and"; 9102 9103 default: 9104 gcc_unreachable (); 9105 } 9106} 9107 9108/* Ensure valid constant shifts and return the appropriate shift mnemonic 9109 for the operation code. The returned result should not be overwritten. 9110 OP is the rtx code of the shift. 9111 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant 9112 shift. */ 9113static const char * 9114shift_op (rtx op, HOST_WIDE_INT *amountp) 9115{ 9116 const char * mnem; 9117 enum rtx_code code = GET_CODE (op); 9118 9119 switch (GET_CODE (XEXP (op, 1))) 9120 { 9121 case REG: 9122 case SUBREG: 9123 *amountp = -1; 9124 break; 9125 9126 case CONST_INT: 9127 *amountp = INTVAL (XEXP (op, 1)); 9128 break; 9129 9130 default: 9131 gcc_unreachable (); 9132 } 9133 9134 switch (code) 9135 { 9136 case ASHIFT: 9137 mnem = "asl"; 9138 break; 9139 9140 case ASHIFTRT: 9141 mnem = "asr"; 9142 break; 9143 9144 case LSHIFTRT: 9145 mnem = "lsr"; 9146 break; 9147 9148 case ROTATE: 9149 gcc_assert (*amountp != -1); 9150 *amountp = 32 - *amountp; 9151 9152 /* Fall through. */ 9153 9154 case ROTATERT: 9155 mnem = "ror"; 9156 break; 9157 9158 case MULT: 9159 /* We never have to worry about the amount being other than a 9160 power of 2, since this case can never be reloaded from a reg. */ 9161 gcc_assert (*amountp != -1); 9162 *amountp = int_log2 (*amountp); 9163 return "asl"; 9164 9165 default: 9166 gcc_unreachable (); 9167 } 9168 9169 if (*amountp != -1) 9170 { 9171 /* This is not 100% correct, but follows from the desire to merge 9172 multiplication by a power of 2 with the recognizer for a 9173 shift. >=32 is not a valid shift for "asl", so we must try and 9174 output a shift that produces the correct arithmetical result. 9175 Using lsr #32 is identical except for the fact that the carry bit 9176 is not set correctly if we set the flags; but we never use the 9177 carry bit from such an operation, so we can ignore that. */ 9178 if (code == ROTATERT) 9179 /* Rotate is just modulo 32. */ 9180 *amountp &= 31; 9181 else if (*amountp != (*amountp & 31)) 9182 { 9183 if (code == ASHIFT) 9184 mnem = "lsr"; 9185 *amountp = 32; 9186 } 9187 9188 /* Shifts of 0 are no-ops. */ 9189 if (*amountp == 0) 9190 return NULL; 9191 } 9192 9193 return mnem; 9194} 9195 9196/* Obtain the shift from the POWER of two. */ 9197 9198static HOST_WIDE_INT 9199int_log2 (HOST_WIDE_INT power) 9200{ 9201 HOST_WIDE_INT shift = 0; 9202 9203 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) 9204 { 9205 gcc_assert (shift <= 31); 9206 shift++; 9207 } 9208 9209 return shift; 9210} 9211 9212/* Output a .ascii pseudo-op, keeping track of lengths. This is 9213 because /bin/as is horribly restrictive. The judgement about 9214 whether or not each character is 'printable' (and can be output as 9215 is) or not (and must be printed with an octal escape) must be made 9216 with reference to the *host* character set -- the situation is 9217 similar to that discussed in the comments above pp_c_char in 9218 c-pretty-print.c. */ 9219 9220#define MAX_ASCII_LEN 51 9221 9222void 9223output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) 9224{ 9225 int i; 9226 int len_so_far = 0; 9227 9228 fputs ("\t.ascii\t\"", stream); 9229 9230 for (i = 0; i < len; i++) 9231 { 9232 int c = p[i]; 9233 9234 if (len_so_far >= MAX_ASCII_LEN) 9235 { 9236 fputs ("\"\n\t.ascii\t\"", stream); 9237 len_so_far = 0; 9238 } 9239 9240 if (ISPRINT (c)) 9241 { 9242 if (c == '\\' || c == '\"') 9243 { 9244 putc ('\\', stream); 9245 len_so_far++; 9246 } 9247 putc (c, stream); 9248 len_so_far++; 9249 } 9250 else 9251 { 9252 fprintf (stream, "\\%03o", c); 9253 len_so_far += 4; 9254 } 9255 } 9256 9257 fputs ("\"\n", stream); 9258} 9259 9260/* Compute the register save mask for registers 0 through 12 9261 inclusive. This code is used by arm_compute_save_reg_mask. */ 9262 9263static unsigned long 9264arm_compute_save_reg0_reg12_mask (void) 9265{ 9266 unsigned long func_type = arm_current_func_type (); 9267 unsigned long save_reg_mask = 0; 9268 unsigned int reg; 9269 9270 if (IS_INTERRUPT (func_type)) 9271 { 9272 unsigned int max_reg; 9273 /* Interrupt functions must not corrupt any registers, 9274 even call clobbered ones. If this is a leaf function 9275 we can just examine the registers used by the RTL, but 9276 otherwise we have to assume that whatever function is 9277 called might clobber anything, and so we have to save 9278 all the call-clobbered registers as well. */ 9279 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) 9280 /* FIQ handlers have registers r8 - r12 banked, so 9281 we only need to check r0 - r7, Normal ISRs only 9282 bank r14 and r15, so we must check up to r12. 9283 r13 is the stack pointer which is always preserved, 9284 so we do not need to consider it here. */ 9285 max_reg = 7; 9286 else 9287 max_reg = 12; 9288 9289 for (reg = 0; reg <= max_reg; reg++) 9290 if (regs_ever_live[reg] 9291 || (! current_function_is_leaf && call_used_regs [reg])) 9292 save_reg_mask |= (1 << reg); 9293 9294 /* Also save the pic base register if necessary. */ 9295 if (flag_pic 9296 && !TARGET_SINGLE_PIC_BASE 9297 && arm_pic_register != INVALID_REGNUM 9298 && current_function_uses_pic_offset_table) 9299 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; 9300 } 9301 else 9302 { 9303 /* In the normal case we only need to save those registers 9304 which are call saved and which are used by this function. */ 9305 for (reg = 0; reg <= 10; reg++) 9306 if (regs_ever_live[reg] && ! call_used_regs [reg]) 9307 save_reg_mask |= (1 << reg); 9308 9309 /* Handle the frame pointer as a special case. */ 9310 if (! TARGET_APCS_FRAME 9311 && ! frame_pointer_needed 9312 && regs_ever_live[HARD_FRAME_POINTER_REGNUM] 9313 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) 9314 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; 9315 9316 /* If we aren't loading the PIC register, 9317 don't stack it even though it may be live. */ 9318 if (flag_pic 9319 && !TARGET_SINGLE_PIC_BASE 9320 && arm_pic_register != INVALID_REGNUM 9321 && (regs_ever_live[PIC_OFFSET_TABLE_REGNUM] 9322 || current_function_uses_pic_offset_table)) 9323 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; 9324 } 9325 9326 /* Save registers so the exception handler can modify them. */ 9327 if (current_function_calls_eh_return) 9328 { 9329 unsigned int i; 9330 9331 for (i = 0; ; i++) 9332 { 9333 reg = EH_RETURN_DATA_REGNO (i); 9334 if (reg == INVALID_REGNUM) 9335 break; 9336 save_reg_mask |= 1 << reg; 9337 } 9338 } 9339 9340 return save_reg_mask; 9341} 9342 9343/* Compute a bit mask of which registers need to be 9344 saved on the stack for the current function. */ 9345 9346static unsigned long 9347arm_compute_save_reg_mask (void) 9348{ 9349 unsigned int save_reg_mask = 0; 9350 unsigned long func_type = arm_current_func_type (); 9351 9352 if (IS_NAKED (func_type)) 9353 /* This should never really happen. */ 9354 return 0; 9355 9356 /* If we are creating a stack frame, then we must save the frame pointer, 9357 IP (which will hold the old stack pointer), LR and the PC. */ 9358 if (frame_pointer_needed) 9359 save_reg_mask |= 9360 (1 << ARM_HARD_FRAME_POINTER_REGNUM) 9361 | (1 << IP_REGNUM) 9362 | (1 << LR_REGNUM) 9363 | (1 << PC_REGNUM); 9364 9365 /* Volatile functions do not return, so there 9366 is no need to save any other registers. */ 9367 if (IS_VOLATILE (func_type)) 9368 return save_reg_mask; 9369 9370 save_reg_mask |= arm_compute_save_reg0_reg12_mask (); 9371 9372 /* Decide if we need to save the link register. 9373 Interrupt routines have their own banked link register, 9374 so they never need to save it. 9375 Otherwise if we do not use the link register we do not need to save 9376 it. If we are pushing other registers onto the stack however, we 9377 can save an instruction in the epilogue by pushing the link register 9378 now and then popping it back into the PC. This incurs extra memory 9379 accesses though, so we only do it when optimizing for size, and only 9380 if we know that we will not need a fancy return sequence. */ 9381 if (regs_ever_live [LR_REGNUM] 9382 || (save_reg_mask 9383 && optimize_size 9384 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL 9385 && !current_function_calls_eh_return)) 9386 save_reg_mask |= 1 << LR_REGNUM; 9387 9388 if (cfun->machine->lr_save_eliminated) 9389 save_reg_mask &= ~ (1 << LR_REGNUM); 9390 9391 if (TARGET_REALLY_IWMMXT 9392 && ((bit_count (save_reg_mask) 9393 + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0) 9394 { 9395 unsigned int reg; 9396 9397 /* The total number of registers that are going to be pushed 9398 onto the stack is odd. We need to ensure that the stack 9399 is 64-bit aligned before we start to save iWMMXt registers, 9400 and also before we start to create locals. (A local variable 9401 might be a double or long long which we will load/store using 9402 an iWMMXt instruction). Therefore we need to push another 9403 ARM register, so that the stack will be 64-bit aligned. We 9404 try to avoid using the arg registers (r0 -r3) as they might be 9405 used to pass values in a tail call. */ 9406 for (reg = 4; reg <= 12; reg++) 9407 if ((save_reg_mask & (1 << reg)) == 0) 9408 break; 9409 9410 if (reg <= 12) 9411 save_reg_mask |= (1 << reg); 9412 else 9413 { 9414 cfun->machine->sibcall_blocked = 1; 9415 save_reg_mask |= (1 << 3); 9416 } 9417 } 9418 9419 return save_reg_mask; 9420} 9421 9422 9423/* Compute a bit mask of which registers need to be 9424 saved on the stack for the current function. */ 9425static unsigned long 9426thumb_compute_save_reg_mask (void) 9427{ 9428 unsigned long mask; 9429 unsigned reg; 9430 9431 mask = 0; 9432 for (reg = 0; reg < 12; reg ++) 9433 if (regs_ever_live[reg] && !call_used_regs[reg]) 9434 mask |= 1 << reg; 9435 9436 if (flag_pic 9437 && !TARGET_SINGLE_PIC_BASE 9438 && arm_pic_register != INVALID_REGNUM 9439 && current_function_uses_pic_offset_table) 9440 mask |= 1 << PIC_OFFSET_TABLE_REGNUM; 9441 9442 /* See if we might need r11 for calls to _interwork_r11_call_via_rN(). */ 9443 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) 9444 mask |= 1 << ARM_HARD_FRAME_POINTER_REGNUM; 9445 9446 /* LR will also be pushed if any lo regs are pushed. */ 9447 if (mask & 0xff || thumb_force_lr_save ()) 9448 mask |= (1 << LR_REGNUM); 9449 9450 /* Make sure we have a low work register if we need one. 9451 We will need one if we are going to push a high register, 9452 but we are not currently intending to push a low register. */ 9453 if ((mask & 0xff) == 0 9454 && ((mask & 0x0f00) || TARGET_BACKTRACE)) 9455 { 9456 /* Use thumb_find_work_register to choose which register 9457 we will use. If the register is live then we will 9458 have to push it. Use LAST_LO_REGNUM as our fallback 9459 choice for the register to select. */ 9460 reg = thumb_find_work_register (1 << LAST_LO_REGNUM); 9461 9462 if (! call_used_regs[reg]) 9463 mask |= 1 << reg; 9464 } 9465 9466 return mask; 9467} 9468 9469 9470/* Return the number of bytes required to save VFP registers. */ 9471static int 9472arm_get_vfp_saved_size (void) 9473{ 9474 unsigned int regno; 9475 int count; 9476 int saved; 9477 9478 saved = 0; 9479 /* Space for saved VFP registers. */ 9480 if (TARGET_HARD_FLOAT && TARGET_VFP) 9481 { 9482 count = 0; 9483 for (regno = FIRST_VFP_REGNUM; 9484 regno < LAST_VFP_REGNUM; 9485 regno += 2) 9486 { 9487 if ((!regs_ever_live[regno] || call_used_regs[regno]) 9488 && (!regs_ever_live[regno + 1] || call_used_regs[regno + 1])) 9489 { 9490 if (count > 0) 9491 { 9492 /* Workaround ARM10 VFPr1 bug. */ 9493 if (count == 2 && !arm_arch6) 9494 count++; 9495 saved += count * 8 + 4; 9496 } 9497 count = 0; 9498 } 9499 else 9500 count++; 9501 } 9502 if (count > 0) 9503 { 9504 if (count == 2 && !arm_arch6) 9505 count++; 9506 saved += count * 8 + 4; 9507 } 9508 } 9509 return saved; 9510} 9511 9512 9513/* Generate a function exit sequence. If REALLY_RETURN is false, then do 9514 everything bar the final return instruction. */ 9515const char * 9516output_return_instruction (rtx operand, int really_return, int reverse) 9517{ 9518 char conditional[10]; 9519 char instr[100]; 9520 unsigned reg; 9521 unsigned long live_regs_mask; 9522 unsigned long func_type; 9523 arm_stack_offsets *offsets; 9524 9525 func_type = arm_current_func_type (); 9526 9527 if (IS_NAKED (func_type)) 9528 return ""; 9529 9530 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) 9531 { 9532 /* If this function was declared non-returning, and we have 9533 found a tail call, then we have to trust that the called 9534 function won't return. */ 9535 if (really_return) 9536 { 9537 rtx ops[2]; 9538 9539 /* Otherwise, trap an attempted return by aborting. */ 9540 ops[0] = operand; 9541 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" 9542 : "abort"); 9543 assemble_external_libcall (ops[1]); 9544 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); 9545 } 9546 9547 return ""; 9548 } 9549 9550 gcc_assert (!current_function_calls_alloca || really_return); 9551 9552 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); 9553 9554 return_used_this_function = 1; 9555 9556 live_regs_mask = arm_compute_save_reg_mask (); 9557 9558 if (live_regs_mask) 9559 { 9560 const char * return_reg; 9561 9562 /* If we do not have any special requirements for function exit 9563 (e.g. interworking, or ISR) then we can load the return address 9564 directly into the PC. Otherwise we must load it into LR. */ 9565 if (really_return 9566 && ! TARGET_INTERWORK) 9567 return_reg = reg_names[PC_REGNUM]; 9568 else 9569 return_reg = reg_names[LR_REGNUM]; 9570 9571 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) 9572 { 9573 /* There are three possible reasons for the IP register 9574 being saved. 1) a stack frame was created, in which case 9575 IP contains the old stack pointer, or 2) an ISR routine 9576 corrupted it, or 3) it was saved to align the stack on 9577 iWMMXt. In case 1, restore IP into SP, otherwise just 9578 restore IP. */ 9579 if (frame_pointer_needed) 9580 { 9581 live_regs_mask &= ~ (1 << IP_REGNUM); 9582 live_regs_mask |= (1 << SP_REGNUM); 9583 } 9584 else 9585 gcc_assert (IS_INTERRUPT (func_type) || TARGET_REALLY_IWMMXT); 9586 } 9587 9588 /* On some ARM architectures it is faster to use LDR rather than 9589 LDM to load a single register. On other architectures, the 9590 cost is the same. In 26 bit mode, or for exception handlers, 9591 we have to use LDM to load the PC so that the CPSR is also 9592 restored. */ 9593 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) 9594 if (live_regs_mask == (1U << reg)) 9595 break; 9596 9597 if (reg <= LAST_ARM_REGNUM 9598 && (reg != LR_REGNUM 9599 || ! really_return 9600 || ! IS_INTERRUPT (func_type))) 9601 { 9602 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, 9603 (reg == LR_REGNUM) ? return_reg : reg_names[reg]); 9604 } 9605 else 9606 { 9607 char *p; 9608 int first = 1; 9609 9610 /* Generate the load multiple instruction to restore the 9611 registers. Note we can get here, even if 9612 frame_pointer_needed is true, but only if sp already 9613 points to the base of the saved core registers. */ 9614 if (live_regs_mask & (1 << SP_REGNUM)) 9615 { 9616 unsigned HOST_WIDE_INT stack_adjust; 9617 9618 offsets = arm_get_frame_offsets (); 9619 stack_adjust = offsets->outgoing_args - offsets->saved_regs; 9620 gcc_assert (stack_adjust == 0 || stack_adjust == 4); 9621 9622 if (stack_adjust && arm_arch5) 9623 sprintf (instr, "ldm%sib\t%%|sp, {", conditional); 9624 else 9625 { 9626 /* If we can't use ldmib (SA110 bug), 9627 then try to pop r3 instead. */ 9628 if (stack_adjust) 9629 live_regs_mask |= 1 << 3; 9630 sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); 9631 } 9632 } 9633 else 9634 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); 9635 9636 p = instr + strlen (instr); 9637 9638 for (reg = 0; reg <= SP_REGNUM; reg++) 9639 if (live_regs_mask & (1 << reg)) 9640 { 9641 int l = strlen (reg_names[reg]); 9642 9643 if (first) 9644 first = 0; 9645 else 9646 { 9647 memcpy (p, ", ", 2); 9648 p += 2; 9649 } 9650 9651 memcpy (p, "%|", 2); 9652 memcpy (p + 2, reg_names[reg], l); 9653 p += l + 2; 9654 } 9655 9656 if (live_regs_mask & (1 << LR_REGNUM)) 9657 { 9658 sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); 9659 /* If returning from an interrupt, restore the CPSR. */ 9660 if (IS_INTERRUPT (func_type)) 9661 strcat (p, "^"); 9662 } 9663 else 9664 strcpy (p, "}"); 9665 } 9666 9667 output_asm_insn (instr, & operand); 9668 9669 /* See if we need to generate an extra instruction to 9670 perform the actual function return. */ 9671 if (really_return 9672 && func_type != ARM_FT_INTERWORKED 9673 && (live_regs_mask & (1 << LR_REGNUM)) != 0) 9674 { 9675 /* The return has already been handled 9676 by loading the LR into the PC. */ 9677 really_return = 0; 9678 } 9679 } 9680 9681 if (really_return) 9682 { 9683 switch ((int) ARM_FUNC_TYPE (func_type)) 9684 { 9685 case ARM_FT_ISR: 9686 case ARM_FT_FIQ: 9687 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); 9688 break; 9689 9690 case ARM_FT_INTERWORKED: 9691 sprintf (instr, "bx%s\t%%|lr", conditional); 9692 break; 9693 9694 case ARM_FT_EXCEPTION: 9695 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); 9696 break; 9697 9698 default: 9699 /* Use bx if it's available. */ 9700 if (arm_arch5 || arm_arch4t) 9701 sprintf (instr, "bx%s\t%%|lr", conditional); 9702 else 9703 sprintf (instr, "mov%s\t%%|pc, %%|lr", conditional); 9704 break; 9705 } 9706 9707 output_asm_insn (instr, & operand); 9708 } 9709 9710 return ""; 9711} 9712 9713/* Write the function name into the code section, directly preceding 9714 the function prologue. 9715 9716 Code will be output similar to this: 9717 t0 9718 .ascii "arm_poke_function_name", 0 9719 .align 9720 t1 9721 .word 0xff000000 + (t1 - t0) 9722 arm_poke_function_name 9723 mov ip, sp 9724 stmfd sp!, {fp, ip, lr, pc} 9725 sub fp, ip, #4 9726 9727 When performing a stack backtrace, code can inspect the value 9728 of 'pc' stored at 'fp' + 0. If the trace function then looks 9729 at location pc - 12 and the top 8 bits are set, then we know 9730 that there is a function name embedded immediately preceding this 9731 location and has length ((pc[-3]) & 0xff000000). 9732 9733 We assume that pc is declared as a pointer to an unsigned long. 9734 9735 It is of no benefit to output the function name if we are assembling 9736 a leaf function. These function types will not contain a stack 9737 backtrace structure, therefore it is not possible to determine the 9738 function name. */ 9739void 9740arm_poke_function_name (FILE *stream, const char *name) 9741{ 9742 unsigned long alignlength; 9743 unsigned long length; 9744 rtx x; 9745 9746 length = strlen (name) + 1; 9747 alignlength = ROUND_UP_WORD (length); 9748 9749 ASM_OUTPUT_ASCII (stream, name, length); 9750 ASM_OUTPUT_ALIGN (stream, 2); 9751 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); 9752 assemble_aligned_integer (UNITS_PER_WORD, x); 9753} 9754 9755/* Place some comments into the assembler stream 9756 describing the current function. */ 9757static void 9758arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) 9759{ 9760 unsigned long func_type; 9761 9762 if (!TARGET_ARM) 9763 { 9764 thumb_output_function_prologue (f, frame_size); 9765 return; 9766 } 9767 9768 /* Sanity check. */ 9769 gcc_assert (!arm_ccfsm_state && !arm_target_insn); 9770 9771 func_type = arm_current_func_type (); 9772 9773 switch ((int) ARM_FUNC_TYPE (func_type)) 9774 { 9775 default: 9776 case ARM_FT_NORMAL: 9777 break; 9778 case ARM_FT_INTERWORKED: 9779 asm_fprintf (f, "\t%@ Function supports interworking.\n"); 9780 break; 9781 case ARM_FT_ISR: 9782 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); 9783 break; 9784 case ARM_FT_FIQ: 9785 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); 9786 break; 9787 case ARM_FT_EXCEPTION: 9788 asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); 9789 break; 9790 } 9791 9792 if (IS_NAKED (func_type)) 9793 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); 9794 9795 if (IS_VOLATILE (func_type)) 9796 asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); 9797 9798 if (IS_NESTED (func_type)) 9799 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); 9800 9801 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", 9802 current_function_args_size, 9803 current_function_pretend_args_size, frame_size); 9804 9805 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", 9806 frame_pointer_needed, 9807 cfun->machine->uses_anonymous_args); 9808 9809 if (cfun->machine->lr_save_eliminated) 9810 asm_fprintf (f, "\t%@ link register save eliminated.\n"); 9811 9812 if (current_function_calls_eh_return) 9813 asm_fprintf (f, "\t@ Calls __builtin_eh_return.\n"); 9814 9815#ifdef AOF_ASSEMBLER 9816 if (flag_pic) 9817 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM); 9818#endif 9819 9820 return_used_this_function = 0; 9821} 9822 9823const char * 9824arm_output_epilogue (rtx sibling) 9825{ 9826 int reg; 9827 unsigned long saved_regs_mask; 9828 unsigned long func_type; 9829 /* Floats_offset is the offset from the "virtual" frame. In an APCS 9830 frame that is $fp + 4 for a non-variadic function. */ 9831 int floats_offset = 0; 9832 rtx operands[3]; 9833 FILE * f = asm_out_file; 9834 unsigned int lrm_count = 0; 9835 int really_return = (sibling == NULL); 9836 int start_reg; 9837 arm_stack_offsets *offsets; 9838 9839 /* If we have already generated the return instruction 9840 then it is futile to generate anything else. */ 9841 if (use_return_insn (FALSE, sibling) && return_used_this_function) 9842 return ""; 9843 9844 func_type = arm_current_func_type (); 9845 9846 if (IS_NAKED (func_type)) 9847 /* Naked functions don't have epilogues. */ 9848 return ""; 9849 9850 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) 9851 { 9852 rtx op; 9853 9854 /* A volatile function should never return. Call abort. */ 9855 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); 9856 assemble_external_libcall (op); 9857 output_asm_insn ("bl\t%a0", &op); 9858 9859 return ""; 9860 } 9861 9862 /* If we are throwing an exception, then we really must be doing a 9863 return, so we can't tail-call. */ 9864 gcc_assert (!current_function_calls_eh_return || really_return); 9865 9866 offsets = arm_get_frame_offsets (); 9867 saved_regs_mask = arm_compute_save_reg_mask (); 9868 9869 if (TARGET_IWMMXT) 9870 lrm_count = bit_count (saved_regs_mask); 9871 9872 floats_offset = offsets->saved_args; 9873 /* Compute how far away the floats will be. */ 9874 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) 9875 if (saved_regs_mask & (1 << reg)) 9876 floats_offset += 4; 9877 9878 if (frame_pointer_needed) 9879 { 9880 /* This variable is for the Virtual Frame Pointer, not VFP regs. */ 9881 int vfp_offset = offsets->frame; 9882 9883 if (arm_fpu_arch == FPUTYPE_FPA_EMU2) 9884 { 9885 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) 9886 if (regs_ever_live[reg] && !call_used_regs[reg]) 9887 { 9888 floats_offset += 12; 9889 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", 9890 reg, FP_REGNUM, floats_offset - vfp_offset); 9891 } 9892 } 9893 else 9894 { 9895 start_reg = LAST_FPA_REGNUM; 9896 9897 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) 9898 { 9899 if (regs_ever_live[reg] && !call_used_regs[reg]) 9900 { 9901 floats_offset += 12; 9902 9903 /* We can't unstack more than four registers at once. */ 9904 if (start_reg - reg == 3) 9905 { 9906 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", 9907 reg, FP_REGNUM, floats_offset - vfp_offset); 9908 start_reg = reg - 1; 9909 } 9910 } 9911 else 9912 { 9913 if (reg != start_reg) 9914 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", 9915 reg + 1, start_reg - reg, 9916 FP_REGNUM, floats_offset - vfp_offset); 9917 start_reg = reg - 1; 9918 } 9919 } 9920 9921 /* Just in case the last register checked also needs unstacking. */ 9922 if (reg != start_reg) 9923 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", 9924 reg + 1, start_reg - reg, 9925 FP_REGNUM, floats_offset - vfp_offset); 9926 } 9927 9928 if (TARGET_HARD_FLOAT && TARGET_VFP) 9929 { 9930 int saved_size; 9931 9932 /* The fldmx insn does not have base+offset addressing modes, 9933 so we use IP to hold the address. */ 9934 saved_size = arm_get_vfp_saved_size (); 9935 9936 if (saved_size > 0) 9937 { 9938 floats_offset += saved_size; 9939 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", IP_REGNUM, 9940 FP_REGNUM, floats_offset - vfp_offset); 9941 } 9942 start_reg = FIRST_VFP_REGNUM; 9943 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) 9944 { 9945 if ((!regs_ever_live[reg] || call_used_regs[reg]) 9946 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) 9947 { 9948 if (start_reg != reg) 9949 arm_output_fldmx (f, IP_REGNUM, 9950 (start_reg - FIRST_VFP_REGNUM) / 2, 9951 (reg - start_reg) / 2); 9952 start_reg = reg + 2; 9953 } 9954 } 9955 if (start_reg != reg) 9956 arm_output_fldmx (f, IP_REGNUM, 9957 (start_reg - FIRST_VFP_REGNUM) / 2, 9958 (reg - start_reg) / 2); 9959 } 9960 9961 if (TARGET_IWMMXT) 9962 { 9963 /* The frame pointer is guaranteed to be non-double-word aligned. 9964 This is because it is set to (old_stack_pointer - 4) and the 9965 old_stack_pointer was double word aligned. Thus the offset to 9966 the iWMMXt registers to be loaded must also be non-double-word 9967 sized, so that the resultant address *is* double-word aligned. 9968 We can ignore floats_offset since that was already included in 9969 the live_regs_mask. */ 9970 lrm_count += (lrm_count % 2 ? 2 : 1); 9971 9972 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) 9973 if (regs_ever_live[reg] && !call_used_regs[reg]) 9974 { 9975 asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", 9976 reg, FP_REGNUM, lrm_count * 4); 9977 lrm_count += 2; 9978 } 9979 } 9980 9981 /* saved_regs_mask should contain the IP, which at the time of stack 9982 frame generation actually contains the old stack pointer. So a 9983 quick way to unwind the stack is just pop the IP register directly 9984 into the stack pointer. */ 9985 gcc_assert (saved_regs_mask & (1 << IP_REGNUM)); 9986 saved_regs_mask &= ~ (1 << IP_REGNUM); 9987 saved_regs_mask |= (1 << SP_REGNUM); 9988 9989 /* There are two registers left in saved_regs_mask - LR and PC. We 9990 only need to restore the LR register (the return address), but to 9991 save time we can load it directly into the PC, unless we need a 9992 special function exit sequence, or we are not really returning. */ 9993 if (really_return 9994 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL 9995 && !current_function_calls_eh_return) 9996 /* Delete the LR from the register mask, so that the LR on 9997 the stack is loaded into the PC in the register mask. */ 9998 saved_regs_mask &= ~ (1 << LR_REGNUM); 9999 else 10000 saved_regs_mask &= ~ (1 << PC_REGNUM); 10001 10002 /* We must use SP as the base register, because SP is one of the 10003 registers being restored. If an interrupt or page fault 10004 happens in the ldm instruction, the SP might or might not 10005 have been restored. That would be bad, as then SP will no 10006 longer indicate the safe area of stack, and we can get stack 10007 corruption. Using SP as the base register means that it will 10008 be reset correctly to the original value, should an interrupt 10009 occur. If the stack pointer already points at the right 10010 place, then omit the subtraction. */ 10011 if (offsets->outgoing_args != (1 + (int) bit_count (saved_regs_mask)) 10012 || current_function_calls_alloca) 10013 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM, 10014 4 * bit_count (saved_regs_mask)); 10015 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); 10016 10017 if (IS_INTERRUPT (func_type)) 10018 /* Interrupt handlers will have pushed the 10019 IP onto the stack, so restore it now. */ 10020 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, 1 << IP_REGNUM); 10021 } 10022 else 10023 { 10024 /* Restore stack pointer if necessary. */ 10025 if (offsets->outgoing_args != offsets->saved_regs) 10026 { 10027 operands[0] = operands[1] = stack_pointer_rtx; 10028 operands[2] = GEN_INT (offsets->outgoing_args - offsets->saved_regs); 10029 output_add_immediate (operands); 10030 } 10031 10032 if (arm_fpu_arch == FPUTYPE_FPA_EMU2) 10033 { 10034 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) 10035 if (regs_ever_live[reg] && !call_used_regs[reg]) 10036 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", 10037 reg, SP_REGNUM); 10038 } 10039 else 10040 { 10041 start_reg = FIRST_FPA_REGNUM; 10042 10043 for (reg = FIRST_FPA_REGNUM; reg <= LAST_FPA_REGNUM; reg++) 10044 { 10045 if (regs_ever_live[reg] && !call_used_regs[reg]) 10046 { 10047 if (reg - start_reg == 3) 10048 { 10049 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", 10050 start_reg, SP_REGNUM); 10051 start_reg = reg + 1; 10052 } 10053 } 10054 else 10055 { 10056 if (reg != start_reg) 10057 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", 10058 start_reg, reg - start_reg, 10059 SP_REGNUM); 10060 10061 start_reg = reg + 1; 10062 } 10063 } 10064 10065 /* Just in case the last register checked also needs unstacking. */ 10066 if (reg != start_reg) 10067 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", 10068 start_reg, reg - start_reg, SP_REGNUM); 10069 } 10070 10071 if (TARGET_HARD_FLOAT && TARGET_VFP) 10072 { 10073 start_reg = FIRST_VFP_REGNUM; 10074 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) 10075 { 10076 if ((!regs_ever_live[reg] || call_used_regs[reg]) 10077 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) 10078 { 10079 if (start_reg != reg) 10080 arm_output_fldmx (f, SP_REGNUM, 10081 (start_reg - FIRST_VFP_REGNUM) / 2, 10082 (reg - start_reg) / 2); 10083 start_reg = reg + 2; 10084 } 10085 } 10086 if (start_reg != reg) 10087 arm_output_fldmx (f, SP_REGNUM, 10088 (start_reg - FIRST_VFP_REGNUM) / 2, 10089 (reg - start_reg) / 2); 10090 } 10091 if (TARGET_IWMMXT) 10092 for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) 10093 if (regs_ever_live[reg] && !call_used_regs[reg]) 10094 asm_fprintf (f, "\twldrd\t%r, [%r], #8\n", reg, SP_REGNUM); 10095 10096 /* If we can, restore the LR into the PC. */ 10097 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL 10098 && really_return 10099 && current_function_pretend_args_size == 0 10100 && saved_regs_mask & (1 << LR_REGNUM) 10101 && !current_function_calls_eh_return) 10102 { 10103 saved_regs_mask &= ~ (1 << LR_REGNUM); 10104 saved_regs_mask |= (1 << PC_REGNUM); 10105 } 10106 10107 /* Load the registers off the stack. If we only have one register 10108 to load use the LDR instruction - it is faster. */ 10109 if (saved_regs_mask == (1 << LR_REGNUM)) 10110 { 10111 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); 10112 } 10113 else if (saved_regs_mask) 10114 { 10115 if (saved_regs_mask & (1 << SP_REGNUM)) 10116 /* Note - write back to the stack register is not enabled 10117 (i.e. "ldmfd sp!..."). We know that the stack pointer is 10118 in the list of registers and if we add writeback the 10119 instruction becomes UNPREDICTABLE. */ 10120 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); 10121 else 10122 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask); 10123 } 10124 10125 if (current_function_pretend_args_size) 10126 { 10127 /* Unwind the pre-pushed regs. */ 10128 operands[0] = operands[1] = stack_pointer_rtx; 10129 operands[2] = GEN_INT (current_function_pretend_args_size); 10130 output_add_immediate (operands); 10131 } 10132 } 10133 10134 /* We may have already restored PC directly from the stack. */ 10135 if (!really_return || saved_regs_mask & (1 << PC_REGNUM)) 10136 return ""; 10137 10138 /* Stack adjustment for exception handler. */ 10139 if (current_function_calls_eh_return) 10140 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, 10141 ARM_EH_STACKADJ_REGNUM); 10142 10143 /* Generate the return instruction. */ 10144 switch ((int) ARM_FUNC_TYPE (func_type)) 10145 { 10146 case ARM_FT_ISR: 10147 case ARM_FT_FIQ: 10148 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); 10149 break; 10150 10151 case ARM_FT_EXCEPTION: 10152 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); 10153 break; 10154 10155 case ARM_FT_INTERWORKED: 10156 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); 10157 break; 10158 10159 default: 10160 if (arm_arch5 || arm_arch4t) 10161 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); 10162 else 10163 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); 10164 break; 10165 } 10166 10167 return ""; 10168} 10169 10170static void 10171arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, 10172 HOST_WIDE_INT frame_size ATTRIBUTE_UNUSED) 10173{ 10174 arm_stack_offsets *offsets; 10175 10176 if (TARGET_THUMB) 10177 { 10178 int regno; 10179 10180 /* Emit any call-via-reg trampolines that are needed for v4t support 10181 of call_reg and call_value_reg type insns. */ 10182 for (regno = 0; regno < LR_REGNUM; regno++) 10183 { 10184 rtx label = cfun->machine->call_via[regno]; 10185 10186 if (label != NULL) 10187 { 10188 switch_to_section (function_section (current_function_decl)); 10189 targetm.asm_out.internal_label (asm_out_file, "L", 10190 CODE_LABEL_NUMBER (label)); 10191 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); 10192 } 10193 } 10194 10195 /* ??? Probably not safe to set this here, since it assumes that a 10196 function will be emitted as assembly immediately after we generate 10197 RTL for it. This does not happen for inline functions. */ 10198 return_used_this_function = 0; 10199 } 10200 else 10201 { 10202 /* We need to take into account any stack-frame rounding. */ 10203 offsets = arm_get_frame_offsets (); 10204 10205 gcc_assert (!use_return_insn (FALSE, NULL) 10206 || !return_used_this_function 10207 || offsets->saved_regs == offsets->outgoing_args 10208 || frame_pointer_needed); 10209 10210 /* Reset the ARM-specific per-function variables. */ 10211 after_arm_reorg = 0; 10212 } 10213} 10214 10215/* Generate and emit an insn that we will recognize as a push_multi. 10216 Unfortunately, since this insn does not reflect very well the actual 10217 semantics of the operation, we need to annotate the insn for the benefit 10218 of DWARF2 frame unwind information. */ 10219static rtx 10220emit_multi_reg_push (unsigned long mask) 10221{ 10222 int num_regs = 0; 10223 int num_dwarf_regs; 10224 int i, j; 10225 rtx par; 10226 rtx dwarf; 10227 int dwarf_par_index; 10228 rtx tmp, reg; 10229 10230 for (i = 0; i <= LAST_ARM_REGNUM; i++) 10231 if (mask & (1 << i)) 10232 num_regs++; 10233 10234 gcc_assert (num_regs && num_regs <= 16); 10235 10236 /* We don't record the PC in the dwarf frame information. */ 10237 num_dwarf_regs = num_regs; 10238 if (mask & (1 << PC_REGNUM)) 10239 num_dwarf_regs--; 10240 10241 /* For the body of the insn we are going to generate an UNSPEC in 10242 parallel with several USEs. This allows the insn to be recognized 10243 by the push_multi pattern in the arm.md file. The insn looks 10244 something like this: 10245 10246 (parallel [ 10247 (set (mem:BLK (pre_dec:BLK (reg:SI sp))) 10248 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) 10249 (use (reg:SI 11 fp)) 10250 (use (reg:SI 12 ip)) 10251 (use (reg:SI 14 lr)) 10252 (use (reg:SI 15 pc)) 10253 ]) 10254 10255 For the frame note however, we try to be more explicit and actually 10256 show each register being stored into the stack frame, plus a (single) 10257 decrement of the stack pointer. We do it this way in order to be 10258 friendly to the stack unwinding code, which only wants to see a single 10259 stack decrement per instruction. The RTL we generate for the note looks 10260 something like this: 10261 10262 (sequence [ 10263 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) 10264 (set (mem:SI (reg:SI sp)) (reg:SI r4)) 10265 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) 10266 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip)) 10267 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr)) 10268 ]) 10269 10270 This sequence is used both by the code to support stack unwinding for 10271 exceptions handlers and the code to generate dwarf2 frame debugging. */ 10272 10273 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); 10274 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); 10275 dwarf_par_index = 1; 10276 10277 for (i = 0; i <= LAST_ARM_REGNUM; i++) 10278 { 10279 if (mask & (1 << i)) 10280 { 10281 reg = gen_rtx_REG (SImode, i); 10282 10283 XVECEXP (par, 0, 0) 10284 = gen_rtx_SET (VOIDmode, 10285 gen_frame_mem (BLKmode, 10286 gen_rtx_PRE_DEC (BLKmode, 10287 stack_pointer_rtx)), 10288 gen_rtx_UNSPEC (BLKmode, 10289 gen_rtvec (1, reg), 10290 UNSPEC_PUSH_MULT)); 10291 10292 if (i != PC_REGNUM) 10293 { 10294 tmp = gen_rtx_SET (VOIDmode, 10295 gen_frame_mem (SImode, stack_pointer_rtx), 10296 reg); 10297 RTX_FRAME_RELATED_P (tmp) = 1; 10298 XVECEXP (dwarf, 0, dwarf_par_index) = tmp; 10299 dwarf_par_index++; 10300 } 10301 10302 break; 10303 } 10304 } 10305 10306 for (j = 1, i++; j < num_regs; i++) 10307 { 10308 if (mask & (1 << i)) 10309 { 10310 reg = gen_rtx_REG (SImode, i); 10311 10312 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); 10313 10314 if (i != PC_REGNUM) 10315 { 10316 tmp 10317 = gen_rtx_SET (VOIDmode, 10318 gen_frame_mem (SImode, 10319 plus_constant (stack_pointer_rtx, 10320 4 * j)), 10321 reg); 10322 RTX_FRAME_RELATED_P (tmp) = 1; 10323 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; 10324 } 10325 10326 j++; 10327 } 10328 } 10329 10330 par = emit_insn (par); 10331 10332 tmp = gen_rtx_SET (VOIDmode, 10333 stack_pointer_rtx, 10334 plus_constant (stack_pointer_rtx, -4 * num_regs)); 10335 RTX_FRAME_RELATED_P (tmp) = 1; 10336 XVECEXP (dwarf, 0, 0) = tmp; 10337 10338 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, 10339 REG_NOTES (par)); 10340 return par; 10341} 10342 10343/* Calculate the size of the return value that is passed in registers. */ 10344static int 10345arm_size_return_regs (void) 10346{ 10347 enum machine_mode mode; 10348 10349 if (current_function_return_rtx != 0) 10350 mode = GET_MODE (current_function_return_rtx); 10351 else 10352 mode = DECL_MODE (DECL_RESULT (current_function_decl)); 10353 10354 return GET_MODE_SIZE (mode); 10355} 10356 10357static rtx 10358emit_sfm (int base_reg, int count) 10359{ 10360 rtx par; 10361 rtx dwarf; 10362 rtx tmp, reg; 10363 int i; 10364 10365 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 10366 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (count + 1)); 10367 10368 reg = gen_rtx_REG (XFmode, base_reg++); 10369 10370 XVECEXP (par, 0, 0) 10371 = gen_rtx_SET (VOIDmode, 10372 gen_frame_mem (BLKmode, 10373 gen_rtx_PRE_DEC (BLKmode, 10374 stack_pointer_rtx)), 10375 gen_rtx_UNSPEC (BLKmode, 10376 gen_rtvec (1, reg), 10377 UNSPEC_PUSH_MULT)); 10378 tmp = gen_rtx_SET (VOIDmode, 10379 gen_frame_mem (XFmode, stack_pointer_rtx), reg); 10380 RTX_FRAME_RELATED_P (tmp) = 1; 10381 XVECEXP (dwarf, 0, 1) = tmp; 10382 10383 for (i = 1; i < count; i++) 10384 { 10385 reg = gen_rtx_REG (XFmode, base_reg++); 10386 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); 10387 10388 tmp = gen_rtx_SET (VOIDmode, 10389 gen_frame_mem (XFmode, 10390 plus_constant (stack_pointer_rtx, 10391 i * 12)), 10392 reg); 10393 RTX_FRAME_RELATED_P (tmp) = 1; 10394 XVECEXP (dwarf, 0, i + 1) = tmp; 10395 } 10396 10397 tmp = gen_rtx_SET (VOIDmode, 10398 stack_pointer_rtx, 10399 plus_constant (stack_pointer_rtx, -12 * count)); 10400 10401 RTX_FRAME_RELATED_P (tmp) = 1; 10402 XVECEXP (dwarf, 0, 0) = tmp; 10403 10404 par = emit_insn (par); 10405 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, 10406 REG_NOTES (par)); 10407 return par; 10408} 10409 10410 10411/* Return true if the current function needs to save/restore LR. */ 10412 10413static bool 10414thumb_force_lr_save (void) 10415{ 10416 return !cfun->machine->lr_save_eliminated 10417 && (!leaf_function_p () 10418 || thumb_far_jump_used_p () 10419 || regs_ever_live [LR_REGNUM]); 10420} 10421 10422 10423/* Compute the distance from register FROM to register TO. 10424 These can be the arg pointer (26), the soft frame pointer (25), 10425 the stack pointer (13) or the hard frame pointer (11). 10426 In thumb mode r7 is used as the soft frame pointer, if needed. 10427 Typical stack layout looks like this: 10428 10429 old stack pointer -> | | 10430 ---- 10431 | | \ 10432 | | saved arguments for 10433 | | vararg functions 10434 | | / 10435 -- 10436 hard FP & arg pointer -> | | \ 10437 | | stack 10438 | | frame 10439 | | / 10440 -- 10441 | | \ 10442 | | call saved 10443 | | registers 10444 soft frame pointer -> | | / 10445 -- 10446 | | \ 10447 | | local 10448 | | variables 10449 locals base pointer -> | | / 10450 -- 10451 | | \ 10452 | | outgoing 10453 | | arguments 10454 current stack pointer -> | | / 10455 -- 10456 10457 For a given function some or all of these stack components 10458 may not be needed, giving rise to the possibility of 10459 eliminating some of the registers. 10460 10461 The values returned by this function must reflect the behavior 10462 of arm_expand_prologue() and arm_compute_save_reg_mask(). 10463 10464 The sign of the number returned reflects the direction of stack 10465 growth, so the values are positive for all eliminations except 10466 from the soft frame pointer to the hard frame pointer. 10467 10468 SFP may point just inside the local variables block to ensure correct 10469 alignment. */ 10470 10471 10472/* Calculate stack offsets. These are used to calculate register elimination 10473 offsets and in prologue/epilogue code. */ 10474 10475static arm_stack_offsets * 10476arm_get_frame_offsets (void) 10477{ 10478 struct arm_stack_offsets *offsets; 10479 unsigned long func_type; 10480 int leaf; 10481 int saved; 10482 HOST_WIDE_INT frame_size; 10483 10484 offsets = &cfun->machine->stack_offsets; 10485 10486 /* We need to know if we are a leaf function. Unfortunately, it 10487 is possible to be called after start_sequence has been called, 10488 which causes get_insns to return the insns for the sequence, 10489 not the function, which will cause leaf_function_p to return 10490 the incorrect result. 10491 10492 to know about leaf functions once reload has completed, and the 10493 frame size cannot be changed after that time, so we can safely 10494 use the cached value. */ 10495 10496 if (reload_completed) 10497 return offsets; 10498 10499 /* Initially this is the size of the local variables. It will translated 10500 into an offset once we have determined the size of preceding data. */ 10501 frame_size = ROUND_UP_WORD (get_frame_size ()); 10502 10503 leaf = leaf_function_p (); 10504 10505 /* Space for variadic functions. */ 10506 offsets->saved_args = current_function_pretend_args_size; 10507 10508 offsets->frame = offsets->saved_args + (frame_pointer_needed ? 4 : 0); 10509 10510 if (TARGET_ARM) 10511 { 10512 unsigned int regno; 10513 10514 saved = bit_count (arm_compute_save_reg_mask ()) * 4; 10515 10516 /* We know that SP will be doubleword aligned on entry, and we must 10517 preserve that condition at any subroutine call. We also require the 10518 soft frame pointer to be doubleword aligned. */ 10519 10520 if (TARGET_REALLY_IWMMXT) 10521 { 10522 /* Check for the call-saved iWMMXt registers. */ 10523 for (regno = FIRST_IWMMXT_REGNUM; 10524 regno <= LAST_IWMMXT_REGNUM; 10525 regno++) 10526 if (regs_ever_live [regno] && ! call_used_regs [regno]) 10527 saved += 8; 10528 } 10529 10530 func_type = arm_current_func_type (); 10531 if (! IS_VOLATILE (func_type)) 10532 { 10533 /* Space for saved FPA registers. */ 10534 for (regno = FIRST_FPA_REGNUM; regno <= LAST_FPA_REGNUM; regno++) 10535 if (regs_ever_live[regno] && ! call_used_regs[regno]) 10536 saved += 12; 10537 10538 /* Space for saved VFP registers. */ 10539 if (TARGET_HARD_FLOAT && TARGET_VFP) 10540 saved += arm_get_vfp_saved_size (); 10541 } 10542 } 10543 else /* TARGET_THUMB */ 10544 { 10545 saved = bit_count (thumb_compute_save_reg_mask ()) * 4; 10546 if (TARGET_BACKTRACE) 10547 saved += 16; 10548 } 10549 10550 /* Saved registers include the stack frame. */ 10551 offsets->saved_regs = offsets->saved_args + saved; 10552 offsets->soft_frame = offsets->saved_regs + CALLER_INTERWORKING_SLOT_SIZE; 10553 /* A leaf function does not need any stack alignment if it has nothing 10554 on the stack. */ 10555 if (leaf && frame_size == 0) 10556 { 10557 offsets->outgoing_args = offsets->soft_frame; 10558 return offsets; 10559 } 10560 10561 /* Ensure SFP has the correct alignment. */ 10562 if (ARM_DOUBLEWORD_ALIGN 10563 && (offsets->soft_frame & 7)) 10564 offsets->soft_frame += 4; 10565 10566 offsets->locals_base = offsets->soft_frame + frame_size; 10567 offsets->outgoing_args = (offsets->locals_base 10568 + current_function_outgoing_args_size); 10569 10570 if (ARM_DOUBLEWORD_ALIGN) 10571 { 10572 /* Ensure SP remains doubleword aligned. */ 10573 if (offsets->outgoing_args & 7) 10574 offsets->outgoing_args += 4; 10575 gcc_assert (!(offsets->outgoing_args & 7)); 10576 } 10577 10578 return offsets; 10579} 10580 10581 10582/* Calculate the relative offsets for the different stack pointers. Positive 10583 offsets are in the direction of stack growth. */ 10584 10585HOST_WIDE_INT 10586arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) 10587{ 10588 arm_stack_offsets *offsets; 10589 10590 offsets = arm_get_frame_offsets (); 10591 10592 /* OK, now we have enough information to compute the distances. 10593 There must be an entry in these switch tables for each pair 10594 of registers in ELIMINABLE_REGS, even if some of the entries 10595 seem to be redundant or useless. */ 10596 switch (from) 10597 { 10598 case ARG_POINTER_REGNUM: 10599 switch (to) 10600 { 10601 case THUMB_HARD_FRAME_POINTER_REGNUM: 10602 return 0; 10603 10604 case FRAME_POINTER_REGNUM: 10605 /* This is the reverse of the soft frame pointer 10606 to hard frame pointer elimination below. */ 10607 return offsets->soft_frame - offsets->saved_args; 10608 10609 case ARM_HARD_FRAME_POINTER_REGNUM: 10610 /* If there is no stack frame then the hard 10611 frame pointer and the arg pointer coincide. */ 10612 if (offsets->frame == offsets->saved_regs) 10613 return 0; 10614 /* FIXME: Not sure about this. Maybe we should always return 0 ? */ 10615 return (frame_pointer_needed 10616 && cfun->static_chain_decl != NULL 10617 && ! cfun->machine->uses_anonymous_args) ? 4 : 0; 10618 10619 case STACK_POINTER_REGNUM: 10620 /* If nothing has been pushed on the stack at all 10621 then this will return -4. This *is* correct! */ 10622 return offsets->outgoing_args - (offsets->saved_args + 4); 10623 10624 default: 10625 gcc_unreachable (); 10626 } 10627 gcc_unreachable (); 10628 10629 case FRAME_POINTER_REGNUM: 10630 switch (to) 10631 { 10632 case THUMB_HARD_FRAME_POINTER_REGNUM: 10633 return 0; 10634 10635 case ARM_HARD_FRAME_POINTER_REGNUM: 10636 /* The hard frame pointer points to the top entry in the 10637 stack frame. The soft frame pointer to the bottom entry 10638 in the stack frame. If there is no stack frame at all, 10639 then they are identical. */ 10640 10641 return offsets->frame - offsets->soft_frame; 10642 10643 case STACK_POINTER_REGNUM: 10644 return offsets->outgoing_args - offsets->soft_frame; 10645 10646 default: 10647 gcc_unreachable (); 10648 } 10649 gcc_unreachable (); 10650 10651 default: 10652 /* You cannot eliminate from the stack pointer. 10653 In theory you could eliminate from the hard frame 10654 pointer to the stack pointer, but this will never 10655 happen, since if a stack frame is not needed the 10656 hard frame pointer will never be used. */ 10657 gcc_unreachable (); 10658 } 10659} 10660 10661 10662/* Generate the prologue instructions for entry into an ARM function. */ 10663void 10664arm_expand_prologue (void) 10665{ 10666 int reg; 10667 rtx amount; 10668 rtx insn; 10669 rtx ip_rtx; 10670 unsigned long live_regs_mask; 10671 unsigned long func_type; 10672 int fp_offset = 0; 10673 int saved_pretend_args = 0; 10674 int saved_regs = 0; 10675 unsigned HOST_WIDE_INT args_to_push; 10676 arm_stack_offsets *offsets; 10677 10678 func_type = arm_current_func_type (); 10679 10680 /* Naked functions don't have prologues. */ 10681 if (IS_NAKED (func_type)) 10682 return; 10683 10684 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ 10685 args_to_push = current_function_pretend_args_size; 10686 10687 /* Compute which register we will have to save onto the stack. */ 10688 live_regs_mask = arm_compute_save_reg_mask (); 10689 10690 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); 10691 10692 if (frame_pointer_needed) 10693 { 10694 if (IS_INTERRUPT (func_type)) 10695 { 10696 /* Interrupt functions must not corrupt any registers. 10697 Creating a frame pointer however, corrupts the IP 10698 register, so we must push it first. */ 10699 insn = emit_multi_reg_push (1 << IP_REGNUM); 10700 10701 /* Do not set RTX_FRAME_RELATED_P on this insn. 10702 The dwarf stack unwinding code only wants to see one 10703 stack decrement per function, and this is not it. If 10704 this instruction is labeled as being part of the frame 10705 creation sequence then dwarf2out_frame_debug_expr will 10706 die when it encounters the assignment of IP to FP 10707 later on, since the use of SP here establishes SP as 10708 the CFA register and not IP. 10709 10710 Anyway this instruction is not really part of the stack 10711 frame creation although it is part of the prologue. */ 10712 } 10713 else if (IS_NESTED (func_type)) 10714 { 10715 /* The Static chain register is the same as the IP register 10716 used as a scratch register during stack frame creation. 10717 To get around this need to find somewhere to store IP 10718 whilst the frame is being created. We try the following 10719 places in order: 10720 10721 1. The last argument register. 10722 2. A slot on the stack above the frame. (This only 10723 works if the function is not a varargs function). 10724 3. Register r3, after pushing the argument registers 10725 onto the stack. 10726 10727 Note - we only need to tell the dwarf2 backend about the SP 10728 adjustment in the second variant; the static chain register 10729 doesn't need to be unwound, as it doesn't contain a value 10730 inherited from the caller. */ 10731 10732 if (regs_ever_live[3] == 0) 10733 insn = emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); 10734 else if (args_to_push == 0) 10735 { 10736 rtx dwarf; 10737 10738 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); 10739 insn = emit_set_insn (gen_frame_mem (SImode, insn), ip_rtx); 10740 fp_offset = 4; 10741 10742 /* Just tell the dwarf backend that we adjusted SP. */ 10743 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, 10744 plus_constant (stack_pointer_rtx, 10745 -fp_offset)); 10746 RTX_FRAME_RELATED_P (insn) = 1; 10747 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 10748 dwarf, REG_NOTES (insn)); 10749 } 10750 else 10751 { 10752 /* Store the args on the stack. */ 10753 if (cfun->machine->uses_anonymous_args) 10754 insn = emit_multi_reg_push 10755 ((0xf0 >> (args_to_push / 4)) & 0xf); 10756 else 10757 insn = emit_insn 10758 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 10759 GEN_INT (- args_to_push))); 10760 10761 RTX_FRAME_RELATED_P (insn) = 1; 10762 10763 saved_pretend_args = 1; 10764 fp_offset = args_to_push; 10765 args_to_push = 0; 10766 10767 /* Now reuse r3 to preserve IP. */ 10768 emit_set_insn (gen_rtx_REG (SImode, 3), ip_rtx); 10769 } 10770 } 10771 10772 insn = emit_set_insn (ip_rtx, 10773 plus_constant (stack_pointer_rtx, fp_offset)); 10774 RTX_FRAME_RELATED_P (insn) = 1; 10775 } 10776 10777 if (args_to_push) 10778 { 10779 /* Push the argument registers, or reserve space for them. */ 10780 if (cfun->machine->uses_anonymous_args) 10781 insn = emit_multi_reg_push 10782 ((0xf0 >> (args_to_push / 4)) & 0xf); 10783 else 10784 insn = emit_insn 10785 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 10786 GEN_INT (- args_to_push))); 10787 RTX_FRAME_RELATED_P (insn) = 1; 10788 } 10789 10790 /* If this is an interrupt service routine, and the link register 10791 is going to be pushed, and we are not creating a stack frame, 10792 (which would involve an extra push of IP and a pop in the epilogue) 10793 subtracting four from LR now will mean that the function return 10794 can be done with a single instruction. */ 10795 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) 10796 && (live_regs_mask & (1 << LR_REGNUM)) != 0 10797 && ! frame_pointer_needed) 10798 { 10799 rtx lr = gen_rtx_REG (SImode, LR_REGNUM); 10800 10801 emit_set_insn (lr, plus_constant (lr, -4)); 10802 } 10803 10804 if (live_regs_mask) 10805 { 10806 insn = emit_multi_reg_push (live_regs_mask); 10807 saved_regs += bit_count (live_regs_mask) * 4; 10808 RTX_FRAME_RELATED_P (insn) = 1; 10809 } 10810 10811 if (TARGET_IWMMXT) 10812 for (reg = LAST_IWMMXT_REGNUM; reg >= FIRST_IWMMXT_REGNUM; reg--) 10813 if (regs_ever_live[reg] && ! call_used_regs [reg]) 10814 { 10815 insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx); 10816 insn = gen_frame_mem (V2SImode, insn); 10817 insn = emit_set_insn (insn, gen_rtx_REG (V2SImode, reg)); 10818 RTX_FRAME_RELATED_P (insn) = 1; 10819 saved_regs += 8; 10820 } 10821 10822 if (! IS_VOLATILE (func_type)) 10823 { 10824 int start_reg; 10825 10826 /* Save any floating point call-saved registers used by this 10827 function. */ 10828 if (arm_fpu_arch == FPUTYPE_FPA_EMU2) 10829 { 10830 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) 10831 if (regs_ever_live[reg] && !call_used_regs[reg]) 10832 { 10833 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); 10834 insn = gen_frame_mem (XFmode, insn); 10835 insn = emit_set_insn (insn, gen_rtx_REG (XFmode, reg)); 10836 RTX_FRAME_RELATED_P (insn) = 1; 10837 saved_regs += 12; 10838 } 10839 } 10840 else 10841 { 10842 start_reg = LAST_FPA_REGNUM; 10843 10844 for (reg = LAST_FPA_REGNUM; reg >= FIRST_FPA_REGNUM; reg--) 10845 { 10846 if (regs_ever_live[reg] && !call_used_regs[reg]) 10847 { 10848 if (start_reg - reg == 3) 10849 { 10850 insn = emit_sfm (reg, 4); 10851 RTX_FRAME_RELATED_P (insn) = 1; 10852 saved_regs += 48; 10853 start_reg = reg - 1; 10854 } 10855 } 10856 else 10857 { 10858 if (start_reg != reg) 10859 { 10860 insn = emit_sfm (reg + 1, start_reg - reg); 10861 RTX_FRAME_RELATED_P (insn) = 1; 10862 saved_regs += (start_reg - reg) * 12; 10863 } 10864 start_reg = reg - 1; 10865 } 10866 } 10867 10868 if (start_reg != reg) 10869 { 10870 insn = emit_sfm (reg + 1, start_reg - reg); 10871 saved_regs += (start_reg - reg) * 12; 10872 RTX_FRAME_RELATED_P (insn) = 1; 10873 } 10874 } 10875 if (TARGET_HARD_FLOAT && TARGET_VFP) 10876 { 10877 start_reg = FIRST_VFP_REGNUM; 10878 10879 for (reg = FIRST_VFP_REGNUM; reg < LAST_VFP_REGNUM; reg += 2) 10880 { 10881 if ((!regs_ever_live[reg] || call_used_regs[reg]) 10882 && (!regs_ever_live[reg + 1] || call_used_regs[reg + 1])) 10883 { 10884 if (start_reg != reg) 10885 saved_regs += vfp_emit_fstmx (start_reg, 10886 (reg - start_reg) / 2); 10887 start_reg = reg + 2; 10888 } 10889 } 10890 if (start_reg != reg) 10891 saved_regs += vfp_emit_fstmx (start_reg, 10892 (reg - start_reg) / 2); 10893 } 10894 } 10895 10896 if (frame_pointer_needed) 10897 { 10898 /* Create the new frame pointer. */ 10899 insn = GEN_INT (-(4 + args_to_push + fp_offset)); 10900 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); 10901 RTX_FRAME_RELATED_P (insn) = 1; 10902 10903 if (IS_NESTED (func_type)) 10904 { 10905 /* Recover the static chain register. */ 10906 if (regs_ever_live [3] == 0 10907 || saved_pretend_args) 10908 insn = gen_rtx_REG (SImode, 3); 10909 else /* if (current_function_pretend_args_size == 0) */ 10910 { 10911 insn = plus_constant (hard_frame_pointer_rtx, 4); 10912 insn = gen_frame_mem (SImode, insn); 10913 } 10914 10915 emit_set_insn (ip_rtx, insn); 10916 /* Add a USE to stop propagate_one_insn() from barfing. */ 10917 emit_insn (gen_prologue_use (ip_rtx)); 10918 } 10919 } 10920 10921 offsets = arm_get_frame_offsets (); 10922 if (offsets->outgoing_args != offsets->saved_args + saved_regs) 10923 { 10924 /* This add can produce multiple insns for a large constant, so we 10925 need to get tricky. */ 10926 rtx last = get_last_insn (); 10927 10928 amount = GEN_INT (offsets->saved_args + saved_regs 10929 - offsets->outgoing_args); 10930 10931 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 10932 amount)); 10933 do 10934 { 10935 last = last ? NEXT_INSN (last) : get_insns (); 10936 RTX_FRAME_RELATED_P (last) = 1; 10937 } 10938 while (last != insn); 10939 10940 /* If the frame pointer is needed, emit a special barrier that 10941 will prevent the scheduler from moving stores to the frame 10942 before the stack adjustment. */ 10943 if (frame_pointer_needed) 10944 insn = emit_insn (gen_stack_tie (stack_pointer_rtx, 10945 hard_frame_pointer_rtx)); 10946 } 10947 10948 10949 if (flag_pic && arm_pic_register != INVALID_REGNUM) 10950 arm_load_pic_register (0UL); 10951 10952 /* If we are profiling, make sure no instructions are scheduled before 10953 the call to mcount. Similarly if the user has requested no 10954 scheduling in the prolog. Similarly if we want non-call exceptions 10955 using the EABI unwinder, to prevent faulting instructions from being 10956 swapped with a stack adjustment. */ 10957 if (current_function_profile || !TARGET_SCHED_PROLOG 10958 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) 10959 emit_insn (gen_blockage ()); 10960 10961 /* If the link register is being kept alive, with the return address in it, 10962 then make sure that it does not get reused by the ce2 pass. */ 10963 if ((live_regs_mask & (1 << LR_REGNUM)) == 0) 10964 { 10965 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM))); 10966 cfun->machine->lr_save_eliminated = 1; 10967 } 10968} 10969 10970/* If CODE is 'd', then the X is a condition operand and the instruction 10971 should only be executed if the condition is true. 10972 if CODE is 'D', then the X is a condition operand and the instruction 10973 should only be executed if the condition is false: however, if the mode 10974 of the comparison is CCFPEmode, then always execute the instruction -- we 10975 do this because in these circumstances !GE does not necessarily imply LT; 10976 in these cases the instruction pattern will take care to make sure that 10977 an instruction containing %d will follow, thereby undoing the effects of 10978 doing this instruction unconditionally. 10979 If CODE is 'N' then X is a floating point operand that must be negated 10980 before output. 10981 If CODE is 'B' then output a bitwise inverted value of X (a const int). 10982 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ 10983void 10984arm_print_operand (FILE *stream, rtx x, int code) 10985{ 10986 switch (code) 10987 { 10988 case '@': 10989 fputs (ASM_COMMENT_START, stream); 10990 return; 10991 10992 case '_': 10993 fputs (user_label_prefix, stream); 10994 return; 10995 10996 case '|': 10997 fputs (REGISTER_PREFIX, stream); 10998 return; 10999 11000 case '?': 11001 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) 11002 { 11003 if (TARGET_THUMB) 11004 { 11005 output_operand_lossage ("predicated Thumb instruction"); 11006 break; 11007 } 11008 if (current_insn_predicate != NULL) 11009 { 11010 output_operand_lossage 11011 ("predicated instruction in conditional sequence"); 11012 break; 11013 } 11014 11015 fputs (arm_condition_codes[arm_current_cc], stream); 11016 } 11017 else if (current_insn_predicate) 11018 { 11019 enum arm_cond_code code; 11020 11021 if (TARGET_THUMB) 11022 { 11023 output_operand_lossage ("predicated Thumb instruction"); 11024 break; 11025 } 11026 11027 code = get_arm_condition_code (current_insn_predicate); 11028 fputs (arm_condition_codes[code], stream); 11029 } 11030 return; 11031 11032 case 'N': 11033 { 11034 REAL_VALUE_TYPE r; 11035 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 11036 r = REAL_VALUE_NEGATE (r); 11037 fprintf (stream, "%s", fp_const_from_val (&r)); 11038 } 11039 return; 11040 11041 case 'B': 11042 if (GET_CODE (x) == CONST_INT) 11043 { 11044 HOST_WIDE_INT val; 11045 val = ARM_SIGN_EXTEND (~INTVAL (x)); 11046 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); 11047 } 11048 else 11049 { 11050 putc ('~', stream); 11051 output_addr_const (stream, x); 11052 } 11053 return; 11054 11055 case 'i': 11056 fprintf (stream, "%s", arithmetic_instr (x, 1)); 11057 return; 11058 11059 /* Truncate Cirrus shift counts. */ 11060 case 's': 11061 if (GET_CODE (x) == CONST_INT) 11062 { 11063 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); 11064 return; 11065 } 11066 arm_print_operand (stream, x, 0); 11067 return; 11068 11069 case 'I': 11070 fprintf (stream, "%s", arithmetic_instr (x, 0)); 11071 return; 11072 11073 case 'S': 11074 { 11075 HOST_WIDE_INT val; 11076 const char *shift; 11077 11078 if (!shift_operator (x, SImode)) 11079 { 11080 output_operand_lossage ("invalid shift operand"); 11081 break; 11082 } 11083 11084 shift = shift_op (x, &val); 11085 11086 if (shift) 11087 { 11088 fprintf (stream, ", %s ", shift); 11089 if (val == -1) 11090 arm_print_operand (stream, XEXP (x, 1), 0); 11091 else 11092 fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); 11093 } 11094 } 11095 return; 11096 11097 /* An explanation of the 'Q', 'R' and 'H' register operands: 11098 11099 In a pair of registers containing a DI or DF value the 'Q' 11100 operand returns the register number of the register containing 11101 the least significant part of the value. The 'R' operand returns 11102 the register number of the register containing the most 11103 significant part of the value. 11104 11105 The 'H' operand returns the higher of the two register numbers. 11106 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the 11107 same as the 'Q' operand, since the most significant part of the 11108 value is held in the lower number register. The reverse is true 11109 on systems where WORDS_BIG_ENDIAN is false. 11110 11111 The purpose of these operands is to distinguish between cases 11112 where the endian-ness of the values is important (for example 11113 when they are added together), and cases where the endian-ness 11114 is irrelevant, but the order of register operations is important. 11115 For example when loading a value from memory into a register 11116 pair, the endian-ness does not matter. Provided that the value 11117 from the lower memory address is put into the lower numbered 11118 register, and the value from the higher address is put into the 11119 higher numbered register, the load will work regardless of whether 11120 the value being loaded is big-wordian or little-wordian. The 11121 order of the two register loads can matter however, if the address 11122 of the memory location is actually held in one of the registers 11123 being overwritten by the load. */ 11124 case 'Q': 11125 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) 11126 { 11127 output_operand_lossage ("invalid operand for code '%c'", code); 11128 return; 11129 } 11130 11131 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); 11132 return; 11133 11134 case 'R': 11135 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) 11136 { 11137 output_operand_lossage ("invalid operand for code '%c'", code); 11138 return; 11139 } 11140 11141 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); 11142 return; 11143 11144 case 'H': 11145 if (GET_CODE (x) != REG || REGNO (x) > LAST_ARM_REGNUM) 11146 { 11147 output_operand_lossage ("invalid operand for code '%c'", code); 11148 return; 11149 } 11150 11151 asm_fprintf (stream, "%r", REGNO (x) + 1); 11152 return; 11153 11154 case 'm': 11155 asm_fprintf (stream, "%r", 11156 GET_CODE (XEXP (x, 0)) == REG 11157 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); 11158 return; 11159 11160 case 'M': 11161 asm_fprintf (stream, "{%r-%r}", 11162 REGNO (x), 11163 REGNO (x) + ARM_NUM_REGS (GET_MODE (x)) - 1); 11164 return; 11165 11166 case 'd': 11167 /* CONST_TRUE_RTX means always -- that's the default. */ 11168 if (x == const_true_rtx) 11169 return; 11170 11171 if (!COMPARISON_P (x)) 11172 { 11173 output_operand_lossage ("invalid operand for code '%c'", code); 11174 return; 11175 } 11176 11177 fputs (arm_condition_codes[get_arm_condition_code (x)], 11178 stream); 11179 return; 11180 11181 case 'D': 11182 /* CONST_TRUE_RTX means not always -- i.e. never. We shouldn't ever 11183 want to do that. */ 11184 if (x == const_true_rtx) 11185 { 11186 output_operand_lossage ("instruction never exectued"); 11187 return; 11188 } 11189 if (!COMPARISON_P (x)) 11190 { 11191 output_operand_lossage ("invalid operand for code '%c'", code); 11192 return; 11193 } 11194 11195 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE 11196 (get_arm_condition_code (x))], 11197 stream); 11198 return; 11199 11200 /* Cirrus registers can be accessed in a variety of ways: 11201 single floating point (f) 11202 double floating point (d) 11203 32bit integer (fx) 11204 64bit integer (dx). */ 11205 case 'W': /* Cirrus register in F mode. */ 11206 case 'X': /* Cirrus register in D mode. */ 11207 case 'Y': /* Cirrus register in FX mode. */ 11208 case 'Z': /* Cirrus register in DX mode. */ 11209 gcc_assert (GET_CODE (x) == REG 11210 && REGNO_REG_CLASS (REGNO (x)) == CIRRUS_REGS); 11211 11212 fprintf (stream, "mv%s%s", 11213 code == 'W' ? "f" 11214 : code == 'X' ? "d" 11215 : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); 11216 11217 return; 11218 11219 /* Print cirrus register in the mode specified by the register's mode. */ 11220 case 'V': 11221 { 11222 int mode = GET_MODE (x); 11223 11224 if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) 11225 { 11226 output_operand_lossage ("invalid operand for code '%c'", code); 11227 return; 11228 } 11229 11230 fprintf (stream, "mv%s%s", 11231 mode == DFmode ? "d" 11232 : mode == SImode ? "fx" 11233 : mode == DImode ? "dx" 11234 : "f", reg_names[REGNO (x)] + 2); 11235 11236 return; 11237 } 11238 11239 case 'U': 11240 if (GET_CODE (x) != REG 11241 || REGNO (x) < FIRST_IWMMXT_GR_REGNUM 11242 || REGNO (x) > LAST_IWMMXT_GR_REGNUM) 11243 /* Bad value for wCG register number. */ 11244 { 11245 output_operand_lossage ("invalid operand for code '%c'", code); 11246 return; 11247 } 11248 11249 else 11250 fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); 11251 return; 11252 11253 /* Print an iWMMXt control register name. */ 11254 case 'w': 11255 if (GET_CODE (x) != CONST_INT 11256 || INTVAL (x) < 0 11257 || INTVAL (x) >= 16) 11258 /* Bad value for wC register number. */ 11259 { 11260 output_operand_lossage ("invalid operand for code '%c'", code); 11261 return; 11262 } 11263 11264 else 11265 { 11266 static const char * wc_reg_names [16] = 11267 { 11268 "wCID", "wCon", "wCSSF", "wCASF", 11269 "wC4", "wC5", "wC6", "wC7", 11270 "wCGR0", "wCGR1", "wCGR2", "wCGR3", 11271 "wC12", "wC13", "wC14", "wC15" 11272 }; 11273 11274 fprintf (stream, wc_reg_names [INTVAL (x)]); 11275 } 11276 return; 11277 11278 /* Print a VFP double precision register name. */ 11279 case 'P': 11280 { 11281 int mode = GET_MODE (x); 11282 int num; 11283 11284 if (mode != DImode && mode != DFmode) 11285 { 11286 output_operand_lossage ("invalid operand for code '%c'", code); 11287 return; 11288 } 11289 11290 if (GET_CODE (x) != REG 11291 || !IS_VFP_REGNUM (REGNO (x))) 11292 { 11293 output_operand_lossage ("invalid operand for code '%c'", code); 11294 return; 11295 } 11296 11297 num = REGNO(x) - FIRST_VFP_REGNUM; 11298 if (num & 1) 11299 { 11300 output_operand_lossage ("invalid operand for code '%c'", code); 11301 return; 11302 } 11303 11304 fprintf (stream, "d%d", num >> 1); 11305 } 11306 return; 11307 11308 default: 11309 if (x == 0) 11310 { 11311 output_operand_lossage ("missing operand"); 11312 return; 11313 } 11314 11315 switch (GET_CODE (x)) 11316 { 11317 case REG: 11318 asm_fprintf (stream, "%r", REGNO (x)); 11319 break; 11320 11321 case MEM: 11322 output_memory_reference_mode = GET_MODE (x); 11323 output_address (XEXP (x, 0)); 11324 break; 11325 11326 case CONST_DOUBLE: 11327 fprintf (stream, "#%s", fp_immediate_constant (x)); 11328 break; 11329 11330 default: 11331 gcc_assert (GET_CODE (x) != NEG); 11332 fputc ('#', stream); 11333 output_addr_const (stream, x); 11334 break; 11335 } 11336 } 11337} 11338 11339#ifndef AOF_ASSEMBLER 11340/* Target hook for assembling integer objects. The ARM version needs to 11341 handle word-sized values specially. */ 11342static bool 11343arm_assemble_integer (rtx x, unsigned int size, int aligned_p) 11344{ 11345 if (size == UNITS_PER_WORD && aligned_p) 11346 { 11347 fputs ("\t.word\t", asm_out_file); 11348 output_addr_const (asm_out_file, x); 11349 11350 /* Mark symbols as position independent. We only do this in the 11351 .text segment, not in the .data segment. */ 11352 if (NEED_GOT_RELOC && flag_pic && making_const_table && 11353 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) 11354 { 11355 if (GET_CODE (x) == SYMBOL_REF 11356 && (CONSTANT_POOL_ADDRESS_P (x) 11357 || SYMBOL_REF_LOCAL_P (x))) 11358 fputs ("(GOTOFF)", asm_out_file); 11359 else if (GET_CODE (x) == LABEL_REF) 11360 fputs ("(GOTOFF)", asm_out_file); 11361 else 11362 fputs ("(GOT)", asm_out_file); 11363 } 11364 fputc ('\n', asm_out_file); 11365 return true; 11366 } 11367 11368 if (arm_vector_mode_supported_p (GET_MODE (x))) 11369 { 11370 int i, units; 11371 11372 gcc_assert (GET_CODE (x) == CONST_VECTOR); 11373 11374 units = CONST_VECTOR_NUNITS (x); 11375 11376 switch (GET_MODE (x)) 11377 { 11378 case V2SImode: size = 4; break; 11379 case V4HImode: size = 2; break; 11380 case V8QImode: size = 1; break; 11381 default: 11382 gcc_unreachable (); 11383 } 11384 11385 for (i = 0; i < units; i++) 11386 { 11387 rtx elt; 11388 11389 elt = CONST_VECTOR_ELT (x, i); 11390 assemble_integer 11391 (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); 11392 } 11393 11394 return true; 11395 } 11396 11397 return default_assemble_integer (x, size, aligned_p); 11398} 11399 11400 11401/* Add a function to the list of static constructors. */ 11402 11403static void 11404arm_elf_asm_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) 11405{ 11406 if (!TARGET_AAPCS_BASED) 11407 { 11408 default_named_section_asm_out_constructor (symbol, priority); 11409 return; 11410 } 11411 11412 /* Put these in the .init_array section, using a special relocation. */ 11413 switch_to_section (ctors_section); 11414 assemble_align (POINTER_SIZE); 11415 fputs ("\t.word\t", asm_out_file); 11416 output_addr_const (asm_out_file, symbol); 11417 fputs ("(target1)\n", asm_out_file); 11418} 11419#endif 11420 11421/* A finite state machine takes care of noticing whether or not instructions 11422 can be conditionally executed, and thus decrease execution time and code 11423 size by deleting branch instructions. The fsm is controlled by 11424 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ 11425 11426/* The state of the fsm controlling condition codes are: 11427 0: normal, do nothing special 11428 1: make ASM_OUTPUT_OPCODE not output this instruction 11429 2: make ASM_OUTPUT_OPCODE not output this instruction 11430 3: make instructions conditional 11431 4: make instructions conditional 11432 11433 State transitions (state->state by whom under condition): 11434 0 -> 1 final_prescan_insn if the `target' is a label 11435 0 -> 2 final_prescan_insn if the `target' is an unconditional branch 11436 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch 11437 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch 11438 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached 11439 (the target label has CODE_LABEL_NUMBER equal to arm_target_label). 11440 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached 11441 (the target insn is arm_target_insn). 11442 11443 If the jump clobbers the conditions then we use states 2 and 4. 11444 11445 A similar thing can be done with conditional return insns. 11446 11447 XXX In case the `target' is an unconditional branch, this conditionalising 11448 of the instructions always reduces code size, but not always execution 11449 time. But then, I want to reduce the code size to somewhere near what 11450 /bin/cc produces. */ 11451 11452/* Returns the index of the ARM condition code string in 11453 `arm_condition_codes'. COMPARISON should be an rtx like 11454 `(eq (...) (...))'. */ 11455static enum arm_cond_code 11456get_arm_condition_code (rtx comparison) 11457{ 11458 enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); 11459 int code; 11460 enum rtx_code comp_code = GET_CODE (comparison); 11461 11462 if (GET_MODE_CLASS (mode) != MODE_CC) 11463 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), 11464 XEXP (comparison, 1)); 11465 11466 switch (mode) 11467 { 11468 case CC_DNEmode: code = ARM_NE; goto dominance; 11469 case CC_DEQmode: code = ARM_EQ; goto dominance; 11470 case CC_DGEmode: code = ARM_GE; goto dominance; 11471 case CC_DGTmode: code = ARM_GT; goto dominance; 11472 case CC_DLEmode: code = ARM_LE; goto dominance; 11473 case CC_DLTmode: code = ARM_LT; goto dominance; 11474 case CC_DGEUmode: code = ARM_CS; goto dominance; 11475 case CC_DGTUmode: code = ARM_HI; goto dominance; 11476 case CC_DLEUmode: code = ARM_LS; goto dominance; 11477 case CC_DLTUmode: code = ARM_CC; 11478 11479 dominance: 11480 gcc_assert (comp_code == EQ || comp_code == NE); 11481 11482 if (comp_code == EQ) 11483 return ARM_INVERSE_CONDITION_CODE (code); 11484 return code; 11485 11486 case CC_NOOVmode: 11487 switch (comp_code) 11488 { 11489 case NE: return ARM_NE; 11490 case EQ: return ARM_EQ; 11491 case GE: return ARM_PL; 11492 case LT: return ARM_MI; 11493 default: gcc_unreachable (); 11494 } 11495 11496 case CC_Zmode: 11497 switch (comp_code) 11498 { 11499 case NE: return ARM_NE; 11500 case EQ: return ARM_EQ; 11501 default: gcc_unreachable (); 11502 } 11503 11504 case CC_Nmode: 11505 switch (comp_code) 11506 { 11507 case NE: return ARM_MI; 11508 case EQ: return ARM_PL; 11509 default: gcc_unreachable (); 11510 } 11511 11512 case CCFPEmode: 11513 case CCFPmode: 11514 /* These encodings assume that AC=1 in the FPA system control 11515 byte. This allows us to handle all cases except UNEQ and 11516 LTGT. */ 11517 switch (comp_code) 11518 { 11519 case GE: return ARM_GE; 11520 case GT: return ARM_GT; 11521 case LE: return ARM_LS; 11522 case LT: return ARM_MI; 11523 case NE: return ARM_NE; 11524 case EQ: return ARM_EQ; 11525 case ORDERED: return ARM_VC; 11526 case UNORDERED: return ARM_VS; 11527 case UNLT: return ARM_LT; 11528 case UNLE: return ARM_LE; 11529 case UNGT: return ARM_HI; 11530 case UNGE: return ARM_PL; 11531 /* UNEQ and LTGT do not have a representation. */ 11532 case UNEQ: /* Fall through. */ 11533 case LTGT: /* Fall through. */ 11534 default: gcc_unreachable (); 11535 } 11536 11537 case CC_SWPmode: 11538 switch (comp_code) 11539 { 11540 case NE: return ARM_NE; 11541 case EQ: return ARM_EQ; 11542 case GE: return ARM_LE; 11543 case GT: return ARM_LT; 11544 case LE: return ARM_GE; 11545 case LT: return ARM_GT; 11546 case GEU: return ARM_LS; 11547 case GTU: return ARM_CC; 11548 case LEU: return ARM_CS; 11549 case LTU: return ARM_HI; 11550 default: gcc_unreachable (); 11551 } 11552 11553 case CC_Cmode: 11554 switch (comp_code) 11555 { 11556 case LTU: return ARM_CS; 11557 case GEU: return ARM_CC; 11558 default: gcc_unreachable (); 11559 } 11560 11561 case CCmode: 11562 switch (comp_code) 11563 { 11564 case NE: return ARM_NE; 11565 case EQ: return ARM_EQ; 11566 case GE: return ARM_GE; 11567 case GT: return ARM_GT; 11568 case LE: return ARM_LE; 11569 case LT: return ARM_LT; 11570 case GEU: return ARM_CS; 11571 case GTU: return ARM_HI; 11572 case LEU: return ARM_LS; 11573 case LTU: return ARM_CC; 11574 default: gcc_unreachable (); 11575 } 11576 11577 default: gcc_unreachable (); 11578 } 11579} 11580 11581void 11582arm_final_prescan_insn (rtx insn) 11583{ 11584 /* BODY will hold the body of INSN. */ 11585 rtx body = PATTERN (insn); 11586 11587 /* This will be 1 if trying to repeat the trick, and things need to be 11588 reversed if it appears to fail. */ 11589 int reverse = 0; 11590 11591 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is 11592 taken are clobbered, even if the rtl suggests otherwise. It also 11593 means that we have to grub around within the jump expression to find 11594 out what the conditions are when the jump isn't taken. */ 11595 int jump_clobbers = 0; 11596 11597 /* If we start with a return insn, we only succeed if we find another one. */ 11598 int seeking_return = 0; 11599 11600 /* START_INSN will hold the insn from where we start looking. This is the 11601 first insn after the following code_label if REVERSE is true. */ 11602 rtx start_insn = insn; 11603 11604 /* If in state 4, check if the target branch is reached, in order to 11605 change back to state 0. */ 11606 if (arm_ccfsm_state == 4) 11607 { 11608 if (insn == arm_target_insn) 11609 { 11610 arm_target_insn = NULL; 11611 arm_ccfsm_state = 0; 11612 } 11613 return; 11614 } 11615 11616 /* If in state 3, it is possible to repeat the trick, if this insn is an 11617 unconditional branch to a label, and immediately following this branch 11618 is the previous target label which is only used once, and the label this 11619 branch jumps to is not too far off. */ 11620 if (arm_ccfsm_state == 3) 11621 { 11622 if (simplejump_p (insn)) 11623 { 11624 start_insn = next_nonnote_insn (start_insn); 11625 if (GET_CODE (start_insn) == BARRIER) 11626 { 11627 /* XXX Isn't this always a barrier? */ 11628 start_insn = next_nonnote_insn (start_insn); 11629 } 11630 if (GET_CODE (start_insn) == CODE_LABEL 11631 && CODE_LABEL_NUMBER (start_insn) == arm_target_label 11632 && LABEL_NUSES (start_insn) == 1) 11633 reverse = TRUE; 11634 else 11635 return; 11636 } 11637 else if (GET_CODE (body) == RETURN) 11638 { 11639 start_insn = next_nonnote_insn (start_insn); 11640 if (GET_CODE (start_insn) == BARRIER) 11641 start_insn = next_nonnote_insn (start_insn); 11642 if (GET_CODE (start_insn) == CODE_LABEL 11643 && CODE_LABEL_NUMBER (start_insn) == arm_target_label 11644 && LABEL_NUSES (start_insn) == 1) 11645 { 11646 reverse = TRUE; 11647 seeking_return = 1; 11648 } 11649 else 11650 return; 11651 } 11652 else 11653 return; 11654 } 11655 11656 gcc_assert (!arm_ccfsm_state || reverse); 11657 if (GET_CODE (insn) != JUMP_INSN) 11658 return; 11659 11660 /* This jump might be paralleled with a clobber of the condition codes 11661 the jump should always come first */ 11662 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) 11663 body = XVECEXP (body, 0, 0); 11664 11665 if (reverse 11666 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC 11667 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) 11668 { 11669 int insns_skipped; 11670 int fail = FALSE, succeed = FALSE; 11671 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ 11672 int then_not_else = TRUE; 11673 rtx this_insn = start_insn, label = 0; 11674 11675 /* If the jump cannot be done with one instruction, we cannot 11676 conditionally execute the instruction in the inverse case. */ 11677 if (get_attr_conds (insn) == CONDS_JUMP_CLOB) 11678 { 11679 jump_clobbers = 1; 11680 return; 11681 } 11682 11683 /* Register the insn jumped to. */ 11684 if (reverse) 11685 { 11686 if (!seeking_return) 11687 label = XEXP (SET_SRC (body), 0); 11688 } 11689 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) 11690 label = XEXP (XEXP (SET_SRC (body), 1), 0); 11691 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) 11692 { 11693 label = XEXP (XEXP (SET_SRC (body), 2), 0); 11694 then_not_else = FALSE; 11695 } 11696 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) 11697 seeking_return = 1; 11698 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) 11699 { 11700 seeking_return = 1; 11701 then_not_else = FALSE; 11702 } 11703 else 11704 gcc_unreachable (); 11705 11706 /* See how many insns this branch skips, and what kind of insns. If all 11707 insns are okay, and the label or unconditional branch to the same 11708 label is not too far away, succeed. */ 11709 for (insns_skipped = 0; 11710 !fail && !succeed && insns_skipped++ < max_insns_skipped;) 11711 { 11712 rtx scanbody; 11713 11714 this_insn = next_nonnote_insn (this_insn); 11715 if (!this_insn) 11716 break; 11717 11718 switch (GET_CODE (this_insn)) 11719 { 11720 case CODE_LABEL: 11721 /* Succeed if it is the target label, otherwise fail since 11722 control falls in from somewhere else. */ 11723 if (this_insn == label) 11724 { 11725 if (jump_clobbers) 11726 { 11727 arm_ccfsm_state = 2; 11728 this_insn = next_nonnote_insn (this_insn); 11729 } 11730 else 11731 arm_ccfsm_state = 1; 11732 succeed = TRUE; 11733 } 11734 else 11735 fail = TRUE; 11736 break; 11737 11738 case BARRIER: 11739 /* Succeed if the following insn is the target label. 11740 Otherwise fail. 11741 If return insns are used then the last insn in a function 11742 will be a barrier. */ 11743 this_insn = next_nonnote_insn (this_insn); 11744 if (this_insn && this_insn == label) 11745 { 11746 if (jump_clobbers) 11747 { 11748 arm_ccfsm_state = 2; 11749 this_insn = next_nonnote_insn (this_insn); 11750 } 11751 else 11752 arm_ccfsm_state = 1; 11753 succeed = TRUE; 11754 } 11755 else 11756 fail = TRUE; 11757 break; 11758 11759 case CALL_INSN: 11760 /* The AAPCS says that conditional calls should not be 11761 used since they make interworking inefficient (the 11762 linker can't transform BL<cond> into BLX). That's 11763 only a problem if the machine has BLX. */ 11764 if (arm_arch5) 11765 { 11766 fail = TRUE; 11767 break; 11768 } 11769 11770 /* Succeed if the following insn is the target label, or 11771 if the following two insns are a barrier and the 11772 target label. */ 11773 this_insn = next_nonnote_insn (this_insn); 11774 if (this_insn && GET_CODE (this_insn) == BARRIER) 11775 this_insn = next_nonnote_insn (this_insn); 11776 11777 if (this_insn && this_insn == label 11778 && insns_skipped < max_insns_skipped) 11779 { 11780 if (jump_clobbers) 11781 { 11782 arm_ccfsm_state = 2; 11783 this_insn = next_nonnote_insn (this_insn); 11784 } 11785 else 11786 arm_ccfsm_state = 1; 11787 succeed = TRUE; 11788 } 11789 else 11790 fail = TRUE; 11791 break; 11792 11793 case JUMP_INSN: 11794 /* If this is an unconditional branch to the same label, succeed. 11795 If it is to another label, do nothing. If it is conditional, 11796 fail. */ 11797 /* XXX Probably, the tests for SET and the PC are 11798 unnecessary. */ 11799 11800 scanbody = PATTERN (this_insn); 11801 if (GET_CODE (scanbody) == SET 11802 && GET_CODE (SET_DEST (scanbody)) == PC) 11803 { 11804 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF 11805 && XEXP (SET_SRC (scanbody), 0) == label && !reverse) 11806 { 11807 arm_ccfsm_state = 2; 11808 succeed = TRUE; 11809 } 11810 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) 11811 fail = TRUE; 11812 } 11813 /* Fail if a conditional return is undesirable (e.g. on a 11814 StrongARM), but still allow this if optimizing for size. */ 11815 else if (GET_CODE (scanbody) == RETURN 11816 && !use_return_insn (TRUE, NULL) 11817 && !optimize_size) 11818 fail = TRUE; 11819 else if (GET_CODE (scanbody) == RETURN 11820 && seeking_return) 11821 { 11822 arm_ccfsm_state = 2; 11823 succeed = TRUE; 11824 } 11825 else if (GET_CODE (scanbody) == PARALLEL) 11826 { 11827 switch (get_attr_conds (this_insn)) 11828 { 11829 case CONDS_NOCOND: 11830 break; 11831 default: 11832 fail = TRUE; 11833 break; 11834 } 11835 } 11836 else 11837 fail = TRUE; /* Unrecognized jump (e.g. epilogue). */ 11838 11839 break; 11840 11841 case INSN: 11842 /* Instructions using or affecting the condition codes make it 11843 fail. */ 11844 scanbody = PATTERN (this_insn); 11845 if (!(GET_CODE (scanbody) == SET 11846 || GET_CODE (scanbody) == PARALLEL) 11847 || get_attr_conds (this_insn) != CONDS_NOCOND) 11848 fail = TRUE; 11849 11850 /* A conditional cirrus instruction must be followed by 11851 a non Cirrus instruction. However, since we 11852 conditionalize instructions in this function and by 11853 the time we get here we can't add instructions 11854 (nops), because shorten_branches() has already been 11855 called, we will disable conditionalizing Cirrus 11856 instructions to be safe. */ 11857 if (GET_CODE (scanbody) != USE 11858 && GET_CODE (scanbody) != CLOBBER 11859 && get_attr_cirrus (this_insn) != CIRRUS_NOT) 11860 fail = TRUE; 11861 break; 11862 11863 default: 11864 break; 11865 } 11866 } 11867 if (succeed) 11868 { 11869 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) 11870 arm_target_label = CODE_LABEL_NUMBER (label); 11871 else 11872 { 11873 gcc_assert (seeking_return || arm_ccfsm_state == 2); 11874 11875 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) 11876 { 11877 this_insn = next_nonnote_insn (this_insn); 11878 gcc_assert (!this_insn 11879 || (GET_CODE (this_insn) != BARRIER 11880 && GET_CODE (this_insn) != CODE_LABEL)); 11881 } 11882 if (!this_insn) 11883 { 11884 /* Oh, dear! we ran off the end.. give up. */ 11885 recog (PATTERN (insn), insn, NULL); 11886 arm_ccfsm_state = 0; 11887 arm_target_insn = NULL; 11888 return; 11889 } 11890 arm_target_insn = this_insn; 11891 } 11892 if (jump_clobbers) 11893 { 11894 gcc_assert (!reverse); 11895 arm_current_cc = 11896 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), 11897 0), 0), 1)); 11898 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) 11899 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); 11900 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) 11901 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); 11902 } 11903 else 11904 { 11905 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from 11906 what it was. */ 11907 if (!reverse) 11908 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), 11909 0)); 11910 } 11911 11912 if (reverse || then_not_else) 11913 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); 11914 } 11915 11916 /* Restore recog_data (getting the attributes of other insns can 11917 destroy this array, but final.c assumes that it remains intact 11918 across this call; since the insn has been recognized already we 11919 call recog direct). */ 11920 recog (PATTERN (insn), insn, NULL); 11921 } 11922} 11923 11924/* Returns true if REGNO is a valid register 11925 for holding a quantity of type MODE. */ 11926int 11927arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) 11928{ 11929 if (GET_MODE_CLASS (mode) == MODE_CC) 11930 return (regno == CC_REGNUM 11931 || (TARGET_HARD_FLOAT && TARGET_VFP 11932 && regno == VFPCC_REGNUM)); 11933 11934 if (TARGET_THUMB) 11935 /* For the Thumb we only allow values bigger than SImode in 11936 registers 0 - 6, so that there is always a second low 11937 register available to hold the upper part of the value. 11938 We probably we ought to ensure that the register is the 11939 start of an even numbered register pair. */ 11940 return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); 11941 11942 if (TARGET_HARD_FLOAT && TARGET_MAVERICK 11943 && IS_CIRRUS_REGNUM (regno)) 11944 /* We have outlawed SI values in Cirrus registers because they 11945 reside in the lower 32 bits, but SF values reside in the 11946 upper 32 bits. This causes gcc all sorts of grief. We can't 11947 even split the registers into pairs because Cirrus SI values 11948 get sign extended to 64bits-- aldyh. */ 11949 return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); 11950 11951 if (TARGET_HARD_FLOAT && TARGET_VFP 11952 && IS_VFP_REGNUM (regno)) 11953 { 11954 if (mode == SFmode || mode == SImode) 11955 return TRUE; 11956 11957 /* DFmode values are only valid in even register pairs. */ 11958 if (mode == DFmode) 11959 return ((regno - FIRST_VFP_REGNUM) & 1) == 0; 11960 return FALSE; 11961 } 11962 11963 if (TARGET_REALLY_IWMMXT) 11964 { 11965 if (IS_IWMMXT_GR_REGNUM (regno)) 11966 return mode == SImode; 11967 11968 if (IS_IWMMXT_REGNUM (regno)) 11969 return VALID_IWMMXT_REG_MODE (mode); 11970 } 11971 11972 /* We allow any value to be stored in the general registers. 11973 Restrict doubleword quantities to even register pairs so that we can 11974 use ldrd. */ 11975 if (regno <= LAST_ARM_REGNUM) 11976 return !(TARGET_LDRD && GET_MODE_SIZE (mode) > 4 && (regno & 1) != 0); 11977 11978 if (regno == FRAME_POINTER_REGNUM 11979 || regno == ARG_POINTER_REGNUM) 11980 /* We only allow integers in the fake hard registers. */ 11981 return GET_MODE_CLASS (mode) == MODE_INT; 11982 11983 /* The only registers left are the FPA registers 11984 which we only allow to hold FP values. */ 11985 return (TARGET_HARD_FLOAT && TARGET_FPA 11986 && GET_MODE_CLASS (mode) == MODE_FLOAT 11987 && regno >= FIRST_FPA_REGNUM 11988 && regno <= LAST_FPA_REGNUM); 11989} 11990 11991int 11992arm_regno_class (int regno) 11993{ 11994 if (TARGET_THUMB) 11995 { 11996 if (regno == STACK_POINTER_REGNUM) 11997 return STACK_REG; 11998 if (regno == CC_REGNUM) 11999 return CC_REG; 12000 if (regno < 8) 12001 return LO_REGS; 12002 return HI_REGS; 12003 } 12004 12005 if ( regno <= LAST_ARM_REGNUM 12006 || regno == FRAME_POINTER_REGNUM 12007 || regno == ARG_POINTER_REGNUM) 12008 return GENERAL_REGS; 12009 12010 if (regno == CC_REGNUM || regno == VFPCC_REGNUM) 12011 return NO_REGS; 12012 12013 if (IS_CIRRUS_REGNUM (regno)) 12014 return CIRRUS_REGS; 12015 12016 if (IS_VFP_REGNUM (regno)) 12017 return VFP_REGS; 12018 12019 if (IS_IWMMXT_REGNUM (regno)) 12020 return IWMMXT_REGS; 12021 12022 if (IS_IWMMXT_GR_REGNUM (regno)) 12023 return IWMMXT_GR_REGS; 12024 12025 return FPA_REGS; 12026} 12027 12028/* Handle a special case when computing the offset 12029 of an argument from the frame pointer. */ 12030int 12031arm_debugger_arg_offset (int value, rtx addr) 12032{ 12033 rtx insn; 12034 12035 /* We are only interested if dbxout_parms() failed to compute the offset. */ 12036 if (value != 0) 12037 return 0; 12038 12039 /* We can only cope with the case where the address is held in a register. */ 12040 if (GET_CODE (addr) != REG) 12041 return 0; 12042 12043 /* If we are using the frame pointer to point at the argument, then 12044 an offset of 0 is correct. */ 12045 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) 12046 return 0; 12047 12048 /* If we are using the stack pointer to point at the 12049 argument, then an offset of 0 is correct. */ 12050 if ((TARGET_THUMB || !frame_pointer_needed) 12051 && REGNO (addr) == SP_REGNUM) 12052 return 0; 12053 12054 /* Oh dear. The argument is pointed to by a register rather 12055 than being held in a register, or being stored at a known 12056 offset from the frame pointer. Since GDB only understands 12057 those two kinds of argument we must translate the address 12058 held in the register into an offset from the frame pointer. 12059 We do this by searching through the insns for the function 12060 looking to see where this register gets its value. If the 12061 register is initialized from the frame pointer plus an offset 12062 then we are in luck and we can continue, otherwise we give up. 12063 12064 This code is exercised by producing debugging information 12065 for a function with arguments like this: 12066 12067 double func (double a, double b, int c, double d) {return d;} 12068 12069 Without this code the stab for parameter 'd' will be set to 12070 an offset of 0 from the frame pointer, rather than 8. */ 12071 12072 /* The if() statement says: 12073 12074 If the insn is a normal instruction 12075 and if the insn is setting the value in a register 12076 and if the register being set is the register holding the address of the argument 12077 and if the address is computing by an addition 12078 that involves adding to a register 12079 which is the frame pointer 12080 a constant integer 12081 12082 then... */ 12083 12084 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 12085 { 12086 if ( GET_CODE (insn) == INSN 12087 && GET_CODE (PATTERN (insn)) == SET 12088 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) 12089 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS 12090 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG 12091 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM 12092 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT 12093 ) 12094 { 12095 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); 12096 12097 break; 12098 } 12099 } 12100 12101 if (value == 0) 12102 { 12103 debug_rtx (addr); 12104 warning (0, "unable to compute real location of stacked parameter"); 12105 value = 8; /* XXX magic hack */ 12106 } 12107 12108 return value; 12109} 12110 12111#define def_mbuiltin(MASK, NAME, TYPE, CODE) \ 12112 do \ 12113 { \ 12114 if ((MASK) & insn_flags) \ 12115 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \ 12116 BUILT_IN_MD, NULL, NULL_TREE); \ 12117 } \ 12118 while (0) 12119 12120struct builtin_description 12121{ 12122 const unsigned int mask; 12123 const enum insn_code icode; 12124 const char * const name; 12125 const enum arm_builtins code; 12126 const enum rtx_code comparison; 12127 const unsigned int flag; 12128}; 12129 12130static const struct builtin_description bdesc_2arg[] = 12131{ 12132#define IWMMXT_BUILTIN(code, string, builtin) \ 12133 { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ 12134 ARM_BUILTIN_##builtin, 0, 0 }, 12135 12136 IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) 12137 IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) 12138 IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) 12139 IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) 12140 IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) 12141 IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) 12142 IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) 12143 IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) 12144 IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) 12145 IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) 12146 IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) 12147 IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) 12148 IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) 12149 IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) 12150 IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) 12151 IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) 12152 IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) 12153 IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) 12154 IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) 12155 IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsm", WMULSM) 12156 IWMMXT_BUILTIN (umulv4hi3_highpart, "wmulum", WMULUM) 12157 IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) 12158 IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) 12159 IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) 12160 IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) 12161 IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) 12162 IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) 12163 IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) 12164 IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) 12165 IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) 12166 IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) 12167 IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) 12168 IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) 12169 IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) 12170 IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) 12171 IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) 12172 IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) 12173 IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) 12174 IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) 12175 IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) 12176 IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) 12177 IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) 12178 IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) 12179 IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) 12180 IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) 12181 IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) 12182 IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) 12183 IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) 12184 IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) 12185 IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) 12186 IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) 12187 IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) 12188 IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) 12189 IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) 12190 IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) 12191 IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) 12192 IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS) 12193 IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU) 12194 12195#define IWMMXT_BUILTIN2(code, builtin) \ 12196 { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 }, 12197 12198 IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) 12199 IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) 12200 IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) 12201 IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) 12202 IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) 12203 IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) 12204 IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) 12205 IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI) 12206 IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) 12207 IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI) 12208 IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) 12209 IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) 12210 IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) 12211 IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI) 12212 IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) 12213 IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI) 12214 IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) 12215 IWMMXT_BUILTIN2 (lshrdi3_iwmmxt, WSRLDI) 12216 IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) 12217 IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI) 12218 IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) 12219 IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI) 12220 IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) 12221 IWMMXT_BUILTIN2 (ashrdi3_iwmmxt, WSRADI) 12222 IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) 12223 IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) 12224 IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) 12225 IWMMXT_BUILTIN2 (rorv2si3, WRORWI) 12226 IWMMXT_BUILTIN2 (rordi3_di, WRORD) 12227 IWMMXT_BUILTIN2 (rordi3, WRORDI) 12228 IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) 12229 IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) 12230}; 12231 12232static const struct builtin_description bdesc_1arg[] = 12233{ 12234 IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) 12235 IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) 12236 IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) 12237 IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) 12238 IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) 12239 IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) 12240 IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) 12241 IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) 12242 IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) 12243 IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) 12244 IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) 12245 IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) 12246 IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) 12247 IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) 12248 IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) 12249 IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) 12250 IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) 12251 IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) 12252}; 12253 12254/* Set up all the iWMMXt builtins. This is 12255 not called if TARGET_IWMMXT is zero. */ 12256 12257static void 12258arm_init_iwmmxt_builtins (void) 12259{ 12260 const struct builtin_description * d; 12261 size_t i; 12262 tree endlink = void_list_node; 12263 12264 tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); 12265 tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); 12266 tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); 12267 12268 tree int_ftype_int 12269 = build_function_type (integer_type_node, 12270 tree_cons (NULL_TREE, integer_type_node, endlink)); 12271 tree v8qi_ftype_v8qi_v8qi_int 12272 = build_function_type (V8QI_type_node, 12273 tree_cons (NULL_TREE, V8QI_type_node, 12274 tree_cons (NULL_TREE, V8QI_type_node, 12275 tree_cons (NULL_TREE, 12276 integer_type_node, 12277 endlink)))); 12278 tree v4hi_ftype_v4hi_int 12279 = build_function_type (V4HI_type_node, 12280 tree_cons (NULL_TREE, V4HI_type_node, 12281 tree_cons (NULL_TREE, integer_type_node, 12282 endlink))); 12283 tree v2si_ftype_v2si_int 12284 = build_function_type (V2SI_type_node, 12285 tree_cons (NULL_TREE, V2SI_type_node, 12286 tree_cons (NULL_TREE, integer_type_node, 12287 endlink))); 12288 tree v2si_ftype_di_di 12289 = build_function_type (V2SI_type_node, 12290 tree_cons (NULL_TREE, long_long_integer_type_node, 12291 tree_cons (NULL_TREE, long_long_integer_type_node, 12292 endlink))); 12293 tree di_ftype_di_int 12294 = build_function_type (long_long_integer_type_node, 12295 tree_cons (NULL_TREE, long_long_integer_type_node, 12296 tree_cons (NULL_TREE, integer_type_node, 12297 endlink))); 12298 tree di_ftype_di_int_int 12299 = build_function_type (long_long_integer_type_node, 12300 tree_cons (NULL_TREE, long_long_integer_type_node, 12301 tree_cons (NULL_TREE, integer_type_node, 12302 tree_cons (NULL_TREE, 12303 integer_type_node, 12304 endlink)))); 12305 tree int_ftype_v8qi 12306 = build_function_type (integer_type_node, 12307 tree_cons (NULL_TREE, V8QI_type_node, 12308 endlink)); 12309 tree int_ftype_v4hi 12310 = build_function_type (integer_type_node, 12311 tree_cons (NULL_TREE, V4HI_type_node, 12312 endlink)); 12313 tree int_ftype_v2si 12314 = build_function_type (integer_type_node, 12315 tree_cons (NULL_TREE, V2SI_type_node, 12316 endlink)); 12317 tree int_ftype_v8qi_int 12318 = build_function_type (integer_type_node, 12319 tree_cons (NULL_TREE, V8QI_type_node, 12320 tree_cons (NULL_TREE, integer_type_node, 12321 endlink))); 12322 tree int_ftype_v4hi_int 12323 = build_function_type (integer_type_node, 12324 tree_cons (NULL_TREE, V4HI_type_node, 12325 tree_cons (NULL_TREE, integer_type_node, 12326 endlink))); 12327 tree int_ftype_v2si_int 12328 = build_function_type (integer_type_node, 12329 tree_cons (NULL_TREE, V2SI_type_node, 12330 tree_cons (NULL_TREE, integer_type_node, 12331 endlink))); 12332 tree v8qi_ftype_v8qi_int_int 12333 = build_function_type (V8QI_type_node, 12334 tree_cons (NULL_TREE, V8QI_type_node, 12335 tree_cons (NULL_TREE, integer_type_node, 12336 tree_cons (NULL_TREE, 12337 integer_type_node, 12338 endlink)))); 12339 tree v4hi_ftype_v4hi_int_int 12340 = build_function_type (V4HI_type_node, 12341 tree_cons (NULL_TREE, V4HI_type_node, 12342 tree_cons (NULL_TREE, integer_type_node, 12343 tree_cons (NULL_TREE, 12344 integer_type_node, 12345 endlink)))); 12346 tree v2si_ftype_v2si_int_int 12347 = build_function_type (V2SI_type_node, 12348 tree_cons (NULL_TREE, V2SI_type_node, 12349 tree_cons (NULL_TREE, integer_type_node, 12350 tree_cons (NULL_TREE, 12351 integer_type_node, 12352 endlink)))); 12353 /* Miscellaneous. */ 12354 tree v8qi_ftype_v4hi_v4hi 12355 = build_function_type (V8QI_type_node, 12356 tree_cons (NULL_TREE, V4HI_type_node, 12357 tree_cons (NULL_TREE, V4HI_type_node, 12358 endlink))); 12359 tree v4hi_ftype_v2si_v2si 12360 = build_function_type (V4HI_type_node, 12361 tree_cons (NULL_TREE, V2SI_type_node, 12362 tree_cons (NULL_TREE, V2SI_type_node, 12363 endlink))); 12364 tree v2si_ftype_v4hi_v4hi 12365 = build_function_type (V2SI_type_node, 12366 tree_cons (NULL_TREE, V4HI_type_node, 12367 tree_cons (NULL_TREE, V4HI_type_node, 12368 endlink))); 12369 tree v2si_ftype_v8qi_v8qi 12370 = build_function_type (V2SI_type_node, 12371 tree_cons (NULL_TREE, V8QI_type_node, 12372 tree_cons (NULL_TREE, V8QI_type_node, 12373 endlink))); 12374 tree v4hi_ftype_v4hi_di 12375 = build_function_type (V4HI_type_node, 12376 tree_cons (NULL_TREE, V4HI_type_node, 12377 tree_cons (NULL_TREE, 12378 long_long_integer_type_node, 12379 endlink))); 12380 tree v2si_ftype_v2si_di 12381 = build_function_type (V2SI_type_node, 12382 tree_cons (NULL_TREE, V2SI_type_node, 12383 tree_cons (NULL_TREE, 12384 long_long_integer_type_node, 12385 endlink))); 12386 tree void_ftype_int_int 12387 = build_function_type (void_type_node, 12388 tree_cons (NULL_TREE, integer_type_node, 12389 tree_cons (NULL_TREE, integer_type_node, 12390 endlink))); 12391 tree di_ftype_void 12392 = build_function_type (long_long_unsigned_type_node, endlink); 12393 tree di_ftype_v8qi 12394 = build_function_type (long_long_integer_type_node, 12395 tree_cons (NULL_TREE, V8QI_type_node, 12396 endlink)); 12397 tree di_ftype_v4hi 12398 = build_function_type (long_long_integer_type_node, 12399 tree_cons (NULL_TREE, V4HI_type_node, 12400 endlink)); 12401 tree di_ftype_v2si 12402 = build_function_type (long_long_integer_type_node, 12403 tree_cons (NULL_TREE, V2SI_type_node, 12404 endlink)); 12405 tree v2si_ftype_v4hi 12406 = build_function_type (V2SI_type_node, 12407 tree_cons (NULL_TREE, V4HI_type_node, 12408 endlink)); 12409 tree v4hi_ftype_v8qi 12410 = build_function_type (V4HI_type_node, 12411 tree_cons (NULL_TREE, V8QI_type_node, 12412 endlink)); 12413 12414 tree di_ftype_di_v4hi_v4hi 12415 = build_function_type (long_long_unsigned_type_node, 12416 tree_cons (NULL_TREE, 12417 long_long_unsigned_type_node, 12418 tree_cons (NULL_TREE, V4HI_type_node, 12419 tree_cons (NULL_TREE, 12420 V4HI_type_node, 12421 endlink)))); 12422 12423 tree di_ftype_v4hi_v4hi 12424 = build_function_type (long_long_unsigned_type_node, 12425 tree_cons (NULL_TREE, V4HI_type_node, 12426 tree_cons (NULL_TREE, V4HI_type_node, 12427 endlink))); 12428 12429 /* Normal vector binops. */ 12430 tree v8qi_ftype_v8qi_v8qi 12431 = build_function_type (V8QI_type_node, 12432 tree_cons (NULL_TREE, V8QI_type_node, 12433 tree_cons (NULL_TREE, V8QI_type_node, 12434 endlink))); 12435 tree v4hi_ftype_v4hi_v4hi 12436 = build_function_type (V4HI_type_node, 12437 tree_cons (NULL_TREE, V4HI_type_node, 12438 tree_cons (NULL_TREE, V4HI_type_node, 12439 endlink))); 12440 tree v2si_ftype_v2si_v2si 12441 = build_function_type (V2SI_type_node, 12442 tree_cons (NULL_TREE, V2SI_type_node, 12443 tree_cons (NULL_TREE, V2SI_type_node, 12444 endlink))); 12445 tree di_ftype_di_di 12446 = build_function_type (long_long_unsigned_type_node, 12447 tree_cons (NULL_TREE, long_long_unsigned_type_node, 12448 tree_cons (NULL_TREE, 12449 long_long_unsigned_type_node, 12450 endlink))); 12451 12452 /* Add all builtins that are more or less simple operations on two 12453 operands. */ 12454 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) 12455 { 12456 /* Use one of the operands; the target can have a different mode for 12457 mask-generating compares. */ 12458 enum machine_mode mode; 12459 tree type; 12460 12461 if (d->name == 0) 12462 continue; 12463 12464 mode = insn_data[d->icode].operand[1].mode; 12465 12466 switch (mode) 12467 { 12468 case V8QImode: 12469 type = v8qi_ftype_v8qi_v8qi; 12470 break; 12471 case V4HImode: 12472 type = v4hi_ftype_v4hi_v4hi; 12473 break; 12474 case V2SImode: 12475 type = v2si_ftype_v2si_v2si; 12476 break; 12477 case DImode: 12478 type = di_ftype_di_di; 12479 break; 12480 12481 default: 12482 gcc_unreachable (); 12483 } 12484 12485 def_mbuiltin (d->mask, d->name, type, d->code); 12486 } 12487 12488 /* Add the remaining MMX insns with somewhat more complicated types. */ 12489 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO); 12490 def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX); 12491 def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX); 12492 12493 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH); 12494 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW); 12495 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD); 12496 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI); 12497 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI); 12498 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI); 12499 12500 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH); 12501 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW); 12502 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD); 12503 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI); 12504 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI); 12505 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI); 12506 12507 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH); 12508 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW); 12509 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD); 12510 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI); 12511 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI); 12512 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI); 12513 12514 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH); 12515 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW); 12516 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD); 12517 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI); 12518 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI); 12519 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI); 12520 12521 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH); 12522 12523 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB); 12524 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH); 12525 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ); 12526 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ); 12527 12528 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB); 12529 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH); 12530 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW); 12531 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB); 12532 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH); 12533 def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW); 12534 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB); 12535 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH); 12536 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW); 12537 12538 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB); 12539 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH); 12540 def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW); 12541 12542 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB); 12543 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH); 12544 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW); 12545 12546 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS); 12547 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS); 12548 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS); 12549 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS); 12550 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS); 12551 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS); 12552 12553 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB); 12554 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH); 12555 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW); 12556 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB); 12557 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH); 12558 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW); 12559 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB); 12560 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH); 12561 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW); 12562 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB); 12563 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH); 12564 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW); 12565 12566 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS); 12567 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ); 12568 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU); 12569 def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ); 12570 12571 def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN); 12572 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA); 12573 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH); 12574 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB); 12575 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT); 12576 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB); 12577 def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT); 12578} 12579 12580static void 12581arm_init_tls_builtins (void) 12582{ 12583 tree ftype; 12584 tree nothrow = tree_cons (get_identifier ("nothrow"), NULL, NULL); 12585 tree const_nothrow = tree_cons (get_identifier ("const"), NULL, nothrow); 12586 12587 ftype = build_function_type (ptr_type_node, void_list_node); 12588 lang_hooks.builtin_function ("__builtin_thread_pointer", ftype, 12589 ARM_BUILTIN_THREAD_POINTER, BUILT_IN_MD, 12590 NULL, const_nothrow); 12591} 12592 12593static void 12594arm_init_builtins (void) 12595{ 12596 arm_init_tls_builtins (); 12597 12598 if (TARGET_REALLY_IWMMXT) 12599 arm_init_iwmmxt_builtins (); 12600} 12601 12602/* Errors in the source file can cause expand_expr to return const0_rtx 12603 where we expect a vector. To avoid crashing, use one of the vector 12604 clear instructions. */ 12605 12606static rtx 12607safe_vector_operand (rtx x, enum machine_mode mode) 12608{ 12609 if (x != const0_rtx) 12610 return x; 12611 x = gen_reg_rtx (mode); 12612 12613 emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x 12614 : gen_rtx_SUBREG (DImode, x, 0))); 12615 return x; 12616} 12617 12618/* Subroutine of arm_expand_builtin to take care of binop insns. */ 12619 12620static rtx 12621arm_expand_binop_builtin (enum insn_code icode, 12622 tree arglist, rtx target) 12623{ 12624 rtx pat; 12625 tree arg0 = TREE_VALUE (arglist); 12626 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 12627 rtx op0 = expand_normal (arg0); 12628 rtx op1 = expand_normal (arg1); 12629 enum machine_mode tmode = insn_data[icode].operand[0].mode; 12630 enum machine_mode mode0 = insn_data[icode].operand[1].mode; 12631 enum machine_mode mode1 = insn_data[icode].operand[2].mode; 12632 12633 if (VECTOR_MODE_P (mode0)) 12634 op0 = safe_vector_operand (op0, mode0); 12635 if (VECTOR_MODE_P (mode1)) 12636 op1 = safe_vector_operand (op1, mode1); 12637 12638 if (! target 12639 || GET_MODE (target) != tmode 12640 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 12641 target = gen_reg_rtx (tmode); 12642 12643 gcc_assert (GET_MODE (op0) == mode0 && GET_MODE (op1) == mode1); 12644 12645 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 12646 op0 = copy_to_mode_reg (mode0, op0); 12647 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 12648 op1 = copy_to_mode_reg (mode1, op1); 12649 12650 pat = GEN_FCN (icode) (target, op0, op1); 12651 if (! pat) 12652 return 0; 12653 emit_insn (pat); 12654 return target; 12655} 12656 12657/* Subroutine of arm_expand_builtin to take care of unop insns. */ 12658 12659static rtx 12660arm_expand_unop_builtin (enum insn_code icode, 12661 tree arglist, rtx target, int do_load) 12662{ 12663 rtx pat; 12664 tree arg0 = TREE_VALUE (arglist); 12665 rtx op0 = expand_normal (arg0); 12666 enum machine_mode tmode = insn_data[icode].operand[0].mode; 12667 enum machine_mode mode0 = insn_data[icode].operand[1].mode; 12668 12669 if (! target 12670 || GET_MODE (target) != tmode 12671 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 12672 target = gen_reg_rtx (tmode); 12673 if (do_load) 12674 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); 12675 else 12676 { 12677 if (VECTOR_MODE_P (mode0)) 12678 op0 = safe_vector_operand (op0, mode0); 12679 12680 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 12681 op0 = copy_to_mode_reg (mode0, op0); 12682 } 12683 12684 pat = GEN_FCN (icode) (target, op0); 12685 if (! pat) 12686 return 0; 12687 emit_insn (pat); 12688 return target; 12689} 12690 12691/* Expand an expression EXP that calls a built-in function, 12692 with result going to TARGET if that's convenient 12693 (and in mode MODE if that's convenient). 12694 SUBTARGET may be used as the target for computing one of EXP's operands. 12695 IGNORE is nonzero if the value is to be ignored. */ 12696 12697static rtx 12698arm_expand_builtin (tree exp, 12699 rtx target, 12700 rtx subtarget ATTRIBUTE_UNUSED, 12701 enum machine_mode mode ATTRIBUTE_UNUSED, 12702 int ignore ATTRIBUTE_UNUSED) 12703{ 12704 const struct builtin_description * d; 12705 enum insn_code icode; 12706 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 12707 tree arglist = TREE_OPERAND (exp, 1); 12708 tree arg0; 12709 tree arg1; 12710 tree arg2; 12711 rtx op0; 12712 rtx op1; 12713 rtx op2; 12714 rtx pat; 12715 int fcode = DECL_FUNCTION_CODE (fndecl); 12716 size_t i; 12717 enum machine_mode tmode; 12718 enum machine_mode mode0; 12719 enum machine_mode mode1; 12720 enum machine_mode mode2; 12721 12722 switch (fcode) 12723 { 12724 case ARM_BUILTIN_TEXTRMSB: 12725 case ARM_BUILTIN_TEXTRMUB: 12726 case ARM_BUILTIN_TEXTRMSH: 12727 case ARM_BUILTIN_TEXTRMUH: 12728 case ARM_BUILTIN_TEXTRMSW: 12729 case ARM_BUILTIN_TEXTRMUW: 12730 icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb 12731 : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub 12732 : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh 12733 : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh 12734 : CODE_FOR_iwmmxt_textrmw); 12735 12736 arg0 = TREE_VALUE (arglist); 12737 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 12738 op0 = expand_normal (arg0); 12739 op1 = expand_normal (arg1); 12740 tmode = insn_data[icode].operand[0].mode; 12741 mode0 = insn_data[icode].operand[1].mode; 12742 mode1 = insn_data[icode].operand[2].mode; 12743 12744 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 12745 op0 = copy_to_mode_reg (mode0, op0); 12746 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 12747 { 12748 /* @@@ better error message */ 12749 error ("selector must be an immediate"); 12750 return gen_reg_rtx (tmode); 12751 } 12752 if (target == 0 12753 || GET_MODE (target) != tmode 12754 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 12755 target = gen_reg_rtx (tmode); 12756 pat = GEN_FCN (icode) (target, op0, op1); 12757 if (! pat) 12758 return 0; 12759 emit_insn (pat); 12760 return target; 12761 12762 case ARM_BUILTIN_TINSRB: 12763 case ARM_BUILTIN_TINSRH: 12764 case ARM_BUILTIN_TINSRW: 12765 icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb 12766 : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh 12767 : CODE_FOR_iwmmxt_tinsrw); 12768 arg0 = TREE_VALUE (arglist); 12769 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 12770 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 12771 op0 = expand_normal (arg0); 12772 op1 = expand_normal (arg1); 12773 op2 = expand_normal (arg2); 12774 tmode = insn_data[icode].operand[0].mode; 12775 mode0 = insn_data[icode].operand[1].mode; 12776 mode1 = insn_data[icode].operand[2].mode; 12777 mode2 = insn_data[icode].operand[3].mode; 12778 12779 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 12780 op0 = copy_to_mode_reg (mode0, op0); 12781 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 12782 op1 = copy_to_mode_reg (mode1, op1); 12783 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) 12784 { 12785 /* @@@ better error message */ 12786 error ("selector must be an immediate"); 12787 return const0_rtx; 12788 } 12789 if (target == 0 12790 || GET_MODE (target) != tmode 12791 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 12792 target = gen_reg_rtx (tmode); 12793 pat = GEN_FCN (icode) (target, op0, op1, op2); 12794 if (! pat) 12795 return 0; 12796 emit_insn (pat); 12797 return target; 12798 12799 case ARM_BUILTIN_SETWCX: 12800 arg0 = TREE_VALUE (arglist); 12801 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 12802 op0 = force_reg (SImode, expand_normal (arg0)); 12803 op1 = expand_normal (arg1); 12804 emit_insn (gen_iwmmxt_tmcr (op1, op0)); 12805 return 0; 12806 12807 case ARM_BUILTIN_GETWCX: 12808 arg0 = TREE_VALUE (arglist); 12809 op0 = expand_normal (arg0); 12810 target = gen_reg_rtx (SImode); 12811 emit_insn (gen_iwmmxt_tmrc (target, op0)); 12812 return target; 12813 12814 case ARM_BUILTIN_WSHUFH: 12815 icode = CODE_FOR_iwmmxt_wshufh; 12816 arg0 = TREE_VALUE (arglist); 12817 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 12818 op0 = expand_normal (arg0); 12819 op1 = expand_normal (arg1); 12820 tmode = insn_data[icode].operand[0].mode; 12821 mode1 = insn_data[icode].operand[1].mode; 12822 mode2 = insn_data[icode].operand[2].mode; 12823 12824 if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) 12825 op0 = copy_to_mode_reg (mode1, op0); 12826 if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) 12827 { 12828 /* @@@ better error message */ 12829 error ("mask must be an immediate"); 12830 return const0_rtx; 12831 } 12832 if (target == 0 12833 || GET_MODE (target) != tmode 12834 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 12835 target = gen_reg_rtx (tmode); 12836 pat = GEN_FCN (icode) (target, op0, op1); 12837 if (! pat) 12838 return 0; 12839 emit_insn (pat); 12840 return target; 12841 12842 case ARM_BUILTIN_WSADB: 12843 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target); 12844 case ARM_BUILTIN_WSADH: 12845 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target); 12846 case ARM_BUILTIN_WSADBZ: 12847 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target); 12848 case ARM_BUILTIN_WSADHZ: 12849 return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target); 12850 12851 /* Several three-argument builtins. */ 12852 case ARM_BUILTIN_WMACS: 12853 case ARM_BUILTIN_WMACU: 12854 case ARM_BUILTIN_WALIGN: 12855 case ARM_BUILTIN_TMIA: 12856 case ARM_BUILTIN_TMIAPH: 12857 case ARM_BUILTIN_TMIATT: 12858 case ARM_BUILTIN_TMIATB: 12859 case ARM_BUILTIN_TMIABT: 12860 case ARM_BUILTIN_TMIABB: 12861 icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs 12862 : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu 12863 : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia 12864 : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph 12865 : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb 12866 : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt 12867 : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb 12868 : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt 12869 : CODE_FOR_iwmmxt_walign); 12870 arg0 = TREE_VALUE (arglist); 12871 arg1 = TREE_VALUE (TREE_CHAIN (arglist)); 12872 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); 12873 op0 = expand_normal (arg0); 12874 op1 = expand_normal (arg1); 12875 op2 = expand_normal (arg2); 12876 tmode = insn_data[icode].operand[0].mode; 12877 mode0 = insn_data[icode].operand[1].mode; 12878 mode1 = insn_data[icode].operand[2].mode; 12879 mode2 = insn_data[icode].operand[3].mode; 12880 12881 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 12882 op0 = copy_to_mode_reg (mode0, op0); 12883 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) 12884 op1 = copy_to_mode_reg (mode1, op1); 12885 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) 12886 op2 = copy_to_mode_reg (mode2, op2); 12887 if (target == 0 12888 || GET_MODE (target) != tmode 12889 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 12890 target = gen_reg_rtx (tmode); 12891 pat = GEN_FCN (icode) (target, op0, op1, op2); 12892 if (! pat) 12893 return 0; 12894 emit_insn (pat); 12895 return target; 12896 12897 case ARM_BUILTIN_WZERO: 12898 target = gen_reg_rtx (DImode); 12899 emit_insn (gen_iwmmxt_clrdi (target)); 12900 return target; 12901 12902 case ARM_BUILTIN_THREAD_POINTER: 12903 return arm_load_tp (target); 12904 12905 default: 12906 break; 12907 } 12908 12909 for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) 12910 if (d->code == (const enum arm_builtins) fcode) 12911 return arm_expand_binop_builtin (d->icode, arglist, target); 12912 12913 for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) 12914 if (d->code == (const enum arm_builtins) fcode) 12915 return arm_expand_unop_builtin (d->icode, arglist, target, 0); 12916 12917 /* @@@ Should really do something sensible here. */ 12918 return NULL_RTX; 12919} 12920 12921/* Return the number (counting from 0) of 12922 the least significant set bit in MASK. */ 12923 12924inline static int 12925number_of_first_bit_set (unsigned mask) 12926{ 12927 int bit; 12928 12929 for (bit = 0; 12930 (mask & (1 << bit)) == 0; 12931 ++bit) 12932 continue; 12933 12934 return bit; 12935} 12936 12937/* Emit code to push or pop registers to or from the stack. F is the 12938 assembly file. MASK is the registers to push or pop. PUSH is 12939 nonzero if we should push, and zero if we should pop. For debugging 12940 output, if pushing, adjust CFA_OFFSET by the amount of space added 12941 to the stack. REAL_REGS should have the same number of bits set as 12942 MASK, and will be used instead (in the same order) to describe which 12943 registers were saved - this is used to mark the save slots when we 12944 push high registers after moving them to low registers. */ 12945static void 12946thumb_pushpop (FILE *f, unsigned long mask, int push, int *cfa_offset, 12947 unsigned long real_regs) 12948{ 12949 int regno; 12950 int lo_mask = mask & 0xFF; 12951 int pushed_words = 0; 12952 12953 gcc_assert (mask); 12954 12955 if (lo_mask == 0 && !push && (mask & (1 << PC_REGNUM))) 12956 { 12957 /* Special case. Do not generate a POP PC statement here, do it in 12958 thumb_exit() */ 12959 thumb_exit (f, -1); 12960 return; 12961 } 12962 12963 if (ARM_EABI_UNWIND_TABLES && push) 12964 { 12965 fprintf (f, "\t.save\t{"); 12966 for (regno = 0; regno < 15; regno++) 12967 { 12968 if (real_regs & (1 << regno)) 12969 { 12970 if (real_regs & ((1 << regno) -1)) 12971 fprintf (f, ", "); 12972 asm_fprintf (f, "%r", regno); 12973 } 12974 } 12975 fprintf (f, "}\n"); 12976 } 12977 12978 fprintf (f, "\t%s\t{", push ? "push" : "pop"); 12979 12980 /* Look at the low registers first. */ 12981 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) 12982 { 12983 if (lo_mask & 1) 12984 { 12985 asm_fprintf (f, "%r", regno); 12986 12987 if ((lo_mask & ~1) != 0) 12988 fprintf (f, ", "); 12989 12990 pushed_words++; 12991 } 12992 } 12993 12994 if (push && (mask & (1 << LR_REGNUM))) 12995 { 12996 /* Catch pushing the LR. */ 12997 if (mask & 0xFF) 12998 fprintf (f, ", "); 12999 13000 asm_fprintf (f, "%r", LR_REGNUM); 13001 13002 pushed_words++; 13003 } 13004 else if (!push && (mask & (1 << PC_REGNUM))) 13005 { 13006 /* Catch popping the PC. */ 13007 if (TARGET_INTERWORK || TARGET_BACKTRACE 13008 || current_function_calls_eh_return) 13009 { 13010 /* The PC is never poped directly, instead 13011 it is popped into r3 and then BX is used. */ 13012 fprintf (f, "}\n"); 13013 13014 thumb_exit (f, -1); 13015 13016 return; 13017 } 13018 else 13019 { 13020 if (mask & 0xFF) 13021 fprintf (f, ", "); 13022 13023 asm_fprintf (f, "%r", PC_REGNUM); 13024 } 13025 } 13026 13027 fprintf (f, "}\n"); 13028 13029 if (push && pushed_words && dwarf2out_do_frame ()) 13030 { 13031 char *l = dwarf2out_cfi_label (); 13032 int pushed_mask = real_regs; 13033 13034 *cfa_offset += pushed_words * 4; 13035 dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); 13036 13037 pushed_words = 0; 13038 pushed_mask = real_regs; 13039 for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) 13040 { 13041 if (pushed_mask & 1) 13042 dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); 13043 } 13044 } 13045} 13046 13047/* Generate code to return from a thumb function. 13048 If 'reg_containing_return_addr' is -1, then the return address is 13049 actually on the stack, at the stack pointer. */ 13050static void 13051thumb_exit (FILE *f, int reg_containing_return_addr) 13052{ 13053 unsigned regs_available_for_popping; 13054 unsigned regs_to_pop; 13055 int pops_needed; 13056 unsigned available; 13057 unsigned required; 13058 int mode; 13059 int size; 13060 int restore_a4 = FALSE; 13061 13062 /* Compute the registers we need to pop. */ 13063 regs_to_pop = 0; 13064 pops_needed = 0; 13065 13066 if (reg_containing_return_addr == -1) 13067 { 13068 regs_to_pop |= 1 << LR_REGNUM; 13069 ++pops_needed; 13070 } 13071 13072 if (TARGET_BACKTRACE) 13073 { 13074 /* Restore the (ARM) frame pointer and stack pointer. */ 13075 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); 13076 pops_needed += 2; 13077 } 13078 13079 /* If there is nothing to pop then just emit the BX instruction and 13080 return. */ 13081 if (pops_needed == 0) 13082 { 13083 if (current_function_calls_eh_return) 13084 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); 13085 13086 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); 13087 return; 13088 } 13089 /* Otherwise if we are not supporting interworking and we have not created 13090 a backtrace structure and the function was not entered in ARM mode then 13091 just pop the return address straight into the PC. */ 13092 else if (!TARGET_INTERWORK 13093 && !TARGET_BACKTRACE 13094 && !is_called_in_ARM_mode (current_function_decl) 13095 && !current_function_calls_eh_return) 13096 { 13097 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); 13098 return; 13099 } 13100 13101 /* Find out how many of the (return) argument registers we can corrupt. */ 13102 regs_available_for_popping = 0; 13103 13104 /* If returning via __builtin_eh_return, the bottom three registers 13105 all contain information needed for the return. */ 13106 if (current_function_calls_eh_return) 13107 size = 12; 13108 else 13109 { 13110 /* If we can deduce the registers used from the function's 13111 return value. This is more reliable that examining 13112 regs_ever_live[] because that will be set if the register is 13113 ever used in the function, not just if the register is used 13114 to hold a return value. */ 13115 13116 if (current_function_return_rtx != 0) 13117 mode = GET_MODE (current_function_return_rtx); 13118 else 13119 mode = DECL_MODE (DECL_RESULT (current_function_decl)); 13120 13121 size = GET_MODE_SIZE (mode); 13122 13123 if (size == 0) 13124 { 13125 /* In a void function we can use any argument register. 13126 In a function that returns a structure on the stack 13127 we can use the second and third argument registers. */ 13128 if (mode == VOIDmode) 13129 regs_available_for_popping = 13130 (1 << ARG_REGISTER (1)) 13131 | (1 << ARG_REGISTER (2)) 13132 | (1 << ARG_REGISTER (3)); 13133 else 13134 regs_available_for_popping = 13135 (1 << ARG_REGISTER (2)) 13136 | (1 << ARG_REGISTER (3)); 13137 } 13138 else if (size <= 4) 13139 regs_available_for_popping = 13140 (1 << ARG_REGISTER (2)) 13141 | (1 << ARG_REGISTER (3)); 13142 else if (size <= 8) 13143 regs_available_for_popping = 13144 (1 << ARG_REGISTER (3)); 13145 } 13146 13147 /* Match registers to be popped with registers into which we pop them. */ 13148 for (available = regs_available_for_popping, 13149 required = regs_to_pop; 13150 required != 0 && available != 0; 13151 available &= ~(available & - available), 13152 required &= ~(required & - required)) 13153 -- pops_needed; 13154 13155 /* If we have any popping registers left over, remove them. */ 13156 if (available > 0) 13157 regs_available_for_popping &= ~available; 13158 13159 /* Otherwise if we need another popping register we can use 13160 the fourth argument register. */ 13161 else if (pops_needed) 13162 { 13163 /* If we have not found any free argument registers and 13164 reg a4 contains the return address, we must move it. */ 13165 if (regs_available_for_popping == 0 13166 && reg_containing_return_addr == LAST_ARG_REGNUM) 13167 { 13168 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); 13169 reg_containing_return_addr = LR_REGNUM; 13170 } 13171 else if (size > 12) 13172 { 13173 /* Register a4 is being used to hold part of the return value, 13174 but we have dire need of a free, low register. */ 13175 restore_a4 = TRUE; 13176 13177 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); 13178 } 13179 13180 if (reg_containing_return_addr != LAST_ARG_REGNUM) 13181 { 13182 /* The fourth argument register is available. */ 13183 regs_available_for_popping |= 1 << LAST_ARG_REGNUM; 13184 13185 --pops_needed; 13186 } 13187 } 13188 13189 /* Pop as many registers as we can. */ 13190 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, 13191 regs_available_for_popping); 13192 13193 /* Process the registers we popped. */ 13194 if (reg_containing_return_addr == -1) 13195 { 13196 /* The return address was popped into the lowest numbered register. */ 13197 regs_to_pop &= ~(1 << LR_REGNUM); 13198 13199 reg_containing_return_addr = 13200 number_of_first_bit_set (regs_available_for_popping); 13201 13202 /* Remove this register for the mask of available registers, so that 13203 the return address will not be corrupted by further pops. */ 13204 regs_available_for_popping &= ~(1 << reg_containing_return_addr); 13205 } 13206 13207 /* If we popped other registers then handle them here. */ 13208 if (regs_available_for_popping) 13209 { 13210 int frame_pointer; 13211 13212 /* Work out which register currently contains the frame pointer. */ 13213 frame_pointer = number_of_first_bit_set (regs_available_for_popping); 13214 13215 /* Move it into the correct place. */ 13216 asm_fprintf (f, "\tmov\t%r, %r\n", 13217 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); 13218 13219 /* (Temporarily) remove it from the mask of popped registers. */ 13220 regs_available_for_popping &= ~(1 << frame_pointer); 13221 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); 13222 13223 if (regs_available_for_popping) 13224 { 13225 int stack_pointer; 13226 13227 /* We popped the stack pointer as well, 13228 find the register that contains it. */ 13229 stack_pointer = number_of_first_bit_set (regs_available_for_popping); 13230 13231 /* Move it into the stack register. */ 13232 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); 13233 13234 /* At this point we have popped all necessary registers, so 13235 do not worry about restoring regs_available_for_popping 13236 to its correct value: 13237 13238 assert (pops_needed == 0) 13239 assert (regs_available_for_popping == (1 << frame_pointer)) 13240 assert (regs_to_pop == (1 << STACK_POINTER)) */ 13241 } 13242 else 13243 { 13244 /* Since we have just move the popped value into the frame 13245 pointer, the popping register is available for reuse, and 13246 we know that we still have the stack pointer left to pop. */ 13247 regs_available_for_popping |= (1 << frame_pointer); 13248 } 13249 } 13250 13251 /* If we still have registers left on the stack, but we no longer have 13252 any registers into which we can pop them, then we must move the return 13253 address into the link register and make available the register that 13254 contained it. */ 13255 if (regs_available_for_popping == 0 && pops_needed > 0) 13256 { 13257 regs_available_for_popping |= 1 << reg_containing_return_addr; 13258 13259 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, 13260 reg_containing_return_addr); 13261 13262 reg_containing_return_addr = LR_REGNUM; 13263 } 13264 13265 /* If we have registers left on the stack then pop some more. 13266 We know that at most we will want to pop FP and SP. */ 13267 if (pops_needed > 0) 13268 { 13269 int popped_into; 13270 int move_to; 13271 13272 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, 13273 regs_available_for_popping); 13274 13275 /* We have popped either FP or SP. 13276 Move whichever one it is into the correct register. */ 13277 popped_into = number_of_first_bit_set (regs_available_for_popping); 13278 move_to = number_of_first_bit_set (regs_to_pop); 13279 13280 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); 13281 13282 regs_to_pop &= ~(1 << move_to); 13283 13284 --pops_needed; 13285 } 13286 13287 /* If we still have not popped everything then we must have only 13288 had one register available to us and we are now popping the SP. */ 13289 if (pops_needed > 0) 13290 { 13291 int popped_into; 13292 13293 thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, 13294 regs_available_for_popping); 13295 13296 popped_into = number_of_first_bit_set (regs_available_for_popping); 13297 13298 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); 13299 /* 13300 assert (regs_to_pop == (1 << STACK_POINTER)) 13301 assert (pops_needed == 1) 13302 */ 13303 } 13304 13305 /* If necessary restore the a4 register. */ 13306 if (restore_a4) 13307 { 13308 if (reg_containing_return_addr != LR_REGNUM) 13309 { 13310 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); 13311 reg_containing_return_addr = LR_REGNUM; 13312 } 13313 13314 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); 13315 } 13316 13317 if (current_function_calls_eh_return) 13318 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, ARM_EH_STACKADJ_REGNUM); 13319 13320 /* Return to caller. */ 13321 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); 13322} 13323 13324 13325void 13326thumb_final_prescan_insn (rtx insn) 13327{ 13328 if (flag_print_asm_name) 13329 asm_fprintf (asm_out_file, "%@ 0x%04x\n", 13330 INSN_ADDRESSES (INSN_UID (insn))); 13331} 13332 13333int 13334thumb_shiftable_const (unsigned HOST_WIDE_INT val) 13335{ 13336 unsigned HOST_WIDE_INT mask = 0xff; 13337 int i; 13338 13339 if (val == 0) /* XXX */ 13340 return 0; 13341 13342 for (i = 0; i < 25; i++) 13343 if ((val & (mask << i)) == val) 13344 return 1; 13345 13346 return 0; 13347} 13348 13349/* Returns nonzero if the current function contains, 13350 or might contain a far jump. */ 13351static int 13352thumb_far_jump_used_p (void) 13353{ 13354 rtx insn; 13355 13356 /* This test is only important for leaf functions. */ 13357 /* assert (!leaf_function_p ()); */ 13358 13359 /* If we have already decided that far jumps may be used, 13360 do not bother checking again, and always return true even if 13361 it turns out that they are not being used. Once we have made 13362 the decision that far jumps are present (and that hence the link 13363 register will be pushed onto the stack) we cannot go back on it. */ 13364 if (cfun->machine->far_jump_used) 13365 return 1; 13366 13367 /* If this function is not being called from the prologue/epilogue 13368 generation code then it must be being called from the 13369 INITIAL_ELIMINATION_OFFSET macro. */ 13370 if (!(ARM_DOUBLEWORD_ALIGN || reload_completed)) 13371 { 13372 /* In this case we know that we are being asked about the elimination 13373 of the arg pointer register. If that register is not being used, 13374 then there are no arguments on the stack, and we do not have to 13375 worry that a far jump might force the prologue to push the link 13376 register, changing the stack offsets. In this case we can just 13377 return false, since the presence of far jumps in the function will 13378 not affect stack offsets. 13379 13380 If the arg pointer is live (or if it was live, but has now been 13381 eliminated and so set to dead) then we do have to test to see if 13382 the function might contain a far jump. This test can lead to some 13383 false negatives, since before reload is completed, then length of 13384 branch instructions is not known, so gcc defaults to returning their 13385 longest length, which in turn sets the far jump attribute to true. 13386 13387 A false negative will not result in bad code being generated, but it 13388 will result in a needless push and pop of the link register. We 13389 hope that this does not occur too often. 13390 13391 If we need doubleword stack alignment this could affect the other 13392 elimination offsets so we can't risk getting it wrong. */ 13393 if (regs_ever_live [ARG_POINTER_REGNUM]) 13394 cfun->machine->arg_pointer_live = 1; 13395 else if (!cfun->machine->arg_pointer_live) 13396 return 0; 13397 } 13398 13399 /* Check to see if the function contains a branch 13400 insn with the far jump attribute set. */ 13401 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 13402 { 13403 if (GET_CODE (insn) == JUMP_INSN 13404 /* Ignore tablejump patterns. */ 13405 && GET_CODE (PATTERN (insn)) != ADDR_VEC 13406 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC 13407 && get_attr_far_jump (insn) == FAR_JUMP_YES 13408 ) 13409 { 13410 /* Record the fact that we have decided that 13411 the function does use far jumps. */ 13412 cfun->machine->far_jump_used = 1; 13413 return 1; 13414 } 13415 } 13416 13417 return 0; 13418} 13419 13420/* Return nonzero if FUNC must be entered in ARM mode. */ 13421int 13422is_called_in_ARM_mode (tree func) 13423{ 13424 gcc_assert (TREE_CODE (func) == FUNCTION_DECL); 13425 13426 /* Ignore the problem about functions whose address is taken. */ 13427 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) 13428 return TRUE; 13429 13430#ifdef ARM_PE 13431 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; 13432#else 13433 return FALSE; 13434#endif 13435} 13436 13437/* The bits which aren't usefully expanded as rtl. */ 13438const char * 13439thumb_unexpanded_epilogue (void) 13440{ 13441 int regno; 13442 unsigned long live_regs_mask = 0; 13443 int high_regs_pushed = 0; 13444 int had_to_push_lr; 13445 int size; 13446 13447 if (return_used_this_function) 13448 return ""; 13449 13450 if (IS_NAKED (arm_current_func_type ())) 13451 return ""; 13452 13453 live_regs_mask = thumb_compute_save_reg_mask (); 13454 high_regs_pushed = bit_count (live_regs_mask & 0x0f00); 13455 13456 /* If we can deduce the registers used from the function's return value. 13457 This is more reliable that examining regs_ever_live[] because that 13458 will be set if the register is ever used in the function, not just if 13459 the register is used to hold a return value. */ 13460 size = arm_size_return_regs (); 13461 13462 /* The prolog may have pushed some high registers to use as 13463 work registers. e.g. the testsuite file: 13464 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c 13465 compiles to produce: 13466 push {r4, r5, r6, r7, lr} 13467 mov r7, r9 13468 mov r6, r8 13469 push {r6, r7} 13470 as part of the prolog. We have to undo that pushing here. */ 13471 13472 if (high_regs_pushed) 13473 { 13474 unsigned long mask = live_regs_mask & 0xff; 13475 int next_hi_reg; 13476 13477 /* The available low registers depend on the size of the value we are 13478 returning. */ 13479 if (size <= 12) 13480 mask |= 1 << 3; 13481 if (size <= 8) 13482 mask |= 1 << 2; 13483 13484 if (mask == 0) 13485 /* Oh dear! We have no low registers into which we can pop 13486 high registers! */ 13487 internal_error 13488 ("no low registers available for popping high registers"); 13489 13490 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) 13491 if (live_regs_mask & (1 << next_hi_reg)) 13492 break; 13493 13494 while (high_regs_pushed) 13495 { 13496 /* Find lo register(s) into which the high register(s) can 13497 be popped. */ 13498 for (regno = 0; regno <= LAST_LO_REGNUM; regno++) 13499 { 13500 if (mask & (1 << regno)) 13501 high_regs_pushed--; 13502 if (high_regs_pushed == 0) 13503 break; 13504 } 13505 13506 mask &= (2 << regno) - 1; /* A noop if regno == 8 */ 13507 13508 /* Pop the values into the low register(s). */ 13509 thumb_pushpop (asm_out_file, mask, 0, NULL, mask); 13510 13511 /* Move the value(s) into the high registers. */ 13512 for (regno = 0; regno <= LAST_LO_REGNUM; regno++) 13513 { 13514 if (mask & (1 << regno)) 13515 { 13516 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, 13517 regno); 13518 13519 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) 13520 if (live_regs_mask & (1 << next_hi_reg)) 13521 break; 13522 } 13523 } 13524 } 13525 live_regs_mask &= ~0x0f00; 13526 } 13527 13528 had_to_push_lr = (live_regs_mask & (1 << LR_REGNUM)) != 0; 13529 live_regs_mask &= 0xff; 13530 13531 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE) 13532 { 13533 /* Pop the return address into the PC. */ 13534 if (had_to_push_lr) 13535 live_regs_mask |= 1 << PC_REGNUM; 13536 13537 /* Either no argument registers were pushed or a backtrace 13538 structure was created which includes an adjusted stack 13539 pointer, so just pop everything. */ 13540 if (live_regs_mask) 13541 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, 13542 live_regs_mask); 13543 13544 /* We have either just popped the return address into the 13545 PC or it is was kept in LR for the entire function. */ 13546 if (!had_to_push_lr) 13547 thumb_exit (asm_out_file, LR_REGNUM); 13548 } 13549 else 13550 { 13551 /* Pop everything but the return address. */ 13552 if (live_regs_mask) 13553 thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, 13554 live_regs_mask); 13555 13556 if (had_to_push_lr) 13557 { 13558 if (size > 12) 13559 { 13560 /* We have no free low regs, so save one. */ 13561 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", IP_REGNUM, 13562 LAST_ARG_REGNUM); 13563 } 13564 13565 /* Get the return address into a temporary register. */ 13566 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, 13567 1 << LAST_ARG_REGNUM); 13568 13569 if (size > 12) 13570 { 13571 /* Move the return address to lr. */ 13572 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LR_REGNUM, 13573 LAST_ARG_REGNUM); 13574 /* Restore the low register. */ 13575 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, 13576 IP_REGNUM); 13577 regno = LR_REGNUM; 13578 } 13579 else 13580 regno = LAST_ARG_REGNUM; 13581 } 13582 else 13583 regno = LR_REGNUM; 13584 13585 /* Remove the argument registers that were pushed onto the stack. */ 13586 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", 13587 SP_REGNUM, SP_REGNUM, 13588 current_function_pretend_args_size); 13589 13590 thumb_exit (asm_out_file, regno); 13591 } 13592 13593 return ""; 13594} 13595 13596/* Functions to save and restore machine-specific function data. */ 13597static struct machine_function * 13598arm_init_machine_status (void) 13599{ 13600 struct machine_function *machine; 13601 machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); 13602 13603#if ARM_FT_UNKNOWN != 0 13604 machine->func_type = ARM_FT_UNKNOWN; 13605#endif 13606 return machine; 13607} 13608 13609/* Return an RTX indicating where the return address to the 13610 calling function can be found. */ 13611rtx 13612arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) 13613{ 13614 if (count != 0) 13615 return NULL_RTX; 13616 13617 return get_hard_reg_initial_val (Pmode, LR_REGNUM); 13618} 13619 13620/* Do anything needed before RTL is emitted for each function. */ 13621void 13622arm_init_expanders (void) 13623{ 13624 /* Arrange to initialize and mark the machine per-function status. */ 13625 init_machine_status = arm_init_machine_status; 13626 13627 /* This is to stop the combine pass optimizing away the alignment 13628 adjustment of va_arg. */ 13629 /* ??? It is claimed that this should not be necessary. */ 13630 if (cfun) 13631 mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); 13632} 13633 13634 13635/* Like arm_compute_initial_elimination offset. Simpler because there 13636 isn't an ABI specified frame pointer for Thumb. Instead, we set it 13637 to point at the base of the local variables after static stack 13638 space for a function has been allocated. */ 13639 13640HOST_WIDE_INT 13641thumb_compute_initial_elimination_offset (unsigned int from, unsigned int to) 13642{ 13643 arm_stack_offsets *offsets; 13644 13645 offsets = arm_get_frame_offsets (); 13646 13647 switch (from) 13648 { 13649 case ARG_POINTER_REGNUM: 13650 switch (to) 13651 { 13652 case STACK_POINTER_REGNUM: 13653 return offsets->outgoing_args - offsets->saved_args; 13654 13655 case FRAME_POINTER_REGNUM: 13656 return offsets->soft_frame - offsets->saved_args; 13657 13658 case ARM_HARD_FRAME_POINTER_REGNUM: 13659 return offsets->saved_regs - offsets->saved_args; 13660 13661 case THUMB_HARD_FRAME_POINTER_REGNUM: 13662 return offsets->locals_base - offsets->saved_args; 13663 13664 default: 13665 gcc_unreachable (); 13666 } 13667 break; 13668 13669 case FRAME_POINTER_REGNUM: 13670 switch (to) 13671 { 13672 case STACK_POINTER_REGNUM: 13673 return offsets->outgoing_args - offsets->soft_frame; 13674 13675 case ARM_HARD_FRAME_POINTER_REGNUM: 13676 return offsets->saved_regs - offsets->soft_frame; 13677 13678 case THUMB_HARD_FRAME_POINTER_REGNUM: 13679 return offsets->locals_base - offsets->soft_frame; 13680 13681 default: 13682 gcc_unreachable (); 13683 } 13684 break; 13685 13686 default: 13687 gcc_unreachable (); 13688 } 13689} 13690 13691 13692/* Generate the rest of a function's prologue. */ 13693void 13694thumb_expand_prologue (void) 13695{ 13696 rtx insn, dwarf; 13697 13698 HOST_WIDE_INT amount; 13699 arm_stack_offsets *offsets; 13700 unsigned long func_type; 13701 int regno; 13702 unsigned long live_regs_mask; 13703 13704 func_type = arm_current_func_type (); 13705 13706 /* Naked functions don't have prologues. */ 13707 if (IS_NAKED (func_type)) 13708 return; 13709 13710 if (IS_INTERRUPT (func_type)) 13711 { 13712 error ("interrupt Service Routines cannot be coded in Thumb mode"); 13713 return; 13714 } 13715 13716 live_regs_mask = thumb_compute_save_reg_mask (); 13717 /* Load the pic register before setting the frame pointer, 13718 so we can use r7 as a temporary work register. */ 13719 if (flag_pic && arm_pic_register != INVALID_REGNUM) 13720 arm_load_pic_register (live_regs_mask); 13721 13722 if (!frame_pointer_needed && CALLER_INTERWORKING_SLOT_SIZE > 0) 13723 emit_move_insn (gen_rtx_REG (Pmode, ARM_HARD_FRAME_POINTER_REGNUM), 13724 stack_pointer_rtx); 13725 13726 offsets = arm_get_frame_offsets (); 13727 amount = offsets->outgoing_args - offsets->saved_regs; 13728 if (amount) 13729 { 13730 if (amount < 512) 13731 { 13732 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 13733 GEN_INT (- amount))); 13734 RTX_FRAME_RELATED_P (insn) = 1; 13735 } 13736 else 13737 { 13738 rtx reg; 13739 13740 /* The stack decrement is too big for an immediate value in a single 13741 insn. In theory we could issue multiple subtracts, but after 13742 three of them it becomes more space efficient to place the full 13743 value in the constant pool and load into a register. (Also the 13744 ARM debugger really likes to see only one stack decrement per 13745 function). So instead we look for a scratch register into which 13746 we can load the decrement, and then we subtract this from the 13747 stack pointer. Unfortunately on the thumb the only available 13748 scratch registers are the argument registers, and we cannot use 13749 these as they may hold arguments to the function. Instead we 13750 attempt to locate a call preserved register which is used by this 13751 function. If we can find one, then we know that it will have 13752 been pushed at the start of the prologue and so we can corrupt 13753 it now. */ 13754 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) 13755 if (live_regs_mask & (1 << regno) 13756 && !(frame_pointer_needed 13757 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM))) 13758 break; 13759 13760 if (regno > LAST_LO_REGNUM) /* Very unlikely. */ 13761 { 13762 rtx spare = gen_rtx_REG (SImode, IP_REGNUM); 13763 13764 /* Choose an arbitrary, non-argument low register. */ 13765 reg = gen_rtx_REG (SImode, LAST_LO_REGNUM); 13766 13767 /* Save it by copying it into a high, scratch register. */ 13768 emit_insn (gen_movsi (spare, reg)); 13769 /* Add a USE to stop propagate_one_insn() from barfing. */ 13770 emit_insn (gen_prologue_use (spare)); 13771 13772 /* Decrement the stack. */ 13773 emit_insn (gen_movsi (reg, GEN_INT (- amount))); 13774 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, 13775 stack_pointer_rtx, reg)); 13776 RTX_FRAME_RELATED_P (insn) = 1; 13777 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, 13778 plus_constant (stack_pointer_rtx, 13779 -amount)); 13780 RTX_FRAME_RELATED_P (dwarf) = 1; 13781 REG_NOTES (insn) 13782 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, 13783 REG_NOTES (insn)); 13784 13785 /* Restore the low register's original value. */ 13786 emit_insn (gen_movsi (reg, spare)); 13787 13788 /* Emit a USE of the restored scratch register, so that flow 13789 analysis will not consider the restore redundant. The 13790 register won't be used again in this function and isn't 13791 restored by the epilogue. */ 13792 emit_insn (gen_prologue_use (reg)); 13793 } 13794 else 13795 { 13796 reg = gen_rtx_REG (SImode, regno); 13797 13798 emit_insn (gen_movsi (reg, GEN_INT (- amount))); 13799 13800 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, 13801 stack_pointer_rtx, reg)); 13802 RTX_FRAME_RELATED_P (insn) = 1; 13803 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, 13804 plus_constant (stack_pointer_rtx, 13805 -amount)); 13806 RTX_FRAME_RELATED_P (dwarf) = 1; 13807 REG_NOTES (insn) 13808 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, 13809 REG_NOTES (insn)); 13810 } 13811 } 13812 } 13813 13814 if (frame_pointer_needed) 13815 { 13816 amount = offsets->outgoing_args - offsets->locals_base; 13817 13818 if (amount < 1024) 13819 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, 13820 stack_pointer_rtx, GEN_INT (amount))); 13821 else 13822 { 13823 emit_insn (gen_movsi (hard_frame_pointer_rtx, GEN_INT (amount))); 13824 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, 13825 hard_frame_pointer_rtx, 13826 stack_pointer_rtx)); 13827 dwarf = gen_rtx_SET (VOIDmode, hard_frame_pointer_rtx, 13828 plus_constant (stack_pointer_rtx, amount)); 13829 RTX_FRAME_RELATED_P (dwarf) = 1; 13830 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, 13831 REG_NOTES (insn)); 13832 } 13833 13834 RTX_FRAME_RELATED_P (insn) = 1; 13835 } 13836 13837 /* If we are profiling, make sure no instructions are scheduled before 13838 the call to mcount. Similarly if the user has requested no 13839 scheduling in the prolog. Similarly if we want non-call exceptions 13840 using the EABI unwinder, to prevent faulting instructions from being 13841 swapped with a stack adjustment. */ 13842 if (current_function_profile || !TARGET_SCHED_PROLOG 13843 || (ARM_EABI_UNWIND_TABLES && flag_non_call_exceptions)) 13844 emit_insn (gen_blockage ()); 13845 13846 cfun->machine->lr_save_eliminated = !thumb_force_lr_save (); 13847 if (live_regs_mask & 0xff) 13848 cfun->machine->lr_save_eliminated = 0; 13849 13850 /* If the link register is being kept alive, with the return address in it, 13851 then make sure that it does not get reused by the ce2 pass. */ 13852 if (cfun->machine->lr_save_eliminated) 13853 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM))); 13854} 13855 13856 13857void 13858thumb_expand_epilogue (void) 13859{ 13860 HOST_WIDE_INT amount; 13861 arm_stack_offsets *offsets; 13862 int regno; 13863 13864 /* Naked functions don't have prologues. */ 13865 if (IS_NAKED (arm_current_func_type ())) 13866 return; 13867 13868 offsets = arm_get_frame_offsets (); 13869 amount = offsets->outgoing_args - offsets->saved_regs; 13870 13871 if (frame_pointer_needed) 13872 { 13873 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); 13874 amount = offsets->locals_base - offsets->saved_regs; 13875 } 13876 13877 if (amount) 13878 { 13879 if (amount < 512) 13880 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 13881 GEN_INT (amount))); 13882 else 13883 { 13884 /* r3 is always free in the epilogue. */ 13885 rtx reg = gen_rtx_REG (SImode, LAST_ARG_REGNUM); 13886 13887 emit_insn (gen_movsi (reg, GEN_INT (amount))); 13888 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); 13889 } 13890 } 13891 13892 /* Emit a USE (stack_pointer_rtx), so that 13893 the stack adjustment will not be deleted. */ 13894 emit_insn (gen_prologue_use (stack_pointer_rtx)); 13895 13896 if (current_function_profile || !TARGET_SCHED_PROLOG) 13897 emit_insn (gen_blockage ()); 13898 13899 /* Emit a clobber for each insn that will be restored in the epilogue, 13900 so that flow2 will get register lifetimes correct. */ 13901 for (regno = 0; regno < 13; regno++) 13902 if (regs_ever_live[regno] && !call_used_regs[regno]) 13903 emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno))); 13904 13905 if (! regs_ever_live[LR_REGNUM]) 13906 emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM))); 13907} 13908 13909static void 13910thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 13911{ 13912 unsigned long live_regs_mask = 0; 13913 unsigned long l_mask; 13914 unsigned high_regs_pushed = 0; 13915 int cfa_offset = 0; 13916 int regno; 13917 13918 if (IS_NAKED (arm_current_func_type ())) 13919 return; 13920 13921 if (is_called_in_ARM_mode (current_function_decl)) 13922 { 13923 const char * name; 13924 13925 gcc_assert (GET_CODE (DECL_RTL (current_function_decl)) == MEM); 13926 gcc_assert (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) 13927 == SYMBOL_REF); 13928 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 13929 13930 /* Generate code sequence to switch us into Thumb mode. */ 13931 /* The .code 32 directive has already been emitted by 13932 ASM_DECLARE_FUNCTION_NAME. */ 13933 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); 13934 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); 13935 13936 /* Generate a label, so that the debugger will notice the 13937 change in instruction sets. This label is also used by 13938 the assembler to bypass the ARM code when this function 13939 is called from a Thumb encoded function elsewhere in the 13940 same file. Hence the definition of STUB_NAME here must 13941 agree with the definition in gas/config/tc-arm.c. */ 13942 13943#define STUB_NAME ".real_start_of" 13944 13945 fprintf (f, "\t.code\t16\n"); 13946#ifdef ARM_PE 13947 if (arm_dllexport_name_p (name)) 13948 name = arm_strip_name_encoding (name); 13949#endif 13950 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); 13951 fprintf (f, "\t.thumb_func\n"); 13952 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); 13953 } 13954 13955 if (current_function_pretend_args_size) 13956 { 13957 /* Output unwind directive for the stack adjustment. */ 13958 if (ARM_EABI_UNWIND_TABLES) 13959 fprintf (f, "\t.pad #%d\n", 13960 current_function_pretend_args_size); 13961 13962 if (cfun->machine->uses_anonymous_args) 13963 { 13964 int num_pushes; 13965 13966 fprintf (f, "\tpush\t{"); 13967 13968 num_pushes = ARM_NUM_INTS (current_function_pretend_args_size); 13969 13970 for (regno = LAST_ARG_REGNUM + 1 - num_pushes; 13971 regno <= LAST_ARG_REGNUM; 13972 regno++) 13973 asm_fprintf (f, "%r%s", regno, 13974 regno == LAST_ARG_REGNUM ? "" : ", "); 13975 13976 fprintf (f, "}\n"); 13977 } 13978 else 13979 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", 13980 SP_REGNUM, SP_REGNUM, 13981 current_function_pretend_args_size); 13982 13983 /* We don't need to record the stores for unwinding (would it 13984 help the debugger any if we did?), but record the change in 13985 the stack pointer. */ 13986 if (dwarf2out_do_frame ()) 13987 { 13988 char *l = dwarf2out_cfi_label (); 13989 13990 cfa_offset = cfa_offset + current_function_pretend_args_size; 13991 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); 13992 } 13993 } 13994 13995 /* Get the registers we are going to push. */ 13996 live_regs_mask = thumb_compute_save_reg_mask (); 13997 /* Extract a mask of the ones we can give to the Thumb's push instruction. */ 13998 l_mask = live_regs_mask & 0x40ff; 13999 /* Then count how many other high registers will need to be pushed. */ 14000 high_regs_pushed = bit_count (live_regs_mask & 0x0f00); 14001 14002 if (TARGET_BACKTRACE) 14003 { 14004 unsigned offset; 14005 unsigned work_register; 14006 14007 /* We have been asked to create a stack backtrace structure. 14008 The code looks like this: 14009 14010 0 .align 2 14011 0 func: 14012 0 sub SP, #16 Reserve space for 4 registers. 14013 2 push {R7} Push low registers. 14014 4 add R7, SP, #20 Get the stack pointer before the push. 14015 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). 14016 8 mov R7, PC Get hold of the start of this code plus 12. 14017 10 str R7, [SP, #16] Store it. 14018 12 mov R7, FP Get hold of the current frame pointer. 14019 14 str R7, [SP, #4] Store it. 14020 16 mov R7, LR Get hold of the current return address. 14021 18 str R7, [SP, #12] Store it. 14022 20 add R7, SP, #16 Point at the start of the backtrace structure. 14023 22 mov FP, R7 Put this value into the frame pointer. */ 14024 14025 work_register = thumb_find_work_register (live_regs_mask); 14026 14027 if (ARM_EABI_UNWIND_TABLES) 14028 asm_fprintf (f, "\t.pad #16\n"); 14029 14030 asm_fprintf 14031 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", 14032 SP_REGNUM, SP_REGNUM); 14033 14034 if (dwarf2out_do_frame ()) 14035 { 14036 char *l = dwarf2out_cfi_label (); 14037 14038 cfa_offset = cfa_offset + 16; 14039 dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); 14040 } 14041 14042 if (l_mask) 14043 { 14044 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); 14045 offset = bit_count (l_mask) * UNITS_PER_WORD; 14046 } 14047 else 14048 offset = 0; 14049 14050 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, 14051 offset + 16 + current_function_pretend_args_size); 14052 14053 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 14054 offset + 4); 14055 14056 /* Make sure that the instruction fetching the PC is in the right place 14057 to calculate "start of backtrace creation code + 12". */ 14058 if (l_mask) 14059 { 14060 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); 14061 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 14062 offset + 12); 14063 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, 14064 ARM_HARD_FRAME_POINTER_REGNUM); 14065 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 14066 offset); 14067 } 14068 else 14069 { 14070 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, 14071 ARM_HARD_FRAME_POINTER_REGNUM); 14072 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 14073 offset); 14074 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); 14075 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 14076 offset + 12); 14077 } 14078 14079 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); 14080 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 14081 offset + 8); 14082 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, 14083 offset + 12); 14084 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", 14085 ARM_HARD_FRAME_POINTER_REGNUM, work_register); 14086 } 14087 /* Optimization: If we are not pushing any low registers but we are going 14088 to push some high registers then delay our first push. This will just 14089 be a push of LR and we can combine it with the push of the first high 14090 register. */ 14091 else if ((l_mask & 0xff) != 0 14092 || (high_regs_pushed == 0 && l_mask)) 14093 thumb_pushpop (f, l_mask, 1, &cfa_offset, l_mask); 14094 14095 if (high_regs_pushed) 14096 { 14097 unsigned pushable_regs; 14098 unsigned next_hi_reg; 14099 14100 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) 14101 if (live_regs_mask & (1 << next_hi_reg)) 14102 break; 14103 14104 pushable_regs = l_mask & 0xff; 14105 14106 if (pushable_regs == 0) 14107 pushable_regs = 1 << thumb_find_work_register (live_regs_mask); 14108 14109 while (high_regs_pushed > 0) 14110 { 14111 unsigned long real_regs_mask = 0; 14112 14113 for (regno = LAST_LO_REGNUM; regno >= 0; regno --) 14114 { 14115 if (pushable_regs & (1 << regno)) 14116 { 14117 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); 14118 14119 high_regs_pushed --; 14120 real_regs_mask |= (1 << next_hi_reg); 14121 14122 if (high_regs_pushed) 14123 { 14124 for (next_hi_reg --; next_hi_reg > LAST_LO_REGNUM; 14125 next_hi_reg --) 14126 if (live_regs_mask & (1 << next_hi_reg)) 14127 break; 14128 } 14129 else 14130 { 14131 pushable_regs &= ~((1 << regno) - 1); 14132 break; 14133 } 14134 } 14135 } 14136 14137 /* If we had to find a work register and we have not yet 14138 saved the LR then add it to the list of regs to push. */ 14139 if (l_mask == (1 << LR_REGNUM)) 14140 { 14141 thumb_pushpop (f, pushable_regs | (1 << LR_REGNUM), 14142 1, &cfa_offset, 14143 real_regs_mask | (1 << LR_REGNUM)); 14144 l_mask = 0; 14145 } 14146 else 14147 thumb_pushpop (f, pushable_regs, 1, &cfa_offset, real_regs_mask); 14148 } 14149 } 14150} 14151 14152/* Handle the case of a double word load into a low register from 14153 a computed memory address. The computed address may involve a 14154 register which is overwritten by the load. */ 14155const char * 14156thumb_load_double_from_address (rtx *operands) 14157{ 14158 rtx addr; 14159 rtx base; 14160 rtx offset; 14161 rtx arg1; 14162 rtx arg2; 14163 14164 gcc_assert (GET_CODE (operands[0]) == REG); 14165 gcc_assert (GET_CODE (operands[1]) == MEM); 14166 14167 /* Get the memory address. */ 14168 addr = XEXP (operands[1], 0); 14169 14170 /* Work out how the memory address is computed. */ 14171 switch (GET_CODE (addr)) 14172 { 14173 case REG: 14174 operands[2] = adjust_address (operands[1], SImode, 4); 14175 14176 if (REGNO (operands[0]) == REGNO (addr)) 14177 { 14178 output_asm_insn ("ldr\t%H0, %2", operands); 14179 output_asm_insn ("ldr\t%0, %1", operands); 14180 } 14181 else 14182 { 14183 output_asm_insn ("ldr\t%0, %1", operands); 14184 output_asm_insn ("ldr\t%H0, %2", operands); 14185 } 14186 break; 14187 14188 case CONST: 14189 /* Compute <address> + 4 for the high order load. */ 14190 operands[2] = adjust_address (operands[1], SImode, 4); 14191 14192 output_asm_insn ("ldr\t%0, %1", operands); 14193 output_asm_insn ("ldr\t%H0, %2", operands); 14194 break; 14195 14196 case PLUS: 14197 arg1 = XEXP (addr, 0); 14198 arg2 = XEXP (addr, 1); 14199 14200 if (CONSTANT_P (arg1)) 14201 base = arg2, offset = arg1; 14202 else 14203 base = arg1, offset = arg2; 14204 14205 gcc_assert (GET_CODE (base) == REG); 14206 14207 /* Catch the case of <address> = <reg> + <reg> */ 14208 if (GET_CODE (offset) == REG) 14209 { 14210 int reg_offset = REGNO (offset); 14211 int reg_base = REGNO (base); 14212 int reg_dest = REGNO (operands[0]); 14213 14214 /* Add the base and offset registers together into the 14215 higher destination register. */ 14216 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", 14217 reg_dest + 1, reg_base, reg_offset); 14218 14219 /* Load the lower destination register from the address in 14220 the higher destination register. */ 14221 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", 14222 reg_dest, reg_dest + 1); 14223 14224 /* Load the higher destination register from its own address 14225 plus 4. */ 14226 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", 14227 reg_dest + 1, reg_dest + 1); 14228 } 14229 else 14230 { 14231 /* Compute <address> + 4 for the high order load. */ 14232 operands[2] = adjust_address (operands[1], SImode, 4); 14233 14234 /* If the computed address is held in the low order register 14235 then load the high order register first, otherwise always 14236 load the low order register first. */ 14237 if (REGNO (operands[0]) == REGNO (base)) 14238 { 14239 output_asm_insn ("ldr\t%H0, %2", operands); 14240 output_asm_insn ("ldr\t%0, %1", operands); 14241 } 14242 else 14243 { 14244 output_asm_insn ("ldr\t%0, %1", operands); 14245 output_asm_insn ("ldr\t%H0, %2", operands); 14246 } 14247 } 14248 break; 14249 14250 case LABEL_REF: 14251 /* With no registers to worry about we can just load the value 14252 directly. */ 14253 operands[2] = adjust_address (operands[1], SImode, 4); 14254 14255 output_asm_insn ("ldr\t%H0, %2", operands); 14256 output_asm_insn ("ldr\t%0, %1", operands); 14257 break; 14258 14259 default: 14260 gcc_unreachable (); 14261 } 14262 14263 return ""; 14264} 14265 14266const char * 14267thumb_output_move_mem_multiple (int n, rtx *operands) 14268{ 14269 rtx tmp; 14270 14271 switch (n) 14272 { 14273 case 2: 14274 if (REGNO (operands[4]) > REGNO (operands[5])) 14275 { 14276 tmp = operands[4]; 14277 operands[4] = operands[5]; 14278 operands[5] = tmp; 14279 } 14280 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); 14281 output_asm_insn ("stmia\t%0!, {%4, %5}", operands); 14282 break; 14283 14284 case 3: 14285 if (REGNO (operands[4]) > REGNO (operands[5])) 14286 { 14287 tmp = operands[4]; 14288 operands[4] = operands[5]; 14289 operands[5] = tmp; 14290 } 14291 if (REGNO (operands[5]) > REGNO (operands[6])) 14292 { 14293 tmp = operands[5]; 14294 operands[5] = operands[6]; 14295 operands[6] = tmp; 14296 } 14297 if (REGNO (operands[4]) > REGNO (operands[5])) 14298 { 14299 tmp = operands[4]; 14300 operands[4] = operands[5]; 14301 operands[5] = tmp; 14302 } 14303 14304 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); 14305 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); 14306 break; 14307 14308 default: 14309 gcc_unreachable (); 14310 } 14311 14312 return ""; 14313} 14314 14315/* Output a call-via instruction for thumb state. */ 14316const char * 14317thumb_call_via_reg (rtx reg) 14318{ 14319 int regno = REGNO (reg); 14320 rtx *labelp; 14321 14322 gcc_assert (regno < LR_REGNUM); 14323 14324 /* If we are in the normal text section we can use a single instance 14325 per compilation unit. If we are doing function sections, then we need 14326 an entry per section, since we can't rely on reachability. */ 14327 if (in_section == text_section) 14328 { 14329 thumb_call_reg_needed = 1; 14330 14331 if (thumb_call_via_label[regno] == NULL) 14332 thumb_call_via_label[regno] = gen_label_rtx (); 14333 labelp = thumb_call_via_label + regno; 14334 } 14335 else 14336 { 14337 if (cfun->machine->call_via[regno] == NULL) 14338 cfun->machine->call_via[regno] = gen_label_rtx (); 14339 labelp = cfun->machine->call_via + regno; 14340 } 14341 14342 output_asm_insn ("bl\t%a0", labelp); 14343 return ""; 14344} 14345 14346/* Routines for generating rtl. */ 14347void 14348thumb_expand_movmemqi (rtx *operands) 14349{ 14350 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); 14351 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); 14352 HOST_WIDE_INT len = INTVAL (operands[2]); 14353 HOST_WIDE_INT offset = 0; 14354 14355 while (len >= 12) 14356 { 14357 emit_insn (gen_movmem12b (out, in, out, in)); 14358 len -= 12; 14359 } 14360 14361 if (len >= 8) 14362 { 14363 emit_insn (gen_movmem8b (out, in, out, in)); 14364 len -= 8; 14365 } 14366 14367 if (len >= 4) 14368 { 14369 rtx reg = gen_reg_rtx (SImode); 14370 emit_insn (gen_movsi (reg, gen_rtx_MEM (SImode, in))); 14371 emit_insn (gen_movsi (gen_rtx_MEM (SImode, out), reg)); 14372 len -= 4; 14373 offset += 4; 14374 } 14375 14376 if (len >= 2) 14377 { 14378 rtx reg = gen_reg_rtx (HImode); 14379 emit_insn (gen_movhi (reg, gen_rtx_MEM (HImode, 14380 plus_constant (in, offset)))); 14381 emit_insn (gen_movhi (gen_rtx_MEM (HImode, plus_constant (out, offset)), 14382 reg)); 14383 len -= 2; 14384 offset += 2; 14385 } 14386 14387 if (len) 14388 { 14389 rtx reg = gen_reg_rtx (QImode); 14390 emit_insn (gen_movqi (reg, gen_rtx_MEM (QImode, 14391 plus_constant (in, offset)))); 14392 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (out, offset)), 14393 reg)); 14394 } 14395} 14396 14397void 14398thumb_reload_out_hi (rtx *operands) 14399{ 14400 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); 14401} 14402 14403/* Handle reading a half-word from memory during reload. */ 14404void 14405thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) 14406{ 14407 gcc_unreachable (); 14408} 14409 14410/* Return the length of a function name prefix 14411 that starts with the character 'c'. */ 14412static int 14413arm_get_strip_length (int c) 14414{ 14415 switch (c) 14416 { 14417 ARM_NAME_ENCODING_LENGTHS 14418 default: return 0; 14419 } 14420} 14421 14422/* Return a pointer to a function's name with any 14423 and all prefix encodings stripped from it. */ 14424const char * 14425arm_strip_name_encoding (const char *name) 14426{ 14427 int skip; 14428 14429 while ((skip = arm_get_strip_length (* name))) 14430 name += skip; 14431 14432 return name; 14433} 14434 14435/* If there is a '*' anywhere in the name's prefix, then 14436 emit the stripped name verbatim, otherwise prepend an 14437 underscore if leading underscores are being used. */ 14438void 14439arm_asm_output_labelref (FILE *stream, const char *name) 14440{ 14441 int skip; 14442 int verbatim = 0; 14443 14444 while ((skip = arm_get_strip_length (* name))) 14445 { 14446 verbatim |= (*name == '*'); 14447 name += skip; 14448 } 14449 14450 if (verbatim) 14451 fputs (name, stream); 14452 else 14453 asm_fprintf (stream, "%U%s", name); 14454} 14455 14456static void 14457arm_file_end (void) 14458{ 14459 int regno; 14460 14461 if (! thumb_call_reg_needed) 14462 return; 14463 14464 switch_to_section (text_section); 14465 asm_fprintf (asm_out_file, "\t.code 16\n"); 14466 ASM_OUTPUT_ALIGN (asm_out_file, 1); 14467 14468 for (regno = 0; regno < LR_REGNUM; regno++) 14469 { 14470 rtx label = thumb_call_via_label[regno]; 14471 14472 if (label != 0) 14473 { 14474 targetm.asm_out.internal_label (asm_out_file, "L", 14475 CODE_LABEL_NUMBER (label)); 14476 asm_fprintf (asm_out_file, "\tbx\t%r\n", regno); 14477 } 14478 } 14479} 14480 14481rtx aof_pic_label; 14482 14483#ifdef AOF_ASSEMBLER 14484/* Special functions only needed when producing AOF syntax assembler. */ 14485 14486struct pic_chain 14487{ 14488 struct pic_chain * next; 14489 const char * symname; 14490}; 14491 14492static struct pic_chain * aof_pic_chain = NULL; 14493 14494rtx 14495aof_pic_entry (rtx x) 14496{ 14497 struct pic_chain ** chainp; 14498 int offset; 14499 14500 if (aof_pic_label == NULL_RTX) 14501 { 14502 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons"); 14503 } 14504 14505 for (offset = 0, chainp = &aof_pic_chain; *chainp; 14506 offset += 4, chainp = &(*chainp)->next) 14507 if ((*chainp)->symname == XSTR (x, 0)) 14508 return plus_constant (aof_pic_label, offset); 14509 14510 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain)); 14511 (*chainp)->next = NULL; 14512 (*chainp)->symname = XSTR (x, 0); 14513 return plus_constant (aof_pic_label, offset); 14514} 14515 14516void 14517aof_dump_pic_table (FILE *f) 14518{ 14519 struct pic_chain * chain; 14520 14521 if (aof_pic_chain == NULL) 14522 return; 14523 14524 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n", 14525 PIC_OFFSET_TABLE_REGNUM, 14526 PIC_OFFSET_TABLE_REGNUM); 14527 fputs ("|x$adcons|\n", f); 14528 14529 for (chain = aof_pic_chain; chain; chain = chain->next) 14530 { 14531 fputs ("\tDCD\t", f); 14532 assemble_name (f, chain->symname); 14533 fputs ("\n", f); 14534 } 14535} 14536 14537int arm_text_section_count = 1; 14538 14539/* A get_unnamed_section callback for switching to the text section. */ 14540 14541static void 14542aof_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED) 14543{ 14544 fprintf (asm_out_file, "\tAREA |C$$code%d|, CODE, READONLY", 14545 arm_text_section_count++); 14546 if (flag_pic) 14547 fprintf (asm_out_file, ", PIC, REENTRANT"); 14548 fprintf (asm_out_file, "\n"); 14549} 14550 14551static int arm_data_section_count = 1; 14552 14553/* A get_unnamed_section callback for switching to the data section. */ 14554 14555static void 14556aof_output_data_section_asm_op (const void *data ATTRIBUTE_UNUSED) 14557{ 14558 fprintf (asm_out_file, "\tAREA |C$$data%d|, DATA\n", 14559 arm_data_section_count++); 14560} 14561 14562/* Implement TARGET_ASM_INIT_SECTIONS. 14563 14564 AOF Assembler syntax is a nightmare when it comes to areas, since once 14565 we change from one area to another, we can't go back again. Instead, 14566 we must create a new area with the same attributes and add the new output 14567 to that. Unfortunately, there is nothing we can do here to guarantee that 14568 two areas with the same attributes will be linked adjacently in the 14569 resulting executable, so we have to be careful not to do pc-relative 14570 addressing across such boundaries. */ 14571 14572static void 14573aof_asm_init_sections (void) 14574{ 14575 text_section = get_unnamed_section (SECTION_CODE, 14576 aof_output_text_section_asm_op, NULL); 14577 data_section = get_unnamed_section (SECTION_WRITE, 14578 aof_output_data_section_asm_op, NULL); 14579 readonly_data_section = text_section; 14580} 14581 14582void 14583zero_init_section (void) 14584{ 14585 static int zero_init_count = 1; 14586 14587 fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", zero_init_count++); 14588 in_section = NULL; 14589} 14590 14591/* The AOF assembler is religiously strict about declarations of 14592 imported and exported symbols, so that it is impossible to declare 14593 a function as imported near the beginning of the file, and then to 14594 export it later on. It is, however, possible to delay the decision 14595 until all the functions in the file have been compiled. To get 14596 around this, we maintain a list of the imports and exports, and 14597 delete from it any that are subsequently defined. At the end of 14598 compilation we spit the remainder of the list out before the END 14599 directive. */ 14600 14601struct import 14602{ 14603 struct import * next; 14604 const char * name; 14605}; 14606 14607static struct import * imports_list = NULL; 14608 14609void 14610aof_add_import (const char *name) 14611{ 14612 struct import * new; 14613 14614 for (new = imports_list; new; new = new->next) 14615 if (new->name == name) 14616 return; 14617 14618 new = (struct import *) xmalloc (sizeof (struct import)); 14619 new->next = imports_list; 14620 imports_list = new; 14621 new->name = name; 14622} 14623 14624void 14625aof_delete_import (const char *name) 14626{ 14627 struct import ** old; 14628 14629 for (old = &imports_list; *old; old = & (*old)->next) 14630 { 14631 if ((*old)->name == name) 14632 { 14633 *old = (*old)->next; 14634 return; 14635 } 14636 } 14637} 14638 14639int arm_main_function = 0; 14640 14641static void 14642aof_dump_imports (FILE *f) 14643{ 14644 /* The AOF assembler needs this to cause the startup code to be extracted 14645 from the library. Brining in __main causes the whole thing to work 14646 automagically. */ 14647 if (arm_main_function) 14648 { 14649 switch_to_section (text_section); 14650 fputs ("\tIMPORT __main\n", f); 14651 fputs ("\tDCD __main\n", f); 14652 } 14653 14654 /* Now dump the remaining imports. */ 14655 while (imports_list) 14656 { 14657 fprintf (f, "\tIMPORT\t"); 14658 assemble_name (f, imports_list->name); 14659 fputc ('\n', f); 14660 imports_list = imports_list->next; 14661 } 14662} 14663 14664static void 14665aof_globalize_label (FILE *stream, const char *name) 14666{ 14667 default_globalize_label (stream, name); 14668 if (! strcmp (name, "main")) 14669 arm_main_function = 1; 14670} 14671 14672static void 14673aof_file_start (void) 14674{ 14675 fputs ("__r0\tRN\t0\n", asm_out_file); 14676 fputs ("__a1\tRN\t0\n", asm_out_file); 14677 fputs ("__a2\tRN\t1\n", asm_out_file); 14678 fputs ("__a3\tRN\t2\n", asm_out_file); 14679 fputs ("__a4\tRN\t3\n", asm_out_file); 14680 fputs ("__v1\tRN\t4\n", asm_out_file); 14681 fputs ("__v2\tRN\t5\n", asm_out_file); 14682 fputs ("__v3\tRN\t6\n", asm_out_file); 14683 fputs ("__v4\tRN\t7\n", asm_out_file); 14684 fputs ("__v5\tRN\t8\n", asm_out_file); 14685 fputs ("__v6\tRN\t9\n", asm_out_file); 14686 fputs ("__sl\tRN\t10\n", asm_out_file); 14687 fputs ("__fp\tRN\t11\n", asm_out_file); 14688 fputs ("__ip\tRN\t12\n", asm_out_file); 14689 fputs ("__sp\tRN\t13\n", asm_out_file); 14690 fputs ("__lr\tRN\t14\n", asm_out_file); 14691 fputs ("__pc\tRN\t15\n", asm_out_file); 14692 fputs ("__f0\tFN\t0\n", asm_out_file); 14693 fputs ("__f1\tFN\t1\n", asm_out_file); 14694 fputs ("__f2\tFN\t2\n", asm_out_file); 14695 fputs ("__f3\tFN\t3\n", asm_out_file); 14696 fputs ("__f4\tFN\t4\n", asm_out_file); 14697 fputs ("__f5\tFN\t5\n", asm_out_file); 14698 fputs ("__f6\tFN\t6\n", asm_out_file); 14699 fputs ("__f7\tFN\t7\n", asm_out_file); 14700 switch_to_section (text_section); 14701} 14702 14703static void 14704aof_file_end (void) 14705{ 14706 if (flag_pic) 14707 aof_dump_pic_table (asm_out_file); 14708 arm_file_end (); 14709 aof_dump_imports (asm_out_file); 14710 fputs ("\tEND\n", asm_out_file); 14711} 14712#endif /* AOF_ASSEMBLER */ 14713 14714#ifndef ARM_PE 14715/* Symbols in the text segment can be accessed without indirecting via the 14716 constant pool; it may take an extra binary operation, but this is still 14717 faster than indirecting via memory. Don't do this when not optimizing, 14718 since we won't be calculating al of the offsets necessary to do this 14719 simplification. */ 14720 14721static void 14722arm_encode_section_info (tree decl, rtx rtl, int first) 14723{ 14724 /* This doesn't work with AOF syntax, since the string table may be in 14725 a different AREA. */ 14726#ifndef AOF_ASSEMBLER 14727 if (optimize > 0 && TREE_CONSTANT (decl)) 14728 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; 14729#endif 14730 14731 /* If we are referencing a function that is weak then encode a long call 14732 flag in the function name, otherwise if the function is static or 14733 or known to be defined in this file then encode a short call flag. */ 14734 if (first && DECL_P (decl)) 14735 { 14736 if (TREE_CODE (decl) == FUNCTION_DECL && DECL_WEAK (decl)) 14737 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); 14738 else if (! TREE_PUBLIC (decl)) 14739 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); 14740 } 14741 14742 default_encode_section_info (decl, rtl, first); 14743} 14744#endif /* !ARM_PE */ 14745 14746static void 14747arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno) 14748{ 14749 if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno 14750 && !strcmp (prefix, "L")) 14751 { 14752 arm_ccfsm_state = 0; 14753 arm_target_insn = NULL; 14754 } 14755 default_internal_label (stream, prefix, labelno); 14756} 14757 14758/* Output code to add DELTA to the first argument, and then jump 14759 to FUNCTION. Used for C++ multiple inheritance. */ 14760static void 14761arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, 14762 HOST_WIDE_INT delta, 14763 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, 14764 tree function) 14765{ 14766 static int thunk_label = 0; 14767 char label[256]; 14768 char labelpc[256]; 14769 int mi_delta = delta; 14770 const char *const mi_op = mi_delta < 0 ? "sub" : "add"; 14771 int shift = 0; 14772 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) 14773 ? 1 : 0); 14774 if (mi_delta < 0) 14775 mi_delta = - mi_delta; 14776 if (TARGET_THUMB) 14777 { 14778 int labelno = thunk_label++; 14779 ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno); 14780 fputs ("\tldr\tr12, ", file); 14781 assemble_name (file, label); 14782 fputc ('\n', file); 14783 if (flag_pic) 14784 { 14785 /* If we are generating PIC, the ldr instruction below loads 14786 "(target - 7) - .LTHUNKPCn" into r12. The pc reads as 14787 the address of the add + 8, so we have: 14788 14789 r12 = (target - 7) - .LTHUNKPCn + (.LTHUNKPCn + 8) 14790 = target + 1. 14791 14792 Note that we have "+ 1" because some versions of GNU ld 14793 don't set the low bit of the result for R_ARM_REL32 14794 relocations against thumb function symbols. */ 14795 ASM_GENERATE_INTERNAL_LABEL (labelpc, "LTHUNKPC", labelno); 14796 assemble_name (file, labelpc); 14797 fputs (":\n", file); 14798 fputs ("\tadd\tr12, pc, r12\n", file); 14799 } 14800 } 14801 while (mi_delta != 0) 14802 { 14803 if ((mi_delta & (3 << shift)) == 0) 14804 shift += 2; 14805 else 14806 { 14807 asm_fprintf (file, "\t%s\t%r, %r, #%d\n", 14808 mi_op, this_regno, this_regno, 14809 mi_delta & (0xff << shift)); 14810 mi_delta &= ~(0xff << shift); 14811 shift += 8; 14812 } 14813 } 14814 if (TARGET_THUMB) 14815 { 14816 fprintf (file, "\tbx\tr12\n"); 14817 ASM_OUTPUT_ALIGN (file, 2); 14818 assemble_name (file, label); 14819 fputs (":\n", file); 14820 if (flag_pic) 14821 { 14822 /* Output ".word .LTHUNKn-7-.LTHUNKPCn". */ 14823 rtx tem = XEXP (DECL_RTL (function), 0); 14824 tem = gen_rtx_PLUS (GET_MODE (tem), tem, GEN_INT (-7)); 14825 tem = gen_rtx_MINUS (GET_MODE (tem), 14826 tem, 14827 gen_rtx_SYMBOL_REF (Pmode, 14828 ggc_strdup (labelpc))); 14829 assemble_integer (tem, 4, BITS_PER_WORD, 1); 14830 } 14831 else 14832 /* Output ".word .LTHUNKn". */ 14833 assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); 14834 } 14835 else 14836 { 14837 fputs ("\tb\t", file); 14838 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); 14839 if (NEED_PLT_RELOC) 14840 fputs ("(PLT)", file); 14841 fputc ('\n', file); 14842 } 14843} 14844 14845int 14846arm_emit_vector_const (FILE *file, rtx x) 14847{ 14848 int i; 14849 const char * pattern; 14850 14851 gcc_assert (GET_CODE (x) == CONST_VECTOR); 14852 14853 switch (GET_MODE (x)) 14854 { 14855 case V2SImode: pattern = "%08x"; break; 14856 case V4HImode: pattern = "%04x"; break; 14857 case V8QImode: pattern = "%02x"; break; 14858 default: gcc_unreachable (); 14859 } 14860 14861 fprintf (file, "0x"); 14862 for (i = CONST_VECTOR_NUNITS (x); i--;) 14863 { 14864 rtx element; 14865 14866 element = CONST_VECTOR_ELT (x, i); 14867 fprintf (file, pattern, INTVAL (element)); 14868 } 14869 14870 return 1; 14871} 14872 14873const char * 14874arm_output_load_gr (rtx *operands) 14875{ 14876 rtx reg; 14877 rtx offset; 14878 rtx wcgr; 14879 rtx sum; 14880 14881 if (GET_CODE (operands [1]) != MEM 14882 || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS 14883 || GET_CODE (reg = XEXP (sum, 0)) != REG 14884 || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT 14885 || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) 14886 return "wldrw%?\t%0, %1"; 14887 14888 /* Fix up an out-of-range load of a GR register. */ 14889 output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); 14890 wcgr = operands[0]; 14891 operands[0] = reg; 14892 output_asm_insn ("ldr%?\t%0, %1", operands); 14893 14894 operands[0] = wcgr; 14895 operands[1] = reg; 14896 output_asm_insn ("tmcr%?\t%0, %1", operands); 14897 output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg); 14898 14899 return ""; 14900} 14901 14902/* Worker function for TARGET_SETUP_INCOMING_VARARGS. 14903 14904 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last 14905 named arg and all anonymous args onto the stack. 14906 XXX I know the prologue shouldn't be pushing registers, but it is faster 14907 that way. */ 14908 14909static void 14910arm_setup_incoming_varargs (CUMULATIVE_ARGS *cum, 14911 enum machine_mode mode ATTRIBUTE_UNUSED, 14912 tree type ATTRIBUTE_UNUSED, 14913 int *pretend_size, 14914 int second_time ATTRIBUTE_UNUSED) 14915{ 14916 cfun->machine->uses_anonymous_args = 1; 14917 if (cum->nregs < NUM_ARG_REGS) 14918 *pretend_size = (NUM_ARG_REGS - cum->nregs) * UNITS_PER_WORD; 14919} 14920 14921/* Return nonzero if the CONSUMER instruction (a store) does not need 14922 PRODUCER's value to calculate the address. */ 14923 14924int 14925arm_no_early_store_addr_dep (rtx producer, rtx consumer) 14926{ 14927 rtx value = PATTERN (producer); 14928 rtx addr = PATTERN (consumer); 14929 14930 if (GET_CODE (value) == COND_EXEC) 14931 value = COND_EXEC_CODE (value); 14932 if (GET_CODE (value) == PARALLEL) 14933 value = XVECEXP (value, 0, 0); 14934 value = XEXP (value, 0); 14935 if (GET_CODE (addr) == COND_EXEC) 14936 addr = COND_EXEC_CODE (addr); 14937 if (GET_CODE (addr) == PARALLEL) 14938 addr = XVECEXP (addr, 0, 0); 14939 addr = XEXP (addr, 0); 14940 14941 return !reg_overlap_mentioned_p (value, addr); 14942} 14943 14944/* Return nonzero if the CONSUMER instruction (an ALU op) does not 14945 have an early register shift value or amount dependency on the 14946 result of PRODUCER. */ 14947 14948int 14949arm_no_early_alu_shift_dep (rtx producer, rtx consumer) 14950{ 14951 rtx value = PATTERN (producer); 14952 rtx op = PATTERN (consumer); 14953 rtx early_op; 14954 14955 if (GET_CODE (value) == COND_EXEC) 14956 value = COND_EXEC_CODE (value); 14957 if (GET_CODE (value) == PARALLEL) 14958 value = XVECEXP (value, 0, 0); 14959 value = XEXP (value, 0); 14960 if (GET_CODE (op) == COND_EXEC) 14961 op = COND_EXEC_CODE (op); 14962 if (GET_CODE (op) == PARALLEL) 14963 op = XVECEXP (op, 0, 0); 14964 op = XEXP (op, 1); 14965 14966 early_op = XEXP (op, 0); 14967 /* This is either an actual independent shift, or a shift applied to 14968 the first operand of another operation. We want the whole shift 14969 operation. */ 14970 if (GET_CODE (early_op) == REG) 14971 early_op = op; 14972 14973 return !reg_overlap_mentioned_p (value, early_op); 14974} 14975 14976/* Return nonzero if the CONSUMER instruction (an ALU op) does not 14977 have an early register shift value dependency on the result of 14978 PRODUCER. */ 14979 14980int 14981arm_no_early_alu_shift_value_dep (rtx producer, rtx consumer) 14982{ 14983 rtx value = PATTERN (producer); 14984 rtx op = PATTERN (consumer); 14985 rtx early_op; 14986 14987 if (GET_CODE (value) == COND_EXEC) 14988 value = COND_EXEC_CODE (value); 14989 if (GET_CODE (value) == PARALLEL) 14990 value = XVECEXP (value, 0, 0); 14991 value = XEXP (value, 0); 14992 if (GET_CODE (op) == COND_EXEC) 14993 op = COND_EXEC_CODE (op); 14994 if (GET_CODE (op) == PARALLEL) 14995 op = XVECEXP (op, 0, 0); 14996 op = XEXP (op, 1); 14997 14998 early_op = XEXP (op, 0); 14999 15000 /* This is either an actual independent shift, or a shift applied to 15001 the first operand of another operation. We want the value being 15002 shifted, in either case. */ 15003 if (GET_CODE (early_op) != REG) 15004 early_op = XEXP (early_op, 0); 15005 15006 return !reg_overlap_mentioned_p (value, early_op); 15007} 15008 15009/* Return nonzero if the CONSUMER (a mul or mac op) does not 15010 have an early register mult dependency on the result of 15011 PRODUCER. */ 15012 15013int 15014arm_no_early_mul_dep (rtx producer, rtx consumer) 15015{ 15016 rtx value = PATTERN (producer); 15017 rtx op = PATTERN (consumer); 15018 15019 if (GET_CODE (value) == COND_EXEC) 15020 value = COND_EXEC_CODE (value); 15021 if (GET_CODE (value) == PARALLEL) 15022 value = XVECEXP (value, 0, 0); 15023 value = XEXP (value, 0); 15024 if (GET_CODE (op) == COND_EXEC) 15025 op = COND_EXEC_CODE (op); 15026 if (GET_CODE (op) == PARALLEL) 15027 op = XVECEXP (op, 0, 0); 15028 op = XEXP (op, 1); 15029 15030 return (GET_CODE (op) == PLUS 15031 && !reg_overlap_mentioned_p (value, XEXP (op, 0))); 15032} 15033 15034 15035/* We can't rely on the caller doing the proper promotion when 15036 using APCS or ATPCS. */ 15037 15038static bool 15039arm_promote_prototypes (tree t ATTRIBUTE_UNUSED) 15040{ 15041 return !TARGET_AAPCS_BASED; 15042} 15043 15044 15045/* AAPCS based ABIs use short enums by default. */ 15046 15047static bool 15048arm_default_short_enums (void) 15049{ 15050 return TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX; 15051} 15052 15053 15054/* AAPCS requires that anonymous bitfields affect structure alignment. */ 15055 15056static bool 15057arm_align_anon_bitfield (void) 15058{ 15059 return TARGET_AAPCS_BASED; 15060} 15061 15062 15063/* The generic C++ ABI says 64-bit (long long). The EABI says 32-bit. */ 15064 15065static tree 15066arm_cxx_guard_type (void) 15067{ 15068 return TARGET_AAPCS_BASED ? integer_type_node : long_long_integer_type_node; 15069} 15070 15071 15072/* The EABI says test the least significant bit of a guard variable. */ 15073 15074static bool 15075arm_cxx_guard_mask_bit (void) 15076{ 15077 return TARGET_AAPCS_BASED; 15078} 15079 15080 15081/* The EABI specifies that all array cookies are 8 bytes long. */ 15082 15083static tree 15084arm_get_cookie_size (tree type) 15085{ 15086 tree size; 15087 15088 if (!TARGET_AAPCS_BASED) 15089 return default_cxx_get_cookie_size (type); 15090 15091 size = build_int_cst (sizetype, 8); 15092 return size; 15093} 15094 15095 15096/* The EABI says that array cookies should also contain the element size. */ 15097 15098static bool 15099arm_cookie_has_size (void) 15100{ 15101 return TARGET_AAPCS_BASED; 15102} 15103 15104 15105/* The EABI says constructors and destructors should return a pointer to 15106 the object constructed/destroyed. */ 15107 15108static bool 15109arm_cxx_cdtor_returns_this (void) 15110{ 15111 return TARGET_AAPCS_BASED; 15112} 15113 15114/* The EABI says that an inline function may never be the key 15115 method. */ 15116 15117static bool 15118arm_cxx_key_method_may_be_inline (void) 15119{ 15120 return !TARGET_AAPCS_BASED; 15121} 15122 15123static void 15124arm_cxx_determine_class_data_visibility (tree decl) 15125{ 15126 if (!TARGET_AAPCS_BASED) 15127 return; 15128 15129 /* In general, \S 3.2.5.5 of the ARM EABI requires that class data 15130 is exported. However, on systems without dynamic vague linkage, 15131 \S 3.2.5.6 says that COMDAT class data has hidden linkage. */ 15132 if (!TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P && DECL_COMDAT (decl)) 15133 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; 15134 else 15135 DECL_VISIBILITY (decl) = VISIBILITY_DEFAULT; 15136 DECL_VISIBILITY_SPECIFIED (decl) = 1; 15137} 15138 15139static bool 15140arm_cxx_class_data_always_comdat (void) 15141{ 15142 /* \S 3.2.5.4 of the ARM C++ ABI says that class data only have 15143 vague linkage if the class has no key function. */ 15144 return !TARGET_AAPCS_BASED; 15145} 15146 15147 15148/* The EABI says __aeabi_atexit should be used to register static 15149 destructors. */ 15150 15151static bool 15152arm_cxx_use_aeabi_atexit (void) 15153{ 15154 return TARGET_AAPCS_BASED; 15155} 15156 15157 15158void 15159arm_set_return_address (rtx source, rtx scratch) 15160{ 15161 arm_stack_offsets *offsets; 15162 HOST_WIDE_INT delta; 15163 rtx addr; 15164 unsigned long saved_regs; 15165 15166 saved_regs = arm_compute_save_reg_mask (); 15167 15168 if ((saved_regs & (1 << LR_REGNUM)) == 0) 15169 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); 15170 else 15171 { 15172 if (frame_pointer_needed) 15173 addr = plus_constant(hard_frame_pointer_rtx, -4); 15174 else 15175 { 15176 /* LR will be the first saved register. */ 15177 offsets = arm_get_frame_offsets (); 15178 delta = offsets->outgoing_args - (offsets->frame + 4); 15179 15180 15181 if (delta >= 4096) 15182 { 15183 emit_insn (gen_addsi3 (scratch, stack_pointer_rtx, 15184 GEN_INT (delta & ~4095))); 15185 addr = scratch; 15186 delta &= 4095; 15187 } 15188 else 15189 addr = stack_pointer_rtx; 15190 15191 addr = plus_constant (addr, delta); 15192 } 15193 emit_move_insn (gen_frame_mem (Pmode, addr), source); 15194 } 15195} 15196 15197 15198void 15199thumb_set_return_address (rtx source, rtx scratch) 15200{ 15201 arm_stack_offsets *offsets; 15202 HOST_WIDE_INT delta; 15203 int reg; 15204 rtx addr; 15205 unsigned long mask; 15206 15207 emit_insn (gen_rtx_USE (VOIDmode, source)); 15208 15209 mask = thumb_compute_save_reg_mask (); 15210 if (mask & (1 << LR_REGNUM)) 15211 { 15212 offsets = arm_get_frame_offsets (); 15213 15214 /* Find the saved regs. */ 15215 if (frame_pointer_needed) 15216 { 15217 delta = offsets->soft_frame - offsets->saved_args; 15218 reg = THUMB_HARD_FRAME_POINTER_REGNUM; 15219 } 15220 else 15221 { 15222 delta = offsets->outgoing_args - offsets->saved_args; 15223 reg = SP_REGNUM; 15224 } 15225 /* Allow for the stack frame. */ 15226 if (TARGET_BACKTRACE) 15227 delta -= 16; 15228 /* The link register is always the first saved register. */ 15229 delta -= 4; 15230 15231 /* Construct the address. */ 15232 addr = gen_rtx_REG (SImode, reg); 15233 if ((reg != SP_REGNUM && delta >= 128) 15234 || delta >= 1024) 15235 { 15236 emit_insn (gen_movsi (scratch, GEN_INT (delta))); 15237 emit_insn (gen_addsi3 (scratch, scratch, stack_pointer_rtx)); 15238 addr = scratch; 15239 } 15240 else 15241 addr = plus_constant (addr, delta); 15242 15243 emit_move_insn (gen_frame_mem (Pmode, addr), source); 15244 } 15245 else 15246 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); 15247} 15248 15249/* Implements target hook vector_mode_supported_p. */ 15250bool 15251arm_vector_mode_supported_p (enum machine_mode mode) 15252{ 15253 if ((mode == V2SImode) 15254 || (mode == V4HImode) 15255 || (mode == V8QImode)) 15256 return true; 15257 15258 return false; 15259} 15260 15261/* Implement TARGET_SHIFT_TRUNCATION_MASK. SImode shifts use normal 15262 ARM insns and therefore guarantee that the shift count is modulo 256. 15263 DImode shifts (those implemented by lib1funcs.asm or by optabs.c) 15264 guarantee no particular behavior for out-of-range counts. */ 15265 15266static unsigned HOST_WIDE_INT 15267arm_shift_truncation_mask (enum machine_mode mode) 15268{ 15269 return mode == SImode ? 255 : 0; 15270} 15271 15272 15273/* Map internal gcc register numbers to DWARF2 register numbers. */ 15274 15275unsigned int 15276arm_dbx_register_number (unsigned int regno) 15277{ 15278 if (regno < 16) 15279 return regno; 15280 15281 /* TODO: Legacy targets output FPA regs as registers 16-23 for backwards 15282 compatibility. The EABI defines them as registers 96-103. */ 15283 if (IS_FPA_REGNUM (regno)) 15284 return (TARGET_AAPCS_BASED ? 96 : 16) + regno - FIRST_FPA_REGNUM; 15285 15286 if (IS_VFP_REGNUM (regno)) 15287 return 64 + regno - FIRST_VFP_REGNUM; 15288 15289 if (IS_IWMMXT_GR_REGNUM (regno)) 15290 return 104 + regno - FIRST_IWMMXT_GR_REGNUM; 15291 15292 if (IS_IWMMXT_REGNUM (regno)) 15293 return 112 + regno - FIRST_IWMMXT_REGNUM; 15294 15295 gcc_unreachable (); 15296} 15297 15298 15299#ifdef TARGET_UNWIND_INFO 15300/* Emit unwind directives for a store-multiple instruction. This should 15301 only ever be generated by the function prologue code, so we expect it 15302 to have a particular form. */ 15303 15304static void 15305arm_unwind_emit_stm (FILE * asm_out_file, rtx p) 15306{ 15307 int i; 15308 HOST_WIDE_INT offset; 15309 HOST_WIDE_INT nregs; 15310 int reg_size; 15311 unsigned reg; 15312 unsigned lastreg; 15313 rtx e; 15314 15315 /* First insn will adjust the stack pointer. */ 15316 e = XVECEXP (p, 0, 0); 15317 if (GET_CODE (e) != SET 15318 || GET_CODE (XEXP (e, 0)) != REG 15319 || REGNO (XEXP (e, 0)) != SP_REGNUM 15320 || GET_CODE (XEXP (e, 1)) != PLUS) 15321 abort (); 15322 15323 offset = -INTVAL (XEXP (XEXP (e, 1), 1)); 15324 nregs = XVECLEN (p, 0) - 1; 15325 15326 reg = REGNO (XEXP (XVECEXP (p, 0, 1), 1)); 15327 if (reg < 16) 15328 { 15329 /* The function prologue may also push pc, but not annotate it as it is 15330 never restored. We turn this into a stack pointer adjustment. */ 15331 if (nregs * 4 == offset - 4) 15332 { 15333 fprintf (asm_out_file, "\t.pad #4\n"); 15334 offset -= 4; 15335 } 15336 reg_size = 4; 15337 } 15338 else if (IS_VFP_REGNUM (reg)) 15339 { 15340 /* FPA register saves use an additional word. */ 15341 offset -= 4; 15342 reg_size = 8; 15343 } 15344 else if (reg >= FIRST_FPA_REGNUM && reg <= LAST_FPA_REGNUM) 15345 { 15346 /* FPA registers are done differently. */ 15347 asm_fprintf (asm_out_file, "\t.save %r, %wd\n", reg, nregs); 15348 return; 15349 } 15350 else 15351 /* Unknown register type. */ 15352 abort (); 15353 15354 /* If the stack increment doesn't match the size of the saved registers, 15355 something has gone horribly wrong. */ 15356 if (offset != nregs * reg_size) 15357 abort (); 15358 15359 fprintf (asm_out_file, "\t.save {"); 15360 15361 offset = 0; 15362 lastreg = 0; 15363 /* The remaining insns will describe the stores. */ 15364 for (i = 1; i <= nregs; i++) 15365 { 15366 /* Expect (set (mem <addr>) (reg)). 15367 Where <addr> is (reg:SP) or (plus (reg:SP) (const_int)). */ 15368 e = XVECEXP (p, 0, i); 15369 if (GET_CODE (e) != SET 15370 || GET_CODE (XEXP (e, 0)) != MEM 15371 || GET_CODE (XEXP (e, 1)) != REG) 15372 abort (); 15373 15374 reg = REGNO (XEXP (e, 1)); 15375 if (reg < lastreg) 15376 abort (); 15377 15378 if (i != 1) 15379 fprintf (asm_out_file, ", "); 15380 /* We can't use %r for vfp because we need to use the 15381 double precision register names. */ 15382 if (IS_VFP_REGNUM (reg)) 15383 asm_fprintf (asm_out_file, "d%d", (reg - FIRST_VFP_REGNUM) / 2); 15384 else 15385 asm_fprintf (asm_out_file, "%r", reg); 15386 15387#ifdef ENABLE_CHECKING 15388 /* Check that the addresses are consecutive. */ 15389 e = XEXP (XEXP (e, 0), 0); 15390 if (GET_CODE (e) == PLUS) 15391 { 15392 offset += reg_size; 15393 if (GET_CODE (XEXP (e, 0)) != REG 15394 || REGNO (XEXP (e, 0)) != SP_REGNUM 15395 || GET_CODE (XEXP (e, 1)) != CONST_INT 15396 || offset != INTVAL (XEXP (e, 1))) 15397 abort (); 15398 } 15399 else if (i != 1 15400 || GET_CODE (e) != REG 15401 || REGNO (e) != SP_REGNUM) 15402 abort (); 15403#endif 15404 } 15405 fprintf (asm_out_file, "}\n"); 15406} 15407 15408/* Emit unwind directives for a SET. */ 15409 15410static void 15411arm_unwind_emit_set (FILE * asm_out_file, rtx p) 15412{ 15413 rtx e0; 15414 rtx e1; 15415 15416 e0 = XEXP (p, 0); 15417 e1 = XEXP (p, 1); 15418 switch (GET_CODE (e0)) 15419 { 15420 case MEM: 15421 /* Pushing a single register. */ 15422 if (GET_CODE (XEXP (e0, 0)) != PRE_DEC 15423 || GET_CODE (XEXP (XEXP (e0, 0), 0)) != REG 15424 || REGNO (XEXP (XEXP (e0, 0), 0)) != SP_REGNUM) 15425 abort (); 15426 15427 asm_fprintf (asm_out_file, "\t.save "); 15428 if (IS_VFP_REGNUM (REGNO (e1))) 15429 asm_fprintf(asm_out_file, "{d%d}\n", 15430 (REGNO (e1) - FIRST_VFP_REGNUM) / 2); 15431 else 15432 asm_fprintf(asm_out_file, "{%r}\n", REGNO (e1)); 15433 break; 15434 15435 case REG: 15436 if (REGNO (e0) == SP_REGNUM) 15437 { 15438 /* A stack increment. */ 15439 if (GET_CODE (e1) != PLUS 15440 || GET_CODE (XEXP (e1, 0)) != REG 15441 || REGNO (XEXP (e1, 0)) != SP_REGNUM 15442 || GET_CODE (XEXP (e1, 1)) != CONST_INT) 15443 abort (); 15444 15445 asm_fprintf (asm_out_file, "\t.pad #%wd\n", 15446 -INTVAL (XEXP (e1, 1))); 15447 } 15448 else if (REGNO (e0) == HARD_FRAME_POINTER_REGNUM) 15449 { 15450 HOST_WIDE_INT offset; 15451 unsigned reg; 15452 15453 if (GET_CODE (e1) == PLUS) 15454 { 15455 if (GET_CODE (XEXP (e1, 0)) != REG 15456 || GET_CODE (XEXP (e1, 1)) != CONST_INT) 15457 abort (); 15458 reg = REGNO (XEXP (e1, 0)); 15459 offset = INTVAL (XEXP (e1, 1)); 15460 asm_fprintf (asm_out_file, "\t.setfp %r, %r, #%wd\n", 15461 HARD_FRAME_POINTER_REGNUM, reg, 15462 INTVAL (XEXP (e1, 1))); 15463 } 15464 else if (GET_CODE (e1) == REG) 15465 { 15466 reg = REGNO (e1); 15467 asm_fprintf (asm_out_file, "\t.setfp %r, %r\n", 15468 HARD_FRAME_POINTER_REGNUM, reg); 15469 } 15470 else 15471 abort (); 15472 } 15473 else if (GET_CODE (e1) == REG && REGNO (e1) == SP_REGNUM) 15474 { 15475 /* Move from sp to reg. */ 15476 asm_fprintf (asm_out_file, "\t.movsp %r\n", REGNO (e0)); 15477 } 15478 else if (GET_CODE (e1) == PLUS 15479 && GET_CODE (XEXP (e1, 0)) == REG 15480 && REGNO (XEXP (e1, 0)) == SP_REGNUM 15481 && GET_CODE (XEXP (e1, 1)) == CONST_INT) 15482 { 15483 /* Set reg to offset from sp. */ 15484 asm_fprintf (asm_out_file, "\t.movsp %r, #%d\n", 15485 REGNO (e0), (int)INTVAL(XEXP (e1, 1))); 15486 } 15487 else 15488 abort (); 15489 break; 15490 15491 default: 15492 abort (); 15493 } 15494} 15495 15496 15497/* Emit unwind directives for the given insn. */ 15498 15499static void 15500arm_unwind_emit (FILE * asm_out_file, rtx insn) 15501{ 15502 rtx pat; 15503 15504 if (!ARM_EABI_UNWIND_TABLES) 15505 return; 15506 15507 if (GET_CODE (insn) == NOTE || !RTX_FRAME_RELATED_P (insn)) 15508 return; 15509 15510 pat = find_reg_note (insn, REG_FRAME_RELATED_EXPR, NULL_RTX); 15511 if (pat) 15512 pat = XEXP (pat, 0); 15513 else 15514 pat = PATTERN (insn); 15515 15516 switch (GET_CODE (pat)) 15517 { 15518 case SET: 15519 arm_unwind_emit_set (asm_out_file, pat); 15520 break; 15521 15522 case SEQUENCE: 15523 /* Store multiple. */ 15524 arm_unwind_emit_stm (asm_out_file, pat); 15525 break; 15526 15527 default: 15528 abort(); 15529 } 15530} 15531 15532 15533/* Output a reference from a function exception table to the type_info 15534 object X. The EABI specifies that the symbol should be relocated by 15535 an R_ARM_TARGET2 relocation. */ 15536 15537static bool 15538arm_output_ttype (rtx x) 15539{ 15540 fputs ("\t.word\t", asm_out_file); 15541 output_addr_const (asm_out_file, x); 15542 /* Use special relocations for symbol references. */ 15543 if (GET_CODE (x) != CONST_INT) 15544 fputs ("(TARGET2)", asm_out_file); 15545 fputc ('\n', asm_out_file); 15546 15547 return TRUE; 15548} 15549#endif /* TARGET_UNWIND_INFO */ 15550 15551 15552/* Output unwind directives for the start/end of a function. */ 15553 15554void 15555arm_output_fn_unwind (FILE * f, bool prologue) 15556{ 15557 if (!ARM_EABI_UNWIND_TABLES) 15558 return; 15559 15560 if (prologue) 15561 fputs ("\t.fnstart\n", f); 15562 else 15563 fputs ("\t.fnend\n", f); 15564} 15565 15566static bool 15567arm_emit_tls_decoration (FILE *fp, rtx x) 15568{ 15569 enum tls_reloc reloc; 15570 rtx val; 15571 15572 val = XVECEXP (x, 0, 0); 15573 reloc = INTVAL (XVECEXP (x, 0, 1)); 15574 15575 output_addr_const (fp, val); 15576 15577 switch (reloc) 15578 { 15579 case TLS_GD32: 15580 fputs ("(tlsgd)", fp); 15581 break; 15582 case TLS_LDM32: 15583 fputs ("(tlsldm)", fp); 15584 break; 15585 case TLS_LDO32: 15586 fputs ("(tlsldo)", fp); 15587 break; 15588 case TLS_IE32: 15589 fputs ("(gottpoff)", fp); 15590 break; 15591 case TLS_LE32: 15592 fputs ("(tpoff)", fp); 15593 break; 15594 default: 15595 gcc_unreachable (); 15596 } 15597 15598 switch (reloc) 15599 { 15600 case TLS_GD32: 15601 case TLS_LDM32: 15602 case TLS_IE32: 15603 fputs (" + (. - ", fp); 15604 output_addr_const (fp, XVECEXP (x, 0, 2)); 15605 fputs (" - ", fp); 15606 output_addr_const (fp, XVECEXP (x, 0, 3)); 15607 fputc (')', fp); 15608 break; 15609 default: 15610 break; 15611 } 15612 15613 return TRUE; 15614} 15615 15616bool 15617arm_output_addr_const_extra (FILE *fp, rtx x) 15618{ 15619 if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_TLS) 15620 return arm_emit_tls_decoration (fp, x); 15621 else if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PIC_LABEL) 15622 { 15623 char label[256]; 15624 int labelno = INTVAL (XVECEXP (x, 0, 0)); 15625 15626 ASM_GENERATE_INTERNAL_LABEL (label, "LPIC", labelno); 15627 assemble_name_raw (fp, label); 15628 15629 return TRUE; 15630 } 15631 else if (GET_CODE (x) == CONST_VECTOR) 15632 return arm_emit_vector_const (fp, x); 15633 15634 return FALSE; 15635} 15636 15637#include "gt-arm.h" 15638