arm.c revision 107590
1108473Strhodes/* Output routines for GCC for ARM. 2108473Strhodes Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 3108473Strhodes Free Software Foundation, Inc. 4108473Strhodes Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 5230588Ssbruno and Martin Simmons (@harleqn.co.uk). 6108473Strhodes More major hacks by Richard Earnshaw (rearnsha@arm.com). 7108473Strhodes 8108473StrhodesThis file is part of GNU CC. 9108473Strhodes 10111447SruGNU CC is free software; you can redistribute it and/or modify 11108473Strhodesit under the terms of the GNU General Public License as published by 12158762Sbruefferthe Free Software Foundation; either version 2, or (at your option) 13158762Sbruefferany later version. 14158762Sbrueffer 15158762SbruefferGNU CC is distributed in the hope that it will be useful, 16111447Srubut WITHOUT ANY WARRANTY; without even the implied warranty of 17111447SruMERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18158762SbruefferGNU General Public License for more details. 19158762Sbrueffer 20158762SbruefferYou should have received a copy of the GNU General Public License 21158762Sbruefferalong with GNU CC; see the file COPYING. If not, write to 22158762Sbruefferthe Free Software Foundation, 59 Temple Place - Suite 330, 23158762SbruefferBoston, MA 02111-1307, USA. */ 24158762Sbrueffer 25158762Sbrueffer#include "config.h" 26108473Strhodes#include "system.h" 27108473Strhodes#include "rtl.h" 28108473Strhodes#include "tree.h" 29108473Strhodes#include "obstack.h" 30108473Strhodes#include "regs.h" 31108473Strhodes#include "hard-reg-set.h" 32108473Strhodes#include "real.h" 33108473Strhodes#include "insn-config.h" 34108473Strhodes#include "conditions.h" 35108473Strhodes#include "output.h" 36108473Strhodes#include "insn-attr.h" 37111447Sru#include "flags.h" 38111447Sru#include "reload.h" 39108473Strhodes#include "function.h" 40108473Strhodes#include "expr.h" 41108473Strhodes#include "optabs.h" 42111447Sru#include "toplev.h" 43111447Sru#include "recog.h" 44108473Strhodes#include "ggc.h" 45108473Strhodes#include "except.h" 46111447Sru#include "c-pragma.h" 47111447Sru#include "integrate.h" 48131530Sru#include "tm_p.h" 49111447Sru#include "target.h" 50108473Strhodes#include "target-def.h" 51111447Sru 52108473Strhodes/* Forward definitions of types. */ 53108473Strhodestypedef struct minipool_node Mnode; 54108473Strhodestypedef struct minipool_fixup Mfix; 55108473Strhodes 56108473Strhodes/* In order to improve the layout of the prototypes below 57108473Strhodes some short type abbreviations are defined here. */ 58111447Sru#define Hint HOST_WIDE_INT 59111447Sru#define Mmode enum machine_mode 60108473Strhodes#define Ulong unsigned long 61108473Strhodes#define Ccstar const char * 62108473Strhodes 63108473Strhodesconst struct attribute_spec arm_attribute_table[]; 64108473Strhodes 65249350Ssbruno/* Forward function declarations. */ 66108473Strhodesstatic void arm_add_gc_roots PARAMS ((void)); 67249350Ssbrunostatic int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int)); 68249350Ssbrunostatic Ulong bit_count PARAMS ((signed int)); 69249350Ssbrunostatic int const_ok_for_op PARAMS ((Hint, enum rtx_code)); 70111447Srustatic int eliminate_lr2ip PARAMS ((rtx *)); 71111447Srustatic rtx emit_multi_reg_push PARAMS ((int)); 72130951Sscottlstatic rtx emit_sfm PARAMS ((int, int)); 73130951Sscottl#ifndef AOF_ASSEMBLER 74131530Srustatic bool arm_assemble_integer PARAMS ((rtx, unsigned int, int)); 75131530Sru#endif 76130951Sscottlstatic Ccstar fp_const_from_val PARAMS ((REAL_VALUE_TYPE *)); 77131530Srustatic arm_cc get_arm_condition_code PARAMS ((rtx)); 78131530Srustatic void init_fpa_table PARAMS ((void)); 79130951Sscottlstatic Hint int_log2 PARAMS ((Hint)); 80130951Sscottlstatic rtx is_jump_table PARAMS ((rtx)); 81131530Srustatic Ccstar output_multi_immediate PARAMS ((rtx *, Ccstar, Ccstar, int, Hint)); 82249350Ssbrunostatic void print_multi_reg PARAMS ((FILE *, Ccstar, int, int)); 83249361Sjoelstatic Mmode select_dominance_cc_mode PARAMS ((rtx, rtx, Hint)); 84176136Siwasakistatic Ccstar shift_op PARAMS ((rtx, Hint *)); 85176136Siwasakistatic void arm_init_machine_status PARAMS ((struct function *)); 86176136Siwasakistatic void arm_mark_machine_status PARAMS ((struct function *)); 87176136Siwasakistatic void arm_free_machine_status PARAMS ((struct function *)); 88176136Siwasakistatic int number_of_first_bit_set PARAMS ((int)); 89176136Siwasakistatic void replace_symbols_in_block PARAMS ((tree, rtx, rtx)); 90133091Ssimonstatic void thumb_exit PARAMS ((FILE *, int, rtx)); 91133091Ssimonstatic void thumb_pushpop PARAMS ((FILE *, int, int)); 92133091Ssimonstatic Ccstar thumb_condition_code PARAMS ((rtx, int)); 93133091Ssimonstatic rtx is_jump_table PARAMS ((rtx)); 94108473Strhodesstatic Hint get_jump_table_size PARAMS ((rtx)); 95133091Ssimonstatic Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint)); 96111447Srustatic Mnode * add_minipool_forward_ref PARAMS ((Mfix *)); 97249350Ssbrunostatic Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint)); 98111447Srustatic Mnode * add_minipool_backward_ref PARAMS ((Mfix *)); 99111447Srustatic void assign_minipool_offsets PARAMS ((Mfix *)); 100111447Srustatic void arm_print_value PARAMS ((FILE *, rtx)); 101111447Srustatic void dump_minipool PARAMS ((rtx)); 102122225Ssimonstatic int arm_barrier_cost PARAMS ((rtx)); 103122225Ssimonstatic Mfix * create_fix_barrier PARAMS ((Mfix *, Hint)); 104122225Ssimonstatic void push_minipool_barrier PARAMS ((rtx, Hint)); 105122225Ssimonstatic void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx)); 106122225Ssimonstatic void note_invalid_constants PARAMS ((rtx, Hint)); 107122225Ssimonstatic int current_file_function_operand PARAMS ((rtx)); 108122225Ssimonstatic Ulong arm_compute_save_reg0_reg12_mask PARAMS ((void)); 109122225Ssimonstatic Ulong arm_compute_save_reg_mask PARAMS ((void)); 110122225Ssimonstatic Ulong arm_isr_value PARAMS ((tree)); 111122225Ssimonstatic Ulong arm_compute_func_type PARAMS ((void)); 112122225Ssimonstatic tree arm_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *)); 113122225Ssimonstatic tree arm_handle_isr_attribute PARAMS ((tree *, tree, tree, int, bool *)); 114128337Spsstatic void arm_output_function_epilogue PARAMS ((FILE *, Hint)); 115152316Spsstatic void arm_output_function_prologue PARAMS ((FILE *, Hint)); 116130493Ssimonstatic void thumb_output_function_prologue PARAMS ((FILE *, Hint)); 117152316Spsstatic int arm_comp_type_attributes PARAMS ((tree, tree)); 118152316Spsstatic void arm_set_default_type_attributes PARAMS ((tree)); 119179705Spsstatic int arm_adjust_cost PARAMS ((rtx, rtx, rtx, int)); 120179705Sps#ifdef OBJECT_FORMAT_ELF 121230588Ssbrunostatic void arm_elf_asm_named_section PARAMS ((const char *, unsigned int)); 122230588Ssbruno#endif 123230588Ssbruno 124230588Ssbruno#undef Hint 125253980Ssbruno#undef Mmode 126253980Ssbruno#undef Ulong 127152316Sps#undef Ccstar 128152316Sps 129152316Sps/* Initialize the GCC target structure. */ 130152316Sps#ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES 131179705Sps#undef TARGET_MERGE_DECL_ATTRIBUTES 132179705Sps#define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes 133179705Sps#endif 134179705Sps 135179705Sps#undef TARGET_ATTRIBUTE_TABLE 136179705Sps#define TARGET_ATTRIBUTE_TABLE arm_attribute_table 137230316Ssbruno 138230316Ssbruno#ifdef AOF_ASSEMBLER 139230588Ssbruno#undef TARGET_ASM_BYTE_OP 140230588Ssbruno#define TARGET_ASM_BYTE_OP "\tDCB\t" 141230588Ssbruno#undef TARGET_ASM_ALIGNED_HI_OP 142230588Ssbruno#define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t" 143253980Ssbruno#undef TARGET_ASM_ALIGNED_SI_OP 144253980Ssbruno#define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t" 145253980Ssbruno#else 146253980Ssbruno#undef TARGET_ASM_ALIGNED_SI_OP 147253980Ssbruno#define TARGET_ASM_ALIGNED_SI_OP NULL 148253980Ssbruno#undef TARGET_ASM_INTEGER 149253980Ssbruno#define TARGET_ASM_INTEGER arm_assemble_integer 150253980Ssbruno#endif 151253980Ssbruno 152253980Ssbruno#undef TARGET_ASM_FUNCTION_PROLOGUE 153152015Srse#define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue 154130493Ssimon 155230588Ssbruno#undef TARGET_ASM_FUNCTION_EPILOGUE 156230588Ssbruno#define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue 157253980Ssbruno 158253980Ssbruno#undef TARGET_COMP_TYPE_ATTRIBUTES 159152015Srse#define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes 160152015Srse 161179705Sps#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES 162179705Sps#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes 163253980Ssbruno 164253980Ssbruno#undef TARGET_INIT_BUILTINS 165253980Ssbruno#define TARGET_INIT_BUILTINS arm_init_builtins 166253980Ssbruno 167128337Sps#undef TARGET_EXPAND_BUILTIN 168128337Sps#define TARGET_EXPAND_BUILTIN arm_expand_builtin 169128337Sps 170108473Strhodes#undef TARGET_SCHED_ADJUST_COST 171108473Strhodes#define TARGET_SCHED_ADJUST_COST arm_adjust_cost 172108473Strhodes 173108473Strhodesstruct gcc_target targetm = TARGET_INITIALIZER; 174108473Strhodes 175130951Sscottl/* Obstack for minipool constant handling. */ 176111447Srustatic struct obstack minipool_obstack; 177111447Srustatic char * minipool_startobj; 178111447Sru 179111447Sru#define obstack_chunk_alloc xmalloc 180111447Sru#define obstack_chunk_free free 181111447Sru 182108473Strhodes/* The maximum number of insns skipped which 183111447Sru will be conditionalised if possible. */ 184108473Strhodesstatic int max_insns_skipped = 5; 185108473Strhodes 186108473Strhodesextern FILE * asm_out_file; 187108473Strhodes 188111447Sru/* True if we are currently building a constant table. */ 189108508Strhodesint making_const_table; 190108508Strhodes 191/* Define the information needed to generate branch insns. This is 192 stored from the compare operation. */ 193rtx arm_compare_op0, arm_compare_op1; 194 195/* What type of floating point are we tuning for? */ 196enum floating_point_type arm_fpu; 197 198/* What type of floating point instructions are available? */ 199enum floating_point_type arm_fpu_arch; 200 201/* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */ 202enum prog_mode_type arm_prgmode; 203 204/* Set by the -mfp=... option. */ 205const char * target_fp_name = NULL; 206 207/* Used to parse -mstructure_size_boundary command line option. */ 208const char * structure_size_string = NULL; 209int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; 210 211/* Bit values used to identify processor capabilities. */ 212#define FL_CO_PROC (1 << 0) /* Has external co-processor bus */ 213#define FL_FAST_MULT (1 << 1) /* Fast multiply */ 214#define FL_MODE26 (1 << 2) /* 26-bit mode support */ 215#define FL_MODE32 (1 << 3) /* 32-bit mode support */ 216#define FL_ARCH4 (1 << 4) /* Architecture rel 4 */ 217#define FL_ARCH5 (1 << 5) /* Architecture rel 5 */ 218#define FL_THUMB (1 << 6) /* Thumb aware */ 219#define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ 220#define FL_STRONG (1 << 8) /* StrongARM */ 221#define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */ 222#define FL_XSCALE (1 << 10) /* XScale */ 223 224/* The bits in this mask specify which 225 instructions we are allowed to generate. */ 226static int insn_flags = 0; 227 228/* The bits in this mask specify which instruction scheduling options should 229 be used. Note - there is an overlap with the FL_FAST_MULT. For some 230 hardware we want to be able to generate the multiply instructions, but to 231 tune as if they were not present in the architecture. */ 232static int tune_flags = 0; 233 234/* The following are used in the arm.md file as equivalents to bits 235 in the above two flag variables. */ 236 237/* Nonzero if this is an "M" variant of the processor. */ 238int arm_fast_multiply = 0; 239 240/* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 241int arm_arch4 = 0; 242 243/* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 244int arm_arch5 = 0; 245 246/* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 247int arm_arch5e = 0; 248 249/* Nonzero if this chip can benefit from load scheduling. */ 250int arm_ld_sched = 0; 251 252/* Nonzero if this chip is a StrongARM. */ 253int arm_is_strong = 0; 254 255/* Nonzero if this chip is an XScale. */ 256int arm_is_xscale = 0; 257 258/* Nonzero if this chip is an ARM6 or an ARM7. */ 259int arm_is_6_or_7 = 0; 260 261/* Nonzero if generating Thumb instructions. */ 262int thumb_code = 0; 263 264/* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we 265 must report the mode of the memory reference from PRINT_OPERAND to 266 PRINT_OPERAND_ADDRESS. */ 267enum machine_mode output_memory_reference_mode; 268 269/* The register number to be used for the PIC offset register. */ 270const char * arm_pic_register_string = NULL; 271int arm_pic_register = INVALID_REGNUM; 272 273/* Set to 1 when a return insn is output, this means that the epilogue 274 is not needed. */ 275int return_used_this_function; 276 277/* Set to 1 after arm_reorg has started. Reset to start at the start of 278 the next function. */ 279static int after_arm_reorg = 0; 280 281/* The maximum number of insns to be used when loading a constant. */ 282static int arm_constant_limit = 3; 283 284/* For an explanation of these variables, see final_prescan_insn below. */ 285int arm_ccfsm_state; 286enum arm_cond_code arm_current_cc; 287rtx arm_target_insn; 288int arm_target_label; 289 290/* The condition codes of the ARM, and the inverse function. */ 291static const char * const arm_condition_codes[] = 292{ 293 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 294 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv" 295}; 296 297#define streq(string1, string2) (strcmp (string1, string2) == 0) 298 299/* Initialization code. */ 300 301struct processors 302{ 303 const char *const name; 304 const unsigned int flags; 305}; 306 307/* Not all of these give usefully different compilation alternatives, 308 but there is no simple way of generalizing them. */ 309static const struct processors all_cores[] = 310{ 311 /* ARM Cores */ 312 313 {"arm2", FL_CO_PROC | FL_MODE26 }, 314 {"arm250", FL_CO_PROC | FL_MODE26 }, 315 {"arm3", FL_CO_PROC | FL_MODE26 }, 316 {"arm6", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 317 {"arm60", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 318 {"arm600", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 319 {"arm610", FL_MODE26 | FL_MODE32 }, 320 {"arm620", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 321 {"arm7", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 322 /* arm7m doesn't exist on its own, but only with D, (and I), but 323 those don't alter the code, so arm7m is sometimes used. */ 324 {"arm7m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, 325 {"arm7d", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 326 {"arm7dm", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, 327 {"arm7di", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 328 {"arm7dmi", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, 329 {"arm70", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 330 {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 331 {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 332 {"arm710", FL_MODE26 | FL_MODE32 }, 333 {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB }, 334 {"arm720", FL_MODE26 | FL_MODE32 }, 335 {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB }, 336 {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB }, 337 {"arm710c", FL_MODE26 | FL_MODE32 }, 338 {"arm7100", FL_MODE26 | FL_MODE32 }, 339 {"arm7500", FL_MODE26 | FL_MODE32 }, 340 /* Doesn't have an external co-proc, but does have embedded fpu. */ 341 {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 342 {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, 343 {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, 344 {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, 345 {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, 346 {"arm920", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, 347 {"arm920t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, 348 {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, 349 {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, 350 {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, 351 {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, 352 {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, 353 {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, 354 {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, 355 {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, 356 {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, 357 {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE }, 358 359 {NULL, 0} 360}; 361 362static const struct processors all_architectures[] = 363{ 364 /* ARM Architectures */ 365 366 { "armv2", FL_CO_PROC | FL_MODE26 }, 367 { "armv2a", FL_CO_PROC | FL_MODE26 }, 368 { "armv3", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, 369 { "armv3m", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT }, 370 { "armv4", FL_CO_PROC | FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 }, 371 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no 372 implementations that support it, so we will leave it out for now. */ 373 { "armv4t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, 374 { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, 375 { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, 376 { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E }, 377 { NULL, 0 } 378}; 379 380/* This is a magic stucture. The 'string' field is magically filled in 381 with a pointer to the value specified by the user on the command line 382 assuming that the user has specified such a value. */ 383 384struct arm_cpu_select arm_select[] = 385{ 386 /* string name processors */ 387 { NULL, "-mcpu=", all_cores }, 388 { NULL, "-march=", all_architectures }, 389 { NULL, "-mtune=", all_cores } 390}; 391 392/* Return the number of bits set in value' */ 393static unsigned long 394bit_count (value) 395 signed int value; 396{ 397 unsigned long count = 0; 398 399 while (value) 400 { 401 value &= ~(value & -value); 402 ++count; 403 } 404 405 return count; 406} 407 408/* Fix up any incompatible options that the user has specified. 409 This has now turned into a maze. */ 410void 411arm_override_options () 412{ 413 unsigned i; 414 415 /* Set up the flags based on the cpu/architecture selected by the user. */ 416 for (i = ARRAY_SIZE (arm_select); i--;) 417 { 418 struct arm_cpu_select * ptr = arm_select + i; 419 420 if (ptr->string != NULL && ptr->string[0] != '\0') 421 { 422 const struct processors * sel; 423 424 for (sel = ptr->processors; sel->name != NULL; sel++) 425 if (streq (ptr->string, sel->name)) 426 { 427 if (i == 2) 428 tune_flags = sel->flags; 429 else 430 { 431 /* If we have been given an architecture and a processor 432 make sure that they are compatible. We only generate 433 a warning though, and we prefer the CPU over the 434 architecture. */ 435 if (insn_flags != 0 && (insn_flags ^ sel->flags)) 436 warning ("switch -mcpu=%s conflicts with -march= switch", 437 ptr->string); 438 439 insn_flags = sel->flags; 440 } 441 442 break; 443 } 444 445 if (sel->name == NULL) 446 error ("bad value (%s) for %s switch", ptr->string, ptr->name); 447 } 448 } 449 450 /* If the user did not specify a processor, choose one for them. */ 451 if (insn_flags == 0) 452 { 453 const struct processors * sel; 454 unsigned int sought; 455 static const struct cpu_default 456 { 457 const int cpu; 458 const char *const name; 459 } 460 cpu_defaults[] = 461 { 462 { TARGET_CPU_arm2, "arm2" }, 463 { TARGET_CPU_arm6, "arm6" }, 464 { TARGET_CPU_arm610, "arm610" }, 465 { TARGET_CPU_arm710, "arm710" }, 466 { TARGET_CPU_arm7m, "arm7m" }, 467 { TARGET_CPU_arm7500fe, "arm7500fe" }, 468 { TARGET_CPU_arm7tdmi, "arm7tdmi" }, 469 { TARGET_CPU_arm8, "arm8" }, 470 { TARGET_CPU_arm810, "arm810" }, 471 { TARGET_CPU_arm9, "arm9" }, 472 { TARGET_CPU_strongarm, "strongarm" }, 473 { TARGET_CPU_xscale, "xscale" }, 474 { TARGET_CPU_generic, "arm" }, 475 { 0, 0 } 476 }; 477 const struct cpu_default * def; 478 479 /* Find the default. */ 480 for (def = cpu_defaults; def->name; def++) 481 if (def->cpu == TARGET_CPU_DEFAULT) 482 break; 483 484 /* Make sure we found the default CPU. */ 485 if (def->name == NULL) 486 abort (); 487 488 /* Find the default CPU's flags. */ 489 for (sel = all_cores; sel->name != NULL; sel++) 490 if (streq (def->name, sel->name)) 491 break; 492 493 if (sel->name == NULL) 494 abort (); 495 496 insn_flags = sel->flags; 497 498 /* Now check to see if the user has specified some command line 499 switch that require certain abilities from the cpu. */ 500 sought = 0; 501 502 if (TARGET_INTERWORK || TARGET_THUMB) 503 { 504 sought |= (FL_THUMB | FL_MODE32); 505 506 /* Force apcs-32 to be used for interworking. */ 507 target_flags |= ARM_FLAG_APCS_32; 508 509 /* There are no ARM processors that support both APCS-26 and 510 interworking. Therefore we force FL_MODE26 to be removed 511 from insn_flags here (if it was set), so that the search 512 below will always be able to find a compatible processor. */ 513 insn_flags &= ~FL_MODE26; 514 } 515 else if (!TARGET_APCS_32) 516 sought |= FL_MODE26; 517 518 if (sought != 0 && ((sought & insn_flags) != sought)) 519 { 520 /* Try to locate a CPU type that supports all of the abilities 521 of the default CPU, plus the extra abilities requested by 522 the user. */ 523 for (sel = all_cores; sel->name != NULL; sel++) 524 if ((sel->flags & sought) == (sought | insn_flags)) 525 break; 526 527 if (sel->name == NULL) 528 { 529 unsigned int current_bit_count = 0; 530 const struct processors * best_fit = NULL; 531 532 /* Ideally we would like to issue an error message here 533 saying that it was not possible to find a CPU compatible 534 with the default CPU, but which also supports the command 535 line options specified by the programmer, and so they 536 ought to use the -mcpu=<name> command line option to 537 override the default CPU type. 538 539 Unfortunately this does not work with multilibing. We 540 need to be able to support multilibs for -mapcs-26 and for 541 -mthumb-interwork and there is no CPU that can support both 542 options. Instead if we cannot find a cpu that has both the 543 characteristics of the default cpu and the given command line 544 options we scan the array again looking for a best match. */ 545 for (sel = all_cores; sel->name != NULL; sel++) 546 if ((sel->flags & sought) == sought) 547 { 548 unsigned int count; 549 550 count = bit_count (sel->flags & insn_flags); 551 552 if (count >= current_bit_count) 553 { 554 best_fit = sel; 555 current_bit_count = count; 556 } 557 } 558 559 if (best_fit == NULL) 560 abort (); 561 else 562 sel = best_fit; 563 } 564 565 insn_flags = sel->flags; 566 } 567 } 568 569 /* If tuning has not been specified, tune for whichever processor or 570 architecture has been selected. */ 571 if (tune_flags == 0) 572 tune_flags = insn_flags; 573 574 /* Make sure that the processor choice does not conflict with any of the 575 other command line choices. */ 576 if (TARGET_APCS_32 && !(insn_flags & FL_MODE32)) 577 { 578 /* If APCS-32 was not the default then it must have been set by the 579 user, so issue a warning message. If the user has specified 580 "-mapcs-32 -mcpu=arm2" then we loose here. */ 581 if ((TARGET_DEFAULT & ARM_FLAG_APCS_32) == 0) 582 warning ("target CPU does not support APCS-32" ); 583 target_flags &= ~ARM_FLAG_APCS_32; 584 } 585 else if (!TARGET_APCS_32 && !(insn_flags & FL_MODE26)) 586 { 587 warning ("target CPU does not support APCS-26" ); 588 target_flags |= ARM_FLAG_APCS_32; 589 } 590 591 if (TARGET_INTERWORK && !(insn_flags & FL_THUMB)) 592 { 593 warning ("target CPU does not support interworking" ); 594 target_flags &= ~ARM_FLAG_INTERWORK; 595 } 596 597 if (TARGET_THUMB && !(insn_flags & FL_THUMB)) 598 { 599 warning ("target CPU does not support THUMB instructions"); 600 target_flags &= ~ARM_FLAG_THUMB; 601 } 602 603 if (TARGET_APCS_FRAME && TARGET_THUMB) 604 { 605 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */ 606 target_flags &= ~ARM_FLAG_APCS_FRAME; 607 } 608 609 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done 610 from here where no function is being compiled currently. */ 611 if ((target_flags & (THUMB_FLAG_LEAF_BACKTRACE | THUMB_FLAG_BACKTRACE)) 612 && TARGET_ARM) 613 warning ("enabling backtrace support is only meaningful when compiling for the Thumb"); 614 615 if (TARGET_ARM && TARGET_CALLEE_INTERWORKING) 616 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb"); 617 618 if (TARGET_ARM && TARGET_CALLER_INTERWORKING) 619 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb"); 620 621 /* If interworking is enabled then APCS-32 must be selected as well. */ 622 if (TARGET_INTERWORK) 623 { 624 if (!TARGET_APCS_32) 625 warning ("interworking forces APCS-32 to be used" ); 626 target_flags |= ARM_FLAG_APCS_32; 627 } 628 629 if (TARGET_APCS_STACK && !TARGET_APCS_FRAME) 630 { 631 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame"); 632 target_flags |= ARM_FLAG_APCS_FRAME; 633 } 634 635 if (TARGET_POKE_FUNCTION_NAME) 636 target_flags |= ARM_FLAG_APCS_FRAME; 637 638 if (TARGET_APCS_REENT && flag_pic) 639 error ("-fpic and -mapcs-reent are incompatible"); 640 641 if (TARGET_APCS_REENT) 642 warning ("APCS reentrant code not supported. Ignored"); 643 644 /* If this target is normally configured to use APCS frames, warn if they 645 are turned off and debugging is turned on. */ 646 if (TARGET_ARM 647 && write_symbols != NO_DEBUG 648 && !TARGET_APCS_FRAME 649 && (TARGET_DEFAULT & ARM_FLAG_APCS_FRAME)) 650 warning ("-g with -mno-apcs-frame may not give sensible debugging"); 651 652 /* If stack checking is disabled, we can use r10 as the PIC register, 653 which keeps r9 available. */ 654 if (flag_pic) 655 arm_pic_register = TARGET_APCS_STACK ? 9 : 10; 656 657 if (TARGET_APCS_FLOAT) 658 warning ("passing floating point arguments in fp regs not yet supported"); 659 660 /* Initialise boolean versions of the flags, for use in the arm.md file. */ 661 arm_fast_multiply = (insn_flags & FL_FAST_MULT) != 0; 662 arm_arch4 = (insn_flags & FL_ARCH4) != 0; 663 arm_arch5 = (insn_flags & FL_ARCH5) != 0; 664 arm_arch5e = (insn_flags & FL_ARCH5E) != 0; 665 arm_is_xscale = (insn_flags & FL_XSCALE) != 0; 666 667 arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; 668 arm_is_strong = (tune_flags & FL_STRONG) != 0; 669 thumb_code = (TARGET_ARM == 0); 670 arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32)) 671 && !(tune_flags & FL_ARCH4))) != 0; 672 673 /* Default value for floating point code... if no co-processor 674 bus, then schedule for emulated floating point. Otherwise, 675 assume the user has an FPA. 676 Note: this does not prevent use of floating point instructions, 677 -msoft-float does that. */ 678 arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3; 679 680 if (target_fp_name) 681 { 682 if (streq (target_fp_name, "2")) 683 arm_fpu_arch = FP_SOFT2; 684 else if (streq (target_fp_name, "3")) 685 arm_fpu_arch = FP_SOFT3; 686 else 687 error ("invalid floating point emulation option: -mfpe-%s", 688 target_fp_name); 689 } 690 else 691 arm_fpu_arch = FP_DEFAULT; 692 693 if (TARGET_FPE && arm_fpu != FP_HARD) 694 arm_fpu = FP_SOFT2; 695 696 /* For arm2/3 there is no need to do any scheduling if there is only 697 a floating point emulator, or we are doing software floating-point. */ 698 if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) 699 && (tune_flags & FL_MODE32) == 0) 700 flag_schedule_insns = flag_schedule_insns_after_reload = 0; 701 702 arm_prgmode = TARGET_APCS_32 ? PROG_MODE_PROG32 : PROG_MODE_PROG26; 703 704 if (structure_size_string != NULL) 705 { 706 int size = strtol (structure_size_string, NULL, 0); 707 708 if (size == 8 || size == 32) 709 arm_structure_size_boundary = size; 710 else 711 warning ("structure size boundary can only be set to 8 or 32"); 712 } 713 714 if (arm_pic_register_string != NULL) 715 { 716 int pic_register = decode_reg_name (arm_pic_register_string); 717 718 if (!flag_pic) 719 warning ("-mpic-register= is useless without -fpic"); 720 721 /* Prevent the user from choosing an obviously stupid PIC register. */ 722 else if (pic_register < 0 || call_used_regs[pic_register] 723 || pic_register == HARD_FRAME_POINTER_REGNUM 724 || pic_register == STACK_POINTER_REGNUM 725 || pic_register >= PC_REGNUM) 726 error ("unable to use '%s' for PIC register", arm_pic_register_string); 727 else 728 arm_pic_register = pic_register; 729 } 730 731 if (TARGET_THUMB && flag_schedule_insns) 732 { 733 /* Don't warn since it's on by default in -O2. */ 734 flag_schedule_insns = 0; 735 } 736 737 /* If optimizing for space, don't synthesize constants. 738 For processors with load scheduling, it never costs more than 2 cycles 739 to load a constant, and the load scheduler may well reduce that to 1. */ 740 if (optimize_size || (tune_flags & FL_LDSCHED)) 741 arm_constant_limit = 1; 742 743 if (arm_is_xscale) 744 arm_constant_limit = 2; 745 746 /* If optimizing for size, bump the number of instructions that we 747 are prepared to conditionally execute (even on a StrongARM). 748 Otherwise for the StrongARM, which has early execution of branches, 749 a sequence that is worth skipping is shorter. */ 750 if (optimize_size) 751 max_insns_skipped = 6; 752 else if (arm_is_strong) 753 max_insns_skipped = 3; 754 755 /* Register global variables with the garbage collector. */ 756 arm_add_gc_roots (); 757} 758 759static void 760arm_add_gc_roots () 761{ 762 ggc_add_rtx_root (&arm_compare_op0, 1); 763 ggc_add_rtx_root (&arm_compare_op1, 1); 764 ggc_add_rtx_root (&arm_target_insn, 1); /* Not sure this is really a root. */ 765 766 gcc_obstack_init(&minipool_obstack); 767 minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); 768} 769 770/* A table of known ARM exception types. 771 For use with the interrupt function attribute. */ 772 773typedef struct 774{ 775 const char *const arg; 776 const unsigned long return_value; 777} 778isr_attribute_arg; 779 780static const isr_attribute_arg isr_attribute_args [] = 781{ 782 { "IRQ", ARM_FT_ISR }, 783 { "irq", ARM_FT_ISR }, 784 { "FIQ", ARM_FT_FIQ }, 785 { "fiq", ARM_FT_FIQ }, 786 { "ABORT", ARM_FT_ISR }, 787 { "abort", ARM_FT_ISR }, 788 { "ABORT", ARM_FT_ISR }, 789 { "abort", ARM_FT_ISR }, 790 { "UNDEF", ARM_FT_EXCEPTION }, 791 { "undef", ARM_FT_EXCEPTION }, 792 { "SWI", ARM_FT_EXCEPTION }, 793 { "swi", ARM_FT_EXCEPTION }, 794 { NULL, ARM_FT_NORMAL } 795}; 796 797/* Returns the (interrupt) function type of the current 798 function, or ARM_FT_UNKNOWN if the type cannot be determined. */ 799 800static unsigned long 801arm_isr_value (argument) 802 tree argument; 803{ 804 const isr_attribute_arg * ptr; 805 const char * arg; 806 807 /* No argument - default to IRQ. */ 808 if (argument == NULL_TREE) 809 return ARM_FT_ISR; 810 811 /* Get the value of the argument. */ 812 if (TREE_VALUE (argument) == NULL_TREE 813 || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) 814 return ARM_FT_UNKNOWN; 815 816 arg = TREE_STRING_POINTER (TREE_VALUE (argument)); 817 818 /* Check it against the list of known arguments. */ 819 for (ptr = isr_attribute_args; ptr->arg != NULL; ptr ++) 820 if (streq (arg, ptr->arg)) 821 return ptr->return_value; 822 823 /* An unrecognised interrupt type. */ 824 return ARM_FT_UNKNOWN; 825} 826 827/* Computes the type of the current function. */ 828 829static unsigned long 830arm_compute_func_type () 831{ 832 unsigned long type = ARM_FT_UNKNOWN; 833 tree a; 834 tree attr; 835 836 if (TREE_CODE (current_function_decl) != FUNCTION_DECL) 837 abort (); 838 839 /* Decide if the current function is volatile. Such functions 840 never return, and many memory cycles can be saved by not storing 841 register values that will never be needed again. This optimization 842 was added to speed up context switching in a kernel application. */ 843 if (optimize > 0 844 && current_function_nothrow 845 && TREE_THIS_VOLATILE (current_function_decl)) 846 type |= ARM_FT_VOLATILE; 847 848 if (current_function_needs_context) 849 type |= ARM_FT_NESTED; 850 851 attr = DECL_ATTRIBUTES (current_function_decl); 852 853 a = lookup_attribute ("naked", attr); 854 if (a != NULL_TREE) 855 type |= ARM_FT_NAKED; 856 857 if (cfun->machine->eh_epilogue_sp_ofs != NULL_RTX) 858 type |= ARM_FT_EXCEPTION_HANDLER; 859 else 860 { 861 a = lookup_attribute ("isr", attr); 862 if (a == NULL_TREE) 863 a = lookup_attribute ("interrupt", attr); 864 865 if (a == NULL_TREE) 866 type |= TARGET_INTERWORK ? ARM_FT_INTERWORKED : ARM_FT_NORMAL; 867 else 868 type |= arm_isr_value (TREE_VALUE (a)); 869 } 870 871 return type; 872} 873 874/* Returns the type of the current function. */ 875 876unsigned long 877arm_current_func_type () 878{ 879 if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) 880 cfun->machine->func_type = arm_compute_func_type (); 881 882 return cfun->machine->func_type; 883} 884 885/* Return 1 if it is possible to return using a single instruction. */ 886 887int 888use_return_insn (iscond) 889 int iscond; 890{ 891 int regno; 892 unsigned int func_type; 893 unsigned long saved_int_regs; 894 895 /* Never use a return instruction before reload has run. */ 896 if (!reload_completed) 897 return 0; 898 899 func_type = arm_current_func_type (); 900 901 /* Naked functions and volatile functions need special 902 consideration. */ 903 if (func_type & (ARM_FT_VOLATILE | ARM_FT_NAKED)) 904 return 0; 905 906 /* As do variadic functions. */ 907 if (current_function_pretend_args_size 908 || cfun->machine->uses_anonymous_args 909 /* Of if the function calls __builtin_eh_return () */ 910 || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER 911 /* Or if there is no frame pointer and there is a stack adjustment. */ 912 || ((get_frame_size () + current_function_outgoing_args_size != 0) 913 && !frame_pointer_needed)) 914 return 0; 915 916 saved_int_regs = arm_compute_save_reg_mask (); 917 918 /* Can't be done if interworking with Thumb, and any registers have been 919 stacked. */ 920 if (TARGET_INTERWORK && saved_int_regs != 0) 921 return 0; 922 923 /* On StrongARM, conditional returns are expensive if they aren't 924 taken and multiple registers have been stacked. */ 925 if (iscond && arm_is_strong) 926 { 927 /* Conditional return when just the LR is stored is a simple 928 conditional-load instruction, that's not expensive. */ 929 if (saved_int_regs != 0 && saved_int_regs != (1 << LR_REGNUM)) 930 return 0; 931 932 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) 933 return 0; 934 } 935 936 /* If there are saved registers but the LR isn't saved, then we need 937 two instructions for the return. */ 938 if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) 939 return 0; 940 941 /* Can't be done if any of the FPU regs are pushed, 942 since this also requires an insn. */ 943 if (TARGET_HARD_FLOAT) 944 for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++) 945 if (regs_ever_live[regno] && !call_used_regs[regno]) 946 return 0; 947 948 return 1; 949} 950 951/* Return TRUE if int I is a valid immediate ARM constant. */ 952 953int 954const_ok_for_arm (i) 955 HOST_WIDE_INT i; 956{ 957 unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF; 958 959 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must 960 be all zero, or all one. */ 961 if ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0 962 && ((i & ~(unsigned HOST_WIDE_INT) 0xffffffff) 963 != ((~(unsigned HOST_WIDE_INT) 0) 964 & ~(unsigned HOST_WIDE_INT) 0xffffffff))) 965 return FALSE; 966 967 /* Fast return for 0 and powers of 2 */ 968 if ((i & (i - 1)) == 0) 969 return TRUE; 970 971 do 972 { 973 if ((i & mask & (unsigned HOST_WIDE_INT) 0xffffffff) == 0) 974 return TRUE; 975 mask = 976 (mask << 2) | ((mask & (unsigned HOST_WIDE_INT) 0xffffffff) 977 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT) 0xffffffff; 978 } 979 while (mask != ~(unsigned HOST_WIDE_INT) 0xFF); 980 981 return FALSE; 982} 983 984/* Return true if I is a valid constant for the operation CODE. */ 985static int 986const_ok_for_op (i, code) 987 HOST_WIDE_INT i; 988 enum rtx_code code; 989{ 990 if (const_ok_for_arm (i)) 991 return 1; 992 993 switch (code) 994 { 995 case PLUS: 996 return const_ok_for_arm (ARM_SIGN_EXTEND (-i)); 997 998 case MINUS: /* Should only occur with (MINUS I reg) => rsb */ 999 case XOR: 1000 case IOR: 1001 return 0; 1002 1003 case AND: 1004 return const_ok_for_arm (ARM_SIGN_EXTEND (~i)); 1005 1006 default: 1007 abort (); 1008 } 1009} 1010 1011/* Emit a sequence of insns to handle a large constant. 1012 CODE is the code of the operation required, it can be any of SET, PLUS, 1013 IOR, AND, XOR, MINUS; 1014 MODE is the mode in which the operation is being performed; 1015 VAL is the integer to operate on; 1016 SOURCE is the other operand (a register, or a null-pointer for SET); 1017 SUBTARGETS means it is safe to create scratch registers if that will 1018 either produce a simpler sequence, or we will want to cse the values. 1019 Return value is the number of insns emitted. */ 1020 1021int 1022arm_split_constant (code, mode, val, target, source, subtargets) 1023 enum rtx_code code; 1024 enum machine_mode mode; 1025 HOST_WIDE_INT val; 1026 rtx target; 1027 rtx source; 1028 int subtargets; 1029{ 1030 if (subtargets || code == SET 1031 || (GET_CODE (target) == REG && GET_CODE (source) == REG 1032 && REGNO (target) != REGNO (source))) 1033 { 1034 /* After arm_reorg has been called, we can't fix up expensive 1035 constants by pushing them into memory so we must synthesise 1036 them in-line, regardless of the cost. This is only likely to 1037 be more costly on chips that have load delay slots and we are 1038 compiling without running the scheduler (so no splitting 1039 occurred before the final instruction emission). 1040 1041 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c 1042 */ 1043 if (!after_arm_reorg 1044 && (arm_gen_constant (code, mode, val, target, source, 1, 0) 1045 > arm_constant_limit + (code != SET))) 1046 { 1047 if (code == SET) 1048 { 1049 /* Currently SET is the only monadic value for CODE, all 1050 the rest are diadic. */ 1051 emit_insn (gen_rtx_SET (VOIDmode, target, GEN_INT (val))); 1052 return 1; 1053 } 1054 else 1055 { 1056 rtx temp = subtargets ? gen_reg_rtx (mode) : target; 1057 1058 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (val))); 1059 /* For MINUS, the value is subtracted from, since we never 1060 have subtraction of a constant. */ 1061 if (code == MINUS) 1062 emit_insn (gen_rtx_SET (VOIDmode, target, 1063 gen_rtx_MINUS (mode, temp, source))); 1064 else 1065 emit_insn (gen_rtx_SET (VOIDmode, target, 1066 gen_rtx (code, mode, source, temp))); 1067 return 2; 1068 } 1069 } 1070 } 1071 1072 return arm_gen_constant (code, mode, val, target, source, subtargets, 1); 1073} 1074 1075static int 1076count_insns_for_constant (HOST_WIDE_INT remainder, int i) 1077{ 1078 HOST_WIDE_INT temp1; 1079 int num_insns = 0; 1080 do 1081 { 1082 int end; 1083 1084 if (i <= 0) 1085 i += 32; 1086 if (remainder & (3 << (i - 2))) 1087 { 1088 end = i - 8; 1089 if (end < 0) 1090 end += 32; 1091 temp1 = remainder & ((0x0ff << end) 1092 | ((i < end) ? (0xff >> (32 - end)) : 0)); 1093 remainder &= ~temp1; 1094 num_insns++; 1095 i -= 6; 1096 } 1097 i -= 2; 1098 } while (remainder); 1099 return num_insns; 1100} 1101 1102/* As above, but extra parameter GENERATE which, if clear, suppresses 1103 RTL generation. */ 1104 1105static int 1106arm_gen_constant (code, mode, val, target, source, subtargets, generate) 1107 enum rtx_code code; 1108 enum machine_mode mode; 1109 HOST_WIDE_INT val; 1110 rtx target; 1111 rtx source; 1112 int subtargets; 1113 int generate; 1114{ 1115 int can_invert = 0; 1116 int can_negate = 0; 1117 int can_negate_initial = 0; 1118 int can_shift = 0; 1119 int i; 1120 int num_bits_set = 0; 1121 int set_sign_bit_copies = 0; 1122 int clear_sign_bit_copies = 0; 1123 int clear_zero_bit_copies = 0; 1124 int set_zero_bit_copies = 0; 1125 int insns = 0; 1126 unsigned HOST_WIDE_INT temp1, temp2; 1127 unsigned HOST_WIDE_INT remainder = val & 0xffffffff; 1128 1129 /* Find out which operations are safe for a given CODE. Also do a quick 1130 check for degenerate cases; these can occur when DImode operations 1131 are split. */ 1132 switch (code) 1133 { 1134 case SET: 1135 can_invert = 1; 1136 can_shift = 1; 1137 can_negate = 1; 1138 break; 1139 1140 case PLUS: 1141 can_negate = 1; 1142 can_negate_initial = 1; 1143 break; 1144 1145 case IOR: 1146 if (remainder == 0xffffffff) 1147 { 1148 if (generate) 1149 emit_insn (gen_rtx_SET (VOIDmode, target, 1150 GEN_INT (ARM_SIGN_EXTEND (val)))); 1151 return 1; 1152 } 1153 if (remainder == 0) 1154 { 1155 if (reload_completed && rtx_equal_p (target, source)) 1156 return 0; 1157 if (generate) 1158 emit_insn (gen_rtx_SET (VOIDmode, target, source)); 1159 return 1; 1160 } 1161 break; 1162 1163 case AND: 1164 if (remainder == 0) 1165 { 1166 if (generate) 1167 emit_insn (gen_rtx_SET (VOIDmode, target, const0_rtx)); 1168 return 1; 1169 } 1170 if (remainder == 0xffffffff) 1171 { 1172 if (reload_completed && rtx_equal_p (target, source)) 1173 return 0; 1174 if (generate) 1175 emit_insn (gen_rtx_SET (VOIDmode, target, source)); 1176 return 1; 1177 } 1178 can_invert = 1; 1179 break; 1180 1181 case XOR: 1182 if (remainder == 0) 1183 { 1184 if (reload_completed && rtx_equal_p (target, source)) 1185 return 0; 1186 if (generate) 1187 emit_insn (gen_rtx_SET (VOIDmode, target, source)); 1188 return 1; 1189 } 1190 if (remainder == 0xffffffff) 1191 { 1192 if (generate) 1193 emit_insn (gen_rtx_SET (VOIDmode, target, 1194 gen_rtx_NOT (mode, source))); 1195 return 1; 1196 } 1197 1198 /* We don't know how to handle this yet below. */ 1199 abort (); 1200 1201 case MINUS: 1202 /* We treat MINUS as (val - source), since (source - val) is always 1203 passed as (source + (-val)). */ 1204 if (remainder == 0) 1205 { 1206 if (generate) 1207 emit_insn (gen_rtx_SET (VOIDmode, target, 1208 gen_rtx_NEG (mode, source))); 1209 return 1; 1210 } 1211 if (const_ok_for_arm (val)) 1212 { 1213 if (generate) 1214 emit_insn (gen_rtx_SET (VOIDmode, target, 1215 gen_rtx_MINUS (mode, GEN_INT (val), 1216 source))); 1217 return 1; 1218 } 1219 can_negate = 1; 1220 1221 break; 1222 1223 default: 1224 abort (); 1225 } 1226 1227 /* If we can do it in one insn get out quickly. */ 1228 if (const_ok_for_arm (val) 1229 || (can_negate_initial && const_ok_for_arm (-val)) 1230 || (can_invert && const_ok_for_arm (~val))) 1231 { 1232 if (generate) 1233 emit_insn (gen_rtx_SET (VOIDmode, target, 1234 (source ? gen_rtx (code, mode, source, 1235 GEN_INT (val)) 1236 : GEN_INT (val)))); 1237 return 1; 1238 } 1239 1240 /* Calculate a few attributes that may be useful for specific 1241 optimizations. */ 1242 for (i = 31; i >= 0; i--) 1243 { 1244 if ((remainder & (1 << i)) == 0) 1245 clear_sign_bit_copies++; 1246 else 1247 break; 1248 } 1249 1250 for (i = 31; i >= 0; i--) 1251 { 1252 if ((remainder & (1 << i)) != 0) 1253 set_sign_bit_copies++; 1254 else 1255 break; 1256 } 1257 1258 for (i = 0; i <= 31; i++) 1259 { 1260 if ((remainder & (1 << i)) == 0) 1261 clear_zero_bit_copies++; 1262 else 1263 break; 1264 } 1265 1266 for (i = 0; i <= 31; i++) 1267 { 1268 if ((remainder & (1 << i)) != 0) 1269 set_zero_bit_copies++; 1270 else 1271 break; 1272 } 1273 1274 switch (code) 1275 { 1276 case SET: 1277 /* See if we can do this by sign_extending a constant that is known 1278 to be negative. This is a good, way of doing it, since the shift 1279 may well merge into a subsequent insn. */ 1280 if (set_sign_bit_copies > 1) 1281 { 1282 if (const_ok_for_arm 1283 (temp1 = ARM_SIGN_EXTEND (remainder 1284 << (set_sign_bit_copies - 1)))) 1285 { 1286 if (generate) 1287 { 1288 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1289 emit_insn (gen_rtx_SET (VOIDmode, new_src, 1290 GEN_INT (temp1))); 1291 emit_insn (gen_ashrsi3 (target, new_src, 1292 GEN_INT (set_sign_bit_copies - 1))); 1293 } 1294 return 2; 1295 } 1296 /* For an inverted constant, we will need to set the low bits, 1297 these will be shifted out of harm's way. */ 1298 temp1 |= (1 << (set_sign_bit_copies - 1)) - 1; 1299 if (const_ok_for_arm (~temp1)) 1300 { 1301 if (generate) 1302 { 1303 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1304 emit_insn (gen_rtx_SET (VOIDmode, new_src, 1305 GEN_INT (temp1))); 1306 emit_insn (gen_ashrsi3 (target, new_src, 1307 GEN_INT (set_sign_bit_copies - 1))); 1308 } 1309 return 2; 1310 } 1311 } 1312 1313 /* See if we can generate this by setting the bottom (or the top) 1314 16 bits, and then shifting these into the other half of the 1315 word. We only look for the simplest cases, to do more would cost 1316 too much. Be careful, however, not to generate this when the 1317 alternative would take fewer insns. */ 1318 if (val & 0xffff0000) 1319 { 1320 temp1 = remainder & 0xffff0000; 1321 temp2 = remainder & 0x0000ffff; 1322 1323 /* Overlaps outside this range are best done using other methods. */ 1324 for (i = 9; i < 24; i++) 1325 { 1326 if ((((temp2 | (temp2 << i)) & 0xffffffff) == remainder) 1327 && !const_ok_for_arm (temp2)) 1328 { 1329 rtx new_src = (subtargets 1330 ? (generate ? gen_reg_rtx (mode) : NULL_RTX) 1331 : target); 1332 insns = arm_gen_constant (code, mode, temp2, new_src, 1333 source, subtargets, generate); 1334 source = new_src; 1335 if (generate) 1336 emit_insn (gen_rtx_SET 1337 (VOIDmode, target, 1338 gen_rtx_IOR (mode, 1339 gen_rtx_ASHIFT (mode, source, 1340 GEN_INT (i)), 1341 source))); 1342 return insns + 1; 1343 } 1344 } 1345 1346 /* Don't duplicate cases already considered. */ 1347 for (i = 17; i < 24; i++) 1348 { 1349 if (((temp1 | (temp1 >> i)) == remainder) 1350 && !const_ok_for_arm (temp1)) 1351 { 1352 rtx new_src = (subtargets 1353 ? (generate ? gen_reg_rtx (mode) : NULL_RTX) 1354 : target); 1355 insns = arm_gen_constant (code, mode, temp1, new_src, 1356 source, subtargets, generate); 1357 source = new_src; 1358 if (generate) 1359 emit_insn 1360 (gen_rtx_SET (VOIDmode, target, 1361 gen_rtx_IOR 1362 (mode, 1363 gen_rtx_LSHIFTRT (mode, source, 1364 GEN_INT (i)), 1365 source))); 1366 return insns + 1; 1367 } 1368 } 1369 } 1370 break; 1371 1372 case IOR: 1373 case XOR: 1374 /* If we have IOR or XOR, and the constant can be loaded in a 1375 single instruction, and we can find a temporary to put it in, 1376 then this can be done in two instructions instead of 3-4. */ 1377 if (subtargets 1378 /* TARGET can't be NULL if SUBTARGETS is 0 */ 1379 || (reload_completed && !reg_mentioned_p (target, source))) 1380 { 1381 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val))) 1382 { 1383 if (generate) 1384 { 1385 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 1386 1387 emit_insn (gen_rtx_SET (VOIDmode, sub, GEN_INT (val))); 1388 emit_insn (gen_rtx_SET (VOIDmode, target, 1389 gen_rtx (code, mode, source, sub))); 1390 } 1391 return 2; 1392 } 1393 } 1394 1395 if (code == XOR) 1396 break; 1397 1398 if (set_sign_bit_copies > 8 1399 && (val & (-1 << (32 - set_sign_bit_copies))) == val) 1400 { 1401 if (generate) 1402 { 1403 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 1404 rtx shift = GEN_INT (set_sign_bit_copies); 1405 1406 emit_insn (gen_rtx_SET (VOIDmode, sub, 1407 gen_rtx_NOT (mode, 1408 gen_rtx_ASHIFT (mode, 1409 source, 1410 shift)))); 1411 emit_insn (gen_rtx_SET (VOIDmode, target, 1412 gen_rtx_NOT (mode, 1413 gen_rtx_LSHIFTRT (mode, sub, 1414 shift)))); 1415 } 1416 return 2; 1417 } 1418 1419 if (set_zero_bit_copies > 8 1420 && (remainder & ((1 << set_zero_bit_copies) - 1)) == remainder) 1421 { 1422 if (generate) 1423 { 1424 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 1425 rtx shift = GEN_INT (set_zero_bit_copies); 1426 1427 emit_insn (gen_rtx_SET (VOIDmode, sub, 1428 gen_rtx_NOT (mode, 1429 gen_rtx_LSHIFTRT (mode, 1430 source, 1431 shift)))); 1432 emit_insn (gen_rtx_SET (VOIDmode, target, 1433 gen_rtx_NOT (mode, 1434 gen_rtx_ASHIFT (mode, sub, 1435 shift)))); 1436 } 1437 return 2; 1438 } 1439 1440 if (const_ok_for_arm (temp1 = ARM_SIGN_EXTEND (~val))) 1441 { 1442 if (generate) 1443 { 1444 rtx sub = subtargets ? gen_reg_rtx (mode) : target; 1445 emit_insn (gen_rtx_SET (VOIDmode, sub, 1446 gen_rtx_NOT (mode, source))); 1447 source = sub; 1448 if (subtargets) 1449 sub = gen_reg_rtx (mode); 1450 emit_insn (gen_rtx_SET (VOIDmode, sub, 1451 gen_rtx_AND (mode, source, 1452 GEN_INT (temp1)))); 1453 emit_insn (gen_rtx_SET (VOIDmode, target, 1454 gen_rtx_NOT (mode, sub))); 1455 } 1456 return 3; 1457 } 1458 break; 1459 1460 case AND: 1461 /* See if two shifts will do 2 or more insn's worth of work. */ 1462 if (clear_sign_bit_copies >= 16 && clear_sign_bit_copies < 24) 1463 { 1464 HOST_WIDE_INT shift_mask = ((0xffffffff 1465 << (32 - clear_sign_bit_copies)) 1466 & 0xffffffff); 1467 1468 if ((remainder | shift_mask) != 0xffffffff) 1469 { 1470 if (generate) 1471 { 1472 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1473 insns = arm_gen_constant (AND, mode, remainder | shift_mask, 1474 new_src, source, subtargets, 1); 1475 source = new_src; 1476 } 1477 else 1478 { 1479 rtx targ = subtargets ? NULL_RTX : target; 1480 insns = arm_gen_constant (AND, mode, remainder | shift_mask, 1481 targ, source, subtargets, 0); 1482 } 1483 } 1484 1485 if (generate) 1486 { 1487 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1488 rtx shift = GEN_INT (clear_sign_bit_copies); 1489 1490 emit_insn (gen_ashlsi3 (new_src, source, shift)); 1491 emit_insn (gen_lshrsi3 (target, new_src, shift)); 1492 } 1493 1494 return insns + 2; 1495 } 1496 1497 if (clear_zero_bit_copies >= 16 && clear_zero_bit_copies < 24) 1498 { 1499 HOST_WIDE_INT shift_mask = (1 << clear_zero_bit_copies) - 1; 1500 1501 if ((remainder | shift_mask) != 0xffffffff) 1502 { 1503 if (generate) 1504 { 1505 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1506 1507 insns = arm_gen_constant (AND, mode, remainder | shift_mask, 1508 new_src, source, subtargets, 1); 1509 source = new_src; 1510 } 1511 else 1512 { 1513 rtx targ = subtargets ? NULL_RTX : target; 1514 1515 insns = arm_gen_constant (AND, mode, remainder | shift_mask, 1516 targ, source, subtargets, 0); 1517 } 1518 } 1519 1520 if (generate) 1521 { 1522 rtx new_src = subtargets ? gen_reg_rtx (mode) : target; 1523 rtx shift = GEN_INT (clear_zero_bit_copies); 1524 1525 emit_insn (gen_lshrsi3 (new_src, source, shift)); 1526 emit_insn (gen_ashlsi3 (target, new_src, shift)); 1527 } 1528 1529 return insns + 2; 1530 } 1531 1532 break; 1533 1534 default: 1535 break; 1536 } 1537 1538 for (i = 0; i < 32; i++) 1539 if (remainder & (1 << i)) 1540 num_bits_set++; 1541 1542 if (code == AND || (can_invert && num_bits_set > 16)) 1543 remainder = (~remainder) & 0xffffffff; 1544 else if (code == PLUS && num_bits_set > 16) 1545 remainder = (-remainder) & 0xffffffff; 1546 else 1547 { 1548 can_invert = 0; 1549 can_negate = 0; 1550 } 1551 1552 /* Now try and find a way of doing the job in either two or three 1553 instructions. 1554 We start by looking for the largest block of zeros that are aligned on 1555 a 2-bit boundary, we then fill up the temps, wrapping around to the 1556 top of the word when we drop off the bottom. 1557 In the worst case this code should produce no more than four insns. */ 1558 { 1559 int best_start = 0; 1560 int best_consecutive_zeros = 0; 1561 1562 for (i = 0; i < 32; i += 2) 1563 { 1564 int consecutive_zeros = 0; 1565 1566 if (!(remainder & (3 << i))) 1567 { 1568 while ((i < 32) && !(remainder & (3 << i))) 1569 { 1570 consecutive_zeros += 2; 1571 i += 2; 1572 } 1573 if (consecutive_zeros > best_consecutive_zeros) 1574 { 1575 best_consecutive_zeros = consecutive_zeros; 1576 best_start = i - consecutive_zeros; 1577 } 1578 i -= 2; 1579 } 1580 } 1581 1582 /* So long as it won't require any more insns to do so, it's 1583 desirable to emit a small constant (in bits 0...9) in the last 1584 insn. This way there is more chance that it can be combined with 1585 a later addressing insn to form a pre-indexed load or store 1586 operation. Consider: 1587 1588 *((volatile int *)0xe0000100) = 1; 1589 *((volatile int *)0xe0000110) = 2; 1590 1591 We want this to wind up as: 1592 1593 mov rA, #0xe0000000 1594 mov rB, #1 1595 str rB, [rA, #0x100] 1596 mov rB, #2 1597 str rB, [rA, #0x110] 1598 1599 rather than having to synthesize both large constants from scratch. 1600 1601 Therefore, we calculate how many insns would be required to emit 1602 the constant starting from `best_start', and also starting from 1603 zero (ie with bit 31 first to be output). If `best_start' doesn't 1604 yield a shorter sequence, we may as well use zero. */ 1605 if (best_start != 0 1606 && ((((unsigned HOST_WIDE_INT) 1) << best_start) < remainder) 1607 && (count_insns_for_constant (remainder, 0) <= 1608 count_insns_for_constant (remainder, best_start))) 1609 best_start = 0; 1610 1611 /* Now start emitting the insns. */ 1612 i = best_start; 1613 do 1614 { 1615 int end; 1616 1617 if (i <= 0) 1618 i += 32; 1619 if (remainder & (3 << (i - 2))) 1620 { 1621 end = i - 8; 1622 if (end < 0) 1623 end += 32; 1624 temp1 = remainder & ((0x0ff << end) 1625 | ((i < end) ? (0xff >> (32 - end)) : 0)); 1626 remainder &= ~temp1; 1627 1628 if (generate) 1629 { 1630 rtx new_src, temp1_rtx; 1631 1632 if (code == SET || code == MINUS) 1633 { 1634 new_src = (subtargets ? gen_reg_rtx (mode) : target); 1635 if (can_invert && code != MINUS) 1636 temp1 = ~temp1; 1637 } 1638 else 1639 { 1640 if (remainder && subtargets) 1641 new_src = gen_reg_rtx (mode); 1642 else 1643 new_src = target; 1644 if (can_invert) 1645 temp1 = ~temp1; 1646 else if (can_negate) 1647 temp1 = -temp1; 1648 } 1649 1650 temp1 = trunc_int_for_mode (temp1, mode); 1651 temp1_rtx = GEN_INT (temp1); 1652 1653 if (code == SET) 1654 ; 1655 else if (code == MINUS) 1656 temp1_rtx = gen_rtx_MINUS (mode, temp1_rtx, source); 1657 else 1658 temp1_rtx = gen_rtx_fmt_ee (code, mode, source, temp1_rtx); 1659 1660 emit_insn (gen_rtx_SET (VOIDmode, new_src, temp1_rtx)); 1661 source = new_src; 1662 } 1663 1664 if (code == SET) 1665 { 1666 can_invert = 0; 1667 code = PLUS; 1668 } 1669 else if (code == MINUS) 1670 code = PLUS; 1671 1672 insns++; 1673 i -= 6; 1674 } 1675 i -= 2; 1676 } 1677 while (remainder); 1678 } 1679 1680 return insns; 1681} 1682 1683/* Canonicalize a comparison so that we are more likely to recognize it. 1684 This can be done for a few constant compares, where we can make the 1685 immediate value easier to load. */ 1686 1687enum rtx_code 1688arm_canonicalize_comparison (code, op1) 1689 enum rtx_code code; 1690 rtx * op1; 1691{ 1692 unsigned HOST_WIDE_INT i = INTVAL (*op1); 1693 1694 switch (code) 1695 { 1696 case EQ: 1697 case NE: 1698 return code; 1699 1700 case GT: 1701 case LE: 1702 if (i != ((((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) - 1) 1703 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) 1704 { 1705 *op1 = GEN_INT (i + 1); 1706 return code == GT ? GE : LT; 1707 } 1708 break; 1709 1710 case GE: 1711 case LT: 1712 if (i != (((unsigned HOST_WIDE_INT) 1) << (HOST_BITS_PER_WIDE_INT - 1)) 1713 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) 1714 { 1715 *op1 = GEN_INT (i - 1); 1716 return code == GE ? GT : LE; 1717 } 1718 break; 1719 1720 case GTU: 1721 case LEU: 1722 if (i != ~((unsigned HOST_WIDE_INT) 0) 1723 && (const_ok_for_arm (i + 1) || const_ok_for_arm (-(i + 1)))) 1724 { 1725 *op1 = GEN_INT (i + 1); 1726 return code == GTU ? GEU : LTU; 1727 } 1728 break; 1729 1730 case GEU: 1731 case LTU: 1732 if (i != 0 1733 && (const_ok_for_arm (i - 1) || const_ok_for_arm (-(i - 1)))) 1734 { 1735 *op1 = GEN_INT (i - 1); 1736 return code == GEU ? GTU : LEU; 1737 } 1738 break; 1739 1740 default: 1741 abort (); 1742 } 1743 1744 return code; 1745} 1746 1747/* Decide whether a type should be returned in memory (true) 1748 or in a register (false). This is called by the macro 1749 RETURN_IN_MEMORY. */ 1750 1751int 1752arm_return_in_memory (type) 1753 tree type; 1754{ 1755 if (!AGGREGATE_TYPE_P (type)) 1756 /* All simple types are returned in registers. */ 1757 return 0; 1758 1759 /* For the arm-wince targets we choose to be compitable with Microsoft's 1760 ARM and Thumb compilers, which always return aggregates in memory. */ 1761#ifndef ARM_WINCE 1762 /* All structures/unions bigger than one word are returned in memory. 1763 Also catch the case where int_size_in_bytes returns -1. In this case 1764 the aggregate is either huge or of varaible size, and in either case 1765 we will want to return it via memory and not in a register. */ 1766 if (((unsigned int) int_size_in_bytes (type)) > UNITS_PER_WORD) 1767 return 1; 1768 1769 if (TREE_CODE (type) == RECORD_TYPE) 1770 { 1771 tree field; 1772 1773 /* For a struct the APCS says that we only return in a register 1774 if the type is 'integer like' and every addressable element 1775 has an offset of zero. For practical purposes this means 1776 that the structure can have at most one non bit-field element 1777 and that this element must be the first one in the structure. */ 1778 1779 /* Find the first field, ignoring non FIELD_DECL things which will 1780 have been created by C++. */ 1781 for (field = TYPE_FIELDS (type); 1782 field && TREE_CODE (field) != FIELD_DECL; 1783 field = TREE_CHAIN (field)) 1784 continue; 1785 1786 if (field == NULL) 1787 return 0; /* An empty structure. Allowed by an extension to ANSI C. */ 1788 1789 /* Check that the first field is valid for returning in a register. */ 1790 1791 /* ... Floats are not allowed */ 1792 if (FLOAT_TYPE_P (TREE_TYPE (field))) 1793 return 1; 1794 1795 /* ... Aggregates that are not themselves valid for returning in 1796 a register are not allowed. */ 1797 if (RETURN_IN_MEMORY (TREE_TYPE (field))) 1798 return 1; 1799 1800 /* Now check the remaining fields, if any. Only bitfields are allowed, 1801 since they are not addressable. */ 1802 for (field = TREE_CHAIN (field); 1803 field; 1804 field = TREE_CHAIN (field)) 1805 { 1806 if (TREE_CODE (field) != FIELD_DECL) 1807 continue; 1808 1809 if (!DECL_BIT_FIELD_TYPE (field)) 1810 return 1; 1811 } 1812 1813 return 0; 1814 } 1815 1816 if (TREE_CODE (type) == UNION_TYPE) 1817 { 1818 tree field; 1819 1820 /* Unions can be returned in registers if every element is 1821 integral, or can be returned in an integer register. */ 1822 for (field = TYPE_FIELDS (type); 1823 field; 1824 field = TREE_CHAIN (field)) 1825 { 1826 if (TREE_CODE (field) != FIELD_DECL) 1827 continue; 1828 1829 if (FLOAT_TYPE_P (TREE_TYPE (field))) 1830 return 1; 1831 1832 if (RETURN_IN_MEMORY (TREE_TYPE (field))) 1833 return 1; 1834 } 1835 1836 return 0; 1837 } 1838#endif /* not ARM_WINCE */ 1839 1840 /* Return all other types in memory. */ 1841 return 1; 1842} 1843 1844/* Initialize a variable CUM of type CUMULATIVE_ARGS 1845 for a call to a function whose data type is FNTYPE. 1846 For a library call, FNTYPE is NULL. */ 1847void 1848arm_init_cumulative_args (pcum, fntype, libname, indirect) 1849 CUMULATIVE_ARGS * pcum; 1850 tree fntype; 1851 rtx libname ATTRIBUTE_UNUSED; 1852 int indirect ATTRIBUTE_UNUSED; 1853{ 1854 /* On the ARM, the offset starts at 0. */ 1855 pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0); 1856 1857 pcum->call_cookie = CALL_NORMAL; 1858 1859 if (TARGET_LONG_CALLS) 1860 pcum->call_cookie = CALL_LONG; 1861 1862 /* Check for long call/short call attributes. The attributes 1863 override any command line option. */ 1864 if (fntype) 1865 { 1866 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype))) 1867 pcum->call_cookie = CALL_SHORT; 1868 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype))) 1869 pcum->call_cookie = CALL_LONG; 1870 } 1871} 1872 1873/* Determine where to put an argument to a function. 1874 Value is zero to push the argument on the stack, 1875 or a hard register in which to store the argument. 1876 1877 MODE is the argument's machine mode. 1878 TYPE is the data type of the argument (as a tree). 1879 This is null for libcalls where that information may 1880 not be available. 1881 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1882 the preceding args and about the function being called. 1883 NAMED is nonzero if this argument is a named parameter 1884 (otherwise it is an extra parameter matching an ellipsis). */ 1885 1886rtx 1887arm_function_arg (pcum, mode, type, named) 1888 CUMULATIVE_ARGS * pcum; 1889 enum machine_mode mode; 1890 tree type ATTRIBUTE_UNUSED; 1891 int named; 1892{ 1893 if (mode == VOIDmode) 1894 /* Compute operand 2 of the call insn. */ 1895 return GEN_INT (pcum->call_cookie); 1896 1897 if (!named || pcum->nregs >= NUM_ARG_REGS) 1898 return NULL_RTX; 1899 1900 return gen_rtx_REG (mode, pcum->nregs); 1901} 1902 1903/* Encode the current state of the #pragma [no_]long_calls. */ 1904typedef enum 1905{ 1906 OFF, /* No #pramgma [no_]long_calls is in effect. */ 1907 LONG, /* #pragma long_calls is in effect. */ 1908 SHORT /* #pragma no_long_calls is in effect. */ 1909} arm_pragma_enum; 1910 1911static arm_pragma_enum arm_pragma_long_calls = OFF; 1912 1913void 1914arm_pr_long_calls (pfile) 1915 cpp_reader * pfile ATTRIBUTE_UNUSED; 1916{ 1917 arm_pragma_long_calls = LONG; 1918} 1919 1920void 1921arm_pr_no_long_calls (pfile) 1922 cpp_reader * pfile ATTRIBUTE_UNUSED; 1923{ 1924 arm_pragma_long_calls = SHORT; 1925} 1926 1927void 1928arm_pr_long_calls_off (pfile) 1929 cpp_reader * pfile ATTRIBUTE_UNUSED; 1930{ 1931 arm_pragma_long_calls = OFF; 1932} 1933 1934/* Table of machine attributes. */ 1935const struct attribute_spec arm_attribute_table[] = 1936{ 1937 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ 1938 /* Function calls made to this symbol must be done indirectly, because 1939 it may lie outside of the 26 bit addressing range of a normal function 1940 call. */ 1941 { "long_call", 0, 0, false, true, true, NULL }, 1942 /* Whereas these functions are always known to reside within the 26 bit 1943 addressing range. */ 1944 { "short_call", 0, 0, false, true, true, NULL }, 1945 /* Interrupt Service Routines have special prologue and epilogue requirements. */ 1946 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute }, 1947 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute }, 1948 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute }, 1949#ifdef ARM_PE 1950 /* ARM/PE has three new attributes: 1951 interfacearm - ? 1952 dllexport - for exporting a function/variable that will live in a dll 1953 dllimport - for importing a function/variable from a dll 1954 1955 Microsoft allows multiple declspecs in one __declspec, separating 1956 them with spaces. We do NOT support this. Instead, use __declspec 1957 multiple times. 1958 */ 1959 { "dllimport", 0, 0, true, false, false, NULL }, 1960 { "dllexport", 0, 0, true, false, false, NULL }, 1961 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute }, 1962#endif 1963 { NULL, 0, 0, false, false, false, NULL } 1964}; 1965 1966/* Handle an attribute requiring a FUNCTION_DECL; 1967 arguments as in struct attribute_spec.handler. */ 1968 1969static tree 1970arm_handle_fndecl_attribute (node, name, args, flags, no_add_attrs) 1971 tree * node; 1972 tree name; 1973 tree args ATTRIBUTE_UNUSED; 1974 int flags ATTRIBUTE_UNUSED; 1975 bool * no_add_attrs; 1976{ 1977 if (TREE_CODE (*node) != FUNCTION_DECL) 1978 { 1979 warning ("`%s' attribute only applies to functions", 1980 IDENTIFIER_POINTER (name)); 1981 *no_add_attrs = true; 1982 } 1983 1984 return NULL_TREE; 1985} 1986 1987/* Handle an "interrupt" or "isr" attribute; 1988 arguments as in struct attribute_spec.handler. */ 1989 1990static tree 1991arm_handle_isr_attribute (node, name, args, flags, no_add_attrs) 1992 tree * node; 1993 tree name; 1994 tree args; 1995 int flags; 1996 bool * no_add_attrs; 1997{ 1998 if (DECL_P (*node)) 1999 { 2000 if (TREE_CODE (*node) != FUNCTION_DECL) 2001 { 2002 warning ("`%s' attribute only applies to functions", 2003 IDENTIFIER_POINTER (name)); 2004 *no_add_attrs = true; 2005 } 2006 /* FIXME: the argument if any is checked for type attributes; 2007 should it be checked for decl ones? */ 2008 } 2009 else 2010 { 2011 if (TREE_CODE (*node) == FUNCTION_TYPE 2012 || TREE_CODE (*node) == METHOD_TYPE) 2013 { 2014 if (arm_isr_value (args) == ARM_FT_UNKNOWN) 2015 { 2016 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); 2017 *no_add_attrs = true; 2018 } 2019 } 2020 else if (TREE_CODE (*node) == POINTER_TYPE 2021 && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE 2022 || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) 2023 && arm_isr_value (args) != ARM_FT_UNKNOWN) 2024 { 2025 *node = build_type_copy (*node); 2026 TREE_TYPE (*node) = build_type_attribute_variant 2027 (TREE_TYPE (*node), 2028 tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); 2029 *no_add_attrs = true; 2030 } 2031 else 2032 { 2033 /* Possibly pass this attribute on from the type to a decl. */ 2034 if (flags & ((int) ATTR_FLAG_DECL_NEXT 2035 | (int) ATTR_FLAG_FUNCTION_NEXT 2036 | (int) ATTR_FLAG_ARRAY_NEXT)) 2037 { 2038 *no_add_attrs = true; 2039 return tree_cons (name, args, NULL_TREE); 2040 } 2041 else 2042 { 2043 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); 2044 } 2045 } 2046 } 2047 2048 return NULL_TREE; 2049} 2050 2051/* Return 0 if the attributes for two types are incompatible, 1 if they 2052 are compatible, and 2 if they are nearly compatible (which causes a 2053 warning to be generated). */ 2054 2055static int 2056arm_comp_type_attributes (type1, type2) 2057 tree type1; 2058 tree type2; 2059{ 2060 int l1, l2, s1, s2; 2061 2062 /* Check for mismatch of non-default calling convention. */ 2063 if (TREE_CODE (type1) != FUNCTION_TYPE) 2064 return 1; 2065 2066 /* Check for mismatched call attributes. */ 2067 l1 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1)) != NULL; 2068 l2 = lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2)) != NULL; 2069 s1 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1)) != NULL; 2070 s2 = lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2)) != NULL; 2071 2072 /* Only bother to check if an attribute is defined. */ 2073 if (l1 | l2 | s1 | s2) 2074 { 2075 /* If one type has an attribute, the other must have the same attribute. */ 2076 if ((l1 != l2) || (s1 != s2)) 2077 return 0; 2078 2079 /* Disallow mixed attributes. */ 2080 if ((l1 & s2) || (l2 & s1)) 2081 return 0; 2082 } 2083 2084 /* Check for mismatched ISR attribute. */ 2085 l1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; 2086 if (! l1) 2087 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; 2088 l2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; 2089 if (! l2) 2090 l1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; 2091 if (l1 != l2) 2092 return 0; 2093 2094 return 1; 2095} 2096 2097/* Encode long_call or short_call attribute by prefixing 2098 symbol name in DECL with a special character FLAG. */ 2099 2100void 2101arm_encode_call_attribute (decl, flag) 2102 tree decl; 2103 int flag; 2104{ 2105 const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0); 2106 int len = strlen (str); 2107 char * newstr; 2108 2109 /* Do not allow weak functions to be treated as short call. */ 2110 if (DECL_WEAK (decl) && flag == SHORT_CALL_FLAG_CHAR) 2111 return; 2112 2113 newstr = alloca (len + 2); 2114 newstr[0] = flag; 2115 strcpy (newstr + 1, str); 2116 2117 newstr = (char *) ggc_alloc_string (newstr, len + 1); 2118 XSTR (XEXP (DECL_RTL (decl), 0), 0) = newstr; 2119} 2120 2121/* Assigns default attributes to newly defined type. This is used to 2122 set short_call/long_call attributes for function types of 2123 functions defined inside corresponding #pragma scopes. */ 2124 2125static void 2126arm_set_default_type_attributes (type) 2127 tree type; 2128{ 2129 /* Add __attribute__ ((long_call)) to all functions, when 2130 inside #pragma long_calls or __attribute__ ((short_call)), 2131 when inside #pragma no_long_calls. */ 2132 if (TREE_CODE (type) == FUNCTION_TYPE || TREE_CODE (type) == METHOD_TYPE) 2133 { 2134 tree type_attr_list, attr_name; 2135 type_attr_list = TYPE_ATTRIBUTES (type); 2136 2137 if (arm_pragma_long_calls == LONG) 2138 attr_name = get_identifier ("long_call"); 2139 else if (arm_pragma_long_calls == SHORT) 2140 attr_name = get_identifier ("short_call"); 2141 else 2142 return; 2143 2144 type_attr_list = tree_cons (attr_name, NULL_TREE, type_attr_list); 2145 TYPE_ATTRIBUTES (type) = type_attr_list; 2146 } 2147} 2148 2149/* Return 1 if the operand is a SYMBOL_REF for a function known to be 2150 defined within the current compilation unit. If this caanot be 2151 determined, then 0 is returned. */ 2152 2153static int 2154current_file_function_operand (sym_ref) 2155 rtx sym_ref; 2156{ 2157 /* This is a bit of a fib. A function will have a short call flag 2158 applied to its name if it has the short call attribute, or it has 2159 already been defined within the current compilation unit. */ 2160 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref, 0))) 2161 return 1; 2162 2163 /* The current function is always defined within the current compilation 2164 unit. if it s a weak definition however, then this may not be the real 2165 definition of the function, and so we have to say no. */ 2166 if (sym_ref == XEXP (DECL_RTL (current_function_decl), 0) 2167 && !DECL_WEAK (current_function_decl)) 2168 return 1; 2169 2170 /* We cannot make the determination - default to returning 0. */ 2171 return 0; 2172} 2173 2174/* Return non-zero if a 32 bit "long_call" should be generated for 2175 this call. We generate a long_call if the function: 2176 2177 a. has an __attribute__((long call)) 2178 or b. is within the scope of a #pragma long_calls 2179 or c. the -mlong-calls command line switch has been specified 2180 2181 However we do not generate a long call if the function: 2182 2183 d. has an __attribute__ ((short_call)) 2184 or e. is inside the scope of a #pragma no_long_calls 2185 or f. has an __attribute__ ((section)) 2186 or g. is defined within the current compilation unit. 2187 2188 This function will be called by C fragments contained in the machine 2189 description file. CALL_REF and CALL_COOKIE correspond to the matched 2190 rtl operands. CALL_SYMBOL is used to distinguish between 2191 two different callers of the function. It is set to 1 in the 2192 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call" 2193 and "call_value" patterns. This is because of the difference in the 2194 SYM_REFs passed by these patterns. */ 2195 2196int 2197arm_is_longcall_p (sym_ref, call_cookie, call_symbol) 2198 rtx sym_ref; 2199 int call_cookie; 2200 int call_symbol; 2201{ 2202 if (!call_symbol) 2203 { 2204 if (GET_CODE (sym_ref) != MEM) 2205 return 0; 2206 2207 sym_ref = XEXP (sym_ref, 0); 2208 } 2209 2210 if (GET_CODE (sym_ref) != SYMBOL_REF) 2211 return 0; 2212 2213 if (call_cookie & CALL_SHORT) 2214 return 0; 2215 2216 if (TARGET_LONG_CALLS && flag_function_sections) 2217 return 1; 2218 2219 if (current_file_function_operand (sym_ref)) 2220 return 0; 2221 2222 return (call_cookie & CALL_LONG) 2223 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref, 0)) 2224 || TARGET_LONG_CALLS; 2225} 2226 2227/* Return non-zero if it is ok to make a tail-call to DECL. */ 2228 2229int 2230arm_function_ok_for_sibcall (decl) 2231 tree decl; 2232{ 2233 int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL; 2234 2235 /* Never tailcall something for which we have no decl, or if we 2236 are in Thumb mode. */ 2237 if (decl == NULL || TARGET_THUMB) 2238 return 0; 2239 2240 /* Get the calling method. */ 2241 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) 2242 call_type = CALL_SHORT; 2243 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) 2244 call_type = CALL_LONG; 2245 2246 /* Cannot tail-call to long calls, since these are out of range of 2247 a branch instruction. However, if not compiling PIC, we know 2248 we can reach the symbol if it is in this compilation unit. */ 2249 if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl))) 2250 return 0; 2251 2252 /* If we are interworking and the function is not declared static 2253 then we can't tail-call it unless we know that it exists in this 2254 compilation unit (since it might be a Thumb routine). */ 2255 if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) 2256 return 0; 2257 2258 /* Never tailcall from an ISR routine - it needs a special exit sequence. */ 2259 if (IS_INTERRUPT (arm_current_func_type ())) 2260 return 0; 2261 2262 /* Everything else is ok. */ 2263 return 1; 2264} 2265 2266 2267int 2268legitimate_pic_operand_p (x) 2269 rtx x; 2270{ 2271 if (CONSTANT_P (x) 2272 && flag_pic 2273 && (GET_CODE (x) == SYMBOL_REF 2274 || (GET_CODE (x) == CONST 2275 && GET_CODE (XEXP (x, 0)) == PLUS 2276 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))) 2277 return 0; 2278 2279 return 1; 2280} 2281 2282rtx 2283legitimize_pic_address (orig, mode, reg) 2284 rtx orig; 2285 enum machine_mode mode; 2286 rtx reg; 2287{ 2288 if (GET_CODE (orig) == SYMBOL_REF 2289 || GET_CODE (orig) == LABEL_REF) 2290 { 2291#ifndef AOF_ASSEMBLER 2292 rtx pic_ref, address; 2293#endif 2294 rtx insn; 2295 int subregs = 0; 2296 2297 if (reg == 0) 2298 { 2299 if (no_new_pseudos) 2300 abort (); 2301 else 2302 reg = gen_reg_rtx (Pmode); 2303 2304 subregs = 1; 2305 } 2306 2307#ifdef AOF_ASSEMBLER 2308 /* The AOF assembler can generate relocations for these directly, and 2309 understands that the PIC register has to be added into the offset. */ 2310 insn = emit_insn (gen_pic_load_addr_based (reg, orig)); 2311#else 2312 if (subregs) 2313 address = gen_reg_rtx (Pmode); 2314 else 2315 address = reg; 2316 2317 if (TARGET_ARM) 2318 emit_insn (gen_pic_load_addr_arm (address, orig)); 2319 else 2320 emit_insn (gen_pic_load_addr_thumb (address, orig)); 2321 2322 if ((GET_CODE (orig) == LABEL_REF 2323 || (GET_CODE (orig) == SYMBOL_REF && 2324 ENCODED_SHORT_CALL_ATTR_P (XSTR (orig, 0)))) 2325 && NEED_GOT_RELOC) 2326 pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address); 2327 else 2328 { 2329 pic_ref = gen_rtx_MEM (Pmode, 2330 gen_rtx_PLUS (Pmode, pic_offset_table_rtx, 2331 address)); 2332 RTX_UNCHANGING_P (pic_ref) = 1; 2333 } 2334 2335 insn = emit_move_insn (reg, pic_ref); 2336#endif 2337 current_function_uses_pic_offset_table = 1; 2338 /* Put a REG_EQUAL note on this insn, so that it can be optimized 2339 by loop. */ 2340 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, 2341 REG_NOTES (insn)); 2342 return reg; 2343 } 2344 else if (GET_CODE (orig) == CONST) 2345 { 2346 rtx base, offset; 2347 2348 if (GET_CODE (XEXP (orig, 0)) == PLUS 2349 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) 2350 return orig; 2351 2352 if (reg == 0) 2353 { 2354 if (no_new_pseudos) 2355 abort (); 2356 else 2357 reg = gen_reg_rtx (Pmode); 2358 } 2359 2360 if (GET_CODE (XEXP (orig, 0)) == PLUS) 2361 { 2362 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); 2363 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, 2364 base == reg ? 0 : reg); 2365 } 2366 else 2367 abort (); 2368 2369 if (GET_CODE (offset) == CONST_INT) 2370 { 2371 /* The base register doesn't really matter, we only want to 2372 test the index for the appropriate mode. */ 2373 ARM_GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win); 2374 2375 if (!no_new_pseudos) 2376 offset = force_reg (Pmode, offset); 2377 else 2378 abort (); 2379 2380 win: 2381 if (GET_CODE (offset) == CONST_INT) 2382 return plus_constant (base, INTVAL (offset)); 2383 } 2384 2385 if (GET_MODE_SIZE (mode) > 4 2386 && (GET_MODE_CLASS (mode) == MODE_INT 2387 || TARGET_SOFT_FLOAT)) 2388 { 2389 emit_insn (gen_addsi3 (reg, base, offset)); 2390 return reg; 2391 } 2392 2393 return gen_rtx_PLUS (Pmode, base, offset); 2394 } 2395 2396 return orig; 2397} 2398 2399/* Generate code to load the PIC register. PROLOGUE is true if 2400 called from arm_expand_prologue (in which case we want the 2401 generated insns at the start of the function); false if called 2402 by an exception receiver that needs the PIC register reloaded 2403 (in which case the insns are just dumped at the current location). */ 2404 2405void 2406arm_finalize_pic (prologue) 2407 int prologue ATTRIBUTE_UNUSED; 2408{ 2409#ifndef AOF_ASSEMBLER 2410 rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx; 2411 rtx global_offset_table; 2412 2413 if (current_function_uses_pic_offset_table == 0 || TARGET_SINGLE_PIC_BASE) 2414 return; 2415 2416 if (!flag_pic) 2417 abort (); 2418 2419 start_sequence (); 2420 l1 = gen_label_rtx (); 2421 2422 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 2423 /* On the ARM the PC register contains 'dot + 8' at the time of the 2424 addition, on the Thumb it is 'dot + 4'. */ 2425 pic_tmp = plus_constant (gen_rtx_LABEL_REF (Pmode, l1), TARGET_ARM ? 8 : 4); 2426 if (GOT_PCREL) 2427 pic_tmp2 = gen_rtx_CONST (VOIDmode, 2428 gen_rtx_PLUS (Pmode, global_offset_table, pc_rtx)); 2429 else 2430 pic_tmp2 = gen_rtx_CONST (VOIDmode, global_offset_table); 2431 2432 pic_rtx = gen_rtx_CONST (Pmode, gen_rtx_MINUS (Pmode, pic_tmp2, pic_tmp)); 2433 2434 if (TARGET_ARM) 2435 { 2436 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx, pic_rtx)); 2437 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx, l1)); 2438 } 2439 else 2440 { 2441 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx, pic_rtx)); 2442 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx, l1)); 2443 } 2444 2445 seq = gen_sequence (); 2446 end_sequence (); 2447 if (prologue) 2448 emit_insn_after (seq, get_insns ()); 2449 else 2450 emit_insn (seq); 2451 2452 /* Need to emit this whether or not we obey regdecls, 2453 since setjmp/longjmp can cause life info to screw up. */ 2454 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); 2455#endif /* AOF_ASSEMBLER */ 2456} 2457 2458#define REG_OR_SUBREG_REG(X) \ 2459 (GET_CODE (X) == REG \ 2460 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) 2461 2462#define REG_OR_SUBREG_RTX(X) \ 2463 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X)) 2464 2465#ifndef COSTS_N_INSNS 2466#define COSTS_N_INSNS(N) ((N) * 4 - 2) 2467#endif 2468 2469int 2470arm_rtx_costs (x, code, outer) 2471 rtx x; 2472 enum rtx_code code; 2473 enum rtx_code outer; 2474{ 2475 enum machine_mode mode = GET_MODE (x); 2476 enum rtx_code subcode; 2477 int extra_cost; 2478 2479 if (TARGET_THUMB) 2480 { 2481 switch (code) 2482 { 2483 case ASHIFT: 2484 case ASHIFTRT: 2485 case LSHIFTRT: 2486 case ROTATERT: 2487 case PLUS: 2488 case MINUS: 2489 case COMPARE: 2490 case NEG: 2491 case NOT: 2492 return COSTS_N_INSNS (1); 2493 2494 case MULT: 2495 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 2496 { 2497 int cycles = 0; 2498 unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1)); 2499 2500 while (i) 2501 { 2502 i >>= 2; 2503 cycles++; 2504 } 2505 return COSTS_N_INSNS (2) + cycles; 2506 } 2507 return COSTS_N_INSNS (1) + 16; 2508 2509 case SET: 2510 return (COSTS_N_INSNS (1) 2511 + 4 * ((GET_CODE (SET_SRC (x)) == MEM) 2512 + GET_CODE (SET_DEST (x)) == MEM)); 2513 2514 case CONST_INT: 2515 if (outer == SET) 2516 { 2517 if ((unsigned HOST_WIDE_INT) INTVAL (x) < 256) 2518 return 0; 2519 if (thumb_shiftable_const (INTVAL (x))) 2520 return COSTS_N_INSNS (2); 2521 return COSTS_N_INSNS (3); 2522 } 2523 else if (outer == PLUS 2524 && INTVAL (x) < 256 && INTVAL (x) > -256) 2525 return 0; 2526 else if (outer == COMPARE 2527 && (unsigned HOST_WIDE_INT) INTVAL (x) < 256) 2528 return 0; 2529 else if (outer == ASHIFT || outer == ASHIFTRT 2530 || outer == LSHIFTRT) 2531 return 0; 2532 return COSTS_N_INSNS (2); 2533 2534 case CONST: 2535 case CONST_DOUBLE: 2536 case LABEL_REF: 2537 case SYMBOL_REF: 2538 return COSTS_N_INSNS (3); 2539 2540 case UDIV: 2541 case UMOD: 2542 case DIV: 2543 case MOD: 2544 return 100; 2545 2546 case TRUNCATE: 2547 return 99; 2548 2549 case AND: 2550 case XOR: 2551 case IOR: 2552 /* XXX guess. */ 2553 return 8; 2554 2555 case ADDRESSOF: 2556 case MEM: 2557 /* XXX another guess. */ 2558 /* Memory costs quite a lot for the first word, but subsequent words 2559 load at the equivalent of a single insn each. */ 2560 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) 2561 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); 2562 2563 case IF_THEN_ELSE: 2564 /* XXX a guess. */ 2565 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) 2566 return 14; 2567 return 2; 2568 2569 case ZERO_EXTEND: 2570 /* XXX still guessing. */ 2571 switch (GET_MODE (XEXP (x, 0))) 2572 { 2573 case QImode: 2574 return (1 + (mode == DImode ? 4 : 0) 2575 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 2576 2577 case HImode: 2578 return (4 + (mode == DImode ? 4 : 0) 2579 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 2580 2581 case SImode: 2582 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 2583 2584 default: 2585 return 99; 2586 } 2587 2588 default: 2589 return 99; 2590#if 0 2591 case FFS: 2592 case FLOAT: 2593 case FIX: 2594 case UNSIGNED_FIX: 2595 /* XXX guess */ 2596 fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n", 2597 rtx_name[code]); 2598 abort (); 2599#endif 2600 } 2601 } 2602 2603 switch (code) 2604 { 2605 case MEM: 2606 /* Memory costs quite a lot for the first word, but subsequent words 2607 load at the equivalent of a single insn each. */ 2608 return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD) 2609 + (CONSTANT_POOL_ADDRESS_P (x) ? 4 : 0)); 2610 2611 case DIV: 2612 case MOD: 2613 return 100; 2614 2615 case ROTATE: 2616 if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) 2617 return 4; 2618 /* Fall through */ 2619 case ROTATERT: 2620 if (mode != SImode) 2621 return 8; 2622 /* Fall through */ 2623 case ASHIFT: case LSHIFTRT: case ASHIFTRT: 2624 if (mode == DImode) 2625 return (8 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : 8) 2626 + ((GET_CODE (XEXP (x, 0)) == REG 2627 || (GET_CODE (XEXP (x, 0)) == SUBREG 2628 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) 2629 ? 0 : 8)); 2630 return (1 + ((GET_CODE (XEXP (x, 0)) == REG 2631 || (GET_CODE (XEXP (x, 0)) == SUBREG 2632 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)) 2633 ? 0 : 4) 2634 + ((GET_CODE (XEXP (x, 1)) == REG 2635 || (GET_CODE (XEXP (x, 1)) == SUBREG 2636 && GET_CODE (SUBREG_REG (XEXP (x, 1))) == REG) 2637 || (GET_CODE (XEXP (x, 1)) == CONST_INT)) 2638 ? 0 : 4)); 2639 2640 case MINUS: 2641 if (mode == DImode) 2642 return (4 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 8) 2643 + ((REG_OR_SUBREG_REG (XEXP (x, 0)) 2644 || (GET_CODE (XEXP (x, 0)) == CONST_INT 2645 && const_ok_for_arm (INTVAL (XEXP (x, 0))))) 2646 ? 0 : 8)); 2647 2648 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 2649 return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 2650 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE 2651 && const_double_rtx_ok_for_fpu (XEXP (x, 1)))) 2652 ? 0 : 8) 2653 + ((REG_OR_SUBREG_REG (XEXP (x, 0)) 2654 || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE 2655 && const_double_rtx_ok_for_fpu (XEXP (x, 0)))) 2656 ? 0 : 8)); 2657 2658 if (((GET_CODE (XEXP (x, 0)) == CONST_INT 2659 && const_ok_for_arm (INTVAL (XEXP (x, 0))) 2660 && REG_OR_SUBREG_REG (XEXP (x, 1)))) 2661 || (((subcode = GET_CODE (XEXP (x, 1))) == ASHIFT 2662 || subcode == ASHIFTRT || subcode == LSHIFTRT 2663 || subcode == ROTATE || subcode == ROTATERT 2664 || (subcode == MULT 2665 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT 2666 && ((INTVAL (XEXP (XEXP (x, 1), 1)) & 2667 (INTVAL (XEXP (XEXP (x, 1), 1)) - 1)) == 0))) 2668 && REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 0)) 2669 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 1), 1)) 2670 || GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT) 2671 && REG_OR_SUBREG_REG (XEXP (x, 0)))) 2672 return 1; 2673 /* Fall through */ 2674 2675 case PLUS: 2676 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 2677 return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) 2678 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 2679 || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE 2680 && const_double_rtx_ok_for_fpu (XEXP (x, 1)))) 2681 ? 0 : 8)); 2682 2683 /* Fall through */ 2684 case AND: case XOR: case IOR: 2685 extra_cost = 0; 2686 2687 /* Normally the frame registers will be spilt into reg+const during 2688 reload, so it is a bad idea to combine them with other instructions, 2689 since then they might not be moved outside of loops. As a compromise 2690 we allow integration with ops that have a constant as their second 2691 operand. */ 2692 if ((REG_OR_SUBREG_REG (XEXP (x, 0)) 2693 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))) 2694 && GET_CODE (XEXP (x, 1)) != CONST_INT) 2695 || (REG_OR_SUBREG_REG (XEXP (x, 0)) 2696 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x, 0))))) 2697 extra_cost = 4; 2698 2699 if (mode == DImode) 2700 return (4 + extra_cost + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) 2701 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 2702 || (GET_CODE (XEXP (x, 1)) == CONST_INT 2703 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) 2704 ? 0 : 8)); 2705 2706 if (REG_OR_SUBREG_REG (XEXP (x, 0))) 2707 return (1 + (GET_CODE (XEXP (x, 1)) == CONST_INT ? 0 : extra_cost) 2708 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) 2709 || (GET_CODE (XEXP (x, 1)) == CONST_INT 2710 && const_ok_for_op (INTVAL (XEXP (x, 1)), code))) 2711 ? 0 : 4)); 2712 2713 else if (REG_OR_SUBREG_REG (XEXP (x, 1))) 2714 return (1 + extra_cost 2715 + ((((subcode = GET_CODE (XEXP (x, 0))) == ASHIFT 2716 || subcode == LSHIFTRT || subcode == ASHIFTRT 2717 || subcode == ROTATE || subcode == ROTATERT 2718 || (subcode == MULT 2719 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2720 && ((INTVAL (XEXP (XEXP (x, 0), 1)) & 2721 (INTVAL (XEXP (XEXP (x, 0), 1)) - 1)) == 0))) 2722 && (REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 0))) 2723 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x, 0), 1))) 2724 || GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)) 2725 ? 0 : 4)); 2726 2727 return 8; 2728 2729 case MULT: 2730 /* There is no point basing this on the tuning, since it is always the 2731 fast variant if it exists at all. */ 2732 if (arm_fast_multiply && mode == DImode 2733 && (GET_CODE (XEXP (x, 0)) == GET_CODE (XEXP (x, 1))) 2734 && (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 2735 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)) 2736 return 8; 2737 2738 if (GET_MODE_CLASS (mode) == MODE_FLOAT 2739 || mode == DImode) 2740 return 30; 2741 2742 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 2743 { 2744 unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) 2745 & (unsigned HOST_WIDE_INT) 0xffffffff); 2746 int add_cost = const_ok_for_arm (i) ? 4 : 8; 2747 int j; 2748 2749 /* Tune as appropriate. */ 2750 int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2); 2751 2752 for (j = 0; i && j < 32; j += booth_unit_size) 2753 { 2754 i >>= booth_unit_size; 2755 add_cost += 2; 2756 } 2757 2758 return add_cost; 2759 } 2760 2761 return (((tune_flags & FL_FAST_MULT) ? 8 : 30) 2762 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4) 2763 + (REG_OR_SUBREG_REG (XEXP (x, 1)) ? 0 : 4)); 2764 2765 case TRUNCATE: 2766 if (arm_fast_multiply && mode == SImode 2767 && GET_CODE (XEXP (x, 0)) == LSHIFTRT 2768 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT 2769 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) 2770 == GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1))) 2771 && (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ZERO_EXTEND 2772 || GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SIGN_EXTEND)) 2773 return 8; 2774 return 99; 2775 2776 case NEG: 2777 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 2778 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 6); 2779 /* Fall through */ 2780 case NOT: 2781 if (mode == DImode) 2782 return 4 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); 2783 2784 return 1 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 4); 2785 2786 case IF_THEN_ELSE: 2787 if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) 2788 return 14; 2789 return 2; 2790 2791 case COMPARE: 2792 return 1; 2793 2794 case ABS: 2795 return 4 + (mode == DImode ? 4 : 0); 2796 2797 case SIGN_EXTEND: 2798 if (GET_MODE (XEXP (x, 0)) == QImode) 2799 return (4 + (mode == DImode ? 4 : 0) 2800 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 2801 /* Fall through */ 2802 case ZERO_EXTEND: 2803 switch (GET_MODE (XEXP (x, 0))) 2804 { 2805 case QImode: 2806 return (1 + (mode == DImode ? 4 : 0) 2807 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 2808 2809 case HImode: 2810 return (4 + (mode == DImode ? 4 : 0) 2811 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 2812 2813 case SImode: 2814 return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); 2815 2816 default: 2817 break; 2818 } 2819 abort (); 2820 2821 case CONST_INT: 2822 if (const_ok_for_arm (INTVAL (x))) 2823 return outer == SET ? 2 : -1; 2824 else if (outer == AND 2825 && const_ok_for_arm (~INTVAL (x))) 2826 return -1; 2827 else if ((outer == COMPARE 2828 || outer == PLUS || outer == MINUS) 2829 && const_ok_for_arm (-INTVAL (x))) 2830 return -1; 2831 else 2832 return 5; 2833 2834 case CONST: 2835 case LABEL_REF: 2836 case SYMBOL_REF: 2837 return 6; 2838 2839 case CONST_DOUBLE: 2840 if (const_double_rtx_ok_for_fpu (x)) 2841 return outer == SET ? 2 : -1; 2842 else if ((outer == COMPARE || outer == PLUS) 2843 && neg_const_double_rtx_ok_for_fpu (x)) 2844 return -1; 2845 return 7; 2846 2847 default: 2848 return 99; 2849 } 2850} 2851 2852static int 2853arm_adjust_cost (insn, link, dep, cost) 2854 rtx insn; 2855 rtx link; 2856 rtx dep; 2857 int cost; 2858{ 2859 rtx i_pat, d_pat; 2860 2861 /* Some true dependencies can have a higher cost depending 2862 on precisely how certain input operands are used. */ 2863 if (arm_is_xscale 2864 && REG_NOTE_KIND (link) == 0 2865 && recog_memoized (insn) < 0 2866 && recog_memoized (dep) < 0) 2867 { 2868 int shift_opnum = get_attr_shift (insn); 2869 enum attr_type attr_type = get_attr_type (dep); 2870 2871 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted 2872 operand for INSN. If we have a shifted input operand and the 2873 instruction we depend on is another ALU instruction, then we may 2874 have to account for an additional stall. */ 2875 if (shift_opnum != 0 && attr_type == TYPE_NORMAL) 2876 { 2877 rtx shifted_operand; 2878 int opno; 2879 2880 /* Get the shifted operand. */ 2881 extract_insn (insn); 2882 shifted_operand = recog_data.operand[shift_opnum]; 2883 2884 /* Iterate over all the operands in DEP. If we write an operand 2885 that overlaps with SHIFTED_OPERAND, then we have increase the 2886 cost of this dependency. */ 2887 extract_insn (dep); 2888 preprocess_constraints (); 2889 for (opno = 0; opno < recog_data.n_operands; opno++) 2890 { 2891 /* We can ignore strict inputs. */ 2892 if (recog_data.operand_type[opno] == OP_IN) 2893 continue; 2894 2895 if (reg_overlap_mentioned_p (recog_data.operand[opno], 2896 shifted_operand)) 2897 return 2; 2898 } 2899 } 2900 } 2901 2902 /* XXX This is not strictly true for the FPA. */ 2903 if (REG_NOTE_KIND (link) == REG_DEP_ANTI 2904 || REG_NOTE_KIND (link) == REG_DEP_OUTPUT) 2905 return 0; 2906 2907 /* Call insns don't incur a stall, even if they follow a load. */ 2908 if (REG_NOTE_KIND (link) == 0 2909 && GET_CODE (insn) == CALL_INSN) 2910 return 1; 2911 2912 if ((i_pat = single_set (insn)) != NULL 2913 && GET_CODE (SET_SRC (i_pat)) == MEM 2914 && (d_pat = single_set (dep)) != NULL 2915 && GET_CODE (SET_DEST (d_pat)) == MEM) 2916 { 2917 /* This is a load after a store, there is no conflict if the load reads 2918 from a cached area. Assume that loads from the stack, and from the 2919 constant pool are cached, and that others will miss. This is a 2920 hack. */ 2921 2922 if (CONSTANT_POOL_ADDRESS_P (XEXP (SET_SRC (i_pat), 0)) 2923 || reg_mentioned_p (stack_pointer_rtx, XEXP (SET_SRC (i_pat), 0)) 2924 || reg_mentioned_p (frame_pointer_rtx, XEXP (SET_SRC (i_pat), 0)) 2925 || reg_mentioned_p (hard_frame_pointer_rtx, 2926 XEXP (SET_SRC (i_pat), 0))) 2927 return 1; 2928 } 2929 2930 return cost; 2931} 2932 2933/* This code has been fixed for cross compilation. */ 2934 2935static int fpa_consts_inited = 0; 2936 2937static const char * const strings_fpa[8] = 2938{ 2939 "0", "1", "2", "3", 2940 "4", "5", "0.5", "10" 2941}; 2942 2943static REAL_VALUE_TYPE values_fpa[8]; 2944 2945static void 2946init_fpa_table () 2947{ 2948 int i; 2949 REAL_VALUE_TYPE r; 2950 2951 for (i = 0; i < 8; i++) 2952 { 2953 r = REAL_VALUE_ATOF (strings_fpa[i], DFmode); 2954 values_fpa[i] = r; 2955 } 2956 2957 fpa_consts_inited = 1; 2958} 2959 2960/* Return TRUE if rtx X is a valid immediate FPU constant. */ 2961 2962int 2963const_double_rtx_ok_for_fpu (x) 2964 rtx x; 2965{ 2966 REAL_VALUE_TYPE r; 2967 int i; 2968 2969 if (!fpa_consts_inited) 2970 init_fpa_table (); 2971 2972 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 2973 if (REAL_VALUE_MINUS_ZERO (r)) 2974 return 0; 2975 2976 for (i = 0; i < 8; i++) 2977 if (REAL_VALUES_EQUAL (r, values_fpa[i])) 2978 return 1; 2979 2980 return 0; 2981} 2982 2983/* Return TRUE if rtx X is a valid immediate FPU constant. */ 2984 2985int 2986neg_const_double_rtx_ok_for_fpu (x) 2987 rtx x; 2988{ 2989 REAL_VALUE_TYPE r; 2990 int i; 2991 2992 if (!fpa_consts_inited) 2993 init_fpa_table (); 2994 2995 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 2996 r = REAL_VALUE_NEGATE (r); 2997 if (REAL_VALUE_MINUS_ZERO (r)) 2998 return 0; 2999 3000 for (i = 0; i < 8; i++) 3001 if (REAL_VALUES_EQUAL (r, values_fpa[i])) 3002 return 1; 3003 3004 return 0; 3005} 3006 3007/* Predicates for `match_operand' and `match_operator'. */ 3008 3009/* s_register_operand is the same as register_operand, but it doesn't accept 3010 (SUBREG (MEM)...). 3011 3012 This function exists because at the time it was put in it led to better 3013 code. SUBREG(MEM) always needs a reload in the places where 3014 s_register_operand is used, and this seemed to lead to excessive 3015 reloading. */ 3016 3017int 3018s_register_operand (op, mode) 3019 rtx op; 3020 enum machine_mode mode; 3021{ 3022 if (GET_MODE (op) != mode && mode != VOIDmode) 3023 return 0; 3024 3025 if (GET_CODE (op) == SUBREG) 3026 op = SUBREG_REG (op); 3027 3028 /* We don't consider registers whose class is NO_REGS 3029 to be a register operand. */ 3030 /* XXX might have to check for lo regs only for thumb ??? */ 3031 return (GET_CODE (op) == REG 3032 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 3033 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); 3034} 3035 3036/* A hard register operand (even before reload. */ 3037 3038int 3039arm_hard_register_operand (op, mode) 3040 rtx op; 3041 enum machine_mode mode; 3042{ 3043 if (GET_MODE (op) != mode && mode != VOIDmode) 3044 return 0; 3045 3046 return (GET_CODE (op) == REG 3047 && REGNO (op) < FIRST_PSEUDO_REGISTER); 3048} 3049 3050/* Only accept reg, subreg(reg), const_int. */ 3051 3052int 3053reg_or_int_operand (op, mode) 3054 rtx op; 3055 enum machine_mode mode; 3056{ 3057 if (GET_CODE (op) == CONST_INT) 3058 return 1; 3059 3060 if (GET_MODE (op) != mode && mode != VOIDmode) 3061 return 0; 3062 3063 if (GET_CODE (op) == SUBREG) 3064 op = SUBREG_REG (op); 3065 3066 /* We don't consider registers whose class is NO_REGS 3067 to be a register operand. */ 3068 return (GET_CODE (op) == REG 3069 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 3070 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS)); 3071} 3072 3073/* Return 1 if OP is an item in memory, given that we are in reload. */ 3074 3075int 3076arm_reload_memory_operand (op, mode) 3077 rtx op; 3078 enum machine_mode mode ATTRIBUTE_UNUSED; 3079{ 3080 int regno = true_regnum (op); 3081 3082 return (!CONSTANT_P (op) 3083 && (regno == -1 3084 || (GET_CODE (op) == REG 3085 && REGNO (op) >= FIRST_PSEUDO_REGISTER))); 3086} 3087 3088/* Return 1 if OP is a valid memory address, but not valid for a signed byte 3089 memory access (architecture V4). 3090 MODE is QImode if called when computing constraints, or VOIDmode when 3091 emitting patterns. In this latter case we cannot use memory_operand() 3092 because it will fail on badly formed MEMs, which is precisly what we are 3093 trying to catch. */ 3094 3095int 3096bad_signed_byte_operand (op, mode) 3097 rtx op; 3098 enum machine_mode mode ATTRIBUTE_UNUSED; 3099{ 3100#if 0 3101 if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM) 3102 return 0; 3103#endif 3104 if (GET_CODE (op) != MEM) 3105 return 0; 3106 3107 op = XEXP (op, 0); 3108 3109 /* A sum of anything more complex than reg + reg or reg + const is bad. */ 3110 if ((GET_CODE (op) == PLUS || GET_CODE (op) == MINUS) 3111 && (!s_register_operand (XEXP (op, 0), VOIDmode) 3112 || (!s_register_operand (XEXP (op, 1), VOIDmode) 3113 && GET_CODE (XEXP (op, 1)) != CONST_INT))) 3114 return 1; 3115 3116 /* Big constants are also bad. */ 3117 if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT 3118 && (INTVAL (XEXP (op, 1)) > 0xff 3119 || -INTVAL (XEXP (op, 1)) > 0xff)) 3120 return 1; 3121 3122 /* Everything else is good, or can will automatically be made so. */ 3123 return 0; 3124} 3125 3126/* Return TRUE for valid operands for the rhs of an ARM instruction. */ 3127 3128int 3129arm_rhs_operand (op, mode) 3130 rtx op; 3131 enum machine_mode mode; 3132{ 3133 return (s_register_operand (op, mode) 3134 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))); 3135} 3136 3137/* Return TRUE for valid operands for the 3138 rhs of an ARM instruction, or a load. */ 3139 3140int 3141arm_rhsm_operand (op, mode) 3142 rtx op; 3143 enum machine_mode mode; 3144{ 3145 return (s_register_operand (op, mode) 3146 || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))) 3147 || memory_operand (op, mode)); 3148} 3149 3150/* Return TRUE for valid operands for the rhs of an ARM instruction, or if a 3151 constant that is valid when negated. */ 3152 3153int 3154arm_add_operand (op, mode) 3155 rtx op; 3156 enum machine_mode mode; 3157{ 3158 if (TARGET_THUMB) 3159 return thumb_cmp_operand (op, mode); 3160 3161 return (s_register_operand (op, mode) 3162 || (GET_CODE (op) == CONST_INT 3163 && (const_ok_for_arm (INTVAL (op)) 3164 || const_ok_for_arm (-INTVAL (op))))); 3165} 3166 3167int 3168arm_not_operand (op, mode) 3169 rtx op; 3170 enum machine_mode mode; 3171{ 3172 return (s_register_operand (op, mode) 3173 || (GET_CODE (op) == CONST_INT 3174 && (const_ok_for_arm (INTVAL (op)) 3175 || const_ok_for_arm (~INTVAL (op))))); 3176} 3177 3178/* Return TRUE if the operand is a memory reference which contains an 3179 offsettable address. */ 3180 3181int 3182offsettable_memory_operand (op, mode) 3183 rtx op; 3184 enum machine_mode mode; 3185{ 3186 if (mode == VOIDmode) 3187 mode = GET_MODE (op); 3188 3189 return (mode == GET_MODE (op) 3190 && GET_CODE (op) == MEM 3191 && offsettable_address_p (reload_completed | reload_in_progress, 3192 mode, XEXP (op, 0))); 3193} 3194 3195/* Return TRUE if the operand is a memory reference which is, or can be 3196 made word aligned by adjusting the offset. */ 3197 3198int 3199alignable_memory_operand (op, mode) 3200 rtx op; 3201 enum machine_mode mode; 3202{ 3203 rtx reg; 3204 3205 if (mode == VOIDmode) 3206 mode = GET_MODE (op); 3207 3208 if (mode != GET_MODE (op) || GET_CODE (op) != MEM) 3209 return 0; 3210 3211 op = XEXP (op, 0); 3212 3213 return ((GET_CODE (reg = op) == REG 3214 || (GET_CODE (op) == SUBREG 3215 && GET_CODE (reg = SUBREG_REG (op)) == REG) 3216 || (GET_CODE (op) == PLUS 3217 && GET_CODE (XEXP (op, 1)) == CONST_INT 3218 && (GET_CODE (reg = XEXP (op, 0)) == REG 3219 || (GET_CODE (XEXP (op, 0)) == SUBREG 3220 && GET_CODE (reg = SUBREG_REG (XEXP (op, 0))) == REG)))) 3221 && REGNO_POINTER_ALIGN (REGNO (reg)) >= 32); 3222} 3223 3224/* Similar to s_register_operand, but does not allow hard integer 3225 registers. */ 3226 3227int 3228f_register_operand (op, mode) 3229 rtx op; 3230 enum machine_mode mode; 3231{ 3232 if (GET_MODE (op) != mode && mode != VOIDmode) 3233 return 0; 3234 3235 if (GET_CODE (op) == SUBREG) 3236 op = SUBREG_REG (op); 3237 3238 /* We don't consider registers whose class is NO_REGS 3239 to be a register operand. */ 3240 return (GET_CODE (op) == REG 3241 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 3242 || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS)); 3243} 3244 3245/* Return TRUE for valid operands for the rhs of an FPU instruction. */ 3246 3247int 3248fpu_rhs_operand (op, mode) 3249 rtx op; 3250 enum machine_mode mode; 3251{ 3252 if (s_register_operand (op, mode)) 3253 return TRUE; 3254 3255 if (GET_MODE (op) != mode && mode != VOIDmode) 3256 return FALSE; 3257 3258 if (GET_CODE (op) == CONST_DOUBLE) 3259 return const_double_rtx_ok_for_fpu (op); 3260 3261 return FALSE; 3262} 3263 3264int 3265fpu_add_operand (op, mode) 3266 rtx op; 3267 enum machine_mode mode; 3268{ 3269 if (s_register_operand (op, mode)) 3270 return TRUE; 3271 3272 if (GET_MODE (op) != mode && mode != VOIDmode) 3273 return FALSE; 3274 3275 if (GET_CODE (op) == CONST_DOUBLE) 3276 return (const_double_rtx_ok_for_fpu (op) 3277 || neg_const_double_rtx_ok_for_fpu (op)); 3278 3279 return FALSE; 3280} 3281 3282/* Return nonzero if OP is a constant power of two. */ 3283 3284int 3285power_of_two_operand (op, mode) 3286 rtx op; 3287 enum machine_mode mode ATTRIBUTE_UNUSED; 3288{ 3289 if (GET_CODE (op) == CONST_INT) 3290 { 3291 HOST_WIDE_INT value = INTVAL (op); 3292 3293 return value != 0 && (value & (value - 1)) == 0; 3294 } 3295 3296 return FALSE; 3297} 3298 3299/* Return TRUE for a valid operand of a DImode operation. 3300 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). 3301 Note that this disallows MEM(REG+REG), but allows 3302 MEM(PRE/POST_INC/DEC(REG)). */ 3303 3304int 3305di_operand (op, mode) 3306 rtx op; 3307 enum machine_mode mode; 3308{ 3309 if (s_register_operand (op, mode)) 3310 return TRUE; 3311 3312 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) 3313 return FALSE; 3314 3315 if (GET_CODE (op) == SUBREG) 3316 op = SUBREG_REG (op); 3317 3318 switch (GET_CODE (op)) 3319 { 3320 case CONST_DOUBLE: 3321 case CONST_INT: 3322 return TRUE; 3323 3324 case MEM: 3325 return memory_address_p (DImode, XEXP (op, 0)); 3326 3327 default: 3328 return FALSE; 3329 } 3330} 3331 3332/* Like di_operand, but don't accept constants. */ 3333 3334int 3335nonimmediate_di_operand (op, mode) 3336 rtx op; 3337 enum machine_mode mode; 3338{ 3339 if (s_register_operand (op, mode)) 3340 return TRUE; 3341 3342 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode) 3343 return FALSE; 3344 3345 if (GET_CODE (op) == SUBREG) 3346 op = SUBREG_REG (op); 3347 3348 if (GET_CODE (op) == MEM) 3349 return memory_address_p (DImode, XEXP (op, 0)); 3350 3351 return FALSE; 3352} 3353 3354/* Return TRUE for a valid operand of a DFmode operation when -msoft-float. 3355 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). 3356 Note that this disallows MEM(REG+REG), but allows 3357 MEM(PRE/POST_INC/DEC(REG)). */ 3358 3359int 3360soft_df_operand (op, mode) 3361 rtx op; 3362 enum machine_mode mode; 3363{ 3364 if (s_register_operand (op, mode)) 3365 return TRUE; 3366 3367 if (mode != VOIDmode && GET_MODE (op) != mode) 3368 return FALSE; 3369 3370 if (GET_CODE (op) == SUBREG && CONSTANT_P (SUBREG_REG (op))) 3371 return FALSE; 3372 3373 if (GET_CODE (op) == SUBREG) 3374 op = SUBREG_REG (op); 3375 3376 switch (GET_CODE (op)) 3377 { 3378 case CONST_DOUBLE: 3379 return TRUE; 3380 3381 case MEM: 3382 return memory_address_p (DFmode, XEXP (op, 0)); 3383 3384 default: 3385 return FALSE; 3386 } 3387} 3388 3389/* Like soft_df_operand, but don't accept constants. */ 3390 3391int 3392nonimmediate_soft_df_operand (op, mode) 3393 rtx op; 3394 enum machine_mode mode; 3395{ 3396 if (s_register_operand (op, mode)) 3397 return TRUE; 3398 3399 if (mode != VOIDmode && GET_MODE (op) != mode) 3400 return FALSE; 3401 3402 if (GET_CODE (op) == SUBREG) 3403 op = SUBREG_REG (op); 3404 3405 if (GET_CODE (op) == MEM) 3406 return memory_address_p (DFmode, XEXP (op, 0)); 3407 return FALSE; 3408} 3409 3410/* Return TRUE for valid index operands. */ 3411 3412int 3413index_operand (op, mode) 3414 rtx op; 3415 enum machine_mode mode; 3416{ 3417 return (s_register_operand (op, mode) 3418 || (immediate_operand (op, mode) 3419 && (GET_CODE (op) != CONST_INT 3420 || (INTVAL (op) < 4096 && INTVAL (op) > -4096)))); 3421} 3422 3423/* Return TRUE for valid shifts by a constant. This also accepts any 3424 power of two on the (somewhat overly relaxed) assumption that the 3425 shift operator in this case was a mult. */ 3426 3427int 3428const_shift_operand (op, mode) 3429 rtx op; 3430 enum machine_mode mode; 3431{ 3432 return (power_of_two_operand (op, mode) 3433 || (immediate_operand (op, mode) 3434 && (GET_CODE (op) != CONST_INT 3435 || (INTVAL (op) < 32 && INTVAL (op) > 0)))); 3436} 3437 3438/* Return TRUE for arithmetic operators which can be combined with a multiply 3439 (shift). */ 3440 3441int 3442shiftable_operator (x, mode) 3443 rtx x; 3444 enum machine_mode mode; 3445{ 3446 enum rtx_code code; 3447 3448 if (GET_MODE (x) != mode) 3449 return FALSE; 3450 3451 code = GET_CODE (x); 3452 3453 return (code == PLUS || code == MINUS 3454 || code == IOR || code == XOR || code == AND); 3455} 3456 3457/* Return TRUE for binary logical operators. */ 3458 3459int 3460logical_binary_operator (x, mode) 3461 rtx x; 3462 enum machine_mode mode; 3463{ 3464 enum rtx_code code; 3465 3466 if (GET_MODE (x) != mode) 3467 return FALSE; 3468 3469 code = GET_CODE (x); 3470 3471 return (code == IOR || code == XOR || code == AND); 3472} 3473 3474/* Return TRUE for shift operators. */ 3475 3476int 3477shift_operator (x, mode) 3478 rtx x; 3479 enum machine_mode mode; 3480{ 3481 enum rtx_code code; 3482 3483 if (GET_MODE (x) != mode) 3484 return FALSE; 3485 3486 code = GET_CODE (x); 3487 3488 if (code == MULT) 3489 return power_of_two_operand (XEXP (x, 1), mode); 3490 3491 return (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT 3492 || code == ROTATERT); 3493} 3494 3495/* Return TRUE if x is EQ or NE. */ 3496 3497int 3498equality_operator (x, mode) 3499 rtx x; 3500 enum machine_mode mode ATTRIBUTE_UNUSED; 3501{ 3502 return GET_CODE (x) == EQ || GET_CODE (x) == NE; 3503} 3504 3505/* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */ 3506 3507int 3508arm_comparison_operator (x, mode) 3509 rtx x; 3510 enum machine_mode mode; 3511{ 3512 return (comparison_operator (x, mode) 3513 && GET_CODE (x) != LTGT 3514 && GET_CODE (x) != UNEQ); 3515} 3516 3517/* Return TRUE for SMIN SMAX UMIN UMAX operators. */ 3518 3519int 3520minmax_operator (x, mode) 3521 rtx x; 3522 enum machine_mode mode; 3523{ 3524 enum rtx_code code = GET_CODE (x); 3525 3526 if (GET_MODE (x) != mode) 3527 return FALSE; 3528 3529 return code == SMIN || code == SMAX || code == UMIN || code == UMAX; 3530} 3531 3532/* Return TRUE if this is the condition code register, if we aren't given 3533 a mode, accept any class CCmode register. */ 3534 3535int 3536cc_register (x, mode) 3537 rtx x; 3538 enum machine_mode mode; 3539{ 3540 if (mode == VOIDmode) 3541 { 3542 mode = GET_MODE (x); 3543 3544 if (GET_MODE_CLASS (mode) != MODE_CC) 3545 return FALSE; 3546 } 3547 3548 if ( GET_MODE (x) == mode 3549 && GET_CODE (x) == REG 3550 && REGNO (x) == CC_REGNUM) 3551 return TRUE; 3552 3553 return FALSE; 3554} 3555 3556/* Return TRUE if this is the condition code register, if we aren't given 3557 a mode, accept any class CCmode register which indicates a dominance 3558 expression. */ 3559 3560int 3561dominant_cc_register (x, mode) 3562 rtx x; 3563 enum machine_mode mode; 3564{ 3565 if (mode == VOIDmode) 3566 { 3567 mode = GET_MODE (x); 3568 3569 if (GET_MODE_CLASS (mode) != MODE_CC) 3570 return FALSE; 3571 } 3572 3573 if ( mode != CC_DNEmode && mode != CC_DEQmode 3574 && mode != CC_DLEmode && mode != CC_DLTmode 3575 && mode != CC_DGEmode && mode != CC_DGTmode 3576 && mode != CC_DLEUmode && mode != CC_DLTUmode 3577 && mode != CC_DGEUmode && mode != CC_DGTUmode) 3578 return FALSE; 3579 3580 return cc_register (x, mode); 3581} 3582 3583/* Return TRUE if X references a SYMBOL_REF. */ 3584 3585int 3586symbol_mentioned_p (x) 3587 rtx x; 3588{ 3589 const char * fmt; 3590 int i; 3591 3592 if (GET_CODE (x) == SYMBOL_REF) 3593 return 1; 3594 3595 fmt = GET_RTX_FORMAT (GET_CODE (x)); 3596 3597 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 3598 { 3599 if (fmt[i] == 'E') 3600 { 3601 int j; 3602 3603 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3604 if (symbol_mentioned_p (XVECEXP (x, i, j))) 3605 return 1; 3606 } 3607 else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) 3608 return 1; 3609 } 3610 3611 return 0; 3612} 3613 3614/* Return TRUE if X references a LABEL_REF. */ 3615 3616int 3617label_mentioned_p (x) 3618 rtx x; 3619{ 3620 const char * fmt; 3621 int i; 3622 3623 if (GET_CODE (x) == LABEL_REF) 3624 return 1; 3625 3626 fmt = GET_RTX_FORMAT (GET_CODE (x)); 3627 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 3628 { 3629 if (fmt[i] == 'E') 3630 { 3631 int j; 3632 3633 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3634 if (label_mentioned_p (XVECEXP (x, i, j))) 3635 return 1; 3636 } 3637 else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) 3638 return 1; 3639 } 3640 3641 return 0; 3642} 3643 3644enum rtx_code 3645minmax_code (x) 3646 rtx x; 3647{ 3648 enum rtx_code code = GET_CODE (x); 3649 3650 if (code == SMAX) 3651 return GE; 3652 else if (code == SMIN) 3653 return LE; 3654 else if (code == UMIN) 3655 return LEU; 3656 else if (code == UMAX) 3657 return GEU; 3658 3659 abort (); 3660} 3661 3662/* Return 1 if memory locations are adjacent. */ 3663 3664int 3665adjacent_mem_locations (a, b) 3666 rtx a, b; 3667{ 3668 if ((GET_CODE (XEXP (a, 0)) == REG 3669 || (GET_CODE (XEXP (a, 0)) == PLUS 3670 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT)) 3671 && (GET_CODE (XEXP (b, 0)) == REG 3672 || (GET_CODE (XEXP (b, 0)) == PLUS 3673 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT))) 3674 { 3675 int val0 = 0, val1 = 0; 3676 int reg0, reg1; 3677 3678 if (GET_CODE (XEXP (a, 0)) == PLUS) 3679 { 3680 reg0 = REGNO (XEXP (XEXP (a, 0), 0)); 3681 val0 = INTVAL (XEXP (XEXP (a, 0), 1)); 3682 } 3683 else 3684 reg0 = REGNO (XEXP (a, 0)); 3685 3686 if (GET_CODE (XEXP (b, 0)) == PLUS) 3687 { 3688 reg1 = REGNO (XEXP (XEXP (b, 0), 0)); 3689 val1 = INTVAL (XEXP (XEXP (b, 0), 1)); 3690 } 3691 else 3692 reg1 = REGNO (XEXP (b, 0)); 3693 3694 return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4); 3695 } 3696 return 0; 3697} 3698 3699/* Return 1 if OP is a load multiple operation. It is known to be 3700 parallel and the first section will be tested. */ 3701 3702int 3703load_multiple_operation (op, mode) 3704 rtx op; 3705 enum machine_mode mode ATTRIBUTE_UNUSED; 3706{ 3707 HOST_WIDE_INT count = XVECLEN (op, 0); 3708 int dest_regno; 3709 rtx src_addr; 3710 HOST_WIDE_INT i = 1, base = 0; 3711 rtx elt; 3712 3713 if (count <= 1 3714 || GET_CODE (XVECEXP (op, 0, 0)) != SET) 3715 return 0; 3716 3717 /* Check to see if this might be a write-back. */ 3718 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) 3719 { 3720 i++; 3721 base = 1; 3722 3723 /* Now check it more carefully. */ 3724 if (GET_CODE (SET_DEST (elt)) != REG 3725 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG 3726 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) 3727 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT 3728 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) 3729 return 0; 3730 } 3731 3732 /* Perform a quick check so we don't blow up below. */ 3733 if (count <= i 3734 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET 3735 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG 3736 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != MEM) 3737 return 0; 3738 3739 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); 3740 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); 3741 3742 for (; i < count; i++) 3743 { 3744 elt = XVECEXP (op, 0, i); 3745 3746 if (GET_CODE (elt) != SET 3747 || GET_CODE (SET_DEST (elt)) != REG 3748 || GET_MODE (SET_DEST (elt)) != SImode 3749 || REGNO (SET_DEST (elt)) != (unsigned int)(dest_regno + i - base) 3750 || GET_CODE (SET_SRC (elt)) != MEM 3751 || GET_MODE (SET_SRC (elt)) != SImode 3752 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS 3753 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr) 3754 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT 3755 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != (i - base) * 4) 3756 return 0; 3757 } 3758 3759 return 1; 3760} 3761 3762/* Return 1 if OP is a store multiple operation. It is known to be 3763 parallel and the first section will be tested. */ 3764 3765int 3766store_multiple_operation (op, mode) 3767 rtx op; 3768 enum machine_mode mode ATTRIBUTE_UNUSED; 3769{ 3770 HOST_WIDE_INT count = XVECLEN (op, 0); 3771 int src_regno; 3772 rtx dest_addr; 3773 HOST_WIDE_INT i = 1, base = 0; 3774 rtx elt; 3775 3776 if (count <= 1 3777 || GET_CODE (XVECEXP (op, 0, 0)) != SET) 3778 return 0; 3779 3780 /* Check to see if this might be a write-back. */ 3781 if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) 3782 { 3783 i++; 3784 base = 1; 3785 3786 /* Now check it more carefully. */ 3787 if (GET_CODE (SET_DEST (elt)) != REG 3788 || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG 3789 || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) 3790 || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT 3791 || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) 3792 return 0; 3793 } 3794 3795 /* Perform a quick check so we don't blow up below. */ 3796 if (count <= i 3797 || GET_CODE (XVECEXP (op, 0, i - 1)) != SET 3798 || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM 3799 || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != REG) 3800 return 0; 3801 3802 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); 3803 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); 3804 3805 for (; i < count; i++) 3806 { 3807 elt = XVECEXP (op, 0, i); 3808 3809 if (GET_CODE (elt) != SET 3810 || GET_CODE (SET_SRC (elt)) != REG 3811 || GET_MODE (SET_SRC (elt)) != SImode 3812 || REGNO (SET_SRC (elt)) != (unsigned int)(src_regno + i - base) 3813 || GET_CODE (SET_DEST (elt)) != MEM 3814 || GET_MODE (SET_DEST (elt)) != SImode 3815 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS 3816 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr) 3817 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT 3818 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != (i - base) * 4) 3819 return 0; 3820 } 3821 3822 return 1; 3823} 3824 3825int 3826load_multiple_sequence (operands, nops, regs, base, load_offset) 3827 rtx * operands; 3828 int nops; 3829 int * regs; 3830 int * base; 3831 HOST_WIDE_INT * load_offset; 3832{ 3833 int unsorted_regs[4]; 3834 HOST_WIDE_INT unsorted_offsets[4]; 3835 int order[4]; 3836 int base_reg = -1; 3837 int i; 3838 3839 /* Can only handle 2, 3, or 4 insns at present, 3840 though could be easily extended if required. */ 3841 if (nops < 2 || nops > 4) 3842 abort (); 3843 3844 /* Loop over the operands and check that the memory references are 3845 suitable (ie immediate offsets from the same base register). At 3846 the same time, extract the target register, and the memory 3847 offsets. */ 3848 for (i = 0; i < nops; i++) 3849 { 3850 rtx reg; 3851 rtx offset; 3852 3853 /* Convert a subreg of a mem into the mem itself. */ 3854 if (GET_CODE (operands[nops + i]) == SUBREG) 3855 operands[nops + i] = alter_subreg (operands + (nops + i)); 3856 3857 if (GET_CODE (operands[nops + i]) != MEM) 3858 abort (); 3859 3860 /* Don't reorder volatile memory references; it doesn't seem worth 3861 looking for the case where the order is ok anyway. */ 3862 if (MEM_VOLATILE_P (operands[nops + i])) 3863 return 0; 3864 3865 offset = const0_rtx; 3866 3867 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG 3868 || (GET_CODE (reg) == SUBREG 3869 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 3870 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS 3871 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) 3872 == REG) 3873 || (GET_CODE (reg) == SUBREG 3874 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 3875 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) 3876 == CONST_INT))) 3877 { 3878 if (i == 0) 3879 { 3880 base_reg = REGNO (reg); 3881 unsorted_regs[0] = (GET_CODE (operands[i]) == REG 3882 ? REGNO (operands[i]) 3883 : REGNO (SUBREG_REG (operands[i]))); 3884 order[0] = 0; 3885 } 3886 else 3887 { 3888 if (base_reg != (int) REGNO (reg)) 3889 /* Not addressed from the same base register. */ 3890 return 0; 3891 3892 unsorted_regs[i] = (GET_CODE (operands[i]) == REG 3893 ? REGNO (operands[i]) 3894 : REGNO (SUBREG_REG (operands[i]))); 3895 if (unsorted_regs[i] < unsorted_regs[order[0]]) 3896 order[0] = i; 3897 } 3898 3899 /* If it isn't an integer register, or if it overwrites the 3900 base register but isn't the last insn in the list, then 3901 we can't do this. */ 3902 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14 3903 || (i != nops - 1 && unsorted_regs[i] == base_reg)) 3904 return 0; 3905 3906 unsorted_offsets[i] = INTVAL (offset); 3907 } 3908 else 3909 /* Not a suitable memory address. */ 3910 return 0; 3911 } 3912 3913 /* All the useful information has now been extracted from the 3914 operands into unsorted_regs and unsorted_offsets; additionally, 3915 order[0] has been set to the lowest numbered register in the 3916 list. Sort the registers into order, and check that the memory 3917 offsets are ascending and adjacent. */ 3918 3919 for (i = 1; i < nops; i++) 3920 { 3921 int j; 3922 3923 order[i] = order[i - 1]; 3924 for (j = 0; j < nops; j++) 3925 if (unsorted_regs[j] > unsorted_regs[order[i - 1]] 3926 && (order[i] == order[i - 1] 3927 || unsorted_regs[j] < unsorted_regs[order[i]])) 3928 order[i] = j; 3929 3930 /* Have we found a suitable register? if not, one must be used more 3931 than once. */ 3932 if (order[i] == order[i - 1]) 3933 return 0; 3934 3935 /* Is the memory address adjacent and ascending? */ 3936 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) 3937 return 0; 3938 } 3939 3940 if (base) 3941 { 3942 *base = base_reg; 3943 3944 for (i = 0; i < nops; i++) 3945 regs[i] = unsorted_regs[order[i]]; 3946 3947 *load_offset = unsorted_offsets[order[0]]; 3948 } 3949 3950 if (unsorted_offsets[order[0]] == 0) 3951 return 1; /* ldmia */ 3952 3953 if (unsorted_offsets[order[0]] == 4) 3954 return 2; /* ldmib */ 3955 3956 if (unsorted_offsets[order[nops - 1]] == 0) 3957 return 3; /* ldmda */ 3958 3959 if (unsorted_offsets[order[nops - 1]] == -4) 3960 return 4; /* ldmdb */ 3961 3962 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm 3963 if the offset isn't small enough. The reason 2 ldrs are faster 3964 is because these ARMs are able to do more than one cache access 3965 in a single cycle. The ARM9 and StrongARM have Harvard caches, 3966 whilst the ARM8 has a double bandwidth cache. This means that 3967 these cores can do both an instruction fetch and a data fetch in 3968 a single cycle, so the trick of calculating the address into a 3969 scratch register (one of the result regs) and then doing a load 3970 multiple actually becomes slower (and no smaller in code size). 3971 That is the transformation 3972 3973 ldr rd1, [rbase + offset] 3974 ldr rd2, [rbase + offset + 4] 3975 3976 to 3977 3978 add rd1, rbase, offset 3979 ldmia rd1, {rd1, rd2} 3980 3981 produces worse code -- '3 cycles + any stalls on rd2' instead of 3982 '2 cycles + any stalls on rd2'. On ARMs with only one cache 3983 access per cycle, the first sequence could never complete in less 3984 than 6 cycles, whereas the ldm sequence would only take 5 and 3985 would make better use of sequential accesses if not hitting the 3986 cache. 3987 3988 We cheat here and test 'arm_ld_sched' which we currently know to 3989 only be true for the ARM8, ARM9 and StrongARM. If this ever 3990 changes, then the test below needs to be reworked. */ 3991 if (nops == 2 && arm_ld_sched) 3992 return 0; 3993 3994 /* Can't do it without setting up the offset, only do this if it takes 3995 no more than one insn. */ 3996 return (const_ok_for_arm (unsorted_offsets[order[0]]) 3997 || const_ok_for_arm (-unsorted_offsets[order[0]])) ? 5 : 0; 3998} 3999 4000const char * 4001emit_ldm_seq (operands, nops) 4002 rtx * operands; 4003 int nops; 4004{ 4005 int regs[4]; 4006 int base_reg; 4007 HOST_WIDE_INT offset; 4008 char buf[100]; 4009 int i; 4010 4011 switch (load_multiple_sequence (operands, nops, regs, &base_reg, &offset)) 4012 { 4013 case 1: 4014 strcpy (buf, "ldm%?ia\t"); 4015 break; 4016 4017 case 2: 4018 strcpy (buf, "ldm%?ib\t"); 4019 break; 4020 4021 case 3: 4022 strcpy (buf, "ldm%?da\t"); 4023 break; 4024 4025 case 4: 4026 strcpy (buf, "ldm%?db\t"); 4027 break; 4028 4029 case 5: 4030 if (offset >= 0) 4031 sprintf (buf, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, 4032 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], 4033 (long) offset); 4034 else 4035 sprintf (buf, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX, 4036 reg_names[regs[0]], REGISTER_PREFIX, reg_names[base_reg], 4037 (long) -offset); 4038 output_asm_insn (buf, operands); 4039 base_reg = regs[0]; 4040 strcpy (buf, "ldm%?ia\t"); 4041 break; 4042 4043 default: 4044 abort (); 4045 } 4046 4047 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, 4048 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); 4049 4050 for (i = 1; i < nops; i++) 4051 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, 4052 reg_names[regs[i]]); 4053 4054 strcat (buf, "}\t%@ phole ldm"); 4055 4056 output_asm_insn (buf, operands); 4057 return ""; 4058} 4059 4060int 4061store_multiple_sequence (operands, nops, regs, base, load_offset) 4062 rtx * operands; 4063 int nops; 4064 int * regs; 4065 int * base; 4066 HOST_WIDE_INT * load_offset; 4067{ 4068 int unsorted_regs[4]; 4069 HOST_WIDE_INT unsorted_offsets[4]; 4070 int order[4]; 4071 int base_reg = -1; 4072 int i; 4073 4074 /* Can only handle 2, 3, or 4 insns at present, though could be easily 4075 extended if required. */ 4076 if (nops < 2 || nops > 4) 4077 abort (); 4078 4079 /* Loop over the operands and check that the memory references are 4080 suitable (ie immediate offsets from the same base register). At 4081 the same time, extract the target register, and the memory 4082 offsets. */ 4083 for (i = 0; i < nops; i++) 4084 { 4085 rtx reg; 4086 rtx offset; 4087 4088 /* Convert a subreg of a mem into the mem itself. */ 4089 if (GET_CODE (operands[nops + i]) == SUBREG) 4090 operands[nops + i] = alter_subreg (operands + (nops + i)); 4091 4092 if (GET_CODE (operands[nops + i]) != MEM) 4093 abort (); 4094 4095 /* Don't reorder volatile memory references; it doesn't seem worth 4096 looking for the case where the order is ok anyway. */ 4097 if (MEM_VOLATILE_P (operands[nops + i])) 4098 return 0; 4099 4100 offset = const0_rtx; 4101 4102 if ((GET_CODE (reg = XEXP (operands[nops + i], 0)) == REG 4103 || (GET_CODE (reg) == SUBREG 4104 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 4105 || (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS 4106 && ((GET_CODE (reg = XEXP (XEXP (operands[nops + i], 0), 0)) 4107 == REG) 4108 || (GET_CODE (reg) == SUBREG 4109 && GET_CODE (reg = SUBREG_REG (reg)) == REG)) 4110 && (GET_CODE (offset = XEXP (XEXP (operands[nops + i], 0), 1)) 4111 == CONST_INT))) 4112 { 4113 if (i == 0) 4114 { 4115 base_reg = REGNO (reg); 4116 unsorted_regs[0] = (GET_CODE (operands[i]) == REG 4117 ? REGNO (operands[i]) 4118 : REGNO (SUBREG_REG (operands[i]))); 4119 order[0] = 0; 4120 } 4121 else 4122 { 4123 if (base_reg != (int) REGNO (reg)) 4124 /* Not addressed from the same base register. */ 4125 return 0; 4126 4127 unsorted_regs[i] = (GET_CODE (operands[i]) == REG 4128 ? REGNO (operands[i]) 4129 : REGNO (SUBREG_REG (operands[i]))); 4130 if (unsorted_regs[i] < unsorted_regs[order[0]]) 4131 order[0] = i; 4132 } 4133 4134 /* If it isn't an integer register, then we can't do this. */ 4135 if (unsorted_regs[i] < 0 || unsorted_regs[i] > 14) 4136 return 0; 4137 4138 unsorted_offsets[i] = INTVAL (offset); 4139 } 4140 else 4141 /* Not a suitable memory address. */ 4142 return 0; 4143 } 4144 4145 /* All the useful information has now been extracted from the 4146 operands into unsorted_regs and unsorted_offsets; additionally, 4147 order[0] has been set to the lowest numbered register in the 4148 list. Sort the registers into order, and check that the memory 4149 offsets are ascending and adjacent. */ 4150 4151 for (i = 1; i < nops; i++) 4152 { 4153 int j; 4154 4155 order[i] = order[i - 1]; 4156 for (j = 0; j < nops; j++) 4157 if (unsorted_regs[j] > unsorted_regs[order[i - 1]] 4158 && (order[i] == order[i - 1] 4159 || unsorted_regs[j] < unsorted_regs[order[i]])) 4160 order[i] = j; 4161 4162 /* Have we found a suitable register? if not, one must be used more 4163 than once. */ 4164 if (order[i] == order[i - 1]) 4165 return 0; 4166 4167 /* Is the memory address adjacent and ascending? */ 4168 if (unsorted_offsets[order[i]] != unsorted_offsets[order[i - 1]] + 4) 4169 return 0; 4170 } 4171 4172 if (base) 4173 { 4174 *base = base_reg; 4175 4176 for (i = 0; i < nops; i++) 4177 regs[i] = unsorted_regs[order[i]]; 4178 4179 *load_offset = unsorted_offsets[order[0]]; 4180 } 4181 4182 if (unsorted_offsets[order[0]] == 0) 4183 return 1; /* stmia */ 4184 4185 if (unsorted_offsets[order[0]] == 4) 4186 return 2; /* stmib */ 4187 4188 if (unsorted_offsets[order[nops - 1]] == 0) 4189 return 3; /* stmda */ 4190 4191 if (unsorted_offsets[order[nops - 1]] == -4) 4192 return 4; /* stmdb */ 4193 4194 return 0; 4195} 4196 4197const char * 4198emit_stm_seq (operands, nops) 4199 rtx * operands; 4200 int nops; 4201{ 4202 int regs[4]; 4203 int base_reg; 4204 HOST_WIDE_INT offset; 4205 char buf[100]; 4206 int i; 4207 4208 switch (store_multiple_sequence (operands, nops, regs, &base_reg, &offset)) 4209 { 4210 case 1: 4211 strcpy (buf, "stm%?ia\t"); 4212 break; 4213 4214 case 2: 4215 strcpy (buf, "stm%?ib\t"); 4216 break; 4217 4218 case 3: 4219 strcpy (buf, "stm%?da\t"); 4220 break; 4221 4222 case 4: 4223 strcpy (buf, "stm%?db\t"); 4224 break; 4225 4226 default: 4227 abort (); 4228 } 4229 4230 sprintf (buf + strlen (buf), "%s%s, {%s%s", REGISTER_PREFIX, 4231 reg_names[base_reg], REGISTER_PREFIX, reg_names[regs[0]]); 4232 4233 for (i = 1; i < nops; i++) 4234 sprintf (buf + strlen (buf), ", %s%s", REGISTER_PREFIX, 4235 reg_names[regs[i]]); 4236 4237 strcat (buf, "}\t%@ phole stm"); 4238 4239 output_asm_insn (buf, operands); 4240 return ""; 4241} 4242 4243int 4244multi_register_push (op, mode) 4245 rtx op; 4246 enum machine_mode mode ATTRIBUTE_UNUSED; 4247{ 4248 if (GET_CODE (op) != PARALLEL 4249 || (GET_CODE (XVECEXP (op, 0, 0)) != SET) 4250 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC) 4251 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT)) 4252 return 0; 4253 4254 return 1; 4255} 4256 4257/* Routines for use in generating RTL. */ 4258 4259rtx 4260arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p, 4261 in_struct_p, scalar_p) 4262 int base_regno; 4263 int count; 4264 rtx from; 4265 int up; 4266 int write_back; 4267 int unchanging_p; 4268 int in_struct_p; 4269 int scalar_p; 4270{ 4271 int i = 0, j; 4272 rtx result; 4273 int sign = up ? 1 : -1; 4274 rtx mem; 4275 4276 /* XScale has load-store double instructions, but they have stricter 4277 alignment requirements than load-store multiple, so we can not 4278 use them. 4279 4280 For XScale ldm requires 2 + NREGS cycles to complete and blocks 4281 the pipeline until completion. 4282 4283 NREGS CYCLES 4284 1 3 4285 2 4 4286 3 5 4287 4 6 4288 4289 An ldr instruction takes 1-3 cycles, but does not block the 4290 pipeline. 4291 4292 NREGS CYCLES 4293 1 1-3 4294 2 2-6 4295 3 3-9 4296 4 4-12 4297 4298 Best case ldr will always win. However, the more ldr instructions 4299 we issue, the less likely we are to be able to schedule them well. 4300 Using ldr instructions also increases code size. 4301 4302 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm 4303 for counts of 3 or 4 regs. */ 4304 if (arm_is_xscale && count <= 2 && ! optimize_size) 4305 { 4306 rtx seq; 4307 4308 start_sequence (); 4309 4310 for (i = 0; i < count; i++) 4311 { 4312 mem = gen_rtx_MEM (SImode, plus_constant (from, i * 4 * sign)); 4313 RTX_UNCHANGING_P (mem) = unchanging_p; 4314 MEM_IN_STRUCT_P (mem) = in_struct_p; 4315 MEM_SCALAR_P (mem) = scalar_p; 4316 emit_move_insn (gen_rtx_REG (SImode, base_regno + i), mem); 4317 } 4318 4319 if (write_back) 4320 emit_move_insn (from, plus_constant (from, count * 4 * sign)); 4321 4322 seq = gen_sequence (); 4323 end_sequence (); 4324 4325 return seq; 4326 } 4327 4328 result = gen_rtx_PARALLEL (VOIDmode, 4329 rtvec_alloc (count + (write_back ? 1 : 0))); 4330 if (write_back) 4331 { 4332 XVECEXP (result, 0, 0) 4333 = gen_rtx_SET (GET_MODE (from), from, 4334 plus_constant (from, count * 4 * sign)); 4335 i = 1; 4336 count++; 4337 } 4338 4339 for (j = 0; i < count; i++, j++) 4340 { 4341 mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4 * sign)); 4342 RTX_UNCHANGING_P (mem) = unchanging_p; 4343 MEM_IN_STRUCT_P (mem) = in_struct_p; 4344 MEM_SCALAR_P (mem) = scalar_p; 4345 XVECEXP (result, 0, i) 4346 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, base_regno + j), mem); 4347 } 4348 4349 return result; 4350} 4351 4352rtx 4353arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p, 4354 in_struct_p, scalar_p) 4355 int base_regno; 4356 int count; 4357 rtx to; 4358 int up; 4359 int write_back; 4360 int unchanging_p; 4361 int in_struct_p; 4362 int scalar_p; 4363{ 4364 int i = 0, j; 4365 rtx result; 4366 int sign = up ? 1 : -1; 4367 rtx mem; 4368 4369 /* See arm_gen_load_multiple for discussion of 4370 the pros/cons of ldm/stm usage for XScale. */ 4371 if (arm_is_xscale && count <= 2 && ! optimize_size) 4372 { 4373 rtx seq; 4374 4375 start_sequence (); 4376 4377 for (i = 0; i < count; i++) 4378 { 4379 mem = gen_rtx_MEM (SImode, plus_constant (to, i * 4 * sign)); 4380 RTX_UNCHANGING_P (mem) = unchanging_p; 4381 MEM_IN_STRUCT_P (mem) = in_struct_p; 4382 MEM_SCALAR_P (mem) = scalar_p; 4383 emit_move_insn (mem, gen_rtx_REG (SImode, base_regno + i)); 4384 } 4385 4386 if (write_back) 4387 emit_move_insn (to, plus_constant (to, count * 4 * sign)); 4388 4389 seq = gen_sequence (); 4390 end_sequence (); 4391 4392 return seq; 4393 } 4394 4395 result = gen_rtx_PARALLEL (VOIDmode, 4396 rtvec_alloc (count + (write_back ? 1 : 0))); 4397 if (write_back) 4398 { 4399 XVECEXP (result, 0, 0) 4400 = gen_rtx_SET (GET_MODE (to), to, 4401 plus_constant (to, count * 4 * sign)); 4402 i = 1; 4403 count++; 4404 } 4405 4406 for (j = 0; i < count; i++, j++) 4407 { 4408 mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4 * sign)); 4409 RTX_UNCHANGING_P (mem) = unchanging_p; 4410 MEM_IN_STRUCT_P (mem) = in_struct_p; 4411 MEM_SCALAR_P (mem) = scalar_p; 4412 4413 XVECEXP (result, 0, i) 4414 = gen_rtx_SET (VOIDmode, mem, gen_rtx_REG (SImode, base_regno + j)); 4415 } 4416 4417 return result; 4418} 4419 4420int 4421arm_gen_movstrqi (operands) 4422 rtx * operands; 4423{ 4424 HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; 4425 int i; 4426 rtx src, dst; 4427 rtx st_src, st_dst, fin_src, fin_dst; 4428 rtx part_bytes_reg = NULL; 4429 rtx mem; 4430 int dst_unchanging_p, dst_in_struct_p, src_unchanging_p, src_in_struct_p; 4431 int dst_scalar_p, src_scalar_p; 4432 4433 if (GET_CODE (operands[2]) != CONST_INT 4434 || GET_CODE (operands[3]) != CONST_INT 4435 || INTVAL (operands[2]) > 64 4436 || INTVAL (operands[3]) & 3) 4437 return 0; 4438 4439 st_dst = XEXP (operands[0], 0); 4440 st_src = XEXP (operands[1], 0); 4441 4442 dst_unchanging_p = RTX_UNCHANGING_P (operands[0]); 4443 dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]); 4444 dst_scalar_p = MEM_SCALAR_P (operands[0]); 4445 src_unchanging_p = RTX_UNCHANGING_P (operands[1]); 4446 src_in_struct_p = MEM_IN_STRUCT_P (operands[1]); 4447 src_scalar_p = MEM_SCALAR_P (operands[1]); 4448 4449 fin_dst = dst = copy_to_mode_reg (SImode, st_dst); 4450 fin_src = src = copy_to_mode_reg (SImode, st_src); 4451 4452 in_words_to_go = NUM_INTS (INTVAL (operands[2])); 4453 out_words_to_go = INTVAL (operands[2]) / 4; 4454 last_bytes = INTVAL (operands[2]) & 3; 4455 4456 if (out_words_to_go != in_words_to_go && ((in_words_to_go - 1) & 3) != 0) 4457 part_bytes_reg = gen_rtx_REG (SImode, (in_words_to_go - 1) & 3); 4458 4459 for (i = 0; in_words_to_go >= 2; i+=4) 4460 { 4461 if (in_words_to_go > 4) 4462 emit_insn (arm_gen_load_multiple (0, 4, src, TRUE, TRUE, 4463 src_unchanging_p, 4464 src_in_struct_p, 4465 src_scalar_p)); 4466 else 4467 emit_insn (arm_gen_load_multiple (0, in_words_to_go, src, TRUE, 4468 FALSE, src_unchanging_p, 4469 src_in_struct_p, src_scalar_p)); 4470 4471 if (out_words_to_go) 4472 { 4473 if (out_words_to_go > 4) 4474 emit_insn (arm_gen_store_multiple (0, 4, dst, TRUE, TRUE, 4475 dst_unchanging_p, 4476 dst_in_struct_p, 4477 dst_scalar_p)); 4478 else if (out_words_to_go != 1) 4479 emit_insn (arm_gen_store_multiple (0, out_words_to_go, 4480 dst, TRUE, 4481 (last_bytes == 0 4482 ? FALSE : TRUE), 4483 dst_unchanging_p, 4484 dst_in_struct_p, 4485 dst_scalar_p)); 4486 else 4487 { 4488 mem = gen_rtx_MEM (SImode, dst); 4489 RTX_UNCHANGING_P (mem) = dst_unchanging_p; 4490 MEM_IN_STRUCT_P (mem) = dst_in_struct_p; 4491 MEM_SCALAR_P (mem) = dst_scalar_p; 4492 emit_move_insn (mem, gen_rtx_REG (SImode, 0)); 4493 if (last_bytes != 0) 4494 emit_insn (gen_addsi3 (dst, dst, GEN_INT (4))); 4495 } 4496 } 4497 4498 in_words_to_go -= in_words_to_go < 4 ? in_words_to_go : 4; 4499 out_words_to_go -= out_words_to_go < 4 ? out_words_to_go : 4; 4500 } 4501 4502 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */ 4503 if (out_words_to_go) 4504 { 4505 rtx sreg; 4506 4507 mem = gen_rtx_MEM (SImode, src); 4508 RTX_UNCHANGING_P (mem) = src_unchanging_p; 4509 MEM_IN_STRUCT_P (mem) = src_in_struct_p; 4510 MEM_SCALAR_P (mem) = src_scalar_p; 4511 emit_move_insn (sreg = gen_reg_rtx (SImode), mem); 4512 emit_move_insn (fin_src = gen_reg_rtx (SImode), plus_constant (src, 4)); 4513 4514 mem = gen_rtx_MEM (SImode, dst); 4515 RTX_UNCHANGING_P (mem) = dst_unchanging_p; 4516 MEM_IN_STRUCT_P (mem) = dst_in_struct_p; 4517 MEM_SCALAR_P (mem) = dst_scalar_p; 4518 emit_move_insn (mem, sreg); 4519 emit_move_insn (fin_dst = gen_reg_rtx (SImode), plus_constant (dst, 4)); 4520 in_words_to_go--; 4521 4522 if (in_words_to_go) /* Sanity check */ 4523 abort (); 4524 } 4525 4526 if (in_words_to_go) 4527 { 4528 if (in_words_to_go < 0) 4529 abort (); 4530 4531 mem = gen_rtx_MEM (SImode, src); 4532 RTX_UNCHANGING_P (mem) = src_unchanging_p; 4533 MEM_IN_STRUCT_P (mem) = src_in_struct_p; 4534 MEM_SCALAR_P (mem) = src_scalar_p; 4535 part_bytes_reg = copy_to_mode_reg (SImode, mem); 4536 } 4537 4538 if (last_bytes && part_bytes_reg == NULL) 4539 abort (); 4540 4541 if (BYTES_BIG_ENDIAN && last_bytes) 4542 { 4543 rtx tmp = gen_reg_rtx (SImode); 4544 4545 /* The bytes we want are in the top end of the word. */ 4546 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, 4547 GEN_INT (8 * (4 - last_bytes)))); 4548 part_bytes_reg = tmp; 4549 4550 while (last_bytes) 4551 { 4552 mem = gen_rtx_MEM (QImode, plus_constant (dst, last_bytes - 1)); 4553 RTX_UNCHANGING_P (mem) = dst_unchanging_p; 4554 MEM_IN_STRUCT_P (mem) = dst_in_struct_p; 4555 MEM_SCALAR_P (mem) = dst_scalar_p; 4556 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); 4557 4558 if (--last_bytes) 4559 { 4560 tmp = gen_reg_rtx (SImode); 4561 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (8))); 4562 part_bytes_reg = tmp; 4563 } 4564 } 4565 4566 } 4567 else 4568 { 4569 if (last_bytes > 1) 4570 { 4571 mem = gen_rtx_MEM (HImode, dst); 4572 RTX_UNCHANGING_P (mem) = dst_unchanging_p; 4573 MEM_IN_STRUCT_P (mem) = dst_in_struct_p; 4574 MEM_SCALAR_P (mem) = dst_scalar_p; 4575 emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg)); 4576 last_bytes -= 2; 4577 if (last_bytes) 4578 { 4579 rtx tmp = gen_reg_rtx (SImode); 4580 4581 emit_insn (gen_addsi3 (dst, dst, GEN_INT (2))); 4582 emit_insn (gen_lshrsi3 (tmp, part_bytes_reg, GEN_INT (16))); 4583 part_bytes_reg = tmp; 4584 } 4585 } 4586 4587 if (last_bytes) 4588 { 4589 mem = gen_rtx_MEM (QImode, dst); 4590 RTX_UNCHANGING_P (mem) = dst_unchanging_p; 4591 MEM_IN_STRUCT_P (mem) = dst_in_struct_p; 4592 MEM_SCALAR_P (mem) = dst_scalar_p; 4593 emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg)); 4594 } 4595 } 4596 4597 return 1; 4598} 4599 4600/* Generate a memory reference for a half word, such that it will be loaded 4601 into the top 16 bits of the word. We can assume that the address is 4602 known to be alignable and of the form reg, or plus (reg, const). */ 4603 4604rtx 4605arm_gen_rotated_half_load (memref) 4606 rtx memref; 4607{ 4608 HOST_WIDE_INT offset = 0; 4609 rtx base = XEXP (memref, 0); 4610 4611 if (GET_CODE (base) == PLUS) 4612 { 4613 offset = INTVAL (XEXP (base, 1)); 4614 base = XEXP (base, 0); 4615 } 4616 4617 /* If we aren't allowed to generate unaligned addresses, then fail. */ 4618 if (TARGET_MMU_TRAPS 4619 && ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 0))) 4620 return NULL; 4621 4622 base = gen_rtx_MEM (SImode, plus_constant (base, offset & ~2)); 4623 4624 if ((BYTES_BIG_ENDIAN ? 1 : 0) ^ ((offset & 2) == 2)) 4625 return base; 4626 4627 return gen_rtx_ROTATE (SImode, base, GEN_INT (16)); 4628} 4629 4630/* Select a dominance comparison mode if possible. We support three forms. 4631 COND_OR == 0 => (X && Y) 4632 COND_OR == 1 => ((! X( || Y) 4633 COND_OR == 2 => (X || Y) 4634 If we are unable to support a dominance comparsison we return CC mode. 4635 This will then fail to match for the RTL expressions that generate this 4636 call. */ 4637 4638static enum machine_mode 4639select_dominance_cc_mode (x, y, cond_or) 4640 rtx x; 4641 rtx y; 4642 HOST_WIDE_INT cond_or; 4643{ 4644 enum rtx_code cond1, cond2; 4645 int swapped = 0; 4646 4647 /* Currently we will probably get the wrong result if the individual 4648 comparisons are not simple. This also ensures that it is safe to 4649 reverse a comparison if necessary. */ 4650 if ((arm_select_cc_mode (cond1 = GET_CODE (x), XEXP (x, 0), XEXP (x, 1)) 4651 != CCmode) 4652 || (arm_select_cc_mode (cond2 = GET_CODE (y), XEXP (y, 0), XEXP (y, 1)) 4653 != CCmode)) 4654 return CCmode; 4655 4656 /* The if_then_else variant of this tests the second condition if the 4657 first passes, but is true if the first fails. Reverse the first 4658 condition to get a true "inclusive-or" expression. */ 4659 if (cond_or == 1) 4660 cond1 = reverse_condition (cond1); 4661 4662 /* If the comparisons are not equal, and one doesn't dominate the other, 4663 then we can't do this. */ 4664 if (cond1 != cond2 4665 && !comparison_dominates_p (cond1, cond2) 4666 && (swapped = 1, !comparison_dominates_p (cond2, cond1))) 4667 return CCmode; 4668 4669 if (swapped) 4670 { 4671 enum rtx_code temp = cond1; 4672 cond1 = cond2; 4673 cond2 = temp; 4674 } 4675 4676 switch (cond1) 4677 { 4678 case EQ: 4679 if (cond2 == EQ || !cond_or) 4680 return CC_DEQmode; 4681 4682 switch (cond2) 4683 { 4684 case LE: return CC_DLEmode; 4685 case LEU: return CC_DLEUmode; 4686 case GE: return CC_DGEmode; 4687 case GEU: return CC_DGEUmode; 4688 default: break; 4689 } 4690 4691 break; 4692 4693 case LT: 4694 if (cond2 == LT || !cond_or) 4695 return CC_DLTmode; 4696 if (cond2 == LE) 4697 return CC_DLEmode; 4698 if (cond2 == NE) 4699 return CC_DNEmode; 4700 break; 4701 4702 case GT: 4703 if (cond2 == GT || !cond_or) 4704 return CC_DGTmode; 4705 if (cond2 == GE) 4706 return CC_DGEmode; 4707 if (cond2 == NE) 4708 return CC_DNEmode; 4709 break; 4710 4711 case LTU: 4712 if (cond2 == LTU || !cond_or) 4713 return CC_DLTUmode; 4714 if (cond2 == LEU) 4715 return CC_DLEUmode; 4716 if (cond2 == NE) 4717 return CC_DNEmode; 4718 break; 4719 4720 case GTU: 4721 if (cond2 == GTU || !cond_or) 4722 return CC_DGTUmode; 4723 if (cond2 == GEU) 4724 return CC_DGEUmode; 4725 if (cond2 == NE) 4726 return CC_DNEmode; 4727 break; 4728 4729 /* The remaining cases only occur when both comparisons are the 4730 same. */ 4731 case NE: 4732 return CC_DNEmode; 4733 4734 case LE: 4735 return CC_DLEmode; 4736 4737 case GE: 4738 return CC_DGEmode; 4739 4740 case LEU: 4741 return CC_DLEUmode; 4742 4743 case GEU: 4744 return CC_DGEUmode; 4745 4746 default: 4747 break; 4748 } 4749 4750 abort (); 4751} 4752 4753enum machine_mode 4754arm_select_cc_mode (op, x, y) 4755 enum rtx_code op; 4756 rtx x; 4757 rtx y; 4758{ 4759 /* All floating point compares return CCFP if it is an equality 4760 comparison, and CCFPE otherwise. */ 4761 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 4762 { 4763 switch (op) 4764 { 4765 case EQ: 4766 case NE: 4767 case UNORDERED: 4768 case ORDERED: 4769 case UNLT: 4770 case UNLE: 4771 case UNGT: 4772 case UNGE: 4773 case UNEQ: 4774 case LTGT: 4775 return CCFPmode; 4776 4777 case LT: 4778 case LE: 4779 case GT: 4780 case GE: 4781 return CCFPEmode; 4782 4783 default: 4784 abort (); 4785 } 4786 } 4787 4788 /* A compare with a shifted operand. Because of canonicalization, the 4789 comparison will have to be swapped when we emit the assembler. */ 4790 if (GET_MODE (y) == SImode && GET_CODE (y) == REG 4791 && (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT 4792 || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE 4793 || GET_CODE (x) == ROTATERT)) 4794 return CC_SWPmode; 4795 4796 /* This is a special case that is used by combine to allow a 4797 comparison of a shifted byte load to be split into a zero-extend 4798 followed by a comparison of the shifted integer (only valid for 4799 equalities and unsigned inequalities). */ 4800 if (GET_MODE (x) == SImode 4801 && GET_CODE (x) == ASHIFT 4802 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 24 4803 && GET_CODE (XEXP (x, 0)) == SUBREG 4804 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == MEM 4805 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode 4806 && (op == EQ || op == NE 4807 || op == GEU || op == GTU || op == LTU || op == LEU) 4808 && GET_CODE (y) == CONST_INT) 4809 return CC_Zmode; 4810 4811 /* A construct for a conditional compare, if the false arm contains 4812 0, then both conditions must be true, otherwise either condition 4813 must be true. Not all conditions are possible, so CCmode is 4814 returned if it can't be done. */ 4815 if (GET_CODE (x) == IF_THEN_ELSE 4816 && (XEXP (x, 2) == const0_rtx 4817 || XEXP (x, 2) == const1_rtx) 4818 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 4819 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') 4820 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 4821 INTVAL (XEXP (x, 2))); 4822 4823 /* Alternate canonicalizations of the above. These are somewhat cleaner. */ 4824 if (GET_CODE (x) == AND 4825 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 4826 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') 4827 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 0); 4828 4829 if (GET_CODE (x) == IOR 4830 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' 4831 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') 4832 return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 2); 4833 4834 /* An operation that sets the condition codes as a side-effect, the 4835 V flag is not set correctly, so we can only use comparisons where 4836 this doesn't matter. (For LT and GE we can use "mi" and "pl" 4837 instead. */ 4838 if (GET_MODE (x) == SImode 4839 && y == const0_rtx 4840 && (op == EQ || op == NE || op == LT || op == GE) 4841 && (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS 4842 || GET_CODE (x) == AND || GET_CODE (x) == IOR 4843 || GET_CODE (x) == XOR || GET_CODE (x) == MULT 4844 || GET_CODE (x) == NOT || GET_CODE (x) == NEG 4845 || GET_CODE (x) == LSHIFTRT 4846 || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT 4847 || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT)) 4848 return CC_NOOVmode; 4849 4850 if (GET_MODE (x) == QImode && (op == EQ || op == NE)) 4851 return CC_Zmode; 4852 4853 if (GET_MODE (x) == SImode && (op == LTU || op == GEU) 4854 && GET_CODE (x) == PLUS 4855 && (rtx_equal_p (XEXP (x, 0), y) || rtx_equal_p (XEXP (x, 1), y))) 4856 return CC_Cmode; 4857 4858 return CCmode; 4859} 4860 4861/* X and Y are two things to compare using CODE. Emit the compare insn and 4862 return the rtx for register 0 in the proper mode. FP means this is a 4863 floating point compare: I don't think that it is needed on the arm. */ 4864 4865rtx 4866arm_gen_compare_reg (code, x, y) 4867 enum rtx_code code; 4868 rtx x, y; 4869{ 4870 enum machine_mode mode = SELECT_CC_MODE (code, x, y); 4871 rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); 4872 4873 emit_insn (gen_rtx_SET (VOIDmode, cc_reg, 4874 gen_rtx_COMPARE (mode, x, y))); 4875 4876 return cc_reg; 4877} 4878 4879void 4880arm_reload_in_hi (operands) 4881 rtx * operands; 4882{ 4883 rtx ref = operands[1]; 4884 rtx base, scratch; 4885 HOST_WIDE_INT offset = 0; 4886 4887 if (GET_CODE (ref) == SUBREG) 4888 { 4889 offset = SUBREG_BYTE (ref); 4890 ref = SUBREG_REG (ref); 4891 } 4892 4893 if (GET_CODE (ref) == REG) 4894 { 4895 /* We have a pseudo which has been spilt onto the stack; there 4896 are two cases here: the first where there is a simple 4897 stack-slot replacement and a second where the stack-slot is 4898 out of range, or is used as a subreg. */ 4899 if (reg_equiv_mem[REGNO (ref)]) 4900 { 4901 ref = reg_equiv_mem[REGNO (ref)]; 4902 base = find_replacement (&XEXP (ref, 0)); 4903 } 4904 else 4905 /* The slot is out of range, or was dressed up in a SUBREG. */ 4906 base = reg_equiv_address[REGNO (ref)]; 4907 } 4908 else 4909 base = find_replacement (&XEXP (ref, 0)); 4910 4911 /* Handle the case where the address is too complex to be offset by 1. */ 4912 if (GET_CODE (base) == MINUS 4913 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) 4914 { 4915 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 4916 4917 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); 4918 base = base_plus; 4919 } 4920 else if (GET_CODE (base) == PLUS) 4921 { 4922 /* The addend must be CONST_INT, or we would have dealt with it above. */ 4923 HOST_WIDE_INT hi, lo; 4924 4925 offset += INTVAL (XEXP (base, 1)); 4926 base = XEXP (base, 0); 4927 4928 /* Rework the address into a legal sequence of insns. */ 4929 /* Valid range for lo is -4095 -> 4095 */ 4930 lo = (offset >= 0 4931 ? (offset & 0xfff) 4932 : -((-offset) & 0xfff)); 4933 4934 /* Corner case, if lo is the max offset then we would be out of range 4935 once we have added the additional 1 below, so bump the msb into the 4936 pre-loading insn(s). */ 4937 if (lo == 4095) 4938 lo &= 0x7ff; 4939 4940 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) 4941 ^ (HOST_WIDE_INT) 0x80000000) 4942 - (HOST_WIDE_INT) 0x80000000); 4943 4944 if (hi + lo != offset) 4945 abort (); 4946 4947 if (hi != 0) 4948 { 4949 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 4950 4951 /* Get the base address; addsi3 knows how to handle constants 4952 that require more than one insn. */ 4953 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); 4954 base = base_plus; 4955 offset = lo; 4956 } 4957 } 4958 4959 scratch = gen_rtx_REG (SImode, REGNO (operands[2])); 4960 emit_insn (gen_zero_extendqisi2 (scratch, 4961 gen_rtx_MEM (QImode, 4962 plus_constant (base, 4963 offset)))); 4964 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode, operands[0], 0), 4965 gen_rtx_MEM (QImode, 4966 plus_constant (base, 4967 offset + 1)))); 4968 if (!BYTES_BIG_ENDIAN) 4969 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), 4970 gen_rtx_IOR (SImode, 4971 gen_rtx_ASHIFT 4972 (SImode, 4973 gen_rtx_SUBREG (SImode, operands[0], 0), 4974 GEN_INT (8)), 4975 scratch))); 4976 else 4977 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_SUBREG (SImode, operands[0], 0), 4978 gen_rtx_IOR (SImode, 4979 gen_rtx_ASHIFT (SImode, scratch, 4980 GEN_INT (8)), 4981 gen_rtx_SUBREG (SImode, operands[0], 4982 0)))); 4983} 4984 4985/* Handle storing a half-word to memory during reload by synthesising as two 4986 byte stores. Take care not to clobber the input values until after we 4987 have moved them somewhere safe. This code assumes that if the DImode 4988 scratch in operands[2] overlaps either the input value or output address 4989 in some way, then that value must die in this insn (we absolutely need 4990 two scratch registers for some corner cases). */ 4991 4992void 4993arm_reload_out_hi (operands) 4994 rtx * operands; 4995{ 4996 rtx ref = operands[0]; 4997 rtx outval = operands[1]; 4998 rtx base, scratch; 4999 HOST_WIDE_INT offset = 0; 5000 5001 if (GET_CODE (ref) == SUBREG) 5002 { 5003 offset = SUBREG_BYTE (ref); 5004 ref = SUBREG_REG (ref); 5005 } 5006 5007 if (GET_CODE (ref) == REG) 5008 { 5009 /* We have a pseudo which has been spilt onto the stack; there 5010 are two cases here: the first where there is a simple 5011 stack-slot replacement and a second where the stack-slot is 5012 out of range, or is used as a subreg. */ 5013 if (reg_equiv_mem[REGNO (ref)]) 5014 { 5015 ref = reg_equiv_mem[REGNO (ref)]; 5016 base = find_replacement (&XEXP (ref, 0)); 5017 } 5018 else 5019 /* The slot is out of range, or was dressed up in a SUBREG. */ 5020 base = reg_equiv_address[REGNO (ref)]; 5021 } 5022 else 5023 base = find_replacement (&XEXP (ref, 0)); 5024 5025 scratch = gen_rtx_REG (SImode, REGNO (operands[2])); 5026 5027 /* Handle the case where the address is too complex to be offset by 1. */ 5028 if (GET_CODE (base) == MINUS 5029 || (GET_CODE (base) == PLUS && GET_CODE (XEXP (base, 1)) != CONST_INT)) 5030 { 5031 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 5032 5033 /* Be careful not to destroy OUTVAL. */ 5034 if (reg_overlap_mentioned_p (base_plus, outval)) 5035 { 5036 /* Updating base_plus might destroy outval, see if we can 5037 swap the scratch and base_plus. */ 5038 if (!reg_overlap_mentioned_p (scratch, outval)) 5039 { 5040 rtx tmp = scratch; 5041 scratch = base_plus; 5042 base_plus = tmp; 5043 } 5044 else 5045 { 5046 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); 5047 5048 /* Be conservative and copy OUTVAL into the scratch now, 5049 this should only be necessary if outval is a subreg 5050 of something larger than a word. */ 5051 /* XXX Might this clobber base? I can't see how it can, 5052 since scratch is known to overlap with OUTVAL, and 5053 must be wider than a word. */ 5054 emit_insn (gen_movhi (scratch_hi, outval)); 5055 outval = scratch_hi; 5056 } 5057 } 5058 5059 emit_insn (gen_rtx_SET (VOIDmode, base_plus, base)); 5060 base = base_plus; 5061 } 5062 else if (GET_CODE (base) == PLUS) 5063 { 5064 /* The addend must be CONST_INT, or we would have dealt with it above. */ 5065 HOST_WIDE_INT hi, lo; 5066 5067 offset += INTVAL (XEXP (base, 1)); 5068 base = XEXP (base, 0); 5069 5070 /* Rework the address into a legal sequence of insns. */ 5071 /* Valid range for lo is -4095 -> 4095 */ 5072 lo = (offset >= 0 5073 ? (offset & 0xfff) 5074 : -((-offset) & 0xfff)); 5075 5076 /* Corner case, if lo is the max offset then we would be out of range 5077 once we have added the additional 1 below, so bump the msb into the 5078 pre-loading insn(s). */ 5079 if (lo == 4095) 5080 lo &= 0x7ff; 5081 5082 hi = ((((offset - lo) & (HOST_WIDE_INT) 0xffffffff) 5083 ^ (HOST_WIDE_INT) 0x80000000) 5084 - (HOST_WIDE_INT) 0x80000000); 5085 5086 if (hi + lo != offset) 5087 abort (); 5088 5089 if (hi != 0) 5090 { 5091 rtx base_plus = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 5092 5093 /* Be careful not to destroy OUTVAL. */ 5094 if (reg_overlap_mentioned_p (base_plus, outval)) 5095 { 5096 /* Updating base_plus might destroy outval, see if we 5097 can swap the scratch and base_plus. */ 5098 if (!reg_overlap_mentioned_p (scratch, outval)) 5099 { 5100 rtx tmp = scratch; 5101 scratch = base_plus; 5102 base_plus = tmp; 5103 } 5104 else 5105 { 5106 rtx scratch_hi = gen_rtx_REG (HImode, REGNO (operands[2])); 5107 5108 /* Be conservative and copy outval into scratch now, 5109 this should only be necessary if outval is a 5110 subreg of something larger than a word. */ 5111 /* XXX Might this clobber base? I can't see how it 5112 can, since scratch is known to overlap with 5113 outval. */ 5114 emit_insn (gen_movhi (scratch_hi, outval)); 5115 outval = scratch_hi; 5116 } 5117 } 5118 5119 /* Get the base address; addsi3 knows how to handle constants 5120 that require more than one insn. */ 5121 emit_insn (gen_addsi3 (base_plus, base, GEN_INT (hi))); 5122 base = base_plus; 5123 offset = lo; 5124 } 5125 } 5126 5127 if (BYTES_BIG_ENDIAN) 5128 { 5129 emit_insn (gen_movqi (gen_rtx_MEM (QImode, 5130 plus_constant (base, offset + 1)), 5131 gen_lowpart (QImode, outval))); 5132 emit_insn (gen_lshrsi3 (scratch, 5133 gen_rtx_SUBREG (SImode, outval, 0), 5134 GEN_INT (8))); 5135 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), 5136 gen_lowpart (QImode, scratch))); 5137 } 5138 else 5139 { 5140 emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)), 5141 gen_lowpart (QImode, outval))); 5142 emit_insn (gen_lshrsi3 (scratch, 5143 gen_rtx_SUBREG (SImode, outval, 0), 5144 GEN_INT (8))); 5145 emit_insn (gen_movqi (gen_rtx_MEM (QImode, 5146 plus_constant (base, offset + 1)), 5147 gen_lowpart (QImode, scratch))); 5148 } 5149} 5150 5151/* Print a symbolic form of X to the debug file, F. */ 5152 5153static void 5154arm_print_value (f, x) 5155 FILE * f; 5156 rtx x; 5157{ 5158 switch (GET_CODE (x)) 5159 { 5160 case CONST_INT: 5161 fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); 5162 return; 5163 5164 case CONST_DOUBLE: 5165 fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); 5166 return; 5167 5168 case CONST_STRING: 5169 fprintf (f, "\"%s\"", XSTR (x, 0)); 5170 return; 5171 5172 case SYMBOL_REF: 5173 fprintf (f, "`%s'", XSTR (x, 0)); 5174 return; 5175 5176 case LABEL_REF: 5177 fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); 5178 return; 5179 5180 case CONST: 5181 arm_print_value (f, XEXP (x, 0)); 5182 return; 5183 5184 case PLUS: 5185 arm_print_value (f, XEXP (x, 0)); 5186 fprintf (f, "+"); 5187 arm_print_value (f, XEXP (x, 1)); 5188 return; 5189 5190 case PC: 5191 fprintf (f, "pc"); 5192 return; 5193 5194 default: 5195 fprintf (f, "????"); 5196 return; 5197 } 5198} 5199 5200/* Routines for manipulation of the constant pool. */ 5201 5202/* Arm instructions cannot load a large constant directly into a 5203 register; they have to come from a pc relative load. The constant 5204 must therefore be placed in the addressable range of the pc 5205 relative load. Depending on the precise pc relative load 5206 instruction the range is somewhere between 256 bytes and 4k. This 5207 means that we often have to dump a constant inside a function, and 5208 generate code to branch around it. 5209 5210 It is important to minimize this, since the branches will slow 5211 things down and make the code larger. 5212 5213 Normally we can hide the table after an existing unconditional 5214 branch so that there is no interruption of the flow, but in the 5215 worst case the code looks like this: 5216 5217 ldr rn, L1 5218 ... 5219 b L2 5220 align 5221 L1: .long value 5222 L2: 5223 ... 5224 5225 ldr rn, L3 5226 ... 5227 b L4 5228 align 5229 L3: .long value 5230 L4: 5231 ... 5232 5233 We fix this by performing a scan after scheduling, which notices 5234 which instructions need to have their operands fetched from the 5235 constant table and builds the table. 5236 5237 The algorithm starts by building a table of all the constants that 5238 need fixing up and all the natural barriers in the function (places 5239 where a constant table can be dropped without breaking the flow). 5240 For each fixup we note how far the pc-relative replacement will be 5241 able to reach and the offset of the instruction into the function. 5242 5243 Having built the table we then group the fixes together to form 5244 tables that are as large as possible (subject to addressing 5245 constraints) and emit each table of constants after the last 5246 barrier that is within range of all the instructions in the group. 5247 If a group does not contain a barrier, then we forcibly create one 5248 by inserting a jump instruction into the flow. Once the table has 5249 been inserted, the insns are then modified to reference the 5250 relevant entry in the pool. 5251 5252 Possible enhancements to the algorithm (not implemented) are: 5253 5254 1) For some processors and object formats, there may be benefit in 5255 aligning the pools to the start of cache lines; this alignment 5256 would need to be taken into account when calculating addressability 5257 of a pool. */ 5258 5259/* These typedefs are located at the start of this file, so that 5260 they can be used in the prototypes there. This comment is to 5261 remind readers of that fact so that the following structures 5262 can be understood more easily. 5263 5264 typedef struct minipool_node Mnode; 5265 typedef struct minipool_fixup Mfix; */ 5266 5267struct minipool_node 5268{ 5269 /* Doubly linked chain of entries. */ 5270 Mnode * next; 5271 Mnode * prev; 5272 /* The maximum offset into the code that this entry can be placed. While 5273 pushing fixes for forward references, all entries are sorted in order 5274 of increasing max_address. */ 5275 HOST_WIDE_INT max_address; 5276 /* Similarly for an entry inserted for a backwards ref. */ 5277 HOST_WIDE_INT min_address; 5278 /* The number of fixes referencing this entry. This can become zero 5279 if we "unpush" an entry. In this case we ignore the entry when we 5280 come to emit the code. */ 5281 int refcount; 5282 /* The offset from the start of the minipool. */ 5283 HOST_WIDE_INT offset; 5284 /* The value in table. */ 5285 rtx value; 5286 /* The mode of value. */ 5287 enum machine_mode mode; 5288 int fix_size; 5289}; 5290 5291struct minipool_fixup 5292{ 5293 Mfix * next; 5294 rtx insn; 5295 HOST_WIDE_INT address; 5296 rtx * loc; 5297 enum machine_mode mode; 5298 int fix_size; 5299 rtx value; 5300 Mnode * minipool; 5301 HOST_WIDE_INT forwards; 5302 HOST_WIDE_INT backwards; 5303}; 5304 5305/* Fixes less than a word need padding out to a word boundary. */ 5306#define MINIPOOL_FIX_SIZE(mode) \ 5307 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4) 5308 5309static Mnode * minipool_vector_head; 5310static Mnode * minipool_vector_tail; 5311static rtx minipool_vector_label; 5312 5313/* The linked list of all minipool fixes required for this function. */ 5314Mfix * minipool_fix_head; 5315Mfix * minipool_fix_tail; 5316/* The fix entry for the current minipool, once it has been placed. */ 5317Mfix * minipool_barrier; 5318 5319/* Determines if INSN is the start of a jump table. Returns the end 5320 of the TABLE or NULL_RTX. */ 5321 5322static rtx 5323is_jump_table (insn) 5324 rtx insn; 5325{ 5326 rtx table; 5327 5328 if (GET_CODE (insn) == JUMP_INSN 5329 && JUMP_LABEL (insn) != NULL 5330 && ((table = next_real_insn (JUMP_LABEL (insn))) 5331 == next_real_insn (insn)) 5332 && table != NULL 5333 && GET_CODE (table) == JUMP_INSN 5334 && (GET_CODE (PATTERN (table)) == ADDR_VEC 5335 || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) 5336 return table; 5337 5338 return NULL_RTX; 5339} 5340 5341#ifndef JUMP_TABLES_IN_TEXT_SECTION 5342#define JUMP_TABLES_IN_TEXT_SECTION 0 5343#endif 5344 5345static HOST_WIDE_INT 5346get_jump_table_size (insn) 5347 rtx insn; 5348{ 5349 /* ADDR_VECs only take room if read-only data does into the text 5350 section. */ 5351 if (JUMP_TABLES_IN_TEXT_SECTION 5352#if !defined(READONLY_DATA_SECTION) 5353 || 1 5354#endif 5355 ) 5356 { 5357 rtx body = PATTERN (insn); 5358 int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; 5359 5360 return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt); 5361 } 5362 5363 return 0; 5364} 5365 5366/* Move a minipool fix MP from its current location to before MAX_MP. 5367 If MAX_MP is NULL, then MP doesn't need moving, but the addressing 5368 contrains may need updating. */ 5369 5370static Mnode * 5371move_minipool_fix_forward_ref (mp, max_mp, max_address) 5372 Mnode * mp; 5373 Mnode * max_mp; 5374 HOST_WIDE_INT max_address; 5375{ 5376 /* This should never be true and the code below assumes these are 5377 different. */ 5378 if (mp == max_mp) 5379 abort (); 5380 5381 if (max_mp == NULL) 5382 { 5383 if (max_address < mp->max_address) 5384 mp->max_address = max_address; 5385 } 5386 else 5387 { 5388 if (max_address > max_mp->max_address - mp->fix_size) 5389 mp->max_address = max_mp->max_address - mp->fix_size; 5390 else 5391 mp->max_address = max_address; 5392 5393 /* Unlink MP from its current position. Since max_mp is non-null, 5394 mp->prev must be non-null. */ 5395 mp->prev->next = mp->next; 5396 if (mp->next != NULL) 5397 mp->next->prev = mp->prev; 5398 else 5399 minipool_vector_tail = mp->prev; 5400 5401 /* Re-insert it before MAX_MP. */ 5402 mp->next = max_mp; 5403 mp->prev = max_mp->prev; 5404 max_mp->prev = mp; 5405 5406 if (mp->prev != NULL) 5407 mp->prev->next = mp; 5408 else 5409 minipool_vector_head = mp; 5410 } 5411 5412 /* Save the new entry. */ 5413 max_mp = mp; 5414 5415 /* Scan over the preceding entries and adjust their addresses as 5416 required. */ 5417 while (mp->prev != NULL 5418 && mp->prev->max_address > mp->max_address - mp->prev->fix_size) 5419 { 5420 mp->prev->max_address = mp->max_address - mp->prev->fix_size; 5421 mp = mp->prev; 5422 } 5423 5424 return max_mp; 5425} 5426 5427/* Add a constant to the minipool for a forward reference. Returns the 5428 node added or NULL if the constant will not fit in this pool. */ 5429 5430static Mnode * 5431add_minipool_forward_ref (fix) 5432 Mfix * fix; 5433{ 5434 /* If set, max_mp is the first pool_entry that has a lower 5435 constraint than the one we are trying to add. */ 5436 Mnode * max_mp = NULL; 5437 HOST_WIDE_INT max_address = fix->address + fix->forwards; 5438 Mnode * mp; 5439 5440 /* If this fix's address is greater than the address of the first 5441 entry, then we can't put the fix in this pool. We subtract the 5442 size of the current fix to ensure that if the table is fully 5443 packed we still have enough room to insert this value by suffling 5444 the other fixes forwards. */ 5445 if (minipool_vector_head && 5446 fix->address >= minipool_vector_head->max_address - fix->fix_size) 5447 return NULL; 5448 5449 /* Scan the pool to see if a constant with the same value has 5450 already been added. While we are doing this, also note the 5451 location where we must insert the constant if it doesn't already 5452 exist. */ 5453 for (mp = minipool_vector_head; mp != NULL; mp = mp->next) 5454 { 5455 if (GET_CODE (fix->value) == GET_CODE (mp->value) 5456 && fix->mode == mp->mode 5457 && (GET_CODE (fix->value) != CODE_LABEL 5458 || (CODE_LABEL_NUMBER (fix->value) 5459 == CODE_LABEL_NUMBER (mp->value))) 5460 && rtx_equal_p (fix->value, mp->value)) 5461 { 5462 /* More than one fix references this entry. */ 5463 mp->refcount++; 5464 return move_minipool_fix_forward_ref (mp, max_mp, max_address); 5465 } 5466 5467 /* Note the insertion point if necessary. */ 5468 if (max_mp == NULL 5469 && mp->max_address > max_address) 5470 max_mp = mp; 5471 } 5472 5473 /* The value is not currently in the minipool, so we need to create 5474 a new entry for it. If MAX_MP is NULL, the entry will be put on 5475 the end of the list since the placement is less constrained than 5476 any existing entry. Otherwise, we insert the new fix before 5477 MAX_MP and, if neceesary, adjust the constraints on the other 5478 entries. */ 5479 mp = xmalloc (sizeof (* mp)); 5480 mp->fix_size = fix->fix_size; 5481 mp->mode = fix->mode; 5482 mp->value = fix->value; 5483 mp->refcount = 1; 5484 /* Not yet required for a backwards ref. */ 5485 mp->min_address = -65536; 5486 5487 if (max_mp == NULL) 5488 { 5489 mp->max_address = max_address; 5490 mp->next = NULL; 5491 mp->prev = minipool_vector_tail; 5492 5493 if (mp->prev == NULL) 5494 { 5495 minipool_vector_head = mp; 5496 minipool_vector_label = gen_label_rtx (); 5497 } 5498 else 5499 mp->prev->next = mp; 5500 5501 minipool_vector_tail = mp; 5502 } 5503 else 5504 { 5505 if (max_address > max_mp->max_address - mp->fix_size) 5506 mp->max_address = max_mp->max_address - mp->fix_size; 5507 else 5508 mp->max_address = max_address; 5509 5510 mp->next = max_mp; 5511 mp->prev = max_mp->prev; 5512 max_mp->prev = mp; 5513 if (mp->prev != NULL) 5514 mp->prev->next = mp; 5515 else 5516 minipool_vector_head = mp; 5517 } 5518 5519 /* Save the new entry. */ 5520 max_mp = mp; 5521 5522 /* Scan over the preceding entries and adjust their addresses as 5523 required. */ 5524 while (mp->prev != NULL 5525 && mp->prev->max_address > mp->max_address - mp->prev->fix_size) 5526 { 5527 mp->prev->max_address = mp->max_address - mp->prev->fix_size; 5528 mp = mp->prev; 5529 } 5530 5531 return max_mp; 5532} 5533 5534static Mnode * 5535move_minipool_fix_backward_ref (mp, min_mp, min_address) 5536 Mnode * mp; 5537 Mnode * min_mp; 5538 HOST_WIDE_INT min_address; 5539{ 5540 HOST_WIDE_INT offset; 5541 5542 /* This should never be true, and the code below assumes these are 5543 different. */ 5544 if (mp == min_mp) 5545 abort (); 5546 5547 if (min_mp == NULL) 5548 { 5549 if (min_address > mp->min_address) 5550 mp->min_address = min_address; 5551 } 5552 else 5553 { 5554 /* We will adjust this below if it is too loose. */ 5555 mp->min_address = min_address; 5556 5557 /* Unlink MP from its current position. Since min_mp is non-null, 5558 mp->next must be non-null. */ 5559 mp->next->prev = mp->prev; 5560 if (mp->prev != NULL) 5561 mp->prev->next = mp->next; 5562 else 5563 minipool_vector_head = mp->next; 5564 5565 /* Reinsert it after MIN_MP. */ 5566 mp->prev = min_mp; 5567 mp->next = min_mp->next; 5568 min_mp->next = mp; 5569 if (mp->next != NULL) 5570 mp->next->prev = mp; 5571 else 5572 minipool_vector_tail = mp; 5573 } 5574 5575 min_mp = mp; 5576 5577 offset = 0; 5578 for (mp = minipool_vector_head; mp != NULL; mp = mp->next) 5579 { 5580 mp->offset = offset; 5581 if (mp->refcount > 0) 5582 offset += mp->fix_size; 5583 5584 if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) 5585 mp->next->min_address = mp->min_address + mp->fix_size; 5586 } 5587 5588 return min_mp; 5589} 5590 5591/* Add a constant to the minipool for a backward reference. Returns the 5592 node added or NULL if the constant will not fit in this pool. 5593 5594 Note that the code for insertion for a backwards reference can be 5595 somewhat confusing because the calculated offsets for each fix do 5596 not take into account the size of the pool (which is still under 5597 construction. */ 5598 5599static Mnode * 5600add_minipool_backward_ref (fix) 5601 Mfix * fix; 5602{ 5603 /* If set, min_mp is the last pool_entry that has a lower constraint 5604 than the one we are trying to add. */ 5605 Mnode * min_mp = NULL; 5606 /* This can be negative, since it is only a constraint. */ 5607 HOST_WIDE_INT min_address = fix->address - fix->backwards; 5608 Mnode * mp; 5609 5610 /* If we can't reach the current pool from this insn, or if we can't 5611 insert this entry at the end of the pool without pushing other 5612 fixes out of range, then we don't try. This ensures that we 5613 can't fail later on. */ 5614 if (min_address >= minipool_barrier->address 5615 || (minipool_vector_tail->min_address + fix->fix_size 5616 >= minipool_barrier->address)) 5617 return NULL; 5618 5619 /* Scan the pool to see if a constant with the same value has 5620 already been added. While we are doing this, also note the 5621 location where we must insert the constant if it doesn't already 5622 exist. */ 5623 for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) 5624 { 5625 if (GET_CODE (fix->value) == GET_CODE (mp->value) 5626 && fix->mode == mp->mode 5627 && (GET_CODE (fix->value) != CODE_LABEL 5628 || (CODE_LABEL_NUMBER (fix->value) 5629 == CODE_LABEL_NUMBER (mp->value))) 5630 && rtx_equal_p (fix->value, mp->value) 5631 /* Check that there is enough slack to move this entry to the 5632 end of the table (this is conservative). */ 5633 && (mp->max_address 5634 > (minipool_barrier->address 5635 + minipool_vector_tail->offset 5636 + minipool_vector_tail->fix_size))) 5637 { 5638 mp->refcount++; 5639 return move_minipool_fix_backward_ref (mp, min_mp, min_address); 5640 } 5641 5642 if (min_mp != NULL) 5643 mp->min_address += fix->fix_size; 5644 else 5645 { 5646 /* Note the insertion point if necessary. */ 5647 if (mp->min_address < min_address) 5648 min_mp = mp; 5649 else if (mp->max_address 5650 < minipool_barrier->address + mp->offset + fix->fix_size) 5651 { 5652 /* Inserting before this entry would push the fix beyond 5653 its maximum address (which can happen if we have 5654 re-located a forwards fix); force the new fix to come 5655 after it. */ 5656 min_mp = mp; 5657 min_address = mp->min_address + fix->fix_size; 5658 } 5659 } 5660 } 5661 5662 /* We need to create a new entry. */ 5663 mp = xmalloc (sizeof (* mp)); 5664 mp->fix_size = fix->fix_size; 5665 mp->mode = fix->mode; 5666 mp->value = fix->value; 5667 mp->refcount = 1; 5668 mp->max_address = minipool_barrier->address + 65536; 5669 5670 mp->min_address = min_address; 5671 5672 if (min_mp == NULL) 5673 { 5674 mp->prev = NULL; 5675 mp->next = minipool_vector_head; 5676 5677 if (mp->next == NULL) 5678 { 5679 minipool_vector_tail = mp; 5680 minipool_vector_label = gen_label_rtx (); 5681 } 5682 else 5683 mp->next->prev = mp; 5684 5685 minipool_vector_head = mp; 5686 } 5687 else 5688 { 5689 mp->next = min_mp->next; 5690 mp->prev = min_mp; 5691 min_mp->next = mp; 5692 5693 if (mp->next != NULL) 5694 mp->next->prev = mp; 5695 else 5696 minipool_vector_tail = mp; 5697 } 5698 5699 /* Save the new entry. */ 5700 min_mp = mp; 5701 5702 if (mp->prev) 5703 mp = mp->prev; 5704 else 5705 mp->offset = 0; 5706 5707 /* Scan over the following entries and adjust their offsets. */ 5708 while (mp->next != NULL) 5709 { 5710 if (mp->next->min_address < mp->min_address + mp->fix_size) 5711 mp->next->min_address = mp->min_address + mp->fix_size; 5712 5713 if (mp->refcount) 5714 mp->next->offset = mp->offset + mp->fix_size; 5715 else 5716 mp->next->offset = mp->offset; 5717 5718 mp = mp->next; 5719 } 5720 5721 return min_mp; 5722} 5723 5724static void 5725assign_minipool_offsets (barrier) 5726 Mfix * barrier; 5727{ 5728 HOST_WIDE_INT offset = 0; 5729 Mnode * mp; 5730 5731 minipool_barrier = barrier; 5732 5733 for (mp = minipool_vector_head; mp != NULL; mp = mp->next) 5734 { 5735 mp->offset = offset; 5736 5737 if (mp->refcount > 0) 5738 offset += mp->fix_size; 5739 } 5740} 5741 5742/* Output the literal table */ 5743static void 5744dump_minipool (scan) 5745 rtx scan; 5746{ 5747 Mnode * mp; 5748 Mnode * nmp; 5749 5750 if (rtl_dump_file) 5751 fprintf (rtl_dump_file, 5752 ";; Emitting minipool after insn %u; address %ld\n", 5753 INSN_UID (scan), (unsigned long) minipool_barrier->address); 5754 5755 scan = emit_label_after (gen_label_rtx (), scan); 5756 scan = emit_insn_after (gen_align_4 (), scan); 5757 scan = emit_label_after (minipool_vector_label, scan); 5758 5759 for (mp = minipool_vector_head; mp != NULL; mp = nmp) 5760 { 5761 if (mp->refcount > 0) 5762 { 5763 if (rtl_dump_file) 5764 { 5765 fprintf (rtl_dump_file, 5766 ";; Offset %u, min %ld, max %ld ", 5767 (unsigned) mp->offset, (unsigned long) mp->min_address, 5768 (unsigned long) mp->max_address); 5769 arm_print_value (rtl_dump_file, mp->value); 5770 fputc ('\n', rtl_dump_file); 5771 } 5772 5773 switch (mp->fix_size) 5774 { 5775#ifdef HAVE_consttable_1 5776 case 1: 5777 scan = emit_insn_after (gen_consttable_1 (mp->value), scan); 5778 break; 5779 5780#endif 5781#ifdef HAVE_consttable_2 5782 case 2: 5783 scan = emit_insn_after (gen_consttable_2 (mp->value), scan); 5784 break; 5785 5786#endif 5787#ifdef HAVE_consttable_4 5788 case 4: 5789 scan = emit_insn_after (gen_consttable_4 (mp->value), scan); 5790 break; 5791 5792#endif 5793#ifdef HAVE_consttable_8 5794 case 8: 5795 scan = emit_insn_after (gen_consttable_8 (mp->value), scan); 5796 break; 5797 5798#endif 5799 default: 5800 abort (); 5801 break; 5802 } 5803 } 5804 5805 nmp = mp->next; 5806 free (mp); 5807 } 5808 5809 minipool_vector_head = minipool_vector_tail = NULL; 5810 scan = emit_insn_after (gen_consttable_end (), scan); 5811 scan = emit_barrier_after (scan); 5812} 5813 5814/* Return the cost of forcibly inserting a barrier after INSN. */ 5815 5816static int 5817arm_barrier_cost (insn) 5818 rtx insn; 5819{ 5820 /* Basing the location of the pool on the loop depth is preferable, 5821 but at the moment, the basic block information seems to be 5822 corrupt by this stage of the compilation. */ 5823 int base_cost = 50; 5824 rtx next = next_nonnote_insn (insn); 5825 5826 if (next != NULL && GET_CODE (next) == CODE_LABEL) 5827 base_cost -= 20; 5828 5829 switch (GET_CODE (insn)) 5830 { 5831 case CODE_LABEL: 5832 /* It will always be better to place the table before the label, rather 5833 than after it. */ 5834 return 50; 5835 5836 case INSN: 5837 case CALL_INSN: 5838 return base_cost; 5839 5840 case JUMP_INSN: 5841 return base_cost - 10; 5842 5843 default: 5844 return base_cost + 10; 5845 } 5846} 5847 5848/* Find the best place in the insn stream in the range 5849 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. 5850 Create the barrier by inserting a jump and add a new fix entry for 5851 it. */ 5852 5853static Mfix * 5854create_fix_barrier (fix, max_address) 5855 Mfix * fix; 5856 HOST_WIDE_INT max_address; 5857{ 5858 HOST_WIDE_INT count = 0; 5859 rtx barrier; 5860 rtx from = fix->insn; 5861 rtx selected = from; 5862 int selected_cost; 5863 HOST_WIDE_INT selected_address; 5864 Mfix * new_fix; 5865 HOST_WIDE_INT max_count = max_address - fix->address; 5866 rtx label = gen_label_rtx (); 5867 5868 selected_cost = arm_barrier_cost (from); 5869 selected_address = fix->address; 5870 5871 while (from && count < max_count) 5872 { 5873 rtx tmp; 5874 int new_cost; 5875 5876 /* This code shouldn't have been called if there was a natural barrier 5877 within range. */ 5878 if (GET_CODE (from) == BARRIER) 5879 abort (); 5880 5881 /* Count the length of this insn. */ 5882 count += get_attr_length (from); 5883 5884 /* If there is a jump table, add its length. */ 5885 tmp = is_jump_table (from); 5886 if (tmp != NULL) 5887 { 5888 count += get_jump_table_size (tmp); 5889 5890 /* Jump tables aren't in a basic block, so base the cost on 5891 the dispatch insn. If we select this location, we will 5892 still put the pool after the table. */ 5893 new_cost = arm_barrier_cost (from); 5894 5895 if (count < max_count && new_cost <= selected_cost) 5896 { 5897 selected = tmp; 5898 selected_cost = new_cost; 5899 selected_address = fix->address + count; 5900 } 5901 5902 /* Continue after the dispatch table. */ 5903 from = NEXT_INSN (tmp); 5904 continue; 5905 } 5906 5907 new_cost = arm_barrier_cost (from); 5908 5909 if (count < max_count && new_cost <= selected_cost) 5910 { 5911 selected = from; 5912 selected_cost = new_cost; 5913 selected_address = fix->address + count; 5914 } 5915 5916 from = NEXT_INSN (from); 5917 } 5918 5919 /* Create a new JUMP_INSN that branches around a barrier. */ 5920 from = emit_jump_insn_after (gen_jump (label), selected); 5921 JUMP_LABEL (from) = label; 5922 barrier = emit_barrier_after (from); 5923 emit_label_after (label, barrier); 5924 5925 /* Create a minipool barrier entry for the new barrier. */ 5926 new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* new_fix)); 5927 new_fix->insn = barrier; 5928 new_fix->address = selected_address; 5929 new_fix->next = fix->next; 5930 fix->next = new_fix; 5931 5932 return new_fix; 5933} 5934 5935/* Record that there is a natural barrier in the insn stream at 5936 ADDRESS. */ 5937static void 5938push_minipool_barrier (insn, address) 5939 rtx insn; 5940 HOST_WIDE_INT address; 5941{ 5942 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); 5943 5944 fix->insn = insn; 5945 fix->address = address; 5946 5947 fix->next = NULL; 5948 if (minipool_fix_head != NULL) 5949 minipool_fix_tail->next = fix; 5950 else 5951 minipool_fix_head = fix; 5952 5953 minipool_fix_tail = fix; 5954} 5955 5956/* Record INSN, which will need fixing up to load a value from the 5957 minipool. ADDRESS is the offset of the insn since the start of the 5958 function; LOC is a pointer to the part of the insn which requires 5959 fixing; VALUE is the constant that must be loaded, which is of type 5960 MODE. */ 5961static void 5962push_minipool_fix (insn, address, loc, mode, value) 5963 rtx insn; 5964 HOST_WIDE_INT address; 5965 rtx * loc; 5966 enum machine_mode mode; 5967 rtx value; 5968{ 5969 Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); 5970 5971#ifdef AOF_ASSEMBLER 5972 /* PIC symbol refereneces need to be converted into offsets into the 5973 based area. */ 5974 /* XXX This shouldn't be done here. */ 5975 if (flag_pic && GET_CODE (value) == SYMBOL_REF) 5976 value = aof_pic_entry (value); 5977#endif /* AOF_ASSEMBLER */ 5978 5979 fix->insn = insn; 5980 fix->address = address; 5981 fix->loc = loc; 5982 fix->mode = mode; 5983 fix->fix_size = MINIPOOL_FIX_SIZE (mode); 5984 fix->value = value; 5985 fix->forwards = get_attr_pool_range (insn); 5986 fix->backwards = get_attr_neg_pool_range (insn); 5987 fix->minipool = NULL; 5988 5989 /* If an insn doesn't have a range defined for it, then it isn't 5990 expecting to be reworked by this code. Better to abort now than 5991 to generate duff assembly code. */ 5992 if (fix->forwards == 0 && fix->backwards == 0) 5993 abort (); 5994 5995 if (rtl_dump_file) 5996 { 5997 fprintf (rtl_dump_file, 5998 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", 5999 GET_MODE_NAME (mode), 6000 INSN_UID (insn), (unsigned long) address, 6001 -1 * (long)fix->backwards, (long)fix->forwards); 6002 arm_print_value (rtl_dump_file, fix->value); 6003 fprintf (rtl_dump_file, "\n"); 6004 } 6005 6006 /* Add it to the chain of fixes. */ 6007 fix->next = NULL; 6008 6009 if (minipool_fix_head != NULL) 6010 minipool_fix_tail->next = fix; 6011 else 6012 minipool_fix_head = fix; 6013 6014 minipool_fix_tail = fix; 6015} 6016 6017/* Scan INSN and note any of its operands that need fixing. */ 6018 6019static void 6020note_invalid_constants (insn, address) 6021 rtx insn; 6022 HOST_WIDE_INT address; 6023{ 6024 int opno; 6025 6026 extract_insn (insn); 6027 6028 if (!constrain_operands (1)) 6029 fatal_insn_not_found (insn); 6030 6031 /* Fill in recog_op_alt with information about the constraints of this 6032 insn. */ 6033 preprocess_constraints (); 6034 6035 for (opno = 0; opno < recog_data.n_operands; opno++) 6036 { 6037 /* Things we need to fix can only occur in inputs. */ 6038 if (recog_data.operand_type[opno] != OP_IN) 6039 continue; 6040 6041 /* If this alternative is a memory reference, then any mention 6042 of constants in this alternative is really to fool reload 6043 into allowing us to accept one there. We need to fix them up 6044 now so that we output the right code. */ 6045 if (recog_op_alt[opno][which_alternative].memory_ok) 6046 { 6047 rtx op = recog_data.operand[opno]; 6048 6049 if (CONSTANT_P (op)) 6050 push_minipool_fix (insn, address, recog_data.operand_loc[opno], 6051 recog_data.operand_mode[opno], op); 6052#if 0 6053 /* RWE: Now we look correctly at the operands for the insn, 6054 this shouldn't be needed any more. */ 6055#ifndef AOF_ASSEMBLER 6056 /* XXX Is this still needed? */ 6057 else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM) 6058 push_minipool_fix (insn, address, recog_data.operand_loc[opno], 6059 recog_data.operand_mode[opno], 6060 XVECEXP (op, 0, 0)); 6061#endif 6062#endif 6063 else if (GET_CODE (op) == MEM 6064 && GET_CODE (XEXP (op, 0)) == SYMBOL_REF 6065 && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) 6066 push_minipool_fix (insn, address, recog_data.operand_loc[opno], 6067 recog_data.operand_mode[opno], 6068 get_pool_constant (XEXP (op, 0))); 6069 } 6070 } 6071} 6072 6073void 6074arm_reorg (first) 6075 rtx first; 6076{ 6077 rtx insn; 6078 HOST_WIDE_INT address = 0; 6079 Mfix * fix; 6080 6081 minipool_fix_head = minipool_fix_tail = NULL; 6082 6083 /* The first insn must always be a note, or the code below won't 6084 scan it properly. */ 6085 if (GET_CODE (first) != NOTE) 6086 abort (); 6087 6088 /* Scan all the insns and record the operands that will need fixing. */ 6089 for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn)) 6090 { 6091 if (GET_CODE (insn) == BARRIER) 6092 push_minipool_barrier (insn, address); 6093 else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN 6094 || GET_CODE (insn) == JUMP_INSN) 6095 { 6096 rtx table; 6097 6098 note_invalid_constants (insn, address); 6099 address += get_attr_length (insn); 6100 6101 /* If the insn is a vector jump, add the size of the table 6102 and skip the table. */ 6103 if ((table = is_jump_table (insn)) != NULL) 6104 { 6105 address += get_jump_table_size (table); 6106 insn = table; 6107 } 6108 } 6109 } 6110 6111 fix = minipool_fix_head; 6112 6113 /* Now scan the fixups and perform the required changes. */ 6114 while (fix) 6115 { 6116 Mfix * ftmp; 6117 Mfix * fdel; 6118 Mfix * last_added_fix; 6119 Mfix * last_barrier = NULL; 6120 Mfix * this_fix; 6121 6122 /* Skip any further barriers before the next fix. */ 6123 while (fix && GET_CODE (fix->insn) == BARRIER) 6124 fix = fix->next; 6125 6126 /* No more fixes. */ 6127 if (fix == NULL) 6128 break; 6129 6130 last_added_fix = NULL; 6131 6132 for (ftmp = fix; ftmp; ftmp = ftmp->next) 6133 { 6134 if (GET_CODE (ftmp->insn) == BARRIER) 6135 { 6136 if (ftmp->address >= minipool_vector_head->max_address) 6137 break; 6138 6139 last_barrier = ftmp; 6140 } 6141 else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) 6142 break; 6143 6144 last_added_fix = ftmp; /* Keep track of the last fix added. */ 6145 } 6146 6147 /* If we found a barrier, drop back to that; any fixes that we 6148 could have reached but come after the barrier will now go in 6149 the next mini-pool. */ 6150 if (last_barrier != NULL) 6151 { 6152 /* Reduce the refcount for those fixes that won't go into this 6153 pool after all. */ 6154 for (fdel = last_barrier->next; 6155 fdel && fdel != ftmp; 6156 fdel = fdel->next) 6157 { 6158 fdel->minipool->refcount--; 6159 fdel->minipool = NULL; 6160 } 6161 6162 ftmp = last_barrier; 6163 } 6164 else 6165 { 6166 /* ftmp is first fix that we can't fit into this pool and 6167 there no natural barriers that we could use. Insert a 6168 new barrier in the code somewhere between the previous 6169 fix and this one, and arrange to jump around it. */ 6170 HOST_WIDE_INT max_address; 6171 6172 /* The last item on the list of fixes must be a barrier, so 6173 we can never run off the end of the list of fixes without 6174 last_barrier being set. */ 6175 if (ftmp == NULL) 6176 abort (); 6177 6178 max_address = minipool_vector_head->max_address; 6179 /* Check that there isn't another fix that is in range that 6180 we couldn't fit into this pool because the pool was 6181 already too large: we need to put the pool before such an 6182 instruction. */ 6183 if (ftmp->address < max_address) 6184 max_address = ftmp->address; 6185 6186 last_barrier = create_fix_barrier (last_added_fix, max_address); 6187 } 6188 6189 assign_minipool_offsets (last_barrier); 6190 6191 while (ftmp) 6192 { 6193 if (GET_CODE (ftmp->insn) != BARRIER 6194 && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) 6195 == NULL)) 6196 break; 6197 6198 ftmp = ftmp->next; 6199 } 6200 6201 /* Scan over the fixes we have identified for this pool, fixing them 6202 up and adding the constants to the pool itself. */ 6203 for (this_fix = fix; this_fix && ftmp != this_fix; 6204 this_fix = this_fix->next) 6205 if (GET_CODE (this_fix->insn) != BARRIER) 6206 { 6207 rtx addr 6208 = plus_constant (gen_rtx_LABEL_REF (VOIDmode, 6209 minipool_vector_label), 6210 this_fix->minipool->offset); 6211 *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); 6212 } 6213 6214 dump_minipool (last_barrier->insn); 6215 fix = ftmp; 6216 } 6217 6218 /* From now on we must synthesize any constants that we can't handle 6219 directly. This can happen if the RTL gets split during final 6220 instruction generation. */ 6221 after_arm_reorg = 1; 6222 6223 /* Free the minipool memory. */ 6224 obstack_free (&minipool_obstack, minipool_startobj); 6225} 6226 6227/* Routines to output assembly language. */ 6228 6229/* If the rtx is the correct value then return the string of the number. 6230 In this way we can ensure that valid double constants are generated even 6231 when cross compiling. */ 6232 6233const char * 6234fp_immediate_constant (x) 6235 rtx x; 6236{ 6237 REAL_VALUE_TYPE r; 6238 int i; 6239 6240 if (!fpa_consts_inited) 6241 init_fpa_table (); 6242 6243 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 6244 for (i = 0; i < 8; i++) 6245 if (REAL_VALUES_EQUAL (r, values_fpa[i])) 6246 return strings_fpa[i]; 6247 6248 abort (); 6249} 6250 6251/* As for fp_immediate_constant, but value is passed directly, not in rtx. */ 6252 6253static const char * 6254fp_const_from_val (r) 6255 REAL_VALUE_TYPE * r; 6256{ 6257 int i; 6258 6259 if (!fpa_consts_inited) 6260 init_fpa_table (); 6261 6262 for (i = 0; i < 8; i++) 6263 if (REAL_VALUES_EQUAL (*r, values_fpa[i])) 6264 return strings_fpa[i]; 6265 6266 abort (); 6267} 6268 6269/* Output the operands of a LDM/STM instruction to STREAM. 6270 MASK is the ARM register set mask of which only bits 0-15 are important. 6271 REG is the base register, either the frame pointer or the stack pointer, 6272 INSTR is the possibly suffixed load or store instruction. */ 6273 6274static void 6275print_multi_reg (stream, instr, reg, mask) 6276 FILE * stream; 6277 const char * instr; 6278 int reg; 6279 int mask; 6280{ 6281 int i; 6282 int not_first = FALSE; 6283 6284 fputc ('\t', stream); 6285 asm_fprintf (stream, instr, reg); 6286 fputs (", {", stream); 6287 6288 for (i = 0; i <= LAST_ARM_REGNUM; i++) 6289 if (mask & (1 << i)) 6290 { 6291 if (not_first) 6292 fprintf (stream, ", "); 6293 6294 asm_fprintf (stream, "%r", i); 6295 not_first = TRUE; 6296 } 6297 6298 fprintf (stream, "}%s\n", TARGET_APCS_32 ? "" : "^"); 6299} 6300 6301/* Output a 'call' insn. */ 6302 6303const char * 6304output_call (operands) 6305 rtx * operands; 6306{ 6307 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ 6308 6309 if (REGNO (operands[0]) == LR_REGNUM) 6310 { 6311 operands[0] = gen_rtx_REG (SImode, IP_REGNUM); 6312 output_asm_insn ("mov%?\t%0, %|lr", operands); 6313 } 6314 6315 output_asm_insn ("mov%?\t%|lr, %|pc", operands); 6316 6317 if (TARGET_INTERWORK) 6318 output_asm_insn ("bx%?\t%0", operands); 6319 else 6320 output_asm_insn ("mov%?\t%|pc, %0", operands); 6321 6322 return ""; 6323} 6324 6325static int 6326eliminate_lr2ip (x) 6327 rtx * x; 6328{ 6329 int something_changed = 0; 6330 rtx x0 = * x; 6331 int code = GET_CODE (x0); 6332 int i, j; 6333 const char * fmt; 6334 6335 switch (code) 6336 { 6337 case REG: 6338 if (REGNO (x0) == LR_REGNUM) 6339 { 6340 *x = gen_rtx_REG (SImode, IP_REGNUM); 6341 return 1; 6342 } 6343 return 0; 6344 default: 6345 /* Scan through the sub-elements and change any references there. */ 6346 fmt = GET_RTX_FORMAT (code); 6347 6348 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 6349 if (fmt[i] == 'e') 6350 something_changed |= eliminate_lr2ip (&XEXP (x0, i)); 6351 else if (fmt[i] == 'E') 6352 for (j = 0; j < XVECLEN (x0, i); j++) 6353 something_changed |= eliminate_lr2ip (&XVECEXP (x0, i, j)); 6354 6355 return something_changed; 6356 } 6357} 6358 6359/* Output a 'call' insn that is a reference in memory. */ 6360 6361const char * 6362output_call_mem (operands) 6363 rtx * operands; 6364{ 6365 operands[0] = copy_rtx (operands[0]); /* Be ultra careful. */ 6366 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */ 6367 if (eliminate_lr2ip (&operands[0])) 6368 output_asm_insn ("mov%?\t%|ip, %|lr", operands); 6369 6370 if (TARGET_INTERWORK) 6371 { 6372 output_asm_insn ("ldr%?\t%|ip, %0", operands); 6373 output_asm_insn ("mov%?\t%|lr, %|pc", operands); 6374 output_asm_insn ("bx%?\t%|ip", operands); 6375 } 6376 else 6377 { 6378 output_asm_insn ("mov%?\t%|lr, %|pc", operands); 6379 output_asm_insn ("ldr%?\t%|pc, %0", operands); 6380 } 6381 6382 return ""; 6383} 6384 6385 6386/* Output a move from arm registers to an fpu registers. 6387 OPERANDS[0] is an fpu register. 6388 OPERANDS[1] is the first registers of an arm register pair. */ 6389 6390const char * 6391output_mov_long_double_fpu_from_arm (operands) 6392 rtx * operands; 6393{ 6394 int arm_reg0 = REGNO (operands[1]); 6395 rtx ops[3]; 6396 6397 if (arm_reg0 == IP_REGNUM) 6398 abort (); 6399 6400 ops[0] = gen_rtx_REG (SImode, arm_reg0); 6401 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 6402 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); 6403 6404 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops); 6405 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands); 6406 6407 return ""; 6408} 6409 6410/* Output a move from an fpu register to arm registers. 6411 OPERANDS[0] is the first registers of an arm register pair. 6412 OPERANDS[1] is an fpu register. */ 6413 6414const char * 6415output_mov_long_double_arm_from_fpu (operands) 6416 rtx * operands; 6417{ 6418 int arm_reg0 = REGNO (operands[0]); 6419 rtx ops[3]; 6420 6421 if (arm_reg0 == IP_REGNUM) 6422 abort (); 6423 6424 ops[0] = gen_rtx_REG (SImode, arm_reg0); 6425 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 6426 ops[2] = gen_rtx_REG (SImode, 2 + arm_reg0); 6427 6428 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands); 6429 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops); 6430 return ""; 6431} 6432 6433/* Output a move from arm registers to arm registers of a long double 6434 OPERANDS[0] is the destination. 6435 OPERANDS[1] is the source. */ 6436 6437const char * 6438output_mov_long_double_arm_from_arm (operands) 6439 rtx * operands; 6440{ 6441 /* We have to be careful here because the two might overlap. */ 6442 int dest_start = REGNO (operands[0]); 6443 int src_start = REGNO (operands[1]); 6444 rtx ops[2]; 6445 int i; 6446 6447 if (dest_start < src_start) 6448 { 6449 for (i = 0; i < 3; i++) 6450 { 6451 ops[0] = gen_rtx_REG (SImode, dest_start + i); 6452 ops[1] = gen_rtx_REG (SImode, src_start + i); 6453 output_asm_insn ("mov%?\t%0, %1", ops); 6454 } 6455 } 6456 else 6457 { 6458 for (i = 2; i >= 0; i--) 6459 { 6460 ops[0] = gen_rtx_REG (SImode, dest_start + i); 6461 ops[1] = gen_rtx_REG (SImode, src_start + i); 6462 output_asm_insn ("mov%?\t%0, %1", ops); 6463 } 6464 } 6465 6466 return ""; 6467} 6468 6469 6470/* Output a move from arm registers to an fpu registers. 6471 OPERANDS[0] is an fpu register. 6472 OPERANDS[1] is the first registers of an arm register pair. */ 6473 6474const char * 6475output_mov_double_fpu_from_arm (operands) 6476 rtx * operands; 6477{ 6478 int arm_reg0 = REGNO (operands[1]); 6479 rtx ops[2]; 6480 6481 if (arm_reg0 == IP_REGNUM) 6482 abort (); 6483 6484 ops[0] = gen_rtx_REG (SImode, arm_reg0); 6485 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 6486 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops); 6487 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands); 6488 return ""; 6489} 6490 6491/* Output a move from an fpu register to arm registers. 6492 OPERANDS[0] is the first registers of an arm register pair. 6493 OPERANDS[1] is an fpu register. */ 6494 6495const char * 6496output_mov_double_arm_from_fpu (operands) 6497 rtx * operands; 6498{ 6499 int arm_reg0 = REGNO (operands[0]); 6500 rtx ops[2]; 6501 6502 if (arm_reg0 == IP_REGNUM) 6503 abort (); 6504 6505 ops[0] = gen_rtx_REG (SImode, arm_reg0); 6506 ops[1] = gen_rtx_REG (SImode, 1 + arm_reg0); 6507 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands); 6508 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops); 6509 return ""; 6510} 6511 6512/* Output a move between double words. 6513 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM 6514 or MEM<-REG and all MEMs must be offsettable addresses. */ 6515 6516const char * 6517output_move_double (operands) 6518 rtx * operands; 6519{ 6520 enum rtx_code code0 = GET_CODE (operands[0]); 6521 enum rtx_code code1 = GET_CODE (operands[1]); 6522 rtx otherops[3]; 6523 6524 if (code0 == REG) 6525 { 6526 int reg0 = REGNO (operands[0]); 6527 6528 otherops[0] = gen_rtx_REG (SImode, 1 + reg0); 6529 6530 if (code1 == REG) 6531 { 6532 int reg1 = REGNO (operands[1]); 6533 if (reg1 == IP_REGNUM) 6534 abort (); 6535 6536 /* Ensure the second source is not overwritten. */ 6537 if (reg1 == reg0 + (WORDS_BIG_ENDIAN ? -1 : 1)) 6538 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands); 6539 else 6540 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands); 6541 } 6542 else if (code1 == CONST_DOUBLE) 6543 { 6544 if (GET_MODE (operands[1]) == DFmode) 6545 { 6546 long l[2]; 6547 union real_extract u; 6548 6549 memcpy (&u, &CONST_DOUBLE_LOW (operands[1]), sizeof (u)); 6550 REAL_VALUE_TO_TARGET_DOUBLE (u.d, l); 6551 otherops[1] = GEN_INT (l[1]); 6552 operands[1] = GEN_INT (l[0]); 6553 } 6554 else if (GET_MODE (operands[1]) != VOIDmode) 6555 abort (); 6556 else if (WORDS_BIG_ENDIAN) 6557 { 6558 otherops[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); 6559 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); 6560 } 6561 else 6562 { 6563 otherops[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); 6564 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); 6565 } 6566 6567 output_mov_immediate (operands); 6568 output_mov_immediate (otherops); 6569 } 6570 else if (code1 == CONST_INT) 6571 { 6572#if HOST_BITS_PER_WIDE_INT > 32 6573 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us 6574 what the upper word is. */ 6575 if (WORDS_BIG_ENDIAN) 6576 { 6577 otherops[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); 6578 operands[1] = GEN_INT (INTVAL (operands[1]) >> 32); 6579 } 6580 else 6581 { 6582 otherops[1] = GEN_INT (INTVAL (operands[1]) >> 32); 6583 operands[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands[1]))); 6584 } 6585#else 6586 /* Sign extend the intval into the high-order word. */ 6587 if (WORDS_BIG_ENDIAN) 6588 { 6589 otherops[1] = operands[1]; 6590 operands[1] = (INTVAL (operands[1]) < 0 6591 ? constm1_rtx : const0_rtx); 6592 } 6593 else 6594 otherops[1] = INTVAL (operands[1]) < 0 ? constm1_rtx : const0_rtx; 6595#endif 6596 output_mov_immediate (otherops); 6597 output_mov_immediate (operands); 6598 } 6599 else if (code1 == MEM) 6600 { 6601 switch (GET_CODE (XEXP (operands[1], 0))) 6602 { 6603 case REG: 6604 output_asm_insn ("ldm%?ia\t%m1, %M0", operands); 6605 break; 6606 6607 case PRE_INC: 6608 abort (); /* Should never happen now. */ 6609 break; 6610 6611 case PRE_DEC: 6612 output_asm_insn ("ldm%?db\t%m1!, %M0", operands); 6613 break; 6614 6615 case POST_INC: 6616 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands); 6617 break; 6618 6619 case POST_DEC: 6620 abort (); /* Should never happen now. */ 6621 break; 6622 6623 case LABEL_REF: 6624 case CONST: 6625 output_asm_insn ("adr%?\t%0, %1", operands); 6626 output_asm_insn ("ldm%?ia\t%0, %M0", operands); 6627 break; 6628 6629 default: 6630 if (arm_add_operand (XEXP (XEXP (operands[1], 0), 1), 6631 GET_MODE (XEXP (XEXP (operands[1], 0), 1)))) 6632 { 6633 otherops[0] = operands[0]; 6634 otherops[1] = XEXP (XEXP (operands[1], 0), 0); 6635 otherops[2] = XEXP (XEXP (operands[1], 0), 1); 6636 6637 if (GET_CODE (XEXP (operands[1], 0)) == PLUS) 6638 { 6639 if (GET_CODE (otherops[2]) == CONST_INT) 6640 { 6641 switch (INTVAL (otherops[2])) 6642 { 6643 case -8: 6644 output_asm_insn ("ldm%?db\t%1, %M0", otherops); 6645 return ""; 6646 case -4: 6647 output_asm_insn ("ldm%?da\t%1, %M0", otherops); 6648 return ""; 6649 case 4: 6650 output_asm_insn ("ldm%?ib\t%1, %M0", otherops); 6651 return ""; 6652 } 6653 6654 if (!(const_ok_for_arm (INTVAL (otherops[2])))) 6655 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops); 6656 else 6657 output_asm_insn ("add%?\t%0, %1, %2", otherops); 6658 } 6659 else 6660 output_asm_insn ("add%?\t%0, %1, %2", otherops); 6661 } 6662 else 6663 output_asm_insn ("sub%?\t%0, %1, %2", otherops); 6664 6665 return "ldm%?ia\t%0, %M0"; 6666 } 6667 else 6668 { 6669 otherops[1] = adjust_address (operands[1], VOIDmode, 4); 6670 /* Take care of overlapping base/data reg. */ 6671 if (reg_mentioned_p (operands[0], operands[1])) 6672 { 6673 output_asm_insn ("ldr%?\t%0, %1", otherops); 6674 output_asm_insn ("ldr%?\t%0, %1", operands); 6675 } 6676 else 6677 { 6678 output_asm_insn ("ldr%?\t%0, %1", operands); 6679 output_asm_insn ("ldr%?\t%0, %1", otherops); 6680 } 6681 } 6682 } 6683 } 6684 else 6685 abort (); /* Constraints should prevent this. */ 6686 } 6687 else if (code0 == MEM && code1 == REG) 6688 { 6689 if (REGNO (operands[1]) == IP_REGNUM) 6690 abort (); 6691 6692 switch (GET_CODE (XEXP (operands[0], 0))) 6693 { 6694 case REG: 6695 output_asm_insn ("stm%?ia\t%m0, %M1", operands); 6696 break; 6697 6698 case PRE_INC: 6699 abort (); /* Should never happen now. */ 6700 break; 6701 6702 case PRE_DEC: 6703 output_asm_insn ("stm%?db\t%m0!, %M1", operands); 6704 break; 6705 6706 case POST_INC: 6707 output_asm_insn ("stm%?ia\t%m0!, %M1", operands); 6708 break; 6709 6710 case POST_DEC: 6711 abort (); /* Should never happen now. */ 6712 break; 6713 6714 case PLUS: 6715 if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) 6716 { 6717 switch (INTVAL (XEXP (XEXP (operands[0], 0), 1))) 6718 { 6719 case -8: 6720 output_asm_insn ("stm%?db\t%m0, %M1", operands); 6721 return ""; 6722 6723 case -4: 6724 output_asm_insn ("stm%?da\t%m0, %M1", operands); 6725 return ""; 6726 6727 case 4: 6728 output_asm_insn ("stm%?ib\t%m0, %M1", operands); 6729 return ""; 6730 } 6731 } 6732 /* Fall through */ 6733 6734 default: 6735 otherops[0] = adjust_address (operands[0], VOIDmode, 4); 6736 otherops[1] = gen_rtx_REG (SImode, 1 + REGNO (operands[1])); 6737 output_asm_insn ("str%?\t%1, %0", operands); 6738 output_asm_insn ("str%?\t%1, %0", otherops); 6739 } 6740 } 6741 else 6742 /* Constraints should prevent this. */ 6743 abort (); 6744 6745 return ""; 6746} 6747 6748 6749/* Output an arbitrary MOV reg, #n. 6750 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */ 6751 6752const char * 6753output_mov_immediate (operands) 6754 rtx * operands; 6755{ 6756 HOST_WIDE_INT n = INTVAL (operands[1]); 6757 6758 /* Try to use one MOV. */ 6759 if (const_ok_for_arm (n)) 6760 output_asm_insn ("mov%?\t%0, %1", operands); 6761 6762 /* Try to use one MVN. */ 6763 else if (const_ok_for_arm (~n)) 6764 { 6765 operands[1] = GEN_INT (~n); 6766 output_asm_insn ("mvn%?\t%0, %1", operands); 6767 } 6768 else 6769 { 6770 int n_ones = 0; 6771 int i; 6772 6773 /* If all else fails, make it out of ORRs or BICs as appropriate. */ 6774 for (i = 0; i < 32; i ++) 6775 if (n & 1 << i) 6776 n_ones ++; 6777 6778 if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */ 6779 output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n); 6780 else 6781 output_multi_immediate (operands, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n); 6782 } 6783 6784 return ""; 6785} 6786 6787/* Output an ADD r, s, #n where n may be too big for one instruction. 6788 If adding zero to one register, output nothing. */ 6789 6790const char * 6791output_add_immediate (operands) 6792 rtx * operands; 6793{ 6794 HOST_WIDE_INT n = INTVAL (operands[2]); 6795 6796 if (n != 0 || REGNO (operands[0]) != REGNO (operands[1])) 6797 { 6798 if (n < 0) 6799 output_multi_immediate (operands, 6800 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2, 6801 -n); 6802 else 6803 output_multi_immediate (operands, 6804 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2, 6805 n); 6806 } 6807 6808 return ""; 6809} 6810 6811/* Output a multiple immediate operation. 6812 OPERANDS is the vector of operands referred to in the output patterns. 6813 INSTR1 is the output pattern to use for the first constant. 6814 INSTR2 is the output pattern to use for subsequent constants. 6815 IMMED_OP is the index of the constant slot in OPERANDS. 6816 N is the constant value. */ 6817 6818static const char * 6819output_multi_immediate (operands, instr1, instr2, immed_op, n) 6820 rtx * operands; 6821 const char * instr1; 6822 const char * instr2; 6823 int immed_op; 6824 HOST_WIDE_INT n; 6825{ 6826#if HOST_BITS_PER_WIDE_INT > 32 6827 n &= 0xffffffff; 6828#endif 6829 6830 if (n == 0) 6831 { 6832 /* Quick and easy output. */ 6833 operands[immed_op] = const0_rtx; 6834 output_asm_insn (instr1, operands); 6835 } 6836 else 6837 { 6838 int i; 6839 const char * instr = instr1; 6840 6841 /* Note that n is never zero here (which would give no output). */ 6842 for (i = 0; i < 32; i += 2) 6843 { 6844 if (n & (3 << i)) 6845 { 6846 operands[immed_op] = GEN_INT (n & (255 << i)); 6847 output_asm_insn (instr, operands); 6848 instr = instr2; 6849 i += 6; 6850 } 6851 } 6852 } 6853 6854 return ""; 6855} 6856 6857/* Return the appropriate ARM instruction for the operation code. 6858 The returned result should not be overwritten. OP is the rtx of the 6859 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator 6860 was shifted. */ 6861 6862const char * 6863arithmetic_instr (op, shift_first_arg) 6864 rtx op; 6865 int shift_first_arg; 6866{ 6867 switch (GET_CODE (op)) 6868 { 6869 case PLUS: 6870 return "add"; 6871 6872 case MINUS: 6873 return shift_first_arg ? "rsb" : "sub"; 6874 6875 case IOR: 6876 return "orr"; 6877 6878 case XOR: 6879 return "eor"; 6880 6881 case AND: 6882 return "and"; 6883 6884 default: 6885 abort (); 6886 } 6887} 6888 6889/* Ensure valid constant shifts and return the appropriate shift mnemonic 6890 for the operation code. The returned result should not be overwritten. 6891 OP is the rtx code of the shift. 6892 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant 6893 shift. */ 6894 6895static const char * 6896shift_op (op, amountp) 6897 rtx op; 6898 HOST_WIDE_INT *amountp; 6899{ 6900 const char * mnem; 6901 enum rtx_code code = GET_CODE (op); 6902 6903 if (GET_CODE (XEXP (op, 1)) == REG || GET_CODE (XEXP (op, 1)) == SUBREG) 6904 *amountp = -1; 6905 else if (GET_CODE (XEXP (op, 1)) == CONST_INT) 6906 *amountp = INTVAL (XEXP (op, 1)); 6907 else 6908 abort (); 6909 6910 switch (code) 6911 { 6912 case ASHIFT: 6913 mnem = "asl"; 6914 break; 6915 6916 case ASHIFTRT: 6917 mnem = "asr"; 6918 break; 6919 6920 case LSHIFTRT: 6921 mnem = "lsr"; 6922 break; 6923 6924 case ROTATERT: 6925 mnem = "ror"; 6926 break; 6927 6928 case MULT: 6929 /* We never have to worry about the amount being other than a 6930 power of 2, since this case can never be reloaded from a reg. */ 6931 if (*amountp != -1) 6932 *amountp = int_log2 (*amountp); 6933 else 6934 abort (); 6935 return "asl"; 6936 6937 default: 6938 abort (); 6939 } 6940 6941 if (*amountp != -1) 6942 { 6943 /* This is not 100% correct, but follows from the desire to merge 6944 multiplication by a power of 2 with the recognizer for a 6945 shift. >=32 is not a valid shift for "asl", so we must try and 6946 output a shift that produces the correct arithmetical result. 6947 Using lsr #32 is identical except for the fact that the carry bit 6948 is not set correctly if we set the flags; but we never use the 6949 carry bit from such an operation, so we can ignore that. */ 6950 if (code == ROTATERT) 6951 /* Rotate is just modulo 32. */ 6952 *amountp &= 31; 6953 else if (*amountp != (*amountp & 31)) 6954 { 6955 if (code == ASHIFT) 6956 mnem = "lsr"; 6957 *amountp = 32; 6958 } 6959 6960 /* Shifts of 0 are no-ops. */ 6961 if (*amountp == 0) 6962 return NULL; 6963 } 6964 6965 return mnem; 6966} 6967 6968/* Obtain the shift from the POWER of two. */ 6969 6970static HOST_WIDE_INT 6971int_log2 (power) 6972 HOST_WIDE_INT power; 6973{ 6974 HOST_WIDE_INT shift = 0; 6975 6976 while ((((HOST_WIDE_INT) 1 << shift) & power) == 0) 6977 { 6978 if (shift > 31) 6979 abort (); 6980 shift ++; 6981 } 6982 6983 return shift; 6984} 6985 6986/* Output a .ascii pseudo-op, keeping track of lengths. This is because 6987 /bin/as is horribly restrictive. */ 6988#define MAX_ASCII_LEN 51 6989 6990void 6991output_ascii_pseudo_op (stream, p, len) 6992 FILE * stream; 6993 const unsigned char * p; 6994 int len; 6995{ 6996 int i; 6997 int len_so_far = 0; 6998 6999 fputs ("\t.ascii\t\"", stream); 7000 7001 for (i = 0; i < len; i++) 7002 { 7003 int c = p[i]; 7004 7005 if (len_so_far >= MAX_ASCII_LEN) 7006 { 7007 fputs ("\"\n\t.ascii\t\"", stream); 7008 len_so_far = 0; 7009 } 7010 7011 switch (c) 7012 { 7013 case TARGET_TAB: 7014 fputs ("\\t", stream); 7015 len_so_far += 2; 7016 break; 7017 7018 case TARGET_FF: 7019 fputs ("\\f", stream); 7020 len_so_far += 2; 7021 break; 7022 7023 case TARGET_BS: 7024 fputs ("\\b", stream); 7025 len_so_far += 2; 7026 break; 7027 7028 case TARGET_CR: 7029 fputs ("\\r", stream); 7030 len_so_far += 2; 7031 break; 7032 7033 case TARGET_NEWLINE: 7034 fputs ("\\n", stream); 7035 c = p [i + 1]; 7036 if ((c >= ' ' && c <= '~') 7037 || c == TARGET_TAB) 7038 /* This is a good place for a line break. */ 7039 len_so_far = MAX_ASCII_LEN; 7040 else 7041 len_so_far += 2; 7042 break; 7043 7044 case '\"': 7045 case '\\': 7046 putc ('\\', stream); 7047 len_so_far++; 7048 /* drop through. */ 7049 7050 default: 7051 if (c >= ' ' && c <= '~') 7052 { 7053 putc (c, stream); 7054 len_so_far++; 7055 } 7056 else 7057 { 7058 fprintf (stream, "\\%03o", c); 7059 len_so_far += 4; 7060 } 7061 break; 7062 } 7063 } 7064 7065 fputs ("\"\n", stream); 7066} 7067 7068/* Compute the register sabe mask for registers 0 through 12 7069 inclusive. This code is used by both arm_compute_save_reg_mask 7070 and arm_compute_initial_elimination_offset. */ 7071 7072static unsigned long 7073arm_compute_save_reg0_reg12_mask () 7074{ 7075 unsigned long func_type = arm_current_func_type (); 7076 unsigned int save_reg_mask = 0; 7077 unsigned int reg; 7078 7079 if (IS_INTERRUPT (func_type)) 7080 { 7081 unsigned int max_reg; 7082 /* Interrupt functions must not corrupt any registers, 7083 even call clobbered ones. If this is a leaf function 7084 we can just examine the registers used by the RTL, but 7085 otherwise we have to assume that whatever function is 7086 called might clobber anything, and so we have to save 7087 all the call-clobbered registers as well. */ 7088 if (ARM_FUNC_TYPE (func_type) == ARM_FT_FIQ) 7089 /* FIQ handlers have registers r8 - r12 banked, so 7090 we only need to check r0 - r7, Normal ISRs only 7091 bank r14 and r15, so we must check up to r12. 7092 r13 is the stack pointer which is always preserved, 7093 so we do not need to consider it here. */ 7094 max_reg = 7; 7095 else 7096 max_reg = 12; 7097 7098 for (reg = 0; reg <= max_reg; reg++) 7099 if (regs_ever_live[reg] 7100 || (! current_function_is_leaf && call_used_regs [reg])) 7101 save_reg_mask |= (1 << reg); 7102 } 7103 else 7104 { 7105 /* In the normal case we only need to save those registers 7106 which are call saved and which are used by this function. */ 7107 for (reg = 0; reg <= 10; reg++) 7108 if (regs_ever_live[reg] && ! call_used_regs [reg]) 7109 save_reg_mask |= (1 << reg); 7110 7111 /* Handle the frame pointer as a special case. */ 7112 if (! TARGET_APCS_FRAME 7113 && ! frame_pointer_needed 7114 && regs_ever_live[HARD_FRAME_POINTER_REGNUM] 7115 && ! call_used_regs[HARD_FRAME_POINTER_REGNUM]) 7116 save_reg_mask |= 1 << HARD_FRAME_POINTER_REGNUM; 7117 7118 /* If we aren't loading the PIC register, 7119 don't stack it even though it may be live. */ 7120 if (flag_pic 7121 && ! TARGET_SINGLE_PIC_BASE 7122 && regs_ever_live[PIC_OFFSET_TABLE_REGNUM]) 7123 save_reg_mask |= 1 << PIC_OFFSET_TABLE_REGNUM; 7124 } 7125 7126 return save_reg_mask; 7127} 7128 7129/* Compute a bit mask of which registers need to be 7130 saved on the stack for the current function. */ 7131 7132static unsigned long 7133arm_compute_save_reg_mask () 7134{ 7135 unsigned int save_reg_mask = 0; 7136 unsigned long func_type = arm_current_func_type (); 7137 7138 if (IS_NAKED (func_type)) 7139 /* This should never really happen. */ 7140 return 0; 7141 7142 /* If we are creating a stack frame, then we must save the frame pointer, 7143 IP (which will hold the old stack pointer), LR and the PC. */ 7144 if (frame_pointer_needed) 7145 save_reg_mask |= 7146 (1 << ARM_HARD_FRAME_POINTER_REGNUM) 7147 | (1 << IP_REGNUM) 7148 | (1 << LR_REGNUM) 7149 | (1 << PC_REGNUM); 7150 7151 /* Volatile functions do not return, so there 7152 is no need to save any other registers. */ 7153 if (IS_VOLATILE (func_type)) 7154 return save_reg_mask; 7155 7156 save_reg_mask |= arm_compute_save_reg0_reg12_mask (); 7157 7158 /* Decide if we need to save the link register. 7159 Interrupt routines have their own banked link register, 7160 so they never need to save it. 7161 Otherwise if we do not use the link register we do not need to save 7162 it. If we are pushing other registers onto the stack however, we 7163 can save an instruction in the epilogue by pushing the link register 7164 now and then popping it back into the PC. This incurs extra memory 7165 accesses though, so we only do it when optimising for size, and only 7166 if we know that we will not need a fancy return sequence. */ 7167 if (regs_ever_live [LR_REGNUM] 7168 || (save_reg_mask 7169 && optimize_size 7170 && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL)) 7171 save_reg_mask |= 1 << LR_REGNUM; 7172 7173 if (cfun->machine->lr_save_eliminated) 7174 save_reg_mask &= ~ (1 << LR_REGNUM); 7175 7176 return save_reg_mask; 7177} 7178 7179/* Generate a function exit sequence. If REALLY_RETURN is true, then do 7180 everything bar the final return instruction. */ 7181 7182const char * 7183output_return_instruction (operand, really_return, reverse) 7184 rtx operand; 7185 int really_return; 7186 int reverse; 7187{ 7188 char conditional[10]; 7189 char instr[100]; 7190 int reg; 7191 unsigned long live_regs_mask; 7192 unsigned long func_type; 7193 7194 func_type = arm_current_func_type (); 7195 7196 if (IS_NAKED (func_type)) 7197 return ""; 7198 7199 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) 7200 { 7201 /* If this function was declared non-returning, and we have found a tail 7202 call, then we have to trust that the called function won't return. */ 7203 if (really_return) 7204 { 7205 rtx ops[2]; 7206 7207 /* Otherwise, trap an attempted return by aborting. */ 7208 ops[0] = operand; 7209 ops[1] = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" 7210 : "abort"); 7211 assemble_external_libcall (ops[1]); 7212 output_asm_insn (reverse ? "bl%D0\t%a1" : "bl%d0\t%a1", ops); 7213 } 7214 7215 return ""; 7216 } 7217 7218 if (current_function_calls_alloca && !really_return) 7219 abort (); 7220 7221 /* Construct the conditional part of the instruction(s) to be emitted. */ 7222 sprintf (conditional, "%%?%%%c0", reverse ? 'D' : 'd'); 7223 7224 return_used_this_function = 1; 7225 7226 live_regs_mask = arm_compute_save_reg_mask (); 7227 7228 if (live_regs_mask) 7229 { 7230 const char * return_reg; 7231 7232 /* If we do not have any special requirements for function exit 7233 (eg interworking, or ISR) then we can load the return address 7234 directly into the PC. Otherwise we must load it into LR. */ 7235 if (really_return 7236 && ! TARGET_INTERWORK) 7237 return_reg = reg_names[PC_REGNUM]; 7238 else 7239 return_reg = reg_names[LR_REGNUM]; 7240 7241 if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) 7242 /* There are two possible reasons for the IP register being saved. 7243 Either a stack frame was created, in which case IP contains the 7244 old stack pointer, or an ISR routine corrupted it. If this in an 7245 ISR routine then just restore IP, otherwise restore IP into SP. */ 7246 if (! IS_INTERRUPT (func_type)) 7247 { 7248 live_regs_mask &= ~ (1 << IP_REGNUM); 7249 live_regs_mask |= (1 << SP_REGNUM); 7250 } 7251 7252 /* On some ARM architectures it is faster to use LDR rather than 7253 LDM to load a single register. On other architectures, the 7254 cost is the same. In 26 bit mode, or for exception handlers, 7255 we have to use LDM to load the PC so that the CPSR is also 7256 restored. */ 7257 for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) 7258 { 7259 if (live_regs_mask == (unsigned int)(1 << reg)) 7260 break; 7261 } 7262 if (reg <= LAST_ARM_REGNUM 7263 && (reg != LR_REGNUM 7264 || ! really_return 7265 || (TARGET_APCS_32 && ! IS_INTERRUPT (func_type)))) 7266 { 7267 sprintf (instr, "ldr%s\t%%|%s, [%%|sp], #4", conditional, 7268 (reg == LR_REGNUM) ? return_reg : reg_names[reg]); 7269 } 7270 else 7271 { 7272 char *p; 7273 int first = 1; 7274 7275 /* Generate the load multiple instruction to restore the registers. */ 7276 if (frame_pointer_needed) 7277 sprintf (instr, "ldm%sea\t%%|fp, {", conditional); 7278 else 7279 sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); 7280 7281 p = instr + strlen (instr); 7282 7283 for (reg = 0; reg <= SP_REGNUM; reg++) 7284 if (live_regs_mask & (1 << reg)) 7285 { 7286 int l = strlen (reg_names[reg]); 7287 7288 if (first) 7289 first = 0; 7290 else 7291 { 7292 memcpy (p, ", ", 2); 7293 p += 2; 7294 } 7295 7296 memcpy (p, "%|", 2); 7297 memcpy (p + 2, reg_names[reg], l); 7298 p += l + 2; 7299 } 7300 7301 if (live_regs_mask & (1 << LR_REGNUM)) 7302 { 7303 int l = strlen (return_reg); 7304 7305 if (! first) 7306 { 7307 memcpy (p, ", ", 2); 7308 p += 2; 7309 } 7310 7311 memcpy (p, "%|", 2); 7312 memcpy (p + 2, return_reg, l); 7313 strcpy (p + 2 + l, ((TARGET_APCS_32 7314 && !IS_INTERRUPT (func_type)) 7315 || !really_return) 7316 ? "}" : "}^"); 7317 } 7318 else 7319 strcpy (p, "}"); 7320 } 7321 7322 output_asm_insn (instr, & operand); 7323 7324 /* See if we need to generate an extra instruction to 7325 perform the actual function return. */ 7326 if (really_return 7327 && func_type != ARM_FT_INTERWORKED 7328 && (live_regs_mask & (1 << LR_REGNUM)) != 0) 7329 { 7330 /* The return has already been handled 7331 by loading the LR into the PC. */ 7332 really_return = 0; 7333 } 7334 } 7335 7336 if (really_return) 7337 { 7338 switch ((int) ARM_FUNC_TYPE (func_type)) 7339 { 7340 case ARM_FT_ISR: 7341 case ARM_FT_FIQ: 7342 sprintf (instr, "sub%ss\t%%|pc, %%|lr, #4", conditional); 7343 break; 7344 7345 case ARM_FT_INTERWORKED: 7346 sprintf (instr, "bx%s\t%%|lr", conditional); 7347 break; 7348 7349 case ARM_FT_EXCEPTION: 7350 sprintf (instr, "mov%ss\t%%|pc, %%|lr", conditional); 7351 break; 7352 7353 default: 7354 /* ARMv5 implementations always provide BX, so interworking 7355 is the default unless APCS-26 is in use. */ 7356 if ((insn_flags & FL_ARCH5) != 0 && TARGET_APCS_32) 7357 sprintf (instr, "bx%s\t%%|lr", conditional); 7358 else 7359 sprintf (instr, "mov%s%s\t%%|pc, %%|lr", 7360 conditional, TARGET_APCS_32 ? "" : "s"); 7361 break; 7362 } 7363 7364 output_asm_insn (instr, & operand); 7365 } 7366 7367 return ""; 7368} 7369 7370/* Write the function name into the code section, directly preceding 7371 the function prologue. 7372 7373 Code will be output similar to this: 7374 t0 7375 .ascii "arm_poke_function_name", 0 7376 .align 7377 t1 7378 .word 0xff000000 + (t1 - t0) 7379 arm_poke_function_name 7380 mov ip, sp 7381 stmfd sp!, {fp, ip, lr, pc} 7382 sub fp, ip, #4 7383 7384 When performing a stack backtrace, code can inspect the value 7385 of 'pc' stored at 'fp' + 0. If the trace function then looks 7386 at location pc - 12 and the top 8 bits are set, then we know 7387 that there is a function name embedded immediately preceding this 7388 location and has length ((pc[-3]) & 0xff000000). 7389 7390 We assume that pc is declared as a pointer to an unsigned long. 7391 7392 It is of no benefit to output the function name if we are assembling 7393 a leaf function. These function types will not contain a stack 7394 backtrace structure, therefore it is not possible to determine the 7395 function name. */ 7396 7397void 7398arm_poke_function_name (stream, name) 7399 FILE * stream; 7400 const char * name; 7401{ 7402 unsigned long alignlength; 7403 unsigned long length; 7404 rtx x; 7405 7406 length = strlen (name) + 1; 7407 alignlength = ROUND_UP (length); 7408 7409 ASM_OUTPUT_ASCII (stream, name, length); 7410 ASM_OUTPUT_ALIGN (stream, 2); 7411 x = GEN_INT ((unsigned HOST_WIDE_INT) 0xff000000 + alignlength); 7412 assemble_aligned_integer (UNITS_PER_WORD, x); 7413} 7414 7415/* Place some comments into the assembler stream 7416 describing the current function. */ 7417 7418static void 7419arm_output_function_prologue (f, frame_size) 7420 FILE * f; 7421 HOST_WIDE_INT frame_size; 7422{ 7423 unsigned long func_type; 7424 7425 if (!TARGET_ARM) 7426 { 7427 thumb_output_function_prologue (f, frame_size); 7428 return; 7429 } 7430 7431 /* Sanity check. */ 7432 if (arm_ccfsm_state || arm_target_insn) 7433 abort (); 7434 7435 func_type = arm_current_func_type (); 7436 7437 switch ((int) ARM_FUNC_TYPE (func_type)) 7438 { 7439 default: 7440 case ARM_FT_NORMAL: 7441 break; 7442 case ARM_FT_INTERWORKED: 7443 asm_fprintf (f, "\t%@ Function supports interworking.\n"); 7444 break; 7445 case ARM_FT_EXCEPTION_HANDLER: 7446 asm_fprintf (f, "\t%@ C++ Exception Handler.\n"); 7447 break; 7448 case ARM_FT_ISR: 7449 asm_fprintf (f, "\t%@ Interrupt Service Routine.\n"); 7450 break; 7451 case ARM_FT_FIQ: 7452 asm_fprintf (f, "\t%@ Fast Interrupt Service Routine.\n"); 7453 break; 7454 case ARM_FT_EXCEPTION: 7455 asm_fprintf (f, "\t%@ ARM Exception Handler.\n"); 7456 break; 7457 } 7458 7459 if (IS_NAKED (func_type)) 7460 asm_fprintf (f, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n"); 7461 7462 if (IS_VOLATILE (func_type)) 7463 asm_fprintf (f, "\t%@ Volatile: function does not return.\n"); 7464 7465 if (IS_NESTED (func_type)) 7466 asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); 7467 7468 asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n", 7469 current_function_args_size, 7470 current_function_pretend_args_size, frame_size); 7471 7472 asm_fprintf (f, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n", 7473 frame_pointer_needed, 7474 cfun->machine->uses_anonymous_args); 7475 7476 if (cfun->machine->lr_save_eliminated) 7477 asm_fprintf (f, "\t%@ link register save eliminated.\n"); 7478 7479#ifdef AOF_ASSEMBLER 7480 if (flag_pic) 7481 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, PIC_OFFSET_TABLE_REGNUM); 7482#endif 7483 7484 return_used_this_function = 0; 7485} 7486 7487const char * 7488arm_output_epilogue (really_return) 7489 int really_return; 7490{ 7491 int reg; 7492 unsigned long saved_regs_mask; 7493 unsigned long func_type; 7494 /* Floats_offset is the offset from the "virtual" frame. In an APCS 7495 frame that is $fp + 4 for a non-variadic function. */ 7496 int floats_offset = 0; 7497 rtx operands[3]; 7498 int frame_size = get_frame_size (); 7499 FILE * f = asm_out_file; 7500 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; 7501 7502 /* If we have already generated the return instruction 7503 then it is futile to generate anything else. */ 7504 if (use_return_insn (FALSE) && return_used_this_function) 7505 return ""; 7506 7507 func_type = arm_current_func_type (); 7508 7509 if (IS_NAKED (func_type)) 7510 /* Naked functions don't have epilogues. */ 7511 return ""; 7512 7513 if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) 7514 { 7515 rtx op; 7516 7517 /* A volatile function should never return. Call abort. */ 7518 op = gen_rtx_SYMBOL_REF (Pmode, NEED_PLT_RELOC ? "abort(PLT)" : "abort"); 7519 assemble_external_libcall (op); 7520 output_asm_insn ("bl\t%a0", &op); 7521 7522 return ""; 7523 } 7524 7525 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER 7526 && ! really_return) 7527 /* If we are throwing an exception, then we really must 7528 be doing a return, so we can't tail-call. */ 7529 abort (); 7530 7531 saved_regs_mask = arm_compute_save_reg_mask (); 7532 7533 /* XXX We should adjust floats_offset for any anonymous args, and then 7534 re-adjust vfp_offset below to compensate. */ 7535 7536 /* Compute how far away the floats will be. */ 7537 for (reg = 0; reg <= LAST_ARM_REGNUM; reg ++) 7538 if (saved_regs_mask & (1 << reg)) 7539 floats_offset += 4; 7540 7541 if (frame_pointer_needed) 7542 { 7543 int vfp_offset = 4; 7544 7545 if (arm_fpu_arch == FP_SOFT2) 7546 { 7547 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) 7548 if (regs_ever_live[reg] && !call_used_regs[reg]) 7549 { 7550 floats_offset += 12; 7551 asm_fprintf (f, "\tldfe\t%r, [%r, #-%d]\n", 7552 reg, FP_REGNUM, floats_offset - vfp_offset); 7553 } 7554 } 7555 else 7556 { 7557 int start_reg = LAST_ARM_FP_REGNUM; 7558 7559 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) 7560 { 7561 if (regs_ever_live[reg] && !call_used_regs[reg]) 7562 { 7563 floats_offset += 12; 7564 7565 /* We can't unstack more than four registers at once. */ 7566 if (start_reg - reg == 3) 7567 { 7568 asm_fprintf (f, "\tlfm\t%r, 4, [%r, #-%d]\n", 7569 reg, FP_REGNUM, floats_offset - vfp_offset); 7570 start_reg = reg - 1; 7571 } 7572 } 7573 else 7574 { 7575 if (reg != start_reg) 7576 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", 7577 reg + 1, start_reg - reg, 7578 FP_REGNUM, floats_offset - vfp_offset); 7579 start_reg = reg - 1; 7580 } 7581 } 7582 7583 /* Just in case the last register checked also needs unstacking. */ 7584 if (reg != start_reg) 7585 asm_fprintf (f, "\tlfm\t%r, %d, [%r, #-%d]\n", 7586 reg + 1, start_reg - reg, 7587 FP_REGNUM, floats_offset - vfp_offset); 7588 } 7589 7590 /* saved_regs_mask should contain the IP, which at the time of stack 7591 frame generation actually contains the old stack pointer. So a 7592 quick way to unwind the stack is just pop the IP register directly 7593 into the stack pointer. */ 7594 if ((saved_regs_mask & (1 << IP_REGNUM)) == 0) 7595 abort (); 7596 saved_regs_mask &= ~ (1 << IP_REGNUM); 7597 saved_regs_mask |= (1 << SP_REGNUM); 7598 7599 /* There are two registers left in saved_regs_mask - LR and PC. We 7600 only need to restore the LR register (the return address), but to 7601 save time we can load it directly into the PC, unless we need a 7602 special function exit sequence, or we are not really returning. */ 7603 if (really_return && ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL) 7604 /* Delete the LR from the register mask, so that the LR on 7605 the stack is loaded into the PC in the register mask. */ 7606 saved_regs_mask &= ~ (1 << LR_REGNUM); 7607 else 7608 saved_regs_mask &= ~ (1 << PC_REGNUM); 7609 7610 print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask); 7611 7612 if (IS_INTERRUPT (func_type)) 7613 /* Interrupt handlers will have pushed the 7614 IP onto the stack, so restore it now. */ 7615 print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, 1 << IP_REGNUM); 7616 } 7617 else 7618 { 7619 /* Restore stack pointer if necessary. */ 7620 if (frame_size + current_function_outgoing_args_size != 0) 7621 { 7622 operands[0] = operands[1] = stack_pointer_rtx; 7623 operands[2] = GEN_INT (frame_size 7624 + current_function_outgoing_args_size); 7625 output_add_immediate (operands); 7626 } 7627 7628 if (arm_fpu_arch == FP_SOFT2) 7629 { 7630 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) 7631 if (regs_ever_live[reg] && !call_used_regs[reg]) 7632 asm_fprintf (f, "\tldfe\t%r, [%r], #12\n", 7633 reg, SP_REGNUM); 7634 } 7635 else 7636 { 7637 int start_reg = FIRST_ARM_FP_REGNUM; 7638 7639 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) 7640 { 7641 if (regs_ever_live[reg] && !call_used_regs[reg]) 7642 { 7643 if (reg - start_reg == 3) 7644 { 7645 asm_fprintf (f, "\tlfmfd\t%r, 4, [%r]!\n", 7646 start_reg, SP_REGNUM); 7647 start_reg = reg + 1; 7648 } 7649 } 7650 else 7651 { 7652 if (reg != start_reg) 7653 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", 7654 start_reg, reg - start_reg, 7655 SP_REGNUM); 7656 7657 start_reg = reg + 1; 7658 } 7659 } 7660 7661 /* Just in case the last register checked also needs unstacking. */ 7662 if (reg != start_reg) 7663 asm_fprintf (f, "\tlfmfd\t%r, %d, [%r]!\n", 7664 start_reg, reg - start_reg, SP_REGNUM); 7665 } 7666 7667 /* If we can, restore the LR into the PC. */ 7668 if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL 7669 && really_return 7670 && current_function_pretend_args_size == 0 7671 && saved_regs_mask & (1 << LR_REGNUM)) 7672 { 7673 saved_regs_mask &= ~ (1 << LR_REGNUM); 7674 saved_regs_mask |= (1 << PC_REGNUM); 7675 } 7676 7677 /* Load the registers off the stack. If we only have one register 7678 to load use the LDR instruction - it is faster. */ 7679 if (saved_regs_mask == (1 << LR_REGNUM)) 7680 { 7681 /* The exception handler ignores the LR, so we do 7682 not really need to load it off the stack. */ 7683 if (eh_ofs) 7684 asm_fprintf (f, "\tadd\t%r, %r, #4\n", SP_REGNUM, SP_REGNUM); 7685 else 7686 asm_fprintf (f, "\tldr\t%r, [%r], #4\n", LR_REGNUM, SP_REGNUM); 7687 } 7688 else if (saved_regs_mask) 7689 print_multi_reg (f, "ldmfd\t%r!", SP_REGNUM, saved_regs_mask); 7690 7691 if (current_function_pretend_args_size) 7692 { 7693 /* Unwind the pre-pushed regs. */ 7694 operands[0] = operands[1] = stack_pointer_rtx; 7695 operands[2] = GEN_INT (current_function_pretend_args_size); 7696 output_add_immediate (operands); 7697 } 7698 } 7699 7700#if 0 7701 if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER) 7702 /* Adjust the stack to remove the exception handler stuff. */ 7703 asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, 7704 REGNO (eh_ofs)); 7705#endif 7706 7707 if (! really_return 7708 || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL 7709 && current_function_pretend_args_size == 0 7710 && saved_regs_mask & (1 << PC_REGNUM))) 7711 return ""; 7712 7713 /* Generate the return instruction. */ 7714 switch ((int) ARM_FUNC_TYPE (func_type)) 7715 { 7716 case ARM_FT_EXCEPTION_HANDLER: 7717 /* Even in 26-bit mode we do a mov (rather than a movs) 7718 because we don't have the PSR bits set in the address. */ 7719 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, EXCEPTION_LR_REGNUM); 7720 break; 7721 7722 case ARM_FT_ISR: 7723 case ARM_FT_FIQ: 7724 asm_fprintf (f, "\tsubs\t%r, %r, #4\n", PC_REGNUM, LR_REGNUM); 7725 break; 7726 7727 case ARM_FT_EXCEPTION: 7728 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); 7729 break; 7730 7731 case ARM_FT_INTERWORKED: 7732 asm_fprintf (f, "\tbx\t%r\n", LR_REGNUM); 7733 break; 7734 7735 default: 7736 if (frame_pointer_needed) 7737 /* If we used the frame pointer then the return adddress 7738 will have been loaded off the stack directly into the 7739 PC, so there is no need to issue a MOV instruction 7740 here. */ 7741 ; 7742 else if (current_function_pretend_args_size == 0 7743 && (saved_regs_mask & (1 << LR_REGNUM))) 7744 /* Similarly we may have been able to load LR into the PC 7745 even if we did not create a stack frame. */ 7746 ; 7747 else if (TARGET_APCS_32) 7748 asm_fprintf (f, "\tmov\t%r, %r\n", PC_REGNUM, LR_REGNUM); 7749 else 7750 asm_fprintf (f, "\tmovs\t%r, %r\n", PC_REGNUM, LR_REGNUM); 7751 break; 7752 } 7753 7754 return ""; 7755} 7756 7757static void 7758arm_output_function_epilogue (file, frame_size) 7759 FILE *file ATTRIBUTE_UNUSED; 7760 HOST_WIDE_INT frame_size; 7761{ 7762 if (TARGET_THUMB) 7763 { 7764 /* ??? Probably not safe to set this here, since it assumes that a 7765 function will be emitted as assembly immediately after we generate 7766 RTL for it. This does not happen for inline functions. */ 7767 return_used_this_function = 0; 7768 } 7769 else 7770 { 7771 if (use_return_insn (FALSE) 7772 && return_used_this_function 7773 && (frame_size + current_function_outgoing_args_size) != 0 7774 && !frame_pointer_needed) 7775 abort (); 7776 7777 /* Reset the ARM-specific per-function variables. */ 7778 after_arm_reorg = 0; 7779 } 7780} 7781 7782/* Generate and emit an insn that we will recognize as a push_multi. 7783 Unfortunately, since this insn does not reflect very well the actual 7784 semantics of the operation, we need to annotate the insn for the benefit 7785 of DWARF2 frame unwind information. */ 7786 7787static rtx 7788emit_multi_reg_push (mask) 7789 int mask; 7790{ 7791 int num_regs = 0; 7792 int num_dwarf_regs; 7793 int i, j; 7794 rtx par; 7795 rtx dwarf; 7796 int dwarf_par_index; 7797 rtx tmp, reg; 7798 7799 for (i = 0; i <= LAST_ARM_REGNUM; i++) 7800 if (mask & (1 << i)) 7801 num_regs++; 7802 7803 if (num_regs == 0 || num_regs > 16) 7804 abort (); 7805 7806 /* We don't record the PC in the dwarf frame information. */ 7807 num_dwarf_regs = num_regs; 7808 if (mask & (1 << PC_REGNUM)) 7809 num_dwarf_regs--; 7810 7811 /* For the body of the insn we are going to generate an UNSPEC in 7812 parallel with several USEs. This allows the insn to be recognised 7813 by the push_multi pattern in the arm.md file. The insn looks 7814 something like this: 7815 7816 (parallel [ 7817 (set (mem:BLK (pre_dec:BLK (reg:SI sp))) 7818 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT)) 7819 (use (reg:SI 11 fp)) 7820 (use (reg:SI 12 ip)) 7821 (use (reg:SI 14 lr)) 7822 (use (reg:SI 15 pc)) 7823 ]) 7824 7825 For the frame note however, we try to be more explicit and actually 7826 show each register being stored into the stack frame, plus a (single) 7827 decrement of the stack pointer. We do it this way in order to be 7828 friendly to the stack unwinding code, which only wants to see a single 7829 stack decrement per instruction. The RTL we generate for the note looks 7830 something like this: 7831 7832 (sequence [ 7833 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20))) 7834 (set (mem:SI (reg:SI sp)) (reg:SI r4)) 7835 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp)) 7836 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip)) 7837 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr)) 7838 ]) 7839 7840 This sequence is used both by the code to support stack unwinding for 7841 exceptions handlers and the code to generate dwarf2 frame debugging. */ 7842 7843 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_regs)); 7844 dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (num_dwarf_regs + 1)); 7845 RTX_FRAME_RELATED_P (dwarf) = 1; 7846 dwarf_par_index = 1; 7847 7848 for (i = 0; i <= LAST_ARM_REGNUM; i++) 7849 { 7850 if (mask & (1 << i)) 7851 { 7852 reg = gen_rtx_REG (SImode, i); 7853 7854 XVECEXP (par, 0, 0) 7855 = gen_rtx_SET (VOIDmode, 7856 gen_rtx_MEM (BLKmode, 7857 gen_rtx_PRE_DEC (BLKmode, 7858 stack_pointer_rtx)), 7859 gen_rtx_UNSPEC (BLKmode, 7860 gen_rtvec (1, reg), 7861 UNSPEC_PUSH_MULT)); 7862 7863 if (i != PC_REGNUM) 7864 { 7865 tmp = gen_rtx_SET (VOIDmode, 7866 gen_rtx_MEM (SImode, stack_pointer_rtx), 7867 reg); 7868 RTX_FRAME_RELATED_P (tmp) = 1; 7869 XVECEXP (dwarf, 0, dwarf_par_index) = tmp; 7870 dwarf_par_index++; 7871 } 7872 7873 break; 7874 } 7875 } 7876 7877 for (j = 1, i++; j < num_regs; i++) 7878 { 7879 if (mask & (1 << i)) 7880 { 7881 reg = gen_rtx_REG (SImode, i); 7882 7883 XVECEXP (par, 0, j) = gen_rtx_USE (VOIDmode, reg); 7884 7885 if (i != PC_REGNUM) 7886 { 7887 tmp = gen_rtx_SET (VOIDmode, 7888 gen_rtx_MEM (SImode, 7889 plus_constant (stack_pointer_rtx, 7890 4 * j)), 7891 reg); 7892 RTX_FRAME_RELATED_P (tmp) = 1; 7893 XVECEXP (dwarf, 0, dwarf_par_index++) = tmp; 7894 } 7895 7896 j++; 7897 } 7898 } 7899 7900 par = emit_insn (par); 7901 7902 tmp = gen_rtx_SET (SImode, 7903 stack_pointer_rtx, 7904 gen_rtx_PLUS (SImode, 7905 stack_pointer_rtx, 7906 GEN_INT (-4 * num_regs))); 7907 RTX_FRAME_RELATED_P (tmp) = 1; 7908 XVECEXP (dwarf, 0, 0) = tmp; 7909 7910 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, 7911 REG_NOTES (par)); 7912 return par; 7913} 7914 7915static rtx 7916emit_sfm (base_reg, count) 7917 int base_reg; 7918 int count; 7919{ 7920 rtx par; 7921 rtx dwarf; 7922 rtx tmp, reg; 7923 int i; 7924 7925 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 7926 dwarf = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 7927 RTX_FRAME_RELATED_P (dwarf) = 1; 7928 7929 reg = gen_rtx_REG (XFmode, base_reg++); 7930 7931 XVECEXP (par, 0, 0) 7932 = gen_rtx_SET (VOIDmode, 7933 gen_rtx_MEM (BLKmode, 7934 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), 7935 gen_rtx_UNSPEC (BLKmode, 7936 gen_rtvec (1, reg), 7937 UNSPEC_PUSH_MULT)); 7938 tmp 7939 = gen_rtx_SET (VOIDmode, 7940 gen_rtx_MEM (XFmode, 7941 gen_rtx_PRE_DEC (BLKmode, stack_pointer_rtx)), 7942 reg); 7943 RTX_FRAME_RELATED_P (tmp) = 1; 7944 XVECEXP (dwarf, 0, count - 1) = tmp; 7945 7946 for (i = 1; i < count; i++) 7947 { 7948 reg = gen_rtx_REG (XFmode, base_reg++); 7949 XVECEXP (par, 0, i) = gen_rtx_USE (VOIDmode, reg); 7950 7951 tmp = gen_rtx_SET (VOIDmode, 7952 gen_rtx_MEM (XFmode, 7953 gen_rtx_PRE_DEC (BLKmode, 7954 stack_pointer_rtx)), 7955 reg); 7956 RTX_FRAME_RELATED_P (tmp) = 1; 7957 XVECEXP (dwarf, 0, count - i - 1) = tmp; 7958 } 7959 7960 par = emit_insn (par); 7961 REG_NOTES (par) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, 7962 REG_NOTES (par)); 7963 return par; 7964} 7965 7966/* Compute the distance from register FROM to register TO. 7967 These can be the arg pointer (26), the soft frame pointer (25), 7968 the stack pointer (13) or the hard frame pointer (11). 7969 Typical stack layout looks like this: 7970 7971 old stack pointer -> | | 7972 ---- 7973 | | \ 7974 | | saved arguments for 7975 | | vararg functions 7976 | | / 7977 -- 7978 hard FP & arg pointer -> | | \ 7979 | | stack 7980 | | frame 7981 | | / 7982 -- 7983 | | \ 7984 | | call saved 7985 | | registers 7986 soft frame pointer -> | | / 7987 -- 7988 | | \ 7989 | | local 7990 | | variables 7991 | | / 7992 -- 7993 | | \ 7994 | | outgoing 7995 | | arguments 7996 current stack pointer -> | | / 7997 -- 7998 7999 For a given funciton some or all of these stack compomnents 8000 may not be needed, giving rise to the possibility of 8001 eliminating some of the registers. 8002 8003 The values returned by this function must reflect the behaviour 8004 of arm_expand_prologue() and arm_compute_save_reg_mask(). 8005 8006 The sign of the number returned reflects the direction of stack 8007 growth, so the values are positive for all eliminations except 8008 from the soft frame pointer to the hard frame pointer. */ 8009 8010unsigned int 8011arm_compute_initial_elimination_offset (from, to) 8012 unsigned int from; 8013 unsigned int to; 8014{ 8015 unsigned int local_vars = (get_frame_size () + 3) & ~3; 8016 unsigned int outgoing_args = current_function_outgoing_args_size; 8017 unsigned int stack_frame; 8018 unsigned int call_saved_registers; 8019 unsigned long func_type; 8020 8021 func_type = arm_current_func_type (); 8022 8023 /* Volatile functions never return, so there is 8024 no need to save call saved registers. */ 8025 call_saved_registers = 0; 8026 if (! IS_VOLATILE (func_type)) 8027 { 8028 unsigned int reg_mask; 8029 unsigned int reg; 8030 8031 /* Make sure that we compute which registers will be saved 8032 on the stack using the same algorithm that is used by 8033 arm_compute_save_reg_mask(). */ 8034 reg_mask = arm_compute_save_reg0_reg12_mask (); 8035 8036 /* Now count the number of bits set in save_reg_mask. 8037 For each set bit we need 4 bytes of stack space. */ 8038 while (reg_mask) 8039 { 8040 call_saved_registers += 4; 8041 reg_mask = reg_mask & ~ (reg_mask & - reg_mask); 8042 } 8043 8044 if (regs_ever_live[LR_REGNUM] 8045 /* If a stack frame is going to be created, the LR will 8046 be saved as part of that, so we do not need to allow 8047 for it here. */ 8048 && ! frame_pointer_needed) 8049 call_saved_registers += 4; 8050 8051 /* If the hard floating point registers are going to be 8052 used then they must be saved on the stack as well. 8053 Each register occupies 12 bytes of stack space. */ 8054 for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg ++) 8055 if (regs_ever_live[reg] && ! call_used_regs[reg]) 8056 call_saved_registers += 12; 8057 } 8058 8059 /* The stack frame contains 4 registers - the old frame pointer, 8060 the old stack pointer, the return address and PC of the start 8061 of the function. */ 8062 stack_frame = frame_pointer_needed ? 16 : 0; 8063 8064 /* OK, now we have enough information to compute the distances. 8065 There must be an entry in these switch tables for each pair 8066 of registers in ELIMINABLE_REGS, even if some of the entries 8067 seem to be redundant or useless. */ 8068 switch (from) 8069 { 8070 case ARG_POINTER_REGNUM: 8071 switch (to) 8072 { 8073 case THUMB_HARD_FRAME_POINTER_REGNUM: 8074 return 0; 8075 8076 case FRAME_POINTER_REGNUM: 8077 /* This is the reverse of the soft frame pointer 8078 to hard frame pointer elimination below. */ 8079 if (call_saved_registers == 0 && stack_frame == 0) 8080 return 0; 8081 return (call_saved_registers + stack_frame - 4); 8082 8083 case ARM_HARD_FRAME_POINTER_REGNUM: 8084 /* If there is no stack frame then the hard 8085 frame pointer and the arg pointer coincide. */ 8086 if (stack_frame == 0 && call_saved_registers != 0) 8087 return 0; 8088 /* FIXME: Not sure about this. Maybe we should always return 0 ? */ 8089 return (frame_pointer_needed 8090 && current_function_needs_context 8091 && ! cfun->machine->uses_anonymous_args) ? 4 : 0; 8092 8093 case STACK_POINTER_REGNUM: 8094 /* If nothing has been pushed on the stack at all 8095 then this will return -4. This *is* correct! */ 8096 return call_saved_registers + stack_frame + local_vars + outgoing_args - 4; 8097 8098 default: 8099 abort (); 8100 } 8101 break; 8102 8103 case FRAME_POINTER_REGNUM: 8104 switch (to) 8105 { 8106 case THUMB_HARD_FRAME_POINTER_REGNUM: 8107 return 0; 8108 8109 case ARM_HARD_FRAME_POINTER_REGNUM: 8110 /* The hard frame pointer points to the top entry in the 8111 stack frame. The soft frame pointer to the bottom entry 8112 in the stack frame. If there is no stack frame at all, 8113 then they are identical. */ 8114 if (call_saved_registers == 0 && stack_frame == 0) 8115 return 0; 8116 return - (call_saved_registers + stack_frame - 4); 8117 8118 case STACK_POINTER_REGNUM: 8119 return local_vars + outgoing_args; 8120 8121 default: 8122 abort (); 8123 } 8124 break; 8125 8126 default: 8127 /* You cannot eliminate from the stack pointer. 8128 In theory you could eliminate from the hard frame 8129 pointer to the stack pointer, but this will never 8130 happen, since if a stack frame is not needed the 8131 hard frame pointer will never be used. */ 8132 abort (); 8133 } 8134} 8135 8136/* Generate the prologue instructions for entry into an ARM function. */ 8137 8138void 8139arm_expand_prologue () 8140{ 8141 int reg; 8142 rtx amount; 8143 rtx insn; 8144 rtx ip_rtx; 8145 unsigned long live_regs_mask; 8146 unsigned long func_type; 8147 int fp_offset = 0; 8148 int saved_pretend_args = 0; 8149 unsigned int args_to_push; 8150 8151 func_type = arm_current_func_type (); 8152 8153 /* Naked functions don't have prologues. */ 8154 if (IS_NAKED (func_type)) 8155 return; 8156 8157 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */ 8158 args_to_push = current_function_pretend_args_size; 8159 8160 /* Compute which register we will have to save onto the stack. */ 8161 live_regs_mask = arm_compute_save_reg_mask (); 8162 8163 ip_rtx = gen_rtx_REG (SImode, IP_REGNUM); 8164 8165 if (frame_pointer_needed) 8166 { 8167 if (IS_INTERRUPT (func_type)) 8168 { 8169 /* Interrupt functions must not corrupt any registers. 8170 Creating a frame pointer however, corrupts the IP 8171 register, so we must push it first. */ 8172 insn = emit_multi_reg_push (1 << IP_REGNUM); 8173 8174 /* Do not set RTX_FRAME_RELATED_P on this insn. 8175 The dwarf stack unwinding code only wants to see one 8176 stack decrement per function, and this is not it. If 8177 this instruction is labeled as being part of the frame 8178 creation sequence then dwarf2out_frame_debug_expr will 8179 abort when it encounters the assignment of IP to FP 8180 later on, since the use of SP here establishes SP as 8181 the CFA register and not IP. 8182 8183 Anyway this instruction is not really part of the stack 8184 frame creation although it is part of the prologue. */ 8185 } 8186 else if (IS_NESTED (func_type)) 8187 { 8188 /* The Static chain register is the same as the IP register 8189 used as a scratch register during stack frame creation. 8190 To get around this need to find somewhere to store IP 8191 whilst the frame is being created. We try the following 8192 places in order: 8193 8194 1. The last argument register. 8195 2. A slot on the stack above the frame. (This only 8196 works if the function is not a varargs function). 8197 3. Register r3, after pushing the argument registers 8198 onto the stack. 8199 8200 Note - we only need to tell the dwarf2 backend about the SP 8201 adjustment in the second variant; the static chain register 8202 doesn't need to be unwound, as it doesn't contain a value 8203 inherited from the caller. */ 8204 8205 if (regs_ever_live[3] == 0) 8206 { 8207 insn = gen_rtx_REG (SImode, 3); 8208 insn = gen_rtx_SET (SImode, insn, ip_rtx); 8209 insn = emit_insn (insn); 8210 } 8211 else if (args_to_push == 0) 8212 { 8213 rtx dwarf; 8214 insn = gen_rtx_PRE_DEC (SImode, stack_pointer_rtx); 8215 insn = gen_rtx_MEM (SImode, insn); 8216 insn = gen_rtx_SET (VOIDmode, insn, ip_rtx); 8217 insn = emit_insn (insn); 8218 8219 fp_offset = 4; 8220 8221 /* Just tell the dwarf backend that we adjusted SP. */ 8222 dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, 8223 gen_rtx_PLUS (SImode, stack_pointer_rtx, 8224 GEN_INT (-fp_offset))); 8225 RTX_FRAME_RELATED_P (insn) = 1; 8226 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, 8227 dwarf, REG_NOTES (insn)); 8228 } 8229 else 8230 { 8231 /* Store the args on the stack. */ 8232 if (cfun->machine->uses_anonymous_args) 8233 insn = emit_multi_reg_push 8234 ((0xf0 >> (args_to_push / 4)) & 0xf); 8235 else 8236 insn = emit_insn 8237 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 8238 GEN_INT (- args_to_push))); 8239 8240 RTX_FRAME_RELATED_P (insn) = 1; 8241 8242 saved_pretend_args = 1; 8243 fp_offset = args_to_push; 8244 args_to_push = 0; 8245 8246 /* Now reuse r3 to preserve IP. */ 8247 insn = gen_rtx_REG (SImode, 3); 8248 insn = gen_rtx_SET (SImode, insn, ip_rtx); 8249 (void) emit_insn (insn); 8250 } 8251 } 8252 8253 if (fp_offset) 8254 { 8255 insn = gen_rtx_PLUS (SImode, stack_pointer_rtx, GEN_INT (fp_offset)); 8256 insn = gen_rtx_SET (SImode, ip_rtx, insn); 8257 } 8258 else 8259 insn = gen_movsi (ip_rtx, stack_pointer_rtx); 8260 8261 insn = emit_insn (insn); 8262 RTX_FRAME_RELATED_P (insn) = 1; 8263 } 8264 8265 if (args_to_push) 8266 { 8267 /* Push the argument registers, or reserve space for them. */ 8268 if (cfun->machine->uses_anonymous_args) 8269 insn = emit_multi_reg_push 8270 ((0xf0 >> (args_to_push / 4)) & 0xf); 8271 else 8272 insn = emit_insn 8273 (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 8274 GEN_INT (- args_to_push))); 8275 RTX_FRAME_RELATED_P (insn) = 1; 8276 } 8277 8278 /* If this is an interrupt service routine, and the link register is 8279 going to be pushed, subtracting four now will mean that the 8280 function return can be done with a single instruction. */ 8281 if ((func_type == ARM_FT_ISR || func_type == ARM_FT_FIQ) 8282 && (live_regs_mask & (1 << LR_REGNUM)) != 0) 8283 { 8284 emit_insn (gen_rtx_SET (SImode, 8285 gen_rtx_REG (SImode, LR_REGNUM), 8286 gen_rtx_PLUS (SImode, 8287 gen_rtx_REG (SImode, LR_REGNUM), 8288 GEN_INT (-4)))); 8289 } 8290 8291 if (live_regs_mask) 8292 { 8293 insn = emit_multi_reg_push (live_regs_mask); 8294 RTX_FRAME_RELATED_P (insn) = 1; 8295 } 8296 8297 if (! IS_VOLATILE (func_type)) 8298 { 8299 /* Save any floating point call-saved registers used by this function. */ 8300 if (arm_fpu_arch == FP_SOFT2) 8301 { 8302 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --) 8303 if (regs_ever_live[reg] && !call_used_regs[reg]) 8304 { 8305 insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); 8306 insn = gen_rtx_MEM (XFmode, insn); 8307 insn = emit_insn (gen_rtx_SET (VOIDmode, insn, 8308 gen_rtx_REG (XFmode, reg))); 8309 RTX_FRAME_RELATED_P (insn) = 1; 8310 } 8311 } 8312 else 8313 { 8314 int start_reg = LAST_ARM_FP_REGNUM; 8315 8316 for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --) 8317 { 8318 if (regs_ever_live[reg] && !call_used_regs[reg]) 8319 { 8320 if (start_reg - reg == 3) 8321 { 8322 insn = emit_sfm (reg, 4); 8323 RTX_FRAME_RELATED_P (insn) = 1; 8324 start_reg = reg - 1; 8325 } 8326 } 8327 else 8328 { 8329 if (start_reg != reg) 8330 { 8331 insn = emit_sfm (reg + 1, start_reg - reg); 8332 RTX_FRAME_RELATED_P (insn) = 1; 8333 } 8334 start_reg = reg - 1; 8335 } 8336 } 8337 8338 if (start_reg != reg) 8339 { 8340 insn = emit_sfm (reg + 1, start_reg - reg); 8341 RTX_FRAME_RELATED_P (insn) = 1; 8342 } 8343 } 8344 } 8345 8346 if (frame_pointer_needed) 8347 { 8348 /* Create the new frame pointer. */ 8349 insn = GEN_INT (-(4 + args_to_push + fp_offset)); 8350 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx, ip_rtx, insn)); 8351 RTX_FRAME_RELATED_P (insn) = 1; 8352 8353 if (IS_NESTED (func_type)) 8354 { 8355 /* Recover the static chain register. */ 8356 if (regs_ever_live [3] == 0 8357 || saved_pretend_args) 8358 insn = gen_rtx_REG (SImode, 3); 8359 else /* if (current_function_pretend_args_size == 0) */ 8360 { 8361 insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, GEN_INT (4)); 8362 insn = gen_rtx_MEM (SImode, insn); 8363 } 8364 8365 emit_insn (gen_rtx_SET (SImode, ip_rtx, insn)); 8366 /* Add a USE to stop propagate_one_insn() from barfing. */ 8367 emit_insn (gen_prologue_use (ip_rtx)); 8368 } 8369 } 8370 8371 amount = GEN_INT (-(get_frame_size () 8372 + current_function_outgoing_args_size)); 8373 8374 if (amount != const0_rtx) 8375 { 8376 /* This add can produce multiple insns for a large constant, so we 8377 need to get tricky. */ 8378 rtx last = get_last_insn (); 8379 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 8380 amount)); 8381 do 8382 { 8383 last = last ? NEXT_INSN (last) : get_insns (); 8384 RTX_FRAME_RELATED_P (last) = 1; 8385 } 8386 while (last != insn); 8387 8388 /* If the frame pointer is needed, emit a special barrier that 8389 will prevent the scheduler from moving stores to the frame 8390 before the stack adjustment. */ 8391 if (frame_pointer_needed) 8392 { 8393 rtx unspec = gen_rtx_UNSPEC (SImode, 8394 gen_rtvec (2, stack_pointer_rtx, 8395 hard_frame_pointer_rtx), 8396 UNSPEC_PRLG_STK); 8397 8398 insn = emit_insn (gen_rtx_CLOBBER (VOIDmode, 8399 gen_rtx_MEM (BLKmode, unspec))); 8400 } 8401 } 8402 8403 /* If we are profiling, make sure no instructions are scheduled before 8404 the call to mcount. Similarly if the user has requested no 8405 scheduling in the prolog. */ 8406 if (current_function_profile || TARGET_NO_SCHED_PRO) 8407 emit_insn (gen_blockage ()); 8408 8409 /* If the link register is being kept alive, with the return address in it, 8410 then make sure that it does not get reused by the ce2 pass. */ 8411 if ((live_regs_mask & (1 << LR_REGNUM)) == 0) 8412 { 8413 emit_insn (gen_prologue_use (gen_rtx_REG (SImode, LR_REGNUM))); 8414 cfun->machine->lr_save_eliminated = 1; 8415 } 8416} 8417 8418/* If CODE is 'd', then the X is a condition operand and the instruction 8419 should only be executed if the condition is true. 8420 if CODE is 'D', then the X is a condition operand and the instruction 8421 should only be executed if the condition is false: however, if the mode 8422 of the comparison is CCFPEmode, then always execute the instruction -- we 8423 do this because in these circumstances !GE does not necessarily imply LT; 8424 in these cases the instruction pattern will take care to make sure that 8425 an instruction containing %d will follow, thereby undoing the effects of 8426 doing this instruction unconditionally. 8427 If CODE is 'N' then X is a floating point operand that must be negated 8428 before output. 8429 If CODE is 'B' then output a bitwise inverted value of X (a const int). 8430 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ 8431 8432void 8433arm_print_operand (stream, x, code) 8434 FILE * stream; 8435 rtx x; 8436 int code; 8437{ 8438 switch (code) 8439 { 8440 case '@': 8441 fputs (ASM_COMMENT_START, stream); 8442 return; 8443 8444 case '_': 8445 fputs (user_label_prefix, stream); 8446 return; 8447 8448 case '|': 8449 fputs (REGISTER_PREFIX, stream); 8450 return; 8451 8452 case '?': 8453 if (arm_ccfsm_state == 3 || arm_ccfsm_state == 4) 8454 { 8455 if (TARGET_THUMB || current_insn_predicate != NULL) 8456 abort (); 8457 8458 fputs (arm_condition_codes[arm_current_cc], stream); 8459 } 8460 else if (current_insn_predicate) 8461 { 8462 enum arm_cond_code code; 8463 8464 if (TARGET_THUMB) 8465 abort (); 8466 8467 code = get_arm_condition_code (current_insn_predicate); 8468 fputs (arm_condition_codes[code], stream); 8469 } 8470 return; 8471 8472 case 'N': 8473 { 8474 REAL_VALUE_TYPE r; 8475 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 8476 r = REAL_VALUE_NEGATE (r); 8477 fprintf (stream, "%s", fp_const_from_val (&r)); 8478 } 8479 return; 8480 8481 case 'B': 8482 if (GET_CODE (x) == CONST_INT) 8483 { 8484 HOST_WIDE_INT val; 8485 val = ARM_SIGN_EXTEND (~INTVAL (x)); 8486 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); 8487 } 8488 else 8489 { 8490 putc ('~', stream); 8491 output_addr_const (stream, x); 8492 } 8493 return; 8494 8495 case 'i': 8496 fprintf (stream, "%s", arithmetic_instr (x, 1)); 8497 return; 8498 8499 case 'I': 8500 fprintf (stream, "%s", arithmetic_instr (x, 0)); 8501 return; 8502 8503 case 'S': 8504 { 8505 HOST_WIDE_INT val; 8506 const char * shift = shift_op (x, &val); 8507 8508 if (shift) 8509 { 8510 fprintf (stream, ", %s ", shift_op (x, &val)); 8511 if (val == -1) 8512 arm_print_operand (stream, XEXP (x, 1), 0); 8513 else 8514 { 8515 fputc ('#', stream); 8516 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); 8517 } 8518 } 8519 } 8520 return; 8521 8522 /* An explanation of the 'Q', 'R' and 'H' register operands: 8523 8524 In a pair of registers containing a DI or DF value the 'Q' 8525 operand returns the register number of the register containing 8526 the least signficant part of the value. The 'R' operand returns 8527 the register number of the register containing the most 8528 significant part of the value. 8529 8530 The 'H' operand returns the higher of the two register numbers. 8531 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the 8532 same as the 'Q' operand, since the most signficant part of the 8533 value is held in the lower number register. The reverse is true 8534 on systems where WORDS_BIG_ENDIAN is false. 8535 8536 The purpose of these operands is to distinguish between cases 8537 where the endian-ness of the values is important (for example 8538 when they are added together), and cases where the endian-ness 8539 is irrelevant, but the order of register operations is important. 8540 For example when loading a value from memory into a register 8541 pair, the endian-ness does not matter. Provided that the value 8542 from the lower memory address is put into the lower numbered 8543 register, and the value from the higher address is put into the 8544 higher numbered register, the load will work regardless of whether 8545 the value being loaded is big-wordian or little-wordian. The 8546 order of the two register loads can matter however, if the address 8547 of the memory location is actually held in one of the registers 8548 being overwritten by the load. */ 8549 case 'Q': 8550 if (REGNO (x) > LAST_ARM_REGNUM) 8551 abort (); 8552 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 1 : 0)); 8553 return; 8554 8555 case 'R': 8556 if (REGNO (x) > LAST_ARM_REGNUM) 8557 abort (); 8558 asm_fprintf (stream, "%r", REGNO (x) + (WORDS_BIG_ENDIAN ? 0 : 1)); 8559 return; 8560 8561 case 'H': 8562 if (REGNO (x) > LAST_ARM_REGNUM) 8563 abort (); 8564 asm_fprintf (stream, "%r", REGNO (x) + 1); 8565 return; 8566 8567 case 'm': 8568 asm_fprintf (stream, "%r", 8569 GET_CODE (XEXP (x, 0)) == REG 8570 ? REGNO (XEXP (x, 0)) : REGNO (XEXP (XEXP (x, 0), 0))); 8571 return; 8572 8573 case 'M': 8574 asm_fprintf (stream, "{%r-%r}", 8575 REGNO (x), 8576 REGNO (x) + NUM_REGS (GET_MODE (x)) - 1); 8577 return; 8578 8579 case 'd': 8580 if (!x) 8581 return; 8582 8583 if (TARGET_ARM) 8584 fputs (arm_condition_codes[get_arm_condition_code (x)], 8585 stream); 8586 else 8587 fputs (thumb_condition_code (x, 0), stream); 8588 return; 8589 8590 case 'D': 8591 if (!x) 8592 return; 8593 8594 if (TARGET_ARM) 8595 fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE 8596 (get_arm_condition_code (x))], 8597 stream); 8598 else 8599 fputs (thumb_condition_code (x, 1), stream); 8600 return; 8601 8602 default: 8603 if (x == 0) 8604 abort (); 8605 8606 if (GET_CODE (x) == REG) 8607 asm_fprintf (stream, "%r", REGNO (x)); 8608 else if (GET_CODE (x) == MEM) 8609 { 8610 output_memory_reference_mode = GET_MODE (x); 8611 output_address (XEXP (x, 0)); 8612 } 8613 else if (GET_CODE (x) == CONST_DOUBLE) 8614 fprintf (stream, "#%s", fp_immediate_constant (x)); 8615 else if (GET_CODE (x) == NEG) 8616 abort (); /* This should never happen now. */ 8617 else 8618 { 8619 fputc ('#', stream); 8620 output_addr_const (stream, x); 8621 } 8622 } 8623} 8624 8625#ifndef AOF_ASSEMBLER 8626/* Target hook for assembling integer objects. The ARM version needs to 8627 handle word-sized values specially. */ 8628 8629static bool 8630arm_assemble_integer (x, size, aligned_p) 8631 rtx x; 8632 unsigned int size; 8633 int aligned_p; 8634{ 8635 if (size == UNITS_PER_WORD && aligned_p) 8636 { 8637 fputs ("\t.word\t", asm_out_file); 8638 output_addr_const (asm_out_file, x); 8639 8640 /* Mark symbols as position independent. We only do this in the 8641 .text segment, not in the .data segment. */ 8642 if (NEED_GOT_RELOC && flag_pic && making_const_table && 8643 (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) 8644 { 8645 if (GET_CODE (x) == SYMBOL_REF 8646 && (CONSTANT_POOL_ADDRESS_P (x) 8647 || ENCODED_SHORT_CALL_ATTR_P (XSTR (x, 0)))) 8648 fputs ("(GOTOFF)", asm_out_file); 8649 else if (GET_CODE (x) == LABEL_REF) 8650 fputs ("(GOTOFF)", asm_out_file); 8651 else 8652 fputs ("(GOT)", asm_out_file); 8653 } 8654 fputc ('\n', asm_out_file); 8655 return true; 8656 } 8657 8658 return default_assemble_integer (x, size, aligned_p); 8659} 8660#endif 8661 8662/* A finite state machine takes care of noticing whether or not instructions 8663 can be conditionally executed, and thus decrease execution time and code 8664 size by deleting branch instructions. The fsm is controlled by 8665 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */ 8666 8667/* The state of the fsm controlling condition codes are: 8668 0: normal, do nothing special 8669 1: make ASM_OUTPUT_OPCODE not output this instruction 8670 2: make ASM_OUTPUT_OPCODE not output this instruction 8671 3: make instructions conditional 8672 4: make instructions conditional 8673 8674 State transitions (state->state by whom under condition): 8675 0 -> 1 final_prescan_insn if the `target' is a label 8676 0 -> 2 final_prescan_insn if the `target' is an unconditional branch 8677 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch 8678 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch 8679 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached 8680 (the target label has CODE_LABEL_NUMBER equal to arm_target_label). 8681 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached 8682 (the target insn is arm_target_insn). 8683 8684 If the jump clobbers the conditions then we use states 2 and 4. 8685 8686 A similar thing can be done with conditional return insns. 8687 8688 XXX In case the `target' is an unconditional branch, this conditionalising 8689 of the instructions always reduces code size, but not always execution 8690 time. But then, I want to reduce the code size to somewhere near what 8691 /bin/cc produces. */ 8692 8693/* Returns the index of the ARM condition code string in 8694 `arm_condition_codes'. COMPARISON should be an rtx like 8695 `(eq (...) (...))'. */ 8696 8697static enum arm_cond_code 8698get_arm_condition_code (comparison) 8699 rtx comparison; 8700{ 8701 enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); 8702 int code; 8703 enum rtx_code comp_code = GET_CODE (comparison); 8704 8705 if (GET_MODE_CLASS (mode) != MODE_CC) 8706 mode = SELECT_CC_MODE (comp_code, XEXP (comparison, 0), 8707 XEXP (comparison, 1)); 8708 8709 switch (mode) 8710 { 8711 case CC_DNEmode: code = ARM_NE; goto dominance; 8712 case CC_DEQmode: code = ARM_EQ; goto dominance; 8713 case CC_DGEmode: code = ARM_GE; goto dominance; 8714 case CC_DGTmode: code = ARM_GT; goto dominance; 8715 case CC_DLEmode: code = ARM_LE; goto dominance; 8716 case CC_DLTmode: code = ARM_LT; goto dominance; 8717 case CC_DGEUmode: code = ARM_CS; goto dominance; 8718 case CC_DGTUmode: code = ARM_HI; goto dominance; 8719 case CC_DLEUmode: code = ARM_LS; goto dominance; 8720 case CC_DLTUmode: code = ARM_CC; 8721 8722 dominance: 8723 if (comp_code != EQ && comp_code != NE) 8724 abort (); 8725 8726 if (comp_code == EQ) 8727 return ARM_INVERSE_CONDITION_CODE (code); 8728 return code; 8729 8730 case CC_NOOVmode: 8731 switch (comp_code) 8732 { 8733 case NE: return ARM_NE; 8734 case EQ: return ARM_EQ; 8735 case GE: return ARM_PL; 8736 case LT: return ARM_MI; 8737 default: abort (); 8738 } 8739 8740 case CC_Zmode: 8741 switch (comp_code) 8742 { 8743 case NE: return ARM_NE; 8744 case EQ: return ARM_EQ; 8745 default: abort (); 8746 } 8747 8748 case CCFPEmode: 8749 case CCFPmode: 8750 /* These encodings assume that AC=1 in the FPA system control 8751 byte. This allows us to handle all cases except UNEQ and 8752 LTGT. */ 8753 switch (comp_code) 8754 { 8755 case GE: return ARM_GE; 8756 case GT: return ARM_GT; 8757 case LE: return ARM_LS; 8758 case LT: return ARM_MI; 8759 case NE: return ARM_NE; 8760 case EQ: return ARM_EQ; 8761 case ORDERED: return ARM_VC; 8762 case UNORDERED: return ARM_VS; 8763 case UNLT: return ARM_LT; 8764 case UNLE: return ARM_LE; 8765 case UNGT: return ARM_HI; 8766 case UNGE: return ARM_PL; 8767 /* UNEQ and LTGT do not have a representation. */ 8768 case UNEQ: /* Fall through. */ 8769 case LTGT: /* Fall through. */ 8770 default: abort (); 8771 } 8772 8773 case CC_SWPmode: 8774 switch (comp_code) 8775 { 8776 case NE: return ARM_NE; 8777 case EQ: return ARM_EQ; 8778 case GE: return ARM_LE; 8779 case GT: return ARM_LT; 8780 case LE: return ARM_GE; 8781 case LT: return ARM_GT; 8782 case GEU: return ARM_LS; 8783 case GTU: return ARM_CC; 8784 case LEU: return ARM_CS; 8785 case LTU: return ARM_HI; 8786 default: abort (); 8787 } 8788 8789 case CC_Cmode: 8790 switch (comp_code) 8791 { 8792 case LTU: return ARM_CS; 8793 case GEU: return ARM_CC; 8794 default: abort (); 8795 } 8796 8797 case CCmode: 8798 switch (comp_code) 8799 { 8800 case NE: return ARM_NE; 8801 case EQ: return ARM_EQ; 8802 case GE: return ARM_GE; 8803 case GT: return ARM_GT; 8804 case LE: return ARM_LE; 8805 case LT: return ARM_LT; 8806 case GEU: return ARM_CS; 8807 case GTU: return ARM_HI; 8808 case LEU: return ARM_LS; 8809 case LTU: return ARM_CC; 8810 default: abort (); 8811 } 8812 8813 default: abort (); 8814 } 8815 8816 abort (); 8817} 8818 8819 8820void 8821arm_final_prescan_insn (insn) 8822 rtx insn; 8823{ 8824 /* BODY will hold the body of INSN. */ 8825 rtx body = PATTERN (insn); 8826 8827 /* This will be 1 if trying to repeat the trick, and things need to be 8828 reversed if it appears to fail. */ 8829 int reverse = 0; 8830 8831 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is 8832 taken are clobbered, even if the rtl suggests otherwise. It also 8833 means that we have to grub around within the jump expression to find 8834 out what the conditions are when the jump isn't taken. */ 8835 int jump_clobbers = 0; 8836 8837 /* If we start with a return insn, we only succeed if we find another one. */ 8838 int seeking_return = 0; 8839 8840 /* START_INSN will hold the insn from where we start looking. This is the 8841 first insn after the following code_label if REVERSE is true. */ 8842 rtx start_insn = insn; 8843 8844 /* If in state 4, check if the target branch is reached, in order to 8845 change back to state 0. */ 8846 if (arm_ccfsm_state == 4) 8847 { 8848 if (insn == arm_target_insn) 8849 { 8850 arm_target_insn = NULL; 8851 arm_ccfsm_state = 0; 8852 } 8853 return; 8854 } 8855 8856 /* If in state 3, it is possible to repeat the trick, if this insn is an 8857 unconditional branch to a label, and immediately following this branch 8858 is the previous target label which is only used once, and the label this 8859 branch jumps to is not too far off. */ 8860 if (arm_ccfsm_state == 3) 8861 { 8862 if (simplejump_p (insn)) 8863 { 8864 start_insn = next_nonnote_insn (start_insn); 8865 if (GET_CODE (start_insn) == BARRIER) 8866 { 8867 /* XXX Isn't this always a barrier? */ 8868 start_insn = next_nonnote_insn (start_insn); 8869 } 8870 if (GET_CODE (start_insn) == CODE_LABEL 8871 && CODE_LABEL_NUMBER (start_insn) == arm_target_label 8872 && LABEL_NUSES (start_insn) == 1) 8873 reverse = TRUE; 8874 else 8875 return; 8876 } 8877 else if (GET_CODE (body) == RETURN) 8878 { 8879 start_insn = next_nonnote_insn (start_insn); 8880 if (GET_CODE (start_insn) == BARRIER) 8881 start_insn = next_nonnote_insn (start_insn); 8882 if (GET_CODE (start_insn) == CODE_LABEL 8883 && CODE_LABEL_NUMBER (start_insn) == arm_target_label 8884 && LABEL_NUSES (start_insn) == 1) 8885 { 8886 reverse = TRUE; 8887 seeking_return = 1; 8888 } 8889 else 8890 return; 8891 } 8892 else 8893 return; 8894 } 8895 8896 if (arm_ccfsm_state != 0 && !reverse) 8897 abort (); 8898 if (GET_CODE (insn) != JUMP_INSN) 8899 return; 8900 8901 /* This jump might be paralleled with a clobber of the condition codes 8902 the jump should always come first */ 8903 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) 8904 body = XVECEXP (body, 0, 0); 8905 8906#if 0 8907 /* If this is a conditional return then we don't want to know */ 8908 if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC 8909 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE 8910 && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN 8911 || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)) 8912 return; 8913#endif 8914 8915 if (reverse 8916 || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC 8917 && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) 8918 { 8919 int insns_skipped; 8920 int fail = FALSE, succeed = FALSE; 8921 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */ 8922 int then_not_else = TRUE; 8923 rtx this_insn = start_insn, label = 0; 8924 8925 /* If the jump cannot be done with one instruction, we cannot 8926 conditionally execute the instruction in the inverse case. */ 8927 if (get_attr_conds (insn) == CONDS_JUMP_CLOB) 8928 { 8929 jump_clobbers = 1; 8930 return; 8931 } 8932 8933 /* Register the insn jumped to. */ 8934 if (reverse) 8935 { 8936 if (!seeking_return) 8937 label = XEXP (SET_SRC (body), 0); 8938 } 8939 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF) 8940 label = XEXP (XEXP (SET_SRC (body), 1), 0); 8941 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF) 8942 { 8943 label = XEXP (XEXP (SET_SRC (body), 2), 0); 8944 then_not_else = FALSE; 8945 } 8946 else if (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN) 8947 seeking_return = 1; 8948 else if (GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN) 8949 { 8950 seeking_return = 1; 8951 then_not_else = FALSE; 8952 } 8953 else 8954 abort (); 8955 8956 /* See how many insns this branch skips, and what kind of insns. If all 8957 insns are okay, and the label or unconditional branch to the same 8958 label is not too far away, succeed. */ 8959 for (insns_skipped = 0; 8960 !fail && !succeed && insns_skipped++ < max_insns_skipped;) 8961 { 8962 rtx scanbody; 8963 8964 this_insn = next_nonnote_insn (this_insn); 8965 if (!this_insn) 8966 break; 8967 8968 switch (GET_CODE (this_insn)) 8969 { 8970 case CODE_LABEL: 8971 /* Succeed if it is the target label, otherwise fail since 8972 control falls in from somewhere else. */ 8973 if (this_insn == label) 8974 { 8975 if (jump_clobbers) 8976 { 8977 arm_ccfsm_state = 2; 8978 this_insn = next_nonnote_insn (this_insn); 8979 } 8980 else 8981 arm_ccfsm_state = 1; 8982 succeed = TRUE; 8983 } 8984 else 8985 fail = TRUE; 8986 break; 8987 8988 case BARRIER: 8989 /* Succeed if the following insn is the target label. 8990 Otherwise fail. 8991 If return insns are used then the last insn in a function 8992 will be a barrier. */ 8993 this_insn = next_nonnote_insn (this_insn); 8994 if (this_insn && this_insn == label) 8995 { 8996 if (jump_clobbers) 8997 { 8998 arm_ccfsm_state = 2; 8999 this_insn = next_nonnote_insn (this_insn); 9000 } 9001 else 9002 arm_ccfsm_state = 1; 9003 succeed = TRUE; 9004 } 9005 else 9006 fail = TRUE; 9007 break; 9008 9009 case CALL_INSN: 9010 /* If using 32-bit addresses the cc is not preserved over 9011 calls. */ 9012 if (TARGET_APCS_32) 9013 { 9014 /* Succeed if the following insn is the target label, 9015 or if the following two insns are a barrier and 9016 the target label. */ 9017 this_insn = next_nonnote_insn (this_insn); 9018 if (this_insn && GET_CODE (this_insn) == BARRIER) 9019 this_insn = next_nonnote_insn (this_insn); 9020 9021 if (this_insn && this_insn == label 9022 && insns_skipped < max_insns_skipped) 9023 { 9024 if (jump_clobbers) 9025 { 9026 arm_ccfsm_state = 2; 9027 this_insn = next_nonnote_insn (this_insn); 9028 } 9029 else 9030 arm_ccfsm_state = 1; 9031 succeed = TRUE; 9032 } 9033 else 9034 fail = TRUE; 9035 } 9036 break; 9037 9038 case JUMP_INSN: 9039 /* If this is an unconditional branch to the same label, succeed. 9040 If it is to another label, do nothing. If it is conditional, 9041 fail. */ 9042 /* XXX Probably, the tests for SET and the PC are unnecessary. */ 9043 9044 scanbody = PATTERN (this_insn); 9045 if (GET_CODE (scanbody) == SET 9046 && GET_CODE (SET_DEST (scanbody)) == PC) 9047 { 9048 if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF 9049 && XEXP (SET_SRC (scanbody), 0) == label && !reverse) 9050 { 9051 arm_ccfsm_state = 2; 9052 succeed = TRUE; 9053 } 9054 else if (GET_CODE (SET_SRC (scanbody)) == IF_THEN_ELSE) 9055 fail = TRUE; 9056 } 9057 /* Fail if a conditional return is undesirable (eg on a 9058 StrongARM), but still allow this if optimizing for size. */ 9059 else if (GET_CODE (scanbody) == RETURN 9060 && !use_return_insn (TRUE) 9061 && !optimize_size) 9062 fail = TRUE; 9063 else if (GET_CODE (scanbody) == RETURN 9064 && seeking_return) 9065 { 9066 arm_ccfsm_state = 2; 9067 succeed = TRUE; 9068 } 9069 else if (GET_CODE (scanbody) == PARALLEL) 9070 { 9071 switch (get_attr_conds (this_insn)) 9072 { 9073 case CONDS_NOCOND: 9074 break; 9075 default: 9076 fail = TRUE; 9077 break; 9078 } 9079 } 9080 else 9081 fail = TRUE; /* Unrecognized jump (eg epilogue). */ 9082 9083 break; 9084 9085 case INSN: 9086 /* Instructions using or affecting the condition codes make it 9087 fail. */ 9088 scanbody = PATTERN (this_insn); 9089 if (!(GET_CODE (scanbody) == SET 9090 || GET_CODE (scanbody) == PARALLEL) 9091 || get_attr_conds (this_insn) != CONDS_NOCOND) 9092 fail = TRUE; 9093 break; 9094 9095 default: 9096 break; 9097 } 9098 } 9099 if (succeed) 9100 { 9101 if ((!seeking_return) && (arm_ccfsm_state == 1 || reverse)) 9102 arm_target_label = CODE_LABEL_NUMBER (label); 9103 else if (seeking_return || arm_ccfsm_state == 2) 9104 { 9105 while (this_insn && GET_CODE (PATTERN (this_insn)) == USE) 9106 { 9107 this_insn = next_nonnote_insn (this_insn); 9108 if (this_insn && (GET_CODE (this_insn) == BARRIER 9109 || GET_CODE (this_insn) == CODE_LABEL)) 9110 abort (); 9111 } 9112 if (!this_insn) 9113 { 9114 /* Oh, dear! we ran off the end.. give up */ 9115 recog (PATTERN (insn), insn, NULL); 9116 arm_ccfsm_state = 0; 9117 arm_target_insn = NULL; 9118 return; 9119 } 9120 arm_target_insn = this_insn; 9121 } 9122 else 9123 abort (); 9124 if (jump_clobbers) 9125 { 9126 if (reverse) 9127 abort (); 9128 arm_current_cc = 9129 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body), 9130 0), 0), 1)); 9131 if (GET_CODE (XEXP (XEXP (SET_SRC (body), 0), 0)) == AND) 9132 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); 9133 if (GET_CODE (XEXP (SET_SRC (body), 0)) == NE) 9134 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); 9135 } 9136 else 9137 { 9138 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from 9139 what it was. */ 9140 if (!reverse) 9141 arm_current_cc = get_arm_condition_code (XEXP (SET_SRC (body), 9142 0)); 9143 } 9144 9145 if (reverse || then_not_else) 9146 arm_current_cc = ARM_INVERSE_CONDITION_CODE (arm_current_cc); 9147 } 9148 9149 /* Restore recog_data (getting the attributes of other insns can 9150 destroy this array, but final.c assumes that it remains intact 9151 across this call; since the insn has been recognized already we 9152 call recog direct). */ 9153 recog (PATTERN (insn), insn, NULL); 9154 } 9155} 9156 9157/* Returns true if REGNO is a valid register 9158 for holding a quantity of tyoe MODE. */ 9159 9160int 9161arm_hard_regno_mode_ok (regno, mode) 9162 unsigned int regno; 9163 enum machine_mode mode; 9164{ 9165 if (GET_MODE_CLASS (mode) == MODE_CC) 9166 return regno == CC_REGNUM; 9167 9168 if (TARGET_THUMB) 9169 /* For the Thumb we only allow values bigger than SImode in 9170 registers 0 - 6, so that there is always a second low 9171 register available to hold the upper part of the value. 9172 We probably we ought to ensure that the register is the 9173 start of an even numbered register pair. */ 9174 return (NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); 9175 9176 if (regno <= LAST_ARM_REGNUM) 9177 /* We allow any value to be stored in the general regisetrs. */ 9178 return 1; 9179 9180 if ( regno == FRAME_POINTER_REGNUM 9181 || regno == ARG_POINTER_REGNUM) 9182 /* We only allow integers in the fake hard registers. */ 9183 return GET_MODE_CLASS (mode) == MODE_INT; 9184 9185 /* The only registers left are the FPU registers 9186 which we only allow to hold FP values. */ 9187 return GET_MODE_CLASS (mode) == MODE_FLOAT 9188 && regno >= FIRST_ARM_FP_REGNUM 9189 && regno <= LAST_ARM_FP_REGNUM; 9190} 9191 9192int 9193arm_regno_class (regno) 9194 int regno; 9195{ 9196 if (TARGET_THUMB) 9197 { 9198 if (regno == STACK_POINTER_REGNUM) 9199 return STACK_REG; 9200 if (regno == CC_REGNUM) 9201 return CC_REG; 9202 if (regno < 8) 9203 return LO_REGS; 9204 return HI_REGS; 9205 } 9206 9207 if ( regno <= LAST_ARM_REGNUM 9208 || regno == FRAME_POINTER_REGNUM 9209 || regno == ARG_POINTER_REGNUM) 9210 return GENERAL_REGS; 9211 9212 if (regno == CC_REGNUM) 9213 return NO_REGS; 9214 9215 return FPU_REGS; 9216} 9217 9218/* Handle a special case when computing the offset 9219 of an argument from the frame pointer. */ 9220 9221int 9222arm_debugger_arg_offset (value, addr) 9223 int value; 9224 rtx addr; 9225{ 9226 rtx insn; 9227 9228 /* We are only interested if dbxout_parms() failed to compute the offset. */ 9229 if (value != 0) 9230 return 0; 9231 9232 /* We can only cope with the case where the address is held in a register. */ 9233 if (GET_CODE (addr) != REG) 9234 return 0; 9235 9236 /* If we are using the frame pointer to point at the argument, then 9237 an offset of 0 is correct. */ 9238 if (REGNO (addr) == (unsigned) HARD_FRAME_POINTER_REGNUM) 9239 return 0; 9240 9241 /* If we are using the stack pointer to point at the 9242 argument, then an offset of 0 is correct. */ 9243 if ((TARGET_THUMB || !frame_pointer_needed) 9244 && REGNO (addr) == SP_REGNUM) 9245 return 0; 9246 9247 /* Oh dear. The argument is pointed to by a register rather 9248 than being held in a register, or being stored at a known 9249 offset from the frame pointer. Since GDB only understands 9250 those two kinds of argument we must translate the address 9251 held in the register into an offset from the frame pointer. 9252 We do this by searching through the insns for the function 9253 looking to see where this register gets its value. If the 9254 register is initialised from the frame pointer plus an offset 9255 then we are in luck and we can continue, otherwise we give up. 9256 9257 This code is exercised by producing debugging information 9258 for a function with arguments like this: 9259 9260 double func (double a, double b, int c, double d) {return d;} 9261 9262 Without this code the stab for parameter 'd' will be set to 9263 an offset of 0 from the frame pointer, rather than 8. */ 9264 9265 /* The if() statement says: 9266 9267 If the insn is a normal instruction 9268 and if the insn is setting the value in a register 9269 and if the register being set is the register holding the address of the argument 9270 and if the address is computing by an addition 9271 that involves adding to a register 9272 which is the frame pointer 9273 a constant integer 9274 9275 then... */ 9276 9277 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 9278 { 9279 if ( GET_CODE (insn) == INSN 9280 && GET_CODE (PATTERN (insn)) == SET 9281 && REGNO (XEXP (PATTERN (insn), 0)) == REGNO (addr) 9282 && GET_CODE (XEXP (PATTERN (insn), 1)) == PLUS 9283 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 0)) == REG 9284 && REGNO (XEXP (XEXP (PATTERN (insn), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM 9285 && GET_CODE (XEXP (XEXP (PATTERN (insn), 1), 1)) == CONST_INT 9286 ) 9287 { 9288 value = INTVAL (XEXP (XEXP (PATTERN (insn), 1), 1)); 9289 9290 break; 9291 } 9292 } 9293 9294 if (value == 0) 9295 { 9296 debug_rtx (addr); 9297 warning ("unable to compute real location of stacked parameter"); 9298 value = 8; /* XXX magic hack */ 9299 } 9300 9301 return value; 9302} 9303 9304#define def_builtin(NAME, TYPE, CODE) \ 9305 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL) 9306 9307void 9308arm_init_builtins () 9309{ 9310 tree endlink = void_list_node; 9311 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink); 9312 tree pchar_type_node = build_pointer_type (char_type_node); 9313 9314 tree int_ftype_int, void_ftype_pchar; 9315 9316 /* void func (void *) */ 9317 void_ftype_pchar 9318 = build_function_type (void_type_node, 9319 tree_cons (NULL_TREE, pchar_type_node, endlink)); 9320 9321 /* int func (int) */ 9322 int_ftype_int 9323 = build_function_type (integer_type_node, int_endlink); 9324 9325 /* Initialize arm V5 builtins. */ 9326 if (arm_arch5) 9327 def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ); 9328} 9329 9330/* Expand an expression EXP that calls a built-in function, 9331 with result going to TARGET if that's convenient 9332 (and in mode MODE if that's convenient). 9333 SUBTARGET may be used as the target for computing one of EXP's operands. 9334 IGNORE is nonzero if the value is to be ignored. */ 9335 9336rtx 9337arm_expand_builtin (exp, target, subtarget, mode, ignore) 9338 tree exp; 9339 rtx target; 9340 rtx subtarget ATTRIBUTE_UNUSED; 9341 enum machine_mode mode ATTRIBUTE_UNUSED; 9342 int ignore ATTRIBUTE_UNUSED; 9343{ 9344 enum insn_code icode; 9345 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); 9346 tree arglist = TREE_OPERAND (exp, 1); 9347 tree arg0; 9348 rtx op0, pat; 9349 enum machine_mode tmode, mode0; 9350 int fcode = DECL_FUNCTION_CODE (fndecl); 9351 9352 switch (fcode) 9353 { 9354 default: 9355 break; 9356 9357 case ARM_BUILTIN_CLZ: 9358 icode = CODE_FOR_clz; 9359 arg0 = TREE_VALUE (arglist); 9360 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); 9361 tmode = insn_data[icode].operand[0].mode; 9362 mode0 = insn_data[icode].operand[1].mode; 9363 9364 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) 9365 op0 = copy_to_mode_reg (mode0, op0); 9366 if (target == 0 9367 || GET_MODE (target) != tmode 9368 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 9369 target = gen_reg_rtx (tmode); 9370 pat = GEN_FCN (icode) (target, op0); 9371 if (! pat) 9372 return 0; 9373 emit_insn (pat); 9374 return target; 9375 } 9376 9377 /* @@@ Should really do something sensible here. */ 9378 return NULL_RTX; 9379} 9380 9381/* Recursively search through all of the blocks in a function 9382 checking to see if any of the variables created in that 9383 function match the RTX called 'orig'. If they do then 9384 replace them with the RTX called 'new'. */ 9385 9386static void 9387replace_symbols_in_block (block, orig, new) 9388 tree block; 9389 rtx orig; 9390 rtx new; 9391{ 9392 for (; block; block = BLOCK_CHAIN (block)) 9393 { 9394 tree sym; 9395 9396 if (!TREE_USED (block)) 9397 continue; 9398 9399 for (sym = BLOCK_VARS (block); sym; sym = TREE_CHAIN (sym)) 9400 { 9401 if ( (DECL_NAME (sym) == 0 && TREE_CODE (sym) != TYPE_DECL) 9402 || DECL_IGNORED_P (sym) 9403 || TREE_CODE (sym) != VAR_DECL 9404 || DECL_EXTERNAL (sym) 9405 || !rtx_equal_p (DECL_RTL (sym), orig) 9406 ) 9407 continue; 9408 9409 SET_DECL_RTL (sym, new); 9410 } 9411 9412 replace_symbols_in_block (BLOCK_SUBBLOCKS (block), orig, new); 9413 } 9414} 9415 9416/* Return the number (counting from 0) of 9417 the least significant set bit in MASK. */ 9418 9419#ifdef __GNUC__ 9420inline 9421#endif 9422static int 9423number_of_first_bit_set (mask) 9424 int mask; 9425{ 9426 int bit; 9427 9428 for (bit = 0; 9429 (mask & (1 << bit)) == 0; 9430 ++bit) 9431 continue; 9432 9433 return bit; 9434} 9435 9436/* Generate code to return from a thumb function. 9437 If 'reg_containing_return_addr' is -1, then the return address is 9438 actually on the stack, at the stack pointer. */ 9439static void 9440thumb_exit (f, reg_containing_return_addr, eh_ofs) 9441 FILE * f; 9442 int reg_containing_return_addr; 9443 rtx eh_ofs; 9444{ 9445 unsigned regs_available_for_popping; 9446 unsigned regs_to_pop; 9447 int pops_needed; 9448 unsigned available; 9449 unsigned required; 9450 int mode; 9451 int size; 9452 int restore_a4 = FALSE; 9453 9454 /* Compute the registers we need to pop. */ 9455 regs_to_pop = 0; 9456 pops_needed = 0; 9457 9458 /* There is an assumption here, that if eh_ofs is not NULL, the 9459 normal return address will have been pushed. */ 9460 if (reg_containing_return_addr == -1 || eh_ofs) 9461 { 9462 /* When we are generating a return for __builtin_eh_return, 9463 reg_containing_return_addr must specify the return regno. */ 9464 if (eh_ofs && reg_containing_return_addr == -1) 9465 abort (); 9466 9467 regs_to_pop |= 1 << LR_REGNUM; 9468 ++pops_needed; 9469 } 9470 9471 if (TARGET_BACKTRACE) 9472 { 9473 /* Restore the (ARM) frame pointer and stack pointer. */ 9474 regs_to_pop |= (1 << ARM_HARD_FRAME_POINTER_REGNUM) | (1 << SP_REGNUM); 9475 pops_needed += 2; 9476 } 9477 9478 /* If there is nothing to pop then just emit the BX instruction and 9479 return. */ 9480 if (pops_needed == 0) 9481 { 9482 if (eh_ofs) 9483 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); 9484 9485 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); 9486 return; 9487 } 9488 /* Otherwise if we are not supporting interworking and we have not created 9489 a backtrace structure and the function was not entered in ARM mode then 9490 just pop the return address straight into the PC. */ 9491 else if (!TARGET_INTERWORK 9492 && !TARGET_BACKTRACE 9493 && !is_called_in_ARM_mode (current_function_decl)) 9494 { 9495 if (eh_ofs) 9496 { 9497 asm_fprintf (f, "\tadd\t%r, #4\n", SP_REGNUM); 9498 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); 9499 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); 9500 } 9501 else 9502 asm_fprintf (f, "\tpop\t{%r}\n", PC_REGNUM); 9503 9504 return; 9505 } 9506 9507 /* Find out how many of the (return) argument registers we can corrupt. */ 9508 regs_available_for_popping = 0; 9509 9510 /* If returning via __builtin_eh_return, the bottom three registers 9511 all contain information needed for the return. */ 9512 if (eh_ofs) 9513 size = 12; 9514 else 9515 { 9516#ifdef RTX_CODE 9517 /* If we can deduce the registers used from the function's 9518 return value. This is more reliable that examining 9519 regs_ever_live[] because that will be set if the register is 9520 ever used in the function, not just if the register is used 9521 to hold a return value. */ 9522 9523 if (current_function_return_rtx != 0) 9524 mode = GET_MODE (current_function_return_rtx); 9525 else 9526#endif 9527 mode = DECL_MODE (DECL_RESULT (current_function_decl)); 9528 9529 size = GET_MODE_SIZE (mode); 9530 9531 if (size == 0) 9532 { 9533 /* In a void function we can use any argument register. 9534 In a function that returns a structure on the stack 9535 we can use the second and third argument registers. */ 9536 if (mode == VOIDmode) 9537 regs_available_for_popping = 9538 (1 << ARG_REGISTER (1)) 9539 | (1 << ARG_REGISTER (2)) 9540 | (1 << ARG_REGISTER (3)); 9541 else 9542 regs_available_for_popping = 9543 (1 << ARG_REGISTER (2)) 9544 | (1 << ARG_REGISTER (3)); 9545 } 9546 else if (size <= 4) 9547 regs_available_for_popping = 9548 (1 << ARG_REGISTER (2)) 9549 | (1 << ARG_REGISTER (3)); 9550 else if (size <= 8) 9551 regs_available_for_popping = 9552 (1 << ARG_REGISTER (3)); 9553 } 9554 9555 /* Match registers to be popped with registers into which we pop them. */ 9556 for (available = regs_available_for_popping, 9557 required = regs_to_pop; 9558 required != 0 && available != 0; 9559 available &= ~(available & - available), 9560 required &= ~(required & - required)) 9561 -- pops_needed; 9562 9563 /* If we have any popping registers left over, remove them. */ 9564 if (available > 0) 9565 regs_available_for_popping &= ~available; 9566 9567 /* Otherwise if we need another popping register we can use 9568 the fourth argument register. */ 9569 else if (pops_needed) 9570 { 9571 /* If we have not found any free argument registers and 9572 reg a4 contains the return address, we must move it. */ 9573 if (regs_available_for_popping == 0 9574 && reg_containing_return_addr == LAST_ARG_REGNUM) 9575 { 9576 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); 9577 reg_containing_return_addr = LR_REGNUM; 9578 } 9579 else if (size > 12) 9580 { 9581 /* Register a4 is being used to hold part of the return value, 9582 but we have dire need of a free, low register. */ 9583 restore_a4 = TRUE; 9584 9585 asm_fprintf (f, "\tmov\t%r, %r\n",IP_REGNUM, LAST_ARG_REGNUM); 9586 } 9587 9588 if (reg_containing_return_addr != LAST_ARG_REGNUM) 9589 { 9590 /* The fourth argument register is available. */ 9591 regs_available_for_popping |= 1 << LAST_ARG_REGNUM; 9592 9593 --pops_needed; 9594 } 9595 } 9596 9597 /* Pop as many registers as we can. */ 9598 thumb_pushpop (f, regs_available_for_popping, FALSE); 9599 9600 /* Process the registers we popped. */ 9601 if (reg_containing_return_addr == -1) 9602 { 9603 /* The return address was popped into the lowest numbered register. */ 9604 regs_to_pop &= ~(1 << LR_REGNUM); 9605 9606 reg_containing_return_addr = 9607 number_of_first_bit_set (regs_available_for_popping); 9608 9609 /* Remove this register for the mask of available registers, so that 9610 the return address will not be corrupted by futher pops. */ 9611 regs_available_for_popping &= ~(1 << reg_containing_return_addr); 9612 } 9613 9614 /* If we popped other registers then handle them here. */ 9615 if (regs_available_for_popping) 9616 { 9617 int frame_pointer; 9618 9619 /* Work out which register currently contains the frame pointer. */ 9620 frame_pointer = number_of_first_bit_set (regs_available_for_popping); 9621 9622 /* Move it into the correct place. */ 9623 asm_fprintf (f, "\tmov\t%r, %r\n", 9624 ARM_HARD_FRAME_POINTER_REGNUM, frame_pointer); 9625 9626 /* (Temporarily) remove it from the mask of popped registers. */ 9627 regs_available_for_popping &= ~(1 << frame_pointer); 9628 regs_to_pop &= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM); 9629 9630 if (regs_available_for_popping) 9631 { 9632 int stack_pointer; 9633 9634 /* We popped the stack pointer as well, 9635 find the register that contains it. */ 9636 stack_pointer = number_of_first_bit_set (regs_available_for_popping); 9637 9638 /* Move it into the stack register. */ 9639 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, stack_pointer); 9640 9641 /* At this point we have popped all necessary registers, so 9642 do not worry about restoring regs_available_for_popping 9643 to its correct value: 9644 9645 assert (pops_needed == 0) 9646 assert (regs_available_for_popping == (1 << frame_pointer)) 9647 assert (regs_to_pop == (1 << STACK_POINTER)) */ 9648 } 9649 else 9650 { 9651 /* Since we have just move the popped value into the frame 9652 pointer, the popping register is available for reuse, and 9653 we know that we still have the stack pointer left to pop. */ 9654 regs_available_for_popping |= (1 << frame_pointer); 9655 } 9656 } 9657 9658 /* If we still have registers left on the stack, but we no longer have 9659 any registers into which we can pop them, then we must move the return 9660 address into the link register and make available the register that 9661 contained it. */ 9662 if (regs_available_for_popping == 0 && pops_needed > 0) 9663 { 9664 regs_available_for_popping |= 1 << reg_containing_return_addr; 9665 9666 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, 9667 reg_containing_return_addr); 9668 9669 reg_containing_return_addr = LR_REGNUM; 9670 } 9671 9672 /* If we have registers left on the stack then pop some more. 9673 We know that at most we will want to pop FP and SP. */ 9674 if (pops_needed > 0) 9675 { 9676 int popped_into; 9677 int move_to; 9678 9679 thumb_pushpop (f, regs_available_for_popping, FALSE); 9680 9681 /* We have popped either FP or SP. 9682 Move whichever one it is into the correct register. */ 9683 popped_into = number_of_first_bit_set (regs_available_for_popping); 9684 move_to = number_of_first_bit_set (regs_to_pop); 9685 9686 asm_fprintf (f, "\tmov\t%r, %r\n", move_to, popped_into); 9687 9688 regs_to_pop &= ~(1 << move_to); 9689 9690 --pops_needed; 9691 } 9692 9693 /* If we still have not popped everything then we must have only 9694 had one register available to us and we are now popping the SP. */ 9695 if (pops_needed > 0) 9696 { 9697 int popped_into; 9698 9699 thumb_pushpop (f, regs_available_for_popping, FALSE); 9700 9701 popped_into = number_of_first_bit_set (regs_available_for_popping); 9702 9703 asm_fprintf (f, "\tmov\t%r, %r\n", SP_REGNUM, popped_into); 9704 /* 9705 assert (regs_to_pop == (1 << STACK_POINTER)) 9706 assert (pops_needed == 1) 9707 */ 9708 } 9709 9710 /* If necessary restore the a4 register. */ 9711 if (restore_a4) 9712 { 9713 if (reg_containing_return_addr != LR_REGNUM) 9714 { 9715 asm_fprintf (f, "\tmov\t%r, %r\n", LR_REGNUM, LAST_ARG_REGNUM); 9716 reg_containing_return_addr = LR_REGNUM; 9717 } 9718 9719 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); 9720 } 9721 9722 if (eh_ofs) 9723 asm_fprintf (f, "\tadd\t%r, %r\n", SP_REGNUM, REGNO (eh_ofs)); 9724 9725 /* Return to caller. */ 9726 asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); 9727} 9728 9729/* Emit code to push or pop registers to or from the stack. */ 9730 9731static void 9732thumb_pushpop (f, mask, push) 9733 FILE * f; 9734 int mask; 9735 int push; 9736{ 9737 int regno; 9738 int lo_mask = mask & 0xFF; 9739 9740 if (lo_mask == 0 && !push && (mask & (1 << 15))) 9741 { 9742 /* Special case. Do not generate a POP PC statement here, do it in 9743 thumb_exit() */ 9744 thumb_exit (f, -1, NULL_RTX); 9745 return; 9746 } 9747 9748 fprintf (f, "\t%s\t{", push ? "push" : "pop"); 9749 9750 /* Look at the low registers first. */ 9751 for (regno = 0; regno <= LAST_LO_REGNUM; regno++, lo_mask >>= 1) 9752 { 9753 if (lo_mask & 1) 9754 { 9755 asm_fprintf (f, "%r", regno); 9756 9757 if ((lo_mask & ~1) != 0) 9758 fprintf (f, ", "); 9759 } 9760 } 9761 9762 if (push && (mask & (1 << LR_REGNUM))) 9763 { 9764 /* Catch pushing the LR. */ 9765 if (mask & 0xFF) 9766 fprintf (f, ", "); 9767 9768 asm_fprintf (f, "%r", LR_REGNUM); 9769 } 9770 else if (!push && (mask & (1 << PC_REGNUM))) 9771 { 9772 /* Catch popping the PC. */ 9773 if (TARGET_INTERWORK || TARGET_BACKTRACE) 9774 { 9775 /* The PC is never poped directly, instead 9776 it is popped into r3 and then BX is used. */ 9777 fprintf (f, "}\n"); 9778 9779 thumb_exit (f, -1, NULL_RTX); 9780 9781 return; 9782 } 9783 else 9784 { 9785 if (mask & 0xFF) 9786 fprintf (f, ", "); 9787 9788 asm_fprintf (f, "%r", PC_REGNUM); 9789 } 9790 } 9791 9792 fprintf (f, "}\n"); 9793} 9794 9795void 9796thumb_final_prescan_insn (insn) 9797 rtx insn; 9798{ 9799 if (flag_print_asm_name) 9800 asm_fprintf (asm_out_file, "%@ 0x%04x\n", 9801 INSN_ADDRESSES (INSN_UID (insn))); 9802} 9803 9804int 9805thumb_shiftable_const (val) 9806 unsigned HOST_WIDE_INT val; 9807{ 9808 unsigned HOST_WIDE_INT mask = 0xff; 9809 int i; 9810 9811 if (val == 0) /* XXX */ 9812 return 0; 9813 9814 for (i = 0; i < 25; i++) 9815 if ((val & (mask << i)) == val) 9816 return 1; 9817 9818 return 0; 9819} 9820 9821/* Returns non-zero if the current function contains, 9822 or might contain a far jump. */ 9823 9824int 9825thumb_far_jump_used_p (int in_prologue) 9826{ 9827 rtx insn; 9828 9829 /* This test is only important for leaf functions. */ 9830 /* assert (!leaf_function_p ()); */ 9831 9832 /* If we have already decided that far jumps may be used, 9833 do not bother checking again, and always return true even if 9834 it turns out that they are not being used. Once we have made 9835 the decision that far jumps are present (and that hence the link 9836 register will be pushed onto the stack) we cannot go back on it. */ 9837 if (cfun->machine->far_jump_used) 9838 return 1; 9839 9840 /* If this function is not being called from the prologue/epilogue 9841 generation code then it must be being called from the 9842 INITIAL_ELIMINATION_OFFSET macro. */ 9843 if (!in_prologue) 9844 { 9845 /* In this case we know that we are being asked about the elimination 9846 of the arg pointer register. If that register is not being used, 9847 then there are no arguments on the stack, and we do not have to 9848 worry that a far jump might force the prologue to push the link 9849 register, changing the stack offsets. In this case we can just 9850 return false, since the presence of far jumps in the function will 9851 not affect stack offsets. 9852 9853 If the arg pointer is live (or if it was live, but has now been 9854 eliminated and so set to dead) then we do have to test to see if 9855 the function might contain a far jump. This test can lead to some 9856 false negatives, since before reload is completed, then length of 9857 branch instructions is not known, so gcc defaults to returning their 9858 longest length, which in turn sets the far jump attribute to true. 9859 9860 A false negative will not result in bad code being generated, but it 9861 will result in a needless push and pop of the link register. We 9862 hope that this does not occur too often. */ 9863 if (regs_ever_live [ARG_POINTER_REGNUM]) 9864 cfun->machine->arg_pointer_live = 1; 9865 else if (!cfun->machine->arg_pointer_live) 9866 return 0; 9867 } 9868 9869 /* Check to see if the function contains a branch 9870 insn with the far jump attribute set. */ 9871 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 9872 { 9873 if (GET_CODE (insn) == JUMP_INSN 9874 /* Ignore tablejump patterns. */ 9875 && GET_CODE (PATTERN (insn)) != ADDR_VEC 9876 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC 9877 && get_attr_far_jump (insn) == FAR_JUMP_YES 9878 ) 9879 { 9880 /* Record the fact that we have decied that 9881 the function does use far jumps. */ 9882 cfun->machine->far_jump_used = 1; 9883 return 1; 9884 } 9885 } 9886 9887 return 0; 9888} 9889 9890/* Return non-zero if FUNC must be entered in ARM mode. */ 9891 9892int 9893is_called_in_ARM_mode (func) 9894 tree func; 9895{ 9896 if (TREE_CODE (func) != FUNCTION_DECL) 9897 abort (); 9898 9899 /* Ignore the problem about functions whoes address is taken. */ 9900 if (TARGET_CALLEE_INTERWORKING && TREE_PUBLIC (func)) 9901 return TRUE; 9902 9903#ifdef ARM_PE 9904 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func)) != NULL_TREE; 9905#else 9906 return FALSE; 9907#endif 9908} 9909 9910/* The bits which aren't usefully expanded as rtl. */ 9911 9912const char * 9913thumb_unexpanded_epilogue () 9914{ 9915 int regno; 9916 int live_regs_mask = 0; 9917 int high_regs_pushed = 0; 9918 int leaf_function = leaf_function_p (); 9919 int had_to_push_lr; 9920 rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; 9921 9922 if (return_used_this_function) 9923 return ""; 9924 9925 for (regno = 0; regno <= LAST_LO_REGNUM; regno++) 9926 if (regs_ever_live[regno] && !call_used_regs[regno] 9927 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))) 9928 live_regs_mask |= 1 << regno; 9929 9930 for (regno = 8; regno < 13; regno++) 9931 { 9932 if (regs_ever_live[regno] && !call_used_regs[regno] 9933 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))) 9934 high_regs_pushed++; 9935 } 9936 9937 /* The prolog may have pushed some high registers to use as 9938 work registers. eg the testuite file: 9939 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c 9940 compiles to produce: 9941 push {r4, r5, r6, r7, lr} 9942 mov r7, r9 9943 mov r6, r8 9944 push {r6, r7} 9945 as part of the prolog. We have to undo that pushing here. */ 9946 9947 if (high_regs_pushed) 9948 { 9949 int mask = live_regs_mask; 9950 int next_hi_reg; 9951 int size; 9952 int mode; 9953 9954#ifdef RTX_CODE 9955 /* If we can deduce the registers used from the function's return value. 9956 This is more reliable that examining regs_ever_live[] because that 9957 will be set if the register is ever used in the function, not just if 9958 the register is used to hold a return value. */ 9959 9960 if (current_function_return_rtx != 0) 9961 mode = GET_MODE (current_function_return_rtx); 9962 else 9963#endif 9964 mode = DECL_MODE (DECL_RESULT (current_function_decl)); 9965 9966 size = GET_MODE_SIZE (mode); 9967 9968 /* Unless we are returning a type of size > 12 register r3 is 9969 available. */ 9970 if (size < 13) 9971 mask |= 1 << 3; 9972 9973 if (mask == 0) 9974 /* Oh dear! We have no low registers into which we can pop 9975 high registers! */ 9976 internal_error 9977 ("no low registers available for popping high registers"); 9978 9979 for (next_hi_reg = 8; next_hi_reg < 13; next_hi_reg++) 9980 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg] 9981 && !(TARGET_SINGLE_PIC_BASE && (next_hi_reg == arm_pic_register))) 9982 break; 9983 9984 while (high_regs_pushed) 9985 { 9986 /* Find lo register(s) into which the high register(s) can 9987 be popped. */ 9988 for (regno = 0; regno <= LAST_LO_REGNUM; regno++) 9989 { 9990 if (mask & (1 << regno)) 9991 high_regs_pushed--; 9992 if (high_regs_pushed == 0) 9993 break; 9994 } 9995 9996 mask &= (2 << regno) - 1; /* A noop if regno == 8 */ 9997 9998 /* Pop the values into the low register(s). */ 9999 thumb_pushpop (asm_out_file, mask, 0); 10000 10001 /* Move the value(s) into the high registers. */ 10002 for (regno = 0; regno <= LAST_LO_REGNUM; regno++) 10003 { 10004 if (mask & (1 << regno)) 10005 { 10006 asm_fprintf (asm_out_file, "\tmov\t%r, %r\n", next_hi_reg, 10007 regno); 10008 10009 for (next_hi_reg++; next_hi_reg < 13; next_hi_reg++) 10010 if (regs_ever_live[next_hi_reg] 10011 && !call_used_regs[next_hi_reg] 10012 && !(TARGET_SINGLE_PIC_BASE 10013 && (next_hi_reg == arm_pic_register))) 10014 break; 10015 } 10016 } 10017 } 10018 } 10019 10020 had_to_push_lr = (live_regs_mask || !leaf_function 10021 || thumb_far_jump_used_p (1)); 10022 10023 if (TARGET_BACKTRACE 10024 && ((live_regs_mask & 0xFF) == 0) 10025 && regs_ever_live [LAST_ARG_REGNUM] != 0) 10026 { 10027 /* The stack backtrace structure creation code had to 10028 push R7 in order to get a work register, so we pop 10029 it now. */ 10030 live_regs_mask |= (1 << LAST_LO_REGNUM); 10031 } 10032 10033 if (current_function_pretend_args_size == 0 || TARGET_BACKTRACE) 10034 { 10035 if (had_to_push_lr 10036 && !is_called_in_ARM_mode (current_function_decl) 10037 && !eh_ofs) 10038 live_regs_mask |= 1 << PC_REGNUM; 10039 10040 /* Either no argument registers were pushed or a backtrace 10041 structure was created which includes an adjusted stack 10042 pointer, so just pop everything. */ 10043 if (live_regs_mask) 10044 thumb_pushpop (asm_out_file, live_regs_mask, FALSE); 10045 10046 if (eh_ofs) 10047 thumb_exit (asm_out_file, 2, eh_ofs); 10048 /* We have either just popped the return address into the 10049 PC or it is was kept in LR for the entire function or 10050 it is still on the stack because we do not want to 10051 return by doing a pop {pc}. */ 10052 else if ((live_regs_mask & (1 << PC_REGNUM)) == 0) 10053 thumb_exit (asm_out_file, 10054 (had_to_push_lr 10055 && is_called_in_ARM_mode (current_function_decl)) ? 10056 -1 : LR_REGNUM, NULL_RTX); 10057 } 10058 else 10059 { 10060 /* Pop everything but the return address. */ 10061 live_regs_mask &= ~(1 << PC_REGNUM); 10062 10063 if (live_regs_mask) 10064 thumb_pushpop (asm_out_file, live_regs_mask, FALSE); 10065 10066 if (had_to_push_lr) 10067 /* Get the return address into a temporary register. */ 10068 thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0); 10069 10070 /* Remove the argument registers that were pushed onto the stack. */ 10071 asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", 10072 SP_REGNUM, SP_REGNUM, 10073 current_function_pretend_args_size); 10074 10075 if (eh_ofs) 10076 thumb_exit (asm_out_file, 2, eh_ofs); 10077 else 10078 thumb_exit (asm_out_file, 10079 had_to_push_lr ? LAST_ARG_REGNUM : LR_REGNUM, NULL_RTX); 10080 } 10081 10082 return ""; 10083} 10084 10085/* Functions to save and restore machine-specific function data. */ 10086 10087static void 10088arm_mark_machine_status (p) 10089 struct function * p; 10090{ 10091 machine_function *machine = p->machine; 10092 10093 if (machine) 10094 ggc_mark_rtx (machine->eh_epilogue_sp_ofs); 10095} 10096 10097static void 10098arm_init_machine_status (p) 10099 struct function * p; 10100{ 10101 p->machine = 10102 (machine_function *) xcalloc (1, sizeof (machine_function)); 10103 10104#if ARM_FT_UNKNOWWN != 0 10105 ((machine_function *) p->machine)->func_type = ARM_FT_UNKNOWN; 10106#endif 10107} 10108 10109static void 10110arm_free_machine_status (p) 10111 struct function * p; 10112{ 10113 if (p->machine) 10114 { 10115 free (p->machine); 10116 p->machine = NULL; 10117 } 10118} 10119 10120/* Return an RTX indicating where the return address to the 10121 calling function can be found. */ 10122 10123rtx 10124arm_return_addr (count, frame) 10125 int count; 10126 rtx frame ATTRIBUTE_UNUSED; 10127{ 10128 if (count != 0) 10129 return NULL_RTX; 10130 10131 if (TARGET_APCS_32) 10132 return get_hard_reg_initial_val (Pmode, LR_REGNUM); 10133 else 10134 { 10135 rtx lr = gen_rtx_AND (Pmode, gen_rtx_REG (Pmode, LR_REGNUM), 10136 GEN_INT (RETURN_ADDR_MASK26)); 10137 return get_func_hard_reg_initial_val (cfun, lr); 10138 } 10139} 10140 10141/* Do anything needed before RTL is emitted for each function. */ 10142 10143void 10144arm_init_expanders () 10145{ 10146 /* Arrange to initialize and mark the machine per-function status. */ 10147 init_machine_status = arm_init_machine_status; 10148 mark_machine_status = arm_mark_machine_status; 10149 free_machine_status = arm_free_machine_status; 10150} 10151 10152/* Generate the rest of a function's prologue. */ 10153 10154void 10155thumb_expand_prologue () 10156{ 10157 HOST_WIDE_INT amount = (get_frame_size () 10158 + current_function_outgoing_args_size); 10159 unsigned long func_type; 10160 10161 func_type = arm_current_func_type (); 10162 10163 /* Naked functions don't have prologues. */ 10164 if (IS_NAKED (func_type)) 10165 return; 10166 10167 if (IS_INTERRUPT (func_type)) 10168 { 10169 error ("interrupt Service Routines cannot be coded in Thumb mode"); 10170 return; 10171 } 10172 10173 if (frame_pointer_needed) 10174 emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx)); 10175 10176 if (amount) 10177 { 10178 amount = ROUND_UP (amount); 10179 10180 if (amount < 512) 10181 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 10182 GEN_INT (- amount))); 10183 else 10184 { 10185 int regno; 10186 rtx reg; 10187 10188 /* The stack decrement is too big for an immediate value in a single 10189 insn. In theory we could issue multiple subtracts, but after 10190 three of them it becomes more space efficient to place the full 10191 value in the constant pool and load into a register. (Also the 10192 ARM debugger really likes to see only one stack decrement per 10193 function). So instead we look for a scratch register into which 10194 we can load the decrement, and then we subtract this from the 10195 stack pointer. Unfortunately on the thumb the only available 10196 scratch registers are the argument registers, and we cannot use 10197 these as they may hold arguments to the function. Instead we 10198 attempt to locate a call preserved register which is used by this 10199 function. If we can find one, then we know that it will have 10200 been pushed at the start of the prologue and so we can corrupt 10201 it now. */ 10202 for (regno = LAST_ARG_REGNUM + 1; regno <= LAST_LO_REGNUM; regno++) 10203 if (regs_ever_live[regno] 10204 && !call_used_regs[regno] /* Paranoia */ 10205 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register)) 10206 && !(frame_pointer_needed 10207 && (regno == THUMB_HARD_FRAME_POINTER_REGNUM))) 10208 break; 10209 10210 if (regno > LAST_LO_REGNUM) /* Very unlikely */ 10211 { 10212 rtx spare = gen_rtx (REG, SImode, IP_REGNUM); 10213 10214 /* Choose an arbitary, non-argument low register. */ 10215 reg = gen_rtx (REG, SImode, LAST_LO_REGNUM); 10216 10217 /* Save it by copying it into a high, scratch register. */ 10218 emit_insn (gen_movsi (spare, reg)); 10219 /* Add a USE to stop propagate_one_insn() from barfing. */ 10220 emit_insn (gen_prologue_use (spare)); 10221 10222 /* Decrement the stack. */ 10223 emit_insn (gen_movsi (reg, GEN_INT (- amount))); 10224 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 10225 reg)); 10226 10227 /* Restore the low register's original value. */ 10228 emit_insn (gen_movsi (reg, spare)); 10229 10230 /* Emit a USE of the restored scratch register, so that flow 10231 analysis will not consider the restore redundant. The 10232 register won't be used again in this function and isn't 10233 restored by the epilogue. */ 10234 emit_insn (gen_prologue_use (reg)); 10235 } 10236 else 10237 { 10238 reg = gen_rtx (REG, SImode, regno); 10239 10240 emit_insn (gen_movsi (reg, GEN_INT (- amount))); 10241 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 10242 reg)); 10243 } 10244 } 10245 } 10246 10247 if (current_function_profile || TARGET_NO_SCHED_PRO) 10248 emit_insn (gen_blockage ()); 10249} 10250 10251void 10252thumb_expand_epilogue () 10253{ 10254 HOST_WIDE_INT amount = (get_frame_size () 10255 + current_function_outgoing_args_size); 10256 10257 /* Naked functions don't have prologues. */ 10258 if (IS_NAKED (arm_current_func_type ())) 10259 return; 10260 10261 if (frame_pointer_needed) 10262 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); 10263 else if (amount) 10264 { 10265 amount = ROUND_UP (amount); 10266 10267 if (amount < 512) 10268 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 10269 GEN_INT (amount))); 10270 else 10271 { 10272 /* r3 is always free in the epilogue. */ 10273 rtx reg = gen_rtx (REG, SImode, LAST_ARG_REGNUM); 10274 10275 emit_insn (gen_movsi (reg, GEN_INT (amount))); 10276 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, reg)); 10277 } 10278 } 10279 10280 /* Emit a USE (stack_pointer_rtx), so that 10281 the stack adjustment will not be deleted. */ 10282 emit_insn (gen_prologue_use (stack_pointer_rtx)); 10283 10284 if (current_function_profile || TARGET_NO_SCHED_PRO) 10285 emit_insn (gen_blockage ()); 10286} 10287 10288static void 10289thumb_output_function_prologue (f, size) 10290 FILE * f; 10291 HOST_WIDE_INT size ATTRIBUTE_UNUSED; 10292{ 10293 int live_regs_mask = 0; 10294 int high_regs_pushed = 0; 10295 int regno; 10296 10297 if (IS_NAKED (arm_current_func_type ())) 10298 return; 10299 10300 if (is_called_in_ARM_mode (current_function_decl)) 10301 { 10302 const char * name; 10303 10304 if (GET_CODE (DECL_RTL (current_function_decl)) != MEM) 10305 abort (); 10306 if (GET_CODE (XEXP (DECL_RTL (current_function_decl), 0)) != SYMBOL_REF) 10307 abort (); 10308 name = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); 10309 10310 /* Generate code sequence to switch us into Thumb mode. */ 10311 /* The .code 32 directive has already been emitted by 10312 ASM_DECLARE_FUNCTION_NAME. */ 10313 asm_fprintf (f, "\torr\t%r, %r, #1\n", IP_REGNUM, PC_REGNUM); 10314 asm_fprintf (f, "\tbx\t%r\n", IP_REGNUM); 10315 10316 /* Generate a label, so that the debugger will notice the 10317 change in instruction sets. This label is also used by 10318 the assembler to bypass the ARM code when this function 10319 is called from a Thumb encoded function elsewhere in the 10320 same file. Hence the definition of STUB_NAME here must 10321 agree with the definition in gas/config/tc-arm.c */ 10322 10323#define STUB_NAME ".real_start_of" 10324 10325 asm_fprintf (f, "\t.code\t16\n"); 10326#ifdef ARM_PE 10327 if (arm_dllexport_name_p (name)) 10328 name = arm_strip_name_encoding (name); 10329#endif 10330 asm_fprintf (f, "\t.globl %s%U%s\n", STUB_NAME, name); 10331 asm_fprintf (f, "\t.thumb_func\n"); 10332 asm_fprintf (f, "%s%U%s:\n", STUB_NAME, name); 10333 } 10334 10335 if (current_function_pretend_args_size) 10336 { 10337 if (cfun->machine->uses_anonymous_args) 10338 { 10339 int num_pushes; 10340 10341 asm_fprintf (f, "\tpush\t{"); 10342 10343 num_pushes = NUM_INTS (current_function_pretend_args_size); 10344 10345 for (regno = LAST_ARG_REGNUM + 1 - num_pushes; 10346 regno <= LAST_ARG_REGNUM; 10347 regno++) 10348 asm_fprintf (f, "%r%s", regno, 10349 regno == LAST_ARG_REGNUM ? "" : ", "); 10350 10351 asm_fprintf (f, "}\n"); 10352 } 10353 else 10354 asm_fprintf (f, "\tsub\t%r, %r, #%d\n", 10355 SP_REGNUM, SP_REGNUM, 10356 current_function_pretend_args_size); 10357 } 10358 10359 for (regno = 0; regno <= LAST_LO_REGNUM; regno++) 10360 if (regs_ever_live[regno] && !call_used_regs[regno] 10361 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))) 10362 live_regs_mask |= 1 << regno; 10363 10364 if (live_regs_mask || !leaf_function_p () || thumb_far_jump_used_p (1)) 10365 live_regs_mask |= 1 << LR_REGNUM; 10366 10367 if (TARGET_BACKTRACE) 10368 { 10369 int offset; 10370 int work_register = 0; 10371 int wr; 10372 10373 /* We have been asked to create a stack backtrace structure. 10374 The code looks like this: 10375 10376 0 .align 2 10377 0 func: 10378 0 sub SP, #16 Reserve space for 4 registers. 10379 2 push {R7} Get a work register. 10380 4 add R7, SP, #20 Get the stack pointer before the push. 10381 6 str R7, [SP, #8] Store the stack pointer (before reserving the space). 10382 8 mov R7, PC Get hold of the start of this code plus 12. 10383 10 str R7, [SP, #16] Store it. 10384 12 mov R7, FP Get hold of the current frame pointer. 10385 14 str R7, [SP, #4] Store it. 10386 16 mov R7, LR Get hold of the current return address. 10387 18 str R7, [SP, #12] Store it. 10388 20 add R7, SP, #16 Point at the start of the backtrace structure. 10389 22 mov FP, R7 Put this value into the frame pointer. */ 10390 10391 if ((live_regs_mask & 0xFF) == 0) 10392 { 10393 /* See if the a4 register is free. */ 10394 10395 if (regs_ever_live [LAST_ARG_REGNUM] == 0) 10396 work_register = LAST_ARG_REGNUM; 10397 else /* We must push a register of our own */ 10398 live_regs_mask |= (1 << LAST_LO_REGNUM); 10399 } 10400 10401 if (work_register == 0) 10402 { 10403 /* Select a register from the list that will be pushed to 10404 use as our work register. */ 10405 for (work_register = (LAST_LO_REGNUM + 1); work_register--;) 10406 if ((1 << work_register) & live_regs_mask) 10407 break; 10408 } 10409 10410 asm_fprintf 10411 (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", 10412 SP_REGNUM, SP_REGNUM); 10413 10414 if (live_regs_mask) 10415 thumb_pushpop (f, live_regs_mask, 1); 10416 10417 for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1) 10418 if (wr & live_regs_mask) 10419 offset += 4; 10420 10421 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, 10422 offset + 16 + current_function_pretend_args_size); 10423 10424 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 10425 offset + 4); 10426 10427 /* Make sure that the instruction fetching the PC is in the right place 10428 to calculate "start of backtrace creation code + 12". */ 10429 if (live_regs_mask) 10430 { 10431 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); 10432 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 10433 offset + 12); 10434 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, 10435 ARM_HARD_FRAME_POINTER_REGNUM); 10436 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 10437 offset); 10438 } 10439 else 10440 { 10441 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, 10442 ARM_HARD_FRAME_POINTER_REGNUM); 10443 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 10444 offset); 10445 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, PC_REGNUM); 10446 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 10447 offset + 12); 10448 } 10449 10450 asm_fprintf (f, "\tmov\t%r, %r\n", work_register, LR_REGNUM); 10451 asm_fprintf (f, "\tstr\t%r, [%r, #%d]\n", work_register, SP_REGNUM, 10452 offset + 8); 10453 asm_fprintf (f, "\tadd\t%r, %r, #%d\n", work_register, SP_REGNUM, 10454 offset + 12); 10455 asm_fprintf (f, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n", 10456 ARM_HARD_FRAME_POINTER_REGNUM, work_register); 10457 } 10458 else if (live_regs_mask) 10459 thumb_pushpop (f, live_regs_mask, 1); 10460 10461 for (regno = 8; regno < 13; regno++) 10462 { 10463 if (regs_ever_live[regno] && !call_used_regs[regno] 10464 && !(TARGET_SINGLE_PIC_BASE && (regno == arm_pic_register))) 10465 high_regs_pushed++; 10466 } 10467 10468 if (high_regs_pushed) 10469 { 10470 int pushable_regs = 0; 10471 int mask = live_regs_mask & 0xff; 10472 int next_hi_reg; 10473 10474 for (next_hi_reg = 12; next_hi_reg > LAST_LO_REGNUM; next_hi_reg--) 10475 { 10476 if (regs_ever_live[next_hi_reg] && !call_used_regs[next_hi_reg] 10477 && !(TARGET_SINGLE_PIC_BASE 10478 && (next_hi_reg == arm_pic_register))) 10479 break; 10480 } 10481 10482 pushable_regs = mask; 10483 10484 if (pushable_regs == 0) 10485 { 10486 /* Desperation time -- this probably will never happen. */ 10487 if (regs_ever_live[LAST_ARG_REGNUM] 10488 || !call_used_regs[LAST_ARG_REGNUM]) 10489 asm_fprintf (f, "\tmov\t%r, %r\n", IP_REGNUM, LAST_ARG_REGNUM); 10490 mask = 1 << LAST_ARG_REGNUM; 10491 } 10492 10493 while (high_regs_pushed > 0) 10494 { 10495 for (regno = LAST_LO_REGNUM; regno >= 0; regno--) 10496 { 10497 if (mask & (1 << regno)) 10498 { 10499 asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); 10500 10501 high_regs_pushed--; 10502 10503 if (high_regs_pushed) 10504 for (next_hi_reg--; next_hi_reg > LAST_LO_REGNUM; 10505 next_hi_reg--) 10506 { 10507 if (regs_ever_live[next_hi_reg] 10508 && !call_used_regs[next_hi_reg] 10509 && !(TARGET_SINGLE_PIC_BASE 10510 && (next_hi_reg == arm_pic_register))) 10511 break; 10512 } 10513 else 10514 { 10515 mask &= ~((1 << regno) - 1); 10516 break; 10517 } 10518 } 10519 } 10520 10521 thumb_pushpop (f, mask, 1); 10522 } 10523 10524 if (pushable_regs == 0 10525 && (regs_ever_live[LAST_ARG_REGNUM] 10526 || !call_used_regs[LAST_ARG_REGNUM])) 10527 asm_fprintf (f, "\tmov\t%r, %r\n", LAST_ARG_REGNUM, IP_REGNUM); 10528 } 10529} 10530 10531/* Handle the case of a double word load into a low register from 10532 a computed memory address. The computed address may involve a 10533 register which is overwritten by the load. */ 10534 10535const char * 10536thumb_load_double_from_address (operands) 10537 rtx *operands; 10538{ 10539 rtx addr; 10540 rtx base; 10541 rtx offset; 10542 rtx arg1; 10543 rtx arg2; 10544 10545 if (GET_CODE (operands[0]) != REG) 10546 abort (); 10547 10548 if (GET_CODE (operands[1]) != MEM) 10549 abort (); 10550 10551 /* Get the memory address. */ 10552 addr = XEXP (operands[1], 0); 10553 10554 /* Work out how the memory address is computed. */ 10555 switch (GET_CODE (addr)) 10556 { 10557 case REG: 10558 operands[2] = gen_rtx (MEM, SImode, 10559 plus_constant (XEXP (operands[1], 0), 4)); 10560 10561 if (REGNO (operands[0]) == REGNO (addr)) 10562 { 10563 output_asm_insn ("ldr\t%H0, %2", operands); 10564 output_asm_insn ("ldr\t%0, %1", operands); 10565 } 10566 else 10567 { 10568 output_asm_insn ("ldr\t%0, %1", operands); 10569 output_asm_insn ("ldr\t%H0, %2", operands); 10570 } 10571 break; 10572 10573 case CONST: 10574 /* Compute <address> + 4 for the high order load. */ 10575 operands[2] = gen_rtx (MEM, SImode, 10576 plus_constant (XEXP (operands[1], 0), 4)); 10577 10578 output_asm_insn ("ldr\t%0, %1", operands); 10579 output_asm_insn ("ldr\t%H0, %2", operands); 10580 break; 10581 10582 case PLUS: 10583 arg1 = XEXP (addr, 0); 10584 arg2 = XEXP (addr, 1); 10585 10586 if (CONSTANT_P (arg1)) 10587 base = arg2, offset = arg1; 10588 else 10589 base = arg1, offset = arg2; 10590 10591 if (GET_CODE (base) != REG) 10592 abort (); 10593 10594 /* Catch the case of <address> = <reg> + <reg> */ 10595 if (GET_CODE (offset) == REG) 10596 { 10597 int reg_offset = REGNO (offset); 10598 int reg_base = REGNO (base); 10599 int reg_dest = REGNO (operands[0]); 10600 10601 /* Add the base and offset registers together into the 10602 higher destination register. */ 10603 asm_fprintf (asm_out_file, "\tadd\t%r, %r, %r", 10604 reg_dest + 1, reg_base, reg_offset); 10605 10606 /* Load the lower destination register from the address in 10607 the higher destination register. */ 10608 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #0]", 10609 reg_dest, reg_dest + 1); 10610 10611 /* Load the higher destination register from its own address 10612 plus 4. */ 10613 asm_fprintf (asm_out_file, "\tldr\t%r, [%r, #4]", 10614 reg_dest + 1, reg_dest + 1); 10615 } 10616 else 10617 { 10618 /* Compute <address> + 4 for the high order load. */ 10619 operands[2] = gen_rtx (MEM, SImode, 10620 plus_constant (XEXP (operands[1], 0), 4)); 10621 10622 /* If the computed address is held in the low order register 10623 then load the high order register first, otherwise always 10624 load the low order register first. */ 10625 if (REGNO (operands[0]) == REGNO (base)) 10626 { 10627 output_asm_insn ("ldr\t%H0, %2", operands); 10628 output_asm_insn ("ldr\t%0, %1", operands); 10629 } 10630 else 10631 { 10632 output_asm_insn ("ldr\t%0, %1", operands); 10633 output_asm_insn ("ldr\t%H0, %2", operands); 10634 } 10635 } 10636 break; 10637 10638 case LABEL_REF: 10639 /* With no registers to worry about we can just load the value 10640 directly. */ 10641 operands[2] = gen_rtx (MEM, SImode, 10642 plus_constant (XEXP (operands[1], 0), 4)); 10643 10644 output_asm_insn ("ldr\t%H0, %2", operands); 10645 output_asm_insn ("ldr\t%0, %1", operands); 10646 break; 10647 10648 default: 10649 abort (); 10650 break; 10651 } 10652 10653 return ""; 10654} 10655 10656 10657const char * 10658thumb_output_move_mem_multiple (n, operands) 10659 int n; 10660 rtx * operands; 10661{ 10662 rtx tmp; 10663 10664 switch (n) 10665 { 10666 case 2: 10667 if (REGNO (operands[4]) > REGNO (operands[5])) 10668 { 10669 tmp = operands[4]; 10670 operands[4] = operands[5]; 10671 operands[5] = tmp; 10672 } 10673 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands); 10674 output_asm_insn ("stmia\t%0!, {%4, %5}", operands); 10675 break; 10676 10677 case 3: 10678 if (REGNO (operands[4]) > REGNO (operands[5])) 10679 { 10680 tmp = operands[4]; 10681 operands[4] = operands[5]; 10682 operands[5] = tmp; 10683 } 10684 if (REGNO (operands[5]) > REGNO (operands[6])) 10685 { 10686 tmp = operands[5]; 10687 operands[5] = operands[6]; 10688 operands[6] = tmp; 10689 } 10690 if (REGNO (operands[4]) > REGNO (operands[5])) 10691 { 10692 tmp = operands[4]; 10693 operands[4] = operands[5]; 10694 operands[5] = tmp; 10695 } 10696 10697 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands); 10698 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands); 10699 break; 10700 10701 default: 10702 abort (); 10703 } 10704 10705 return ""; 10706} 10707 10708/* Routines for generating rtl. */ 10709 10710void 10711thumb_expand_movstrqi (operands) 10712 rtx * operands; 10713{ 10714 rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); 10715 rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); 10716 HOST_WIDE_INT len = INTVAL (operands[2]); 10717 HOST_WIDE_INT offset = 0; 10718 10719 while (len >= 12) 10720 { 10721 emit_insn (gen_movmem12b (out, in, out, in)); 10722 len -= 12; 10723 } 10724 10725 if (len >= 8) 10726 { 10727 emit_insn (gen_movmem8b (out, in, out, in)); 10728 len -= 8; 10729 } 10730 10731 if (len >= 4) 10732 { 10733 rtx reg = gen_reg_rtx (SImode); 10734 emit_insn (gen_movsi (reg, gen_rtx (MEM, SImode, in))); 10735 emit_insn (gen_movsi (gen_rtx (MEM, SImode, out), reg)); 10736 len -= 4; 10737 offset += 4; 10738 } 10739 10740 if (len >= 2) 10741 { 10742 rtx reg = gen_reg_rtx (HImode); 10743 emit_insn (gen_movhi (reg, gen_rtx (MEM, HImode, 10744 plus_constant (in, offset)))); 10745 emit_insn (gen_movhi (gen_rtx (MEM, HImode, plus_constant (out, offset)), 10746 reg)); 10747 len -= 2; 10748 offset += 2; 10749 } 10750 10751 if (len) 10752 { 10753 rtx reg = gen_reg_rtx (QImode); 10754 emit_insn (gen_movqi (reg, gen_rtx (MEM, QImode, 10755 plus_constant (in, offset)))); 10756 emit_insn (gen_movqi (gen_rtx (MEM, QImode, plus_constant (out, offset)), 10757 reg)); 10758 } 10759} 10760 10761int 10762thumb_cmp_operand (op, mode) 10763 rtx op; 10764 enum machine_mode mode; 10765{ 10766 return ((GET_CODE (op) == CONST_INT 10767 && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256) 10768 || register_operand (op, mode)); 10769} 10770 10771static const char * 10772thumb_condition_code (x, invert) 10773 rtx x; 10774 int invert; 10775{ 10776 static const char * const conds[] = 10777 { 10778 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", 10779 "hi", "ls", "ge", "lt", "gt", "le" 10780 }; 10781 int val; 10782 10783 switch (GET_CODE (x)) 10784 { 10785 case EQ: val = 0; break; 10786 case NE: val = 1; break; 10787 case GEU: val = 2; break; 10788 case LTU: val = 3; break; 10789 case GTU: val = 8; break; 10790 case LEU: val = 9; break; 10791 case GE: val = 10; break; 10792 case LT: val = 11; break; 10793 case GT: val = 12; break; 10794 case LE: val = 13; break; 10795 default: 10796 abort (); 10797 } 10798 10799 return conds[val ^ invert]; 10800} 10801 10802/* Handle storing a half-word to memory during reload. */ 10803 10804void 10805thumb_reload_out_hi (operands) 10806 rtx * operands; 10807{ 10808 emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); 10809} 10810 10811/* Handle storing a half-word to memory during reload. */ 10812 10813void 10814thumb_reload_in_hi (operands) 10815 rtx * operands ATTRIBUTE_UNUSED; 10816{ 10817 abort (); 10818} 10819 10820/* Return the length of a function name prefix 10821 that starts with the character 'c'. */ 10822 10823static int 10824arm_get_strip_length (char c) 10825{ 10826 switch (c) 10827 { 10828 ARM_NAME_ENCODING_LENGTHS 10829 default: return 0; 10830 } 10831} 10832 10833/* Return a pointer to a function's name with any 10834 and all prefix encodings stripped from it. */ 10835 10836const char * 10837arm_strip_name_encoding (const char * name) 10838{ 10839 int skip; 10840 10841 while ((skip = arm_get_strip_length (* name))) 10842 name += skip; 10843 10844 return name; 10845} 10846 10847#ifdef AOF_ASSEMBLER 10848/* Special functions only needed when producing AOF syntax assembler. */ 10849 10850rtx aof_pic_label = NULL_RTX; 10851struct pic_chain 10852{ 10853 struct pic_chain * next; 10854 const char * symname; 10855}; 10856 10857static struct pic_chain * aof_pic_chain = NULL; 10858 10859rtx 10860aof_pic_entry (x) 10861 rtx x; 10862{ 10863 struct pic_chain ** chainp; 10864 int offset; 10865 10866 if (aof_pic_label == NULL_RTX) 10867 { 10868 /* We mark this here and not in arm_add_gc_roots() to avoid 10869 polluting even more code with ifdefs, and because it never 10870 contains anything useful until we assign to it here. */ 10871 ggc_add_rtx_root (&aof_pic_label, 1); 10872 aof_pic_label = gen_rtx_SYMBOL_REF (Pmode, "x$adcons"); 10873 } 10874 10875 for (offset = 0, chainp = &aof_pic_chain; *chainp; 10876 offset += 4, chainp = &(*chainp)->next) 10877 if ((*chainp)->symname == XSTR (x, 0)) 10878 return plus_constant (aof_pic_label, offset); 10879 10880 *chainp = (struct pic_chain *) xmalloc (sizeof (struct pic_chain)); 10881 (*chainp)->next = NULL; 10882 (*chainp)->symname = XSTR (x, 0); 10883 return plus_constant (aof_pic_label, offset); 10884} 10885 10886void 10887aof_dump_pic_table (f) 10888 FILE * f; 10889{ 10890 struct pic_chain * chain; 10891 10892 if (aof_pic_chain == NULL) 10893 return; 10894 10895 asm_fprintf (f, "\tAREA |%r$$adcons|, BASED %r\n", 10896 PIC_OFFSET_TABLE_REGNUM, 10897 PIC_OFFSET_TABLE_REGNUM); 10898 fputs ("|x$adcons|\n", f); 10899 10900 for (chain = aof_pic_chain; chain; chain = chain->next) 10901 { 10902 fputs ("\tDCD\t", f); 10903 assemble_name (f, chain->symname); 10904 fputs ("\n", f); 10905 } 10906} 10907 10908int arm_text_section_count = 1; 10909 10910char * 10911aof_text_section () 10912{ 10913 static char buf[100]; 10914 sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY", 10915 arm_text_section_count++); 10916 if (flag_pic) 10917 strcat (buf, ", PIC, REENTRANT"); 10918 return buf; 10919} 10920 10921static int arm_data_section_count = 1; 10922 10923char * 10924aof_data_section () 10925{ 10926 static char buf[100]; 10927 sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++); 10928 return buf; 10929} 10930 10931/* The AOF assembler is religiously strict about declarations of 10932 imported and exported symbols, so that it is impossible to declare 10933 a function as imported near the beginning of the file, and then to 10934 export it later on. It is, however, possible to delay the decision 10935 until all the functions in the file have been compiled. To get 10936 around this, we maintain a list of the imports and exports, and 10937 delete from it any that are subsequently defined. At the end of 10938 compilation we spit the remainder of the list out before the END 10939 directive. */ 10940 10941struct import 10942{ 10943 struct import * next; 10944 const char * name; 10945}; 10946 10947static struct import * imports_list = NULL; 10948 10949void 10950aof_add_import (name) 10951 const char * name; 10952{ 10953 struct import * new; 10954 10955 for (new = imports_list; new; new = new->next) 10956 if (new->name == name) 10957 return; 10958 10959 new = (struct import *) xmalloc (sizeof (struct import)); 10960 new->next = imports_list; 10961 imports_list = new; 10962 new->name = name; 10963} 10964 10965void 10966aof_delete_import (name) 10967 const char * name; 10968{ 10969 struct import ** old; 10970 10971 for (old = &imports_list; *old; old = & (*old)->next) 10972 { 10973 if ((*old)->name == name) 10974 { 10975 *old = (*old)->next; 10976 return; 10977 } 10978 } 10979} 10980 10981int arm_main_function = 0; 10982 10983void 10984aof_dump_imports (f) 10985 FILE * f; 10986{ 10987 /* The AOF assembler needs this to cause the startup code to be extracted 10988 from the library. Brining in __main causes the whole thing to work 10989 automagically. */ 10990 if (arm_main_function) 10991 { 10992 text_section (); 10993 fputs ("\tIMPORT __main\n", f); 10994 fputs ("\tDCD __main\n", f); 10995 } 10996 10997 /* Now dump the remaining imports. */ 10998 while (imports_list) 10999 { 11000 fprintf (f, "\tIMPORT\t"); 11001 assemble_name (f, imports_list->name); 11002 fputc ('\n', f); 11003 imports_list = imports_list->next; 11004 } 11005} 11006#endif /* AOF_ASSEMBLER */ 11007 11008#ifdef OBJECT_FORMAT_ELF 11009/* Switch to an arbitrary section NAME with attributes as specified 11010 by FLAGS. ALIGN specifies any known alignment requirements for 11011 the section; 0 if the default should be used. 11012 11013 Differs from the default elf version only in the prefix character 11014 used before the section type. */ 11015 11016static void 11017arm_elf_asm_named_section (name, flags) 11018 const char *name; 11019 unsigned int flags; 11020{ 11021 char flagchars[8], *f = flagchars; 11022 const char *type; 11023 11024 if (!(flags & SECTION_DEBUG)) 11025 *f++ = 'a'; 11026 if (flags & SECTION_WRITE) 11027 *f++ = 'w'; 11028 if (flags & SECTION_CODE) 11029 *f++ = 'x'; 11030 if (flags & SECTION_SMALL) 11031 *f++ = 's'; 11032 if (flags & SECTION_MERGE) 11033 *f++ = 'M'; 11034 if (flags & SECTION_STRINGS) 11035 *f++ = 'S'; 11036 *f = '\0'; 11037 11038 if (flags & SECTION_BSS) 11039 type = "nobits"; 11040 else 11041 type = "progbits"; 11042 11043 if (flags & SECTION_ENTSIZE) 11044 fprintf (asm_out_file, "\t.section\t%s,\"%s\",%%%s,%d\n", 11045 name, flagchars, type, flags & SECTION_ENTSIZE); 11046 else 11047 fprintf (asm_out_file, "\t.section\t%s,\"%s\",%%%s\n", 11048 name, flagchars, type); 11049} 11050#endif 11051