ppc.h revision 218822
160484Sobrien/* ppc.h -- Header file for PowerPC opcode table 2218822Sdim Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 3218822Sdim 2007 Free Software Foundation, Inc. 460484Sobrien Written by Ian Lance Taylor, Cygnus Support 560484Sobrien 660484SobrienThis file is part of GDB, GAS, and the GNU binutils. 760484Sobrien 860484SobrienGDB, GAS, and the GNU binutils are free software; you can redistribute 960484Sobrienthem and/or modify them under the terms of the GNU General Public 1060484SobrienLicense as published by the Free Software Foundation; either version 1160484Sobrien1, or (at your option) any later version. 1260484Sobrien 1360484SobrienGDB, GAS, and the GNU binutils are distributed in the hope that they 1460484Sobrienwill be useful, but WITHOUT ANY WARRANTY; without even the implied 1560484Sobrienwarranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 1660484Sobrienthe GNU General Public License for more details. 1760484Sobrien 1860484SobrienYou should have received a copy of the GNU General Public License 1960484Sobrienalong with this file; see the file COPYING. If not, write to the Free 20218822SdimSoftware Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 2160484Sobrien 2260484Sobrien#ifndef PPC_H 2360484Sobrien#define PPC_H 2460484Sobrien 2560484Sobrien/* The opcode table is an array of struct powerpc_opcode. */ 2660484Sobrien 2760484Sobrienstruct powerpc_opcode 2860484Sobrien{ 2960484Sobrien /* The opcode name. */ 3060484Sobrien const char *name; 3160484Sobrien 3260484Sobrien /* The opcode itself. Those bits which will be filled in with 3360484Sobrien operands are zeroes. */ 3460484Sobrien unsigned long opcode; 3560484Sobrien 3660484Sobrien /* The opcode mask. This is used by the disassembler. This is a 3760484Sobrien mask containing ones indicating those bits which must match the 3860484Sobrien opcode field, and zeroes indicating those bits which need not 3960484Sobrien match (and are presumably filled in by operands). */ 4060484Sobrien unsigned long mask; 4160484Sobrien 4260484Sobrien /* One bit flags for the opcode. These are used to indicate which 4360484Sobrien specific processors support the instructions. The defined values 4460484Sobrien are listed below. */ 4560484Sobrien unsigned long flags; 4660484Sobrien 4760484Sobrien /* An array of operand codes. Each code is an index into the 4860484Sobrien operand table. They appear in the order which the operands must 4960484Sobrien appear in assembly code, and are terminated by a zero. */ 5060484Sobrien unsigned char operands[8]; 5160484Sobrien}; 5260484Sobrien 5360484Sobrien/* The table itself is sorted by major opcode number, and is otherwise 5460484Sobrien in the order in which the disassembler should consider 5560484Sobrien instructions. */ 5660484Sobrienextern const struct powerpc_opcode powerpc_opcodes[]; 5760484Sobrienextern const int powerpc_num_opcodes; 5860484Sobrien 5960484Sobrien/* Values defined for the flags field of a struct powerpc_opcode. */ 6060484Sobrien 6160484Sobrien/* Opcode is defined for the PowerPC architecture. */ 62130561Sobrien#define PPC_OPCODE_PPC 1 6360484Sobrien 6460484Sobrien/* Opcode is defined for the POWER (RS/6000) architecture. */ 65130561Sobrien#define PPC_OPCODE_POWER 2 6660484Sobrien 6760484Sobrien/* Opcode is defined for the POWER2 (Rios 2) architecture. */ 68130561Sobrien#define PPC_OPCODE_POWER2 4 6960484Sobrien 7060484Sobrien/* Opcode is only defined on 32 bit architectures. */ 71130561Sobrien#define PPC_OPCODE_32 8 7260484Sobrien 7360484Sobrien/* Opcode is only defined on 64 bit architectures. */ 74130561Sobrien#define PPC_OPCODE_64 0x10 7560484Sobrien 7660484Sobrien/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 7760484Sobrien is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 7860484Sobrien but it also supports many additional POWER instructions. */ 79130561Sobrien#define PPC_OPCODE_601 0x20 8060484Sobrien 8160484Sobrien/* Opcode is supported in both the Power and PowerPC architectures 8260484Sobrien (ie, compiler's -mcpu=common or assembler's -mcom). */ 83130561Sobrien#define PPC_OPCODE_COMMON 0x40 8460484Sobrien 8560484Sobrien/* Opcode is supported for any Power or PowerPC platform (this is 8660484Sobrien for the assembler's -many option, and it eliminates duplicates). */ 87130561Sobrien#define PPC_OPCODE_ANY 0x80 8860484Sobrien 8960484Sobrien/* Opcode is supported as part of the 64-bit bridge. */ 90130561Sobrien#define PPC_OPCODE_64_BRIDGE 0x100 9160484Sobrien 9277298Sobrien/* Opcode is supported by Altivec Vector Unit */ 93130561Sobrien#define PPC_OPCODE_ALTIVEC 0x200 9477298Sobrien 9589857Sobrien/* Opcode is supported by PowerPC 403 processor. */ 96130561Sobrien#define PPC_OPCODE_403 0x400 9789857Sobrien 9889857Sobrien/* Opcode is supported by PowerPC BookE processor. */ 99130561Sobrien#define PPC_OPCODE_BOOKE 0x800 10089857Sobrien 10189857Sobrien/* Opcode is only supported by 64-bit PowerPC BookE processor. */ 102130561Sobrien#define PPC_OPCODE_BOOKE64 0x1000 10389857Sobrien 104130561Sobrien/* Opcode is supported by PowerPC 440 processor. */ 105130561Sobrien#define PPC_OPCODE_440 0x2000 106130561Sobrien 10792828Sobrien/* Opcode is only supported by Power4 architecture. */ 108130561Sobrien#define PPC_OPCODE_POWER4 0x4000 10992828Sobrien 11092828Sobrien/* Opcode isn't supported by Power4 architecture. */ 111130561Sobrien#define PPC_OPCODE_NOPOWER4 0x8000 11292828Sobrien 113130561Sobrien/* Opcode is only supported by POWERPC Classic architecture. */ 114130561Sobrien#define PPC_OPCODE_CLASSIC 0x10000 115130561Sobrien 116130561Sobrien/* Opcode is only supported by e500x2 Core. */ 117130561Sobrien#define PPC_OPCODE_SPE 0x20000 118130561Sobrien 119130561Sobrien/* Opcode is supported by e500x2 Integer select APU. */ 120130561Sobrien#define PPC_OPCODE_ISEL 0x40000 121130561Sobrien 122130561Sobrien/* Opcode is an e500 SPE floating point instruction. */ 123130561Sobrien#define PPC_OPCODE_EFS 0x80000 124130561Sobrien 125130561Sobrien/* Opcode is supported by branch locking APU. */ 126130561Sobrien#define PPC_OPCODE_BRLOCK 0x100000 127130561Sobrien 128130561Sobrien/* Opcode is supported by performance monitor APU. */ 129130561Sobrien#define PPC_OPCODE_PMR 0x200000 130130561Sobrien 131130561Sobrien/* Opcode is supported by cache locking APU. */ 132130561Sobrien#define PPC_OPCODE_CACHELCK 0x400000 133130561Sobrien 134130561Sobrien/* Opcode is supported by machine check APU. */ 135130561Sobrien#define PPC_OPCODE_RFMCI 0x800000 136130561Sobrien 137218822Sdim/* Opcode is only supported by Power5 architecture. */ 138218822Sdim#define PPC_OPCODE_POWER5 0x1000000 139218822Sdim 140218822Sdim/* Opcode is supported by PowerPC e300 family. */ 141218822Sdim#define PPC_OPCODE_E300 0x2000000 142218822Sdim 143218822Sdim/* Opcode is only supported by Power6 architecture. */ 144218822Sdim#define PPC_OPCODE_POWER6 0x4000000 145218822Sdim 146218822Sdim/* Opcode is only supported by PowerPC Cell family. */ 147218822Sdim#define PPC_OPCODE_CELL 0x8000000 148218822Sdim 14960484Sobrien/* A macro to extract the major opcode from an instruction. */ 15060484Sobrien#define PPC_OP(i) (((i) >> 26) & 0x3f) 15160484Sobrien 15260484Sobrien/* The operands table is an array of struct powerpc_operand. */ 15360484Sobrien 15460484Sobrienstruct powerpc_operand 15560484Sobrien{ 156218822Sdim /* A bitmask of bits in the operand. */ 157218822Sdim unsigned int bitm; 15860484Sobrien 159218822Sdim /* How far the operand is left shifted in the instruction. 160218822Sdim -1 to indicate that BITM and SHIFT cannot be used to determine 161218822Sdim where the operand goes in the insn. */ 16260484Sobrien int shift; 16360484Sobrien 16460484Sobrien /* Insertion function. This is used by the assembler. To insert an 16560484Sobrien operand value into an instruction, check this field. 16660484Sobrien 16760484Sobrien If it is NULL, execute 168218822Sdim i |= (op & o->bitm) << o->shift; 16960484Sobrien (i is the instruction which we are filling in, o is a pointer to 170218822Sdim this structure, and op is the operand value). 17160484Sobrien 17260484Sobrien If this field is not NULL, then simply call it with the 17360484Sobrien instruction and the operand value. It will return the new value 17460484Sobrien of the instruction. If the ERRMSG argument is not NULL, then if 17560484Sobrien the operand value is illegal, *ERRMSG will be set to a warning 17660484Sobrien string (the operand will be inserted in any case). If the 17760484Sobrien operand value is legal, *ERRMSG will be unchanged (most operands 17860484Sobrien can accept any value). */ 179130561Sobrien unsigned long (*insert) 180130561Sobrien (unsigned long instruction, long op, int dialect, const char **errmsg); 18160484Sobrien 18260484Sobrien /* Extraction function. This is used by the disassembler. To 18360484Sobrien extract this operand type from an instruction, check this field. 18460484Sobrien 18560484Sobrien If it is NULL, compute 186218822Sdim op = (i >> o->shift) & o->bitm; 187218822Sdim if ((o->flags & PPC_OPERAND_SIGNED) != 0) 188218822Sdim sign_extend (op); 18960484Sobrien (i is the instruction, o is a pointer to this structure, and op 190218822Sdim is the result). 19160484Sobrien 19260484Sobrien If this field is not NULL, then simply call it with the 19360484Sobrien instruction value. It will return the value of the operand. If 19460484Sobrien the INVALID argument is not NULL, *INVALID will be set to 19560484Sobrien non-zero if this operand type can not actually be extracted from 19660484Sobrien this operand (i.e., the instruction does not match). If the 19760484Sobrien operand is valid, *INVALID will not be changed. */ 198130561Sobrien long (*extract) (unsigned long instruction, int dialect, int *invalid); 19960484Sobrien 20060484Sobrien /* One bit syntax flags. */ 20160484Sobrien unsigned long flags; 20260484Sobrien}; 20360484Sobrien 20460484Sobrien/* Elements in the table are retrieved by indexing with values from 20560484Sobrien the operands field of the powerpc_opcodes table. */ 20660484Sobrien 20760484Sobrienextern const struct powerpc_operand powerpc_operands[]; 208218822Sdimextern const unsigned int num_powerpc_operands; 20960484Sobrien 21060484Sobrien/* Values defined for the flags field of a struct powerpc_operand. */ 21160484Sobrien 21260484Sobrien/* This operand takes signed values. */ 213218822Sdim#define PPC_OPERAND_SIGNED (0x1) 21460484Sobrien 21560484Sobrien/* This operand takes signed values, but also accepts a full positive 21660484Sobrien range of values when running in 32 bit mode. That is, if bits is 21760484Sobrien 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 21860484Sobrien this flag is ignored. */ 219218822Sdim#define PPC_OPERAND_SIGNOPT (0x2) 22060484Sobrien 22160484Sobrien/* This operand does not actually exist in the assembler input. This 22260484Sobrien is used to support extended mnemonics such as mr, for which two 22360484Sobrien operands fields are identical. The assembler should call the 22460484Sobrien insert function with any op value. The disassembler should call 22560484Sobrien the extract function, ignore the return value, and check the value 22660484Sobrien placed in the valid argument. */ 227218822Sdim#define PPC_OPERAND_FAKE (0x4) 22860484Sobrien 22960484Sobrien/* The next operand should be wrapped in parentheses rather than 23060484Sobrien separated from this one by a comma. This is used for the load and 23160484Sobrien store instructions which want their operands to look like 23260484Sobrien reg,displacement(reg) 23360484Sobrien */ 234218822Sdim#define PPC_OPERAND_PARENS (0x8) 23560484Sobrien 23660484Sobrien/* This operand may use the symbolic names for the CR fields, which 23760484Sobrien are 23860484Sobrien lt 0 gt 1 eq 2 so 3 un 3 23960484Sobrien cr0 0 cr1 1 cr2 2 cr3 3 24060484Sobrien cr4 4 cr5 5 cr6 6 cr7 7 24160484Sobrien These may be combined arithmetically, as in cr2*4+gt. These are 24260484Sobrien only supported on the PowerPC, not the POWER. */ 243218822Sdim#define PPC_OPERAND_CR (0x10) 24460484Sobrien 24560484Sobrien/* This operand names a register. The disassembler uses this to print 24660484Sobrien register names with a leading 'r'. */ 247218822Sdim#define PPC_OPERAND_GPR (0x20) 24860484Sobrien 249130561Sobrien/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ 250218822Sdim#define PPC_OPERAND_GPR_0 (0x40) 251130561Sobrien 25260484Sobrien/* This operand names a floating point register. The disassembler 25360484Sobrien prints these with a leading 'f'. */ 254218822Sdim#define PPC_OPERAND_FPR (0x80) 25560484Sobrien 25660484Sobrien/* This operand is a relative branch displacement. The disassembler 25760484Sobrien prints these symbolically if possible. */ 258218822Sdim#define PPC_OPERAND_RELATIVE (0x100) 25960484Sobrien 26060484Sobrien/* This operand is an absolute branch address. The disassembler 26160484Sobrien prints these symbolically if possible. */ 262218822Sdim#define PPC_OPERAND_ABSOLUTE (0x200) 26360484Sobrien 26460484Sobrien/* This operand is optional, and is zero if omitted. This is used for 265218822Sdim example, in the optional BF field in the comparison instructions. The 26660484Sobrien assembler must count the number of operands remaining on the line, 26760484Sobrien and the number of operands remaining for the opcode, and decide 26860484Sobrien whether this operand is present or not. The disassembler should 26960484Sobrien print this operand out only if it is not zero. */ 270218822Sdim#define PPC_OPERAND_OPTIONAL (0x400) 27160484Sobrien 27260484Sobrien/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 27360484Sobrien is omitted, then for the next operand use this operand value plus 27460484Sobrien 1, ignoring the next operand field for the opcode. This wretched 27560484Sobrien hack is needed because the Power rotate instructions can take 27660484Sobrien either 4 or 5 operands. The disassembler should print this operand 27760484Sobrien out regardless of the PPC_OPERAND_OPTIONAL field. */ 278218822Sdim#define PPC_OPERAND_NEXT (0x800) 27960484Sobrien 28060484Sobrien/* This operand should be regarded as a negative number for the 28160484Sobrien purposes of overflow checking (i.e., the normal most negative 28260484Sobrien number is disallowed and one more than the normal most positive 28360484Sobrien number is allowed). This flag will only be set for a signed 28460484Sobrien operand. */ 285218822Sdim#define PPC_OPERAND_NEGATIVE (0x1000) 28677298Sobrien 28777298Sobrien/* This operand names a vector unit register. The disassembler 28877298Sobrien prints these with a leading 'v'. */ 289218822Sdim#define PPC_OPERAND_VR (0x2000) 29077298Sobrien 29189857Sobrien/* This operand is for the DS field in a DS form instruction. */ 292218822Sdim#define PPC_OPERAND_DS (0x4000) 293130561Sobrien 294130561Sobrien/* This operand is for the DQ field in a DQ form instruction. */ 295218822Sdim#define PPC_OPERAND_DQ (0x8000) 296218822Sdim 297218822Sdim/* Valid range of operand is 0..n rather than 0..n-1. */ 298218822Sdim#define PPC_OPERAND_PLUS1 (0x10000) 29960484Sobrien 30060484Sobrien/* The POWER and PowerPC assemblers use a few macros. We keep them 30160484Sobrien with the operands table for simplicity. The macro table is an 30260484Sobrien array of struct powerpc_macro. */ 30360484Sobrien 30460484Sobrienstruct powerpc_macro 30560484Sobrien{ 30660484Sobrien /* The macro name. */ 30760484Sobrien const char *name; 30860484Sobrien 30960484Sobrien /* The number of operands the macro takes. */ 31060484Sobrien unsigned int operands; 31160484Sobrien 31260484Sobrien /* One bit flags for the opcode. These are used to indicate which 31360484Sobrien specific processors support the instructions. The values are the 31460484Sobrien same as those for the struct powerpc_opcode flags field. */ 31560484Sobrien unsigned long flags; 31660484Sobrien 31760484Sobrien /* A format string to turn the macro into a normal instruction. 31860484Sobrien Each %N in the string is replaced with operand number N (zero 31960484Sobrien based). */ 32060484Sobrien const char *format; 32160484Sobrien}; 32260484Sobrien 32360484Sobrienextern const struct powerpc_macro powerpc_macros[]; 32460484Sobrienextern const int powerpc_num_macros; 32560484Sobrien 32660484Sobrien#endif /* PPC_H */ 327