1/* 2 * Copyright 2013, winocm. <winocm@icloud.com> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * Redistributions of source code must retain the above copyright notice, this 9 * list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright notice, this 12 * list of conditions and the following disclaimer in the documentation and/or 13 * other materials provided with the distribution. 14 * 15 * If you are going to use this software in any form that does not involve 16 * releasing the source to this project or improving it, let me know beforehand. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 22 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29#ifndef _PEXPERT_ARM_SUN4I_H_ 30#define _PEXPERT_ARM_SUN4I_H_ 31 32#define readl(a) (*(volatile unsigned int *)(a)) 33#define writel(v, a) (*(volatile unsigned int *)(a) = (v)) 34#define readw(a) (*(volatile unsigned short *)(a)) 35#define writew(v, a) (*(volatile unsigned short *)(a) = (v)) 36 37#define UART 0 38#define TX_READY (readl(UART_LSR(UART)) & UART_LSR_TEMT) 39#define UART_BASE 0x01C28000 40/* receive buffer register */ 41#define UART_RBR(n) (uart_base + (n)*0x400 + 0x0) 42/* transmit holding register */ 43#define UART_THR(n) (uart_base + (n)*0x400 + 0x0) 44/* divisor latch low register */ 45#define UART_DLL(n) (uart_base + (n)*0x400 + 0x0) 46/* divisor latch high register */ 47#define UART_DLH(n) (uart_base + (n)*0x400 + 0x4) 48/* interrupt enable reigster */ 49#define UART_IER(n) (uart_base + (n)*0x400 + 0x4) 50/* interrupt identity register */ 51#define UART_IIR(n) (uart_base + (n)*0x400 + 0x8) 52/* fifo control register */ 53#define UART_FCR(n) (uart_base + (n)*0x400 + 0x8) 54/* line control register */ 55#define UART_LCR(n) (uart_base + (n)*0x400 + 0xc) 56#define UART_LCR_DLAB (0x1 << 7) 57/* line status register */ 58#define UART_LSR(n) (uart_base + (n)*0x400 + 0x14) 59#define UART_LSR_TEMT (0x1 << 6) 60/* receive buffer register */ 61#define UART_RBR(n) (uart_base + (n)*0x400 + 0x0) 62/* transmit holding register */ 63#define UART_THR(n) (uart_base + (n)*0x400 + 0x0) 64/* divisor latch low register */ 65#define UART_DLL(n) (uart_base + (n)*0x400 + 0x0) 66#define BAUD_115200 (0xd) /* 24 * 1000 * 1000 / 16 / 115200 = 13 */ 67#define NO_PARITY (0) 68#define ONE_STOP_BIT (0) 69#define DAT_LEN_8_BITS (3) 70#define LC_8_N_1 (NO_PARITY << 3 | ONE_STOP_BIT << 2 | DAT_LEN_8_BITS) 71 72#endif /* !_PEXPERT_ARM_SUN4I_H_ */ 73