1/*
2 * Samsung S5L8930X support
3 */
4
5#ifndef _PEXPERT_S5L8930X_H_
6#define _PEXPERT_S5L8930X_H_
7
8#if defined(BOARD_CONFIG_S5L8930X)
9#define UART0_BASE          0x82500000
10#define GPIO_BASE           0xBFA00000
11#define FRAMEBUFFER_BASE    0x5F700000
12#define CLOCK_GATE_BASE     0xBF101000
13#define TIMER_BASE          0xBF102000
14#elif defined(BOARD_CONFIG_S5L8920X) || defined(BOARD_CONFIG_S5L8922X)
15#define UART0_BASE          0x82500000
16#define GPIO_BASE           0x83000000
17#define FRAMEBUFFER_BASE    0x4FD00000
18#define CLOCK_GATE_BASE     0xBF100000
19#define TIMER_BASE	    0xBF100000
20#endif
21
22#define TIMER0_BASE			TIMER_BASE + 0x0
23
24#define TIMER_IRQ_ENABLE	(1 << 0)
25#define TIMER_EXPIRED		(1 << 1)
26
27#ifdef BOARD_CONFIG_S5L8930X
28#define TIMER0_CLOCK_LOW	0x00
29#define TIMER0_CLOCK_HIGH	0x04
30#define TIMER0_VAL			0x08
31#define TIMER0_CTRL			0x10
32#else
33#define TIMER0_CLOCK_LOW	0x200
34#define TIMER0_CLOCK_HIGH	0x204
35#define TIMER0_VAL			0x208
36#define TIMER0_CTRL			0x220
37#endif
38
39#define CLK_REG_OFF         0x10
40
41#define VIC_START           0xBF200000
42#define VIC_REGISTER_SIZE   0x10000
43#define VIC(x)              (VIC_START + (x * VIC_REGISTER_SIZE))
44
45#define VICIRQSTATUS 		0x000
46#define VICRAWINTR 			0x8
47#define VICINTSELECT 		0xC
48#define VICINTENABLE 		0x10
49#define VICINTENCLEAR 		0x14
50#define VICSWPRIORITYMASK	0x24
51#define VICVECTADDRS 		0x100
52#define VICADDRESS 			0xF00
53
54#define CLOCK_HZ            24000000
55
56#define IRQ_TIMER0          300
57
58#define UART_CLOCKGATE      		0x30
59#define UART_CLOCK_SELECTION_MASK 	(0x3 << 10)
60#define UART_CLOCK_SELECTION_SHIFT 	10
61#define UART_DIVVAL_MASK 			0x0000FFFF
62#define UART_SAMPLERATE_MASK 		0x00030000
63#define UART_SAMPLERATE_SHIFT 		16
64#define UART_UCON_RXMODE_SHIFT 		0
65#define UART_UCON_TXMODE_SHIFT 		2
66#define UART_8BITS 					3
67#define UART_FIFO_RESET_TX 			4
68#define UART_FIFO_RESET_RX 			2
69#define UART_FIFO_ENABLE 			1
70
71#define UART_UCON_MODE_IRQORPOLL 	1
72
73#define ULCON      0x0000 /* Line Control             */
74#define UCON       0x0004 /* Control                  */
75#define UFCON      0x0008 /* FIFO Control             */
76#define UMCON      0x000C /* Modem Control            */
77#define UTRSTAT    0x0010 /* Tx/Rx Status             */
78#define UERSTAT    0x0014 /* UART Error Status        */
79#define UFSTAT     0x0018 /* FIFO Status              */
80#define UMSTAT     0x001C /* Modem Status             */
81#define UTXH       0x0020 /* Transmit Buffer          */
82#define URXH       0x0024 /* Receive Buffer           */
83#define UBRDIV     0x0028 /* Baud Rate Divisor        */
84#define UFRACVAL   0x002C /* Divisor Fractional Value */
85#define UINTP      0x0030 /* Interrupt Pending        */
86#define UINTSP     0x0034 /* Interrupt Source Pending */
87#define UINTM      0x0038 /* Interrupt Mask           */
88
89#define UART_UFSTAT_TXFIFO_FULL			(0x1 << 9)
90#define UART_UFSTAT_RXFIFO_FULL			(0x1 << 8)
91#define UART_UTRSTAT_TRANSMITTEREMPTY 	0x4
92#define UART_UMSTAT_CTS 				0x1
93
94#endif /* !_PEXPERT_S5L8930X_H_ */
95