1/* 2 * Copyright (c) 2008, Google Inc. 3 * All rights reserved. 4 * 5 * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Google, Inc. nor the names of its contributors 17 * may be used to endorse or promote products derived from this 18 * software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 23 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 24 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 27 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34#ifndef _PEXPERT_APQ8060_H_ 35#define _PEXPERT_APQ8060_H_ 36 37#define MSM_TMR_BASE 0x02000000 38#define MSM_GPT_BASE (0x04) 39#define MSM_DGT_BASE (0x24) 40 41#define GPT_REG(off) (MSM_GPT_BASE + (off)) 42#define DGT_REG(off) (MSM_DGT_BASE + (off)) 43 44#define GPT_MATCH_VAL GPT_REG(0x0000) 45#define GPT_COUNT_VAL GPT_REG(0x0004) 46#define GPT_ENABLE GPT_REG(0x0008) 47#define GPT_CLEAR GPT_REG(0x000C) 48 49#define DGT_MATCH_VAL DGT_REG(0x0000) 50#define DGT_COUNT_VAL DGT_REG(0x0004) 51#define DGT_ENABLE DGT_REG(0x0008) 52#define DGT_CLEAR DGT_REG(0x000C) 53#define DGT_CLK_CTL DGT_REG(0x0010) 54 55#define MSM_GIC_DIST_BASE 0x02080000 56#define MSM_GIC_CPU_BASE 0x02081000 57 58#define GIC_CPU_REG(off) ((off)) 59#define GIC_DIST_REG(off) ((off)) 60 61#define GIC_CPU_CTRL GIC_CPU_REG(0x00) 62#define GIC_CPU_PRIMASK GIC_CPU_REG(0x04) 63#define GIC_CPU_BINPOINT GIC_CPU_REG(0x08) 64#define GIC_CPU_INTACK GIC_CPU_REG(0x0c) 65#define GIC_CPU_EOI GIC_CPU_REG(0x10) 66#define GIC_CPU_RUNNINGPRI GIC_CPU_REG(0x14) 67#define GIC_CPU_HIGHPRI GIC_CPU_REG(0x18) 68 69#define GIC_DIST_CTRL GIC_DIST_REG(0x000) 70#define GIC_DIST_CTR GIC_DIST_REG(0x004) 71#define GIC_DIST_ENABLE_SET GIC_DIST_REG(0x100) 72#define GIC_DIST_ENABLE_CLEAR GIC_DIST_REG(0x180) 73#define GIC_DIST_PENDING_SET GIC_DIST_REG(0x200) 74#define GIC_DIST_PENDING_CLEAR GIC_DIST_REG(0x280) 75#define GIC_DIST_ACTIVE_BIT GIC_DIST_REG(0x300) 76#define GIC_DIST_PRI GIC_DIST_REG(0x400) 77#define GIC_DIST_TARGET GIC_DIST_REG(0x800) 78#define GIC_DIST_CONFIG GIC_DIST_REG(0xc00) 79#define GIC_DIST_SOFTINT GIC_DIST_REG(0xf00) 80 81 82/* MSM ACPU Interrupt Numbers */ 83 84/* 0-15: STI/SGI (software triggered/generated interrupts) 85 * 16-31: PPI (private peripheral interrupts) 86 * 32+: SPI (shared peripheral interrupts) 87 */ 88 89#define GIC_PPI_START 16 90#define GIC_SPI_START 32 91 92#define INT_DEBUG_TIMER_EXP (GIC_PPI_START + 1) 93 94#define USB1_HS_BAM_IRQ (GIC_SPI_START + 94) 95#define USB1_HS_IRQ (GIC_SPI_START + 100) 96#define USB2_IRQ (GIC_SPI_START + 141) 97#define USB1_IRQ (GIC_SPI_START + 142) 98 99#define GSBI_QUP_IRQ(id) ((id) <= 8 ? (GIC_SPI_START + 145 + 2*(id)) : \ 100 (GIC_SPI_START + 187 + 2*((id)-8))) 101 102/* Retrofit universal macro names */ 103#define INT_USB_HS USB1_HS_IRQ 104 105#define NR_MSM_IRQS 256 106#define NR_GPIO_IRQS 173 107#define NR_BOARD_IRQS 0 108 109#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS) 110 111#define GPT_ENABLE_CLR_ON_MATCH_EN 2 112#define GPT_ENABLE_EN 1 113#define DGT_ENABLE_CLR_ON_MATCH_EN 2 114#define DGT_ENABLE_EN 1 115 116#define SPSS_TIMER_STATUS_DGT_EN (1 << 0) 117 118#endif /* !_PEXPERT_APQ8060_H_ */