1/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2 3/*- 4 * Copyright (c) 1998, 2001 Ben Harris 5 * Copyright (c) 1994-1996 Mark Brinicombe. 6 * Copyright (c) 1994 Brini. 7 * All rights reserved. 8 * 9 * This code is derived from software written for Brini by Mark Brinicombe 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * $FreeBSD$ 39 */ 40 41#ifndef MACHINE_ARMREG_H 42#define MACHINE_ARMREG_H 43 44#define INSN_SIZE 4 45#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 46#define PSR_MODE 0x0000001f /* mode mask */ 47#define PSR_USR26_MODE 0x00000000 48#define PSR_FIQ26_MODE 0x00000001 49#define PSR_IRQ26_MODE 0x00000002 50#define PSR_SVC26_MODE 0x00000003 51#define PSR_USR32_MODE 0x00000010 52#define PSR_FIQ32_MODE 0x00000011 53#define PSR_IRQ32_MODE 0x00000012 54#define PSR_SVC32_MODE 0x00000013 55#define PSR_ABT32_MODE 0x00000017 56#define PSR_UND32_MODE 0x0000001b 57#define PSR_SYS32_MODE 0x0000001f 58#define PSR_32_MODE 0x00000010 59#define PSR_FLAGS 0xf0000000 /* flags */ 60 61#define PSR_C_bit (1 << 29) /* carry */ 62 63/* The high-order byte is always the implementor */ 64#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 65#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 66#define CPU_ID_DEC 0x44000000 /* 'D' */ 67#define CPU_ID_INTEL 0x69000000 /* 'i' */ 68#define CPU_ID_TI 0x54000000 /* 'T' */ 69#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 70 71/* How to decide what format the CPUID is in. */ 72#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 73#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 74#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 75 76/* On ARM3 and ARM6, this byte holds the foundry ID. */ 77#define CPU_ID_FOUNDRY_MASK 0x00ff0000 78#define CPU_ID_FOUNDRY_VLSI 0x00560000 79 80/* On ARM7 it holds the architecture and variant (sub-model) */ 81#define CPU_ID_7ARCH_MASK 0x00800000 82#define CPU_ID_7ARCH_V3 0x00000000 83#define CPU_ID_7ARCH_V4T 0x00800000 84#define CPU_ID_7VARIANT_MASK 0x007f0000 85 86/* On more recent ARMs, it does the same, but in a different format */ 87#define CPU_ID_ARCH_MASK 0x000f0000 88#define CPU_ID_ARCH_V3 0x00000000 89#define CPU_ID_ARCH_V4 0x00010000 90#define CPU_ID_ARCH_V4T 0x00020000 91#define CPU_ID_ARCH_V5 0x00030000 92#define CPU_ID_ARCH_V5T 0x00040000 93#define CPU_ID_ARCH_V5TE 0x00050000 94#define CPU_ID_ARCH_V5TEJ 0x00060000 95#define CPU_ID_ARCH_V6 0x00070000 96#define CPU_ID_CPUID_SCHEME 0x000f0000 97#define CPU_ID_VARIANT_MASK 0x00f00000 98 99/* Next three nybbles are part number */ 100#define CPU_ID_PARTNO_MASK 0x0000fff0 101 102/* Intel XScale has sub fields in part number */ 103#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 104#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 105#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 106 107/* And finally, the revision number. */ 108#define CPU_ID_REVISION_MASK 0x0000000f 109 110/* Individual CPUs are probably best IDed by everything but the revision. */ 111#define CPU_ID_CPU_MASK 0xfffffff0 112 113/* Fake CPU IDs for ARMs without CP15 */ 114#define CPU_ID_ARM2 0x41560200 115#define CPU_ID_ARM250 0x41560250 116 117/* Pre-ARM7 CPUs -- [15:12] == 0 */ 118#define CPU_ID_ARM3 0x41560300 119#define CPU_ID_ARM600 0x41560600 120#define CPU_ID_ARM610 0x41560610 121#define CPU_ID_ARM620 0x41560620 122 123/* ARM7 CPUs -- [15:12] == 7 */ 124#define CPU_ID_ARM700 0x41007000 /* XXX This is a guess. */ 125#define CPU_ID_ARM710 0x41007100 126#define CPU_ID_ARM7500 0x41027100 127#define CPU_ID_ARM710A 0x41047100 /* inc ARM7100 */ 128#define CPU_ID_ARM7500FE 0x41077100 129#define CPU_ID_ARM710T 0x41807100 130#define CPU_ID_ARM720T 0x41807200 131#define CPU_ID_ARM740T8K 0x41807400 /* XXX no MMU, 8KB cache */ 132#define CPU_ID_ARM740T4K 0x41817400 /* XXX no MMU, 4KB cache */ 133 134/* Post-ARM7 CPUs */ 135#define CPU_ID_ARM810 0x41018100 136#define CPU_ID_ARM920T 0x41129200 137#define CPU_ID_ARM920T_ALT 0x41009200 138#define CPU_ID_ARM922T 0x41029220 139#define CPU_ID_ARM926EJS 0x41069260 140#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 141#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 142#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 143#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 144#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 145#define CPU_ID_ARM1022ES 0x4105a220 146#define CPU_ID_ARM1026EJS 0x4106a260 147#define CPU_ID_ARM1136JS 0x4107b360 148#define CPU_ID_ARM1136JSR1 0x4117b360 149#define CPU_ID_ARM1176JZS 0x410fb760 150#define CPU_ID_CORTEXA5 0x410fc050 151#define CPU_ID_CORTEXA7 0x410fc070 152#define CPU_ID_CORTEXA8R0 0x410fc080 153#define CPU_ID_CORTEXA8R1 0x411fc080 154#define CPU_ID_CORTEXA8R2 0x412fc080 155#define CPU_ID_CORTEXA8R3 0x413fc080 156#define CPU_ID_CORTEXA9R1 0x411fc090 157#define CPU_ID_CORTEXA9R2 0x412fc090 158#define CPU_ID_CORTEXA9R3 0x413fc090 159#define CPU_ID_CORTEXA15 0x410fc0f0 160#define CPU_ID_SA110 0x4401a100 161#define CPU_ID_SA1100 0x4401a110 162#define CPU_ID_TI925T 0x54029250 163#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 164#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 165#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 166 167/* 168 * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported 169 * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. 170 */ 171#ifdef SOC_MV_LOKIPLUS 172#define CPU_ID_MV88FR571_41 0x00000000 173#else 174#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 175#endif 176 177#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ 178#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ 179/* Marvell's CPUIDs with ARM ID in implementor field */ 180#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ 181 182#define CPU_ID_FA526 0x66015260 183#define CPU_ID_FA626TE 0x66056260 184#define CPU_ID_SA1110 0x6901b110 185#define CPU_ID_IXP1200 0x6901c120 186#define CPU_ID_80200 0x69052000 187#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 188#define CPU_ID_PXA210 0x69052120 189#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 190#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 191#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 192#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 193#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 194#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 195#define CPU_ID_PXA27X 0x69054110 196#define CPU_ID_80321_400 0x69052420 197#define CPU_ID_80321_600 0x69052430 198#define CPU_ID_80321_400_B0 0x69052c20 199#define CPU_ID_80321_600_B0 0x69052c30 200#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 201#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 202#define CPU_ID_81342 0x69056810 203#define CPU_ID_IXP425 0x690541c0 204#define CPU_ID_IXP425_533 0x690541c0 205#define CPU_ID_IXP425_400 0x690541d0 206#define CPU_ID_IXP425_266 0x690541f0 207#define CPU_ID_IXP435 0x69054040 208#define CPU_ID_IXP465 0x69054200 209 210/* ARM3-specific coprocessor 15 registers */ 211#define ARM3_CP15_FLUSH 1 212#define ARM3_CP15_CONTROL 2 213#define ARM3_CP15_CACHEABLE 3 214#define ARM3_CP15_UPDATEABLE 4 215#define ARM3_CP15_DISRUPTIVE 5 216 217/* ARM3 Control register bits */ 218#define ARM3_CTL_CACHE_ON 0x00000001 219#define ARM3_CTL_SHARED 0x00000002 220#define ARM3_CTL_MONITOR 0x00000004 221 222/* CPUID registers */ 223#define ARM_PFR0_ARM_ISA_MASK 0x0000000f 224 225#define ARM_PFR0_THUMB_MASK 0x000000f0 226#define ARM_PFR0_THUMB 0x10 227#define ARM_PFR0_THUMB2 0x30 228 229#define ARM_PFR0_JAZELLE_MASK 0x00000f00 230#define ARM_PFR0_THUMBEE_MASK 0x0000f000 231 232#define ARM_PFR1_ARMV4_MASK 0x0000000f 233#define ARM_PFR1_SEC_EXT_MASK 0x000000f0 234#define ARM_PFR1_MICROCTRL_MASK 0x00000f00 235 236/* 237 * Post-ARM3 CP15 registers: 238 * 239 * 1 Control register 240 * 241 * 2 Translation Table Base 242 * 243 * 3 Domain Access Control 244 * 245 * 4 Reserved 246 * 247 * 5 Fault Status 248 * 249 * 6 Fault Address 250 * 251 * 7 Cache/write-buffer Control 252 * 253 * 8 TLB Control 254 * 255 * 9 Cache Lockdown 256 * 257 * 10 TLB Lockdown 258 * 259 * 11 Reserved 260 * 261 * 12 Reserved 262 * 263 * 13 Process ID (for FCSE) 264 * 265 * 14 Reserved 266 * 267 * 15 Implementation Dependent 268 */ 269 270/* Some of the definitions below need cleaning up for V3/V4 architectures */ 271 272/* CPU control register (CP15 register 1) */ 273#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 274#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 275#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 276#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 277#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 278#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 279#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 280#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 281#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 282#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 283#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 284#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 285#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 286#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 287#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 288#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 289#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 290#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 291#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ 292#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 293#define CPU_CONTROL_AF_ENABLE 0x20000000 /* Access Flag enable */ 294 295#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 296 297/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 298#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 299#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 300#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 301#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 302#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 303#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 304#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 305#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 306 307/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 308#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 309 /* This is an undocumented flag 310 * used to work around a cache bug 311 * in r0 steppings. See errata 312 * 364296. 313 */ 314/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 315#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 316#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 317#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 318#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 319 320/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 321#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 322#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 323/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 324#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 325#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 326#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 327#define XSCALE_AUXCTL_MD_MASK 0x00000030 328 329/* Xscale Core 3 only */ 330#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 331 332/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ 333#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ 334#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ 335#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ 336#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ 337#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 338#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ 339#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ 340#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ 341#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ 342#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ 343 344/* Cache type register definitions */ 345#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 346#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 347#define CPU_CT_S (1U << 24) /* split cache */ 348#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 349#define CPU_CT_FORMAT(x) ((x) >> 29) 350 351#define CPU_CT_CTYPE_WT 0 /* write-through */ 352#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 353#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 354#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 355#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 356 357#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 358#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 359#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 360#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 361 362#define CPU_CT_ARMV7 0x4 363/* ARM v7 Cache type definitions */ 364#define CPUV7_CT_CTYPE_WT (1 << 31) 365#define CPUV7_CT_CTYPE_WB (1 << 30) 366#define CPUV7_CT_CTYPE_RA (1 << 29) 367#define CPUV7_CT_CTYPE_WA (1 << 28) 368 369#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ 370#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ 371#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ 372 373#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) 374#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) 375#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) 376#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) 377 378#define CACHE_ICACHE 1 379#define CACHE_DCACHE 2 380#define CACHE_SEP_CACHE 3 381#define CACHE_UNI_CACHE 4 382 383/* Fault status register definitions */ 384 385#define FAULT_TYPE_MASK 0x0f 386#define FAULT_USER 0x10 387 388#define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 389#define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 390#define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 391#define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 392#define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 393#define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 394#define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 395#define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 396#define FAULT_ALIGN_0 0x01 /* Alignment */ 397#define FAULT_ALIGN_1 0x03 /* Alignment */ 398#define FAULT_TRANS_S 0x05 /* Translation -- Section */ 399#define FAULT_TRANS_F 0x06 /* Translation -- Flag */ 400#define FAULT_TRANS_P 0x07 /* Translation -- Page */ 401#define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 402#define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 403#define FAULT_PERM_S 0x0d /* Permission -- Section */ 404#define FAULT_PERM_P 0x0f /* Permission -- Page */ 405 406#define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 407 408/* 409 * Address of the vector page, low and high versions. 410 */ 411#ifndef __ASSEMBLER__ 412#define ARM_VECTORS_LOW 0x00000000U 413#define ARM_VECTORS_HIGH 0xffff0000U 414#else 415#define ARM_VECTORS_LOW 0 416#define ARM_VECTORS_HIGH 0xffff0000 417#endif 418 419/* 420 * ARM Instructions 421 * 422 * 3 3 2 2 2 423 * 1 0 9 8 7 0 424 * +-------+-------------------------------------------------------+ 425 * | cond | instruction dependant | 426 * |c c c c| | 427 * +-------+-------------------------------------------------------+ 428 */ 429 430#define INSN_SIZE 4 /* Always 4 bytes */ 431#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 432#define INSN_COND_AL 0xe0000000 /* Always condition */ 433 434#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 435 436#if !defined(__ASSEMBLER__) && !defined(_RUMPKERNEL) 437#define ARMREG_READ_INLINE(name, __insnstring) \ 438static inline uint32_t armreg_##name##_read(void) \ 439{ \ 440 uint32_t __rv; \ 441 __asm __volatile("mrc " __insnstring : "=r"(__rv)); \ 442 return __rv; \ 443} 444 445#define ARMREG_WRITE_INLINE(name, __insnstring) \ 446static inline void armreg_##name##_write(uint32_t __val) \ 447{ \ 448 __asm __volatile("mcr " __insnstring :: "r"(__val)); \ 449} 450 451#define ARMREG_READ64_INLINE(name, __insnstring) \ 452static inline uint64_t armreg_##name##_read(void) \ 453{ \ 454 uint64_t __rv; \ 455 __asm __volatile("mrrc " __insnstring : "=r"(__rv)); \ 456 return __rv; \ 457} 458 459#define ARMREG_WRITE64_INLINE(name, __insnstring) \ 460static inline void armreg_##name##_write(uint64_t __val) \ 461{ \ 462 __asm __volatile("mcrr " __insnstring :: "r"(__val)); \ 463} 464 465/* cp10 registers */ 466ARMREG_READ_INLINE(fpsid, "p10,7,%0,c0,c0,0") /* VFP System ID */ 467ARMREG_READ_INLINE(fpscr, "p10,7,%0,c1,c0,0") /* VFP Status/Control Register */ 468ARMREG_WRITE_INLINE(fpscr, "p10,7,%0,c1,c0,0") /* VFP Status/Control Register */ 469ARMREG_READ_INLINE(mvfr1, "p10,7,%0,c6,c0,0") /* Media and VFP Feature Register 1 */ 470ARMREG_READ_INLINE(mvfr0, "p10,7,%0,c7,c0,0") /* Media and VFP Feature Register 0 */ 471ARMREG_READ_INLINE(fpexc, "p10,7,%0,c8,c0,0") /* VFP Exception Register */ 472ARMREG_WRITE_INLINE(fpexc, "p10,7,%0,c8,c0,0") /* VFP Exception Register */ 473ARMREG_READ_INLINE(fpinst, "p10,7,%0,c9,c0,0") /* VFP Exception Instruction */ 474ARMREG_WRITE_INLINE(fpinst, "p10,7,%0,c9,c0,0") /* VFP Exception Instruction */ 475ARMREG_READ_INLINE(fpinst2, "p10,7,%0,c10,c0,0") /* VFP Exception Instruction 2 */ 476ARMREG_WRITE_INLINE(fpinst2, "p10,7,%0,c10,c0,0") /* VFP Exception Instruction 2 */ 477 478/* cp15 c0 registers */ 479ARMREG_READ_INLINE(midr, "p15,0,%0,c0,c0,0") /* Main ID Register */ 480ARMREG_READ_INLINE(ctr, "p15,0,%0,c0,c0,1") /* Cache Type Register */ 481ARMREG_READ_INLINE(mpidr, "p15,0,%0,c0,c0,5") /* Multiprocess Affinity Register */ 482ARMREG_READ_INLINE(pfr0, "p15,0,%0,c0,c1,0") /* Processor Feature Register 0 */ 483ARMREG_READ_INLINE(pfr1, "p15,0,%0,c0,c1,1") /* Processor Feature Register 1 */ 484ARMREG_READ_INLINE(mmfr0, "p15,0,%0,c0,c1,4") /* Memory Model Feature Register 0 */ 485ARMREG_READ_INLINE(mmfr1, "p15,0,%0,c0,c1,5") /* Memory Model Feature Register 1 */ 486ARMREG_READ_INLINE(mmfr2, "p15,0,%0,c0,c1,6") /* Memory Model Feature Register 2 */ 487ARMREG_READ_INLINE(mmfr3, "p15,0,%0,c0,c1,7") /* Memory Model Feature Register 3 */ 488ARMREG_READ_INLINE(isar0, "p15,0,%0,c0,c2,0") /* Instruction Set Attribute Register 0 */ 489ARMREG_READ_INLINE(isar1, "p15,0,%0,c0,c2,1") /* Instruction Set Attribute Register 1 */ 490ARMREG_READ_INLINE(isar2, "p15,0,%0,c0,c2,2") /* Instruction Set Attribute Register 2 */ 491ARMREG_READ_INLINE(isar3, "p15,0,%0,c0,c2,3") /* Instruction Set Attribute Register 3 */ 492ARMREG_READ_INLINE(isar4, "p15,0,%0,c0,c2,4") /* Instruction Set Attribute Register 4 */ 493ARMREG_READ_INLINE(isar5, "p15,0,%0,c0,c2,5") /* Instruction Set Attribute Register 5 */ 494ARMREG_READ_INLINE(ccsidr, "p15,1,%0,c0,c0,0") /* Cache Size ID Register */ 495ARMREG_READ_INLINE(clidr, "p15,1,%0,c0,c0,1") /* Cache Level ID Register */ 496ARMREG_READ_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 497ARMREG_WRITE_INLINE(csselr, "p15,2,%0,c0,c0,0") /* Cache Size Selection Register */ 498/* cp15 c1 registers */ 499ARMREG_READ_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */ 500ARMREG_WRITE_INLINE(sctrl, "p15,0,%0,c1,c0,0") /* System Control Register */ 501ARMREG_READ_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 502ARMREG_WRITE_INLINE(auxctl, "p15,0,%0,c1,c0,1") /* Auxiliary Control Register */ 503ARMREG_READ_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 504ARMREG_WRITE_INLINE(cpacr, "p15,0,%0,c1,c0,2") /* Co-Processor Access Control Register */ 505/* cp15 c2 registers */ 506ARMREG_READ_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 507ARMREG_WRITE_INLINE(ttbr, "p15,0,%0,c2,c0,0") /* Translation Table Base Register 0 */ 508ARMREG_READ_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 509ARMREG_WRITE_INLINE(ttbr1, "p15,0,%0,c2,c0,1") /* Translation Table Base Register 1 */ 510ARMREG_READ_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 511ARMREG_WRITE_INLINE(ttbcr, "p15,0,%0,c2,c0,2") /* Translation Table Base Register */ 512/* cp15 c5 registers */ 513ARMREG_READ_INLINE(dfsr, "p15,0,%0,c5,c0,0") /* Data Fault Status Register */ 514ARMREG_READ_INLINE(ifsr, "p15,0,%0,c5,c0,1") /* Instruction Fault Status Register */ 515/* cp15 c6 registers */ 516ARMREG_READ_INLINE(dfar, "p15,0,%0,c6,c0,0") /* Data Fault Address Register */ 517ARMREG_READ_INLINE(ifar, "p15,0,%0,c6,c0,2") /* Instruction Fault Address Register */ 518/* cp15 c7 registers */ 519ARMREG_WRITE_INLINE(icialluis, "p15,0,%0,c7,c1,0") /* Instruction Inv All (IS) */ 520ARMREG_WRITE_INLINE(bpiallis, "p15,0,%0,c7,c1,6") /* Branch Invalidate All (IS) */ 521ARMREG_READ_INLINE(par, "p15,0,%0,c7,c4,0") /* Physical Address Register */ 522ARMREG_WRITE_INLINE(iciallu, "p15,0,%0,c7,c5,0") /* Instruction Invalidate All */ 523ARMREG_WRITE_INLINE(icimvau, "p15,0,%0,c7,c5,1") /* Instruction Invalidate MVA */ 524ARMREG_WRITE_INLINE(isb, "p15,0,%0,c7,c5,4") /* Instruction Synchronization Barrier */ 525ARMREG_WRITE_INLINE(bpiall, "p15,0,%0,c5,c1,6") /* Breakpoint Invalidate All */ 526ARMREG_WRITE_INLINE(dcimvac, "p15,0,%0,c7,c6,1") /* Data Invalidate MVA to PoC */ 527ARMREG_WRITE_INLINE(dcisw, "p15,0,%0,c7,c6,2") /* Data Invalidate Set/Way */ 528ARMREG_WRITE_INLINE(ats1cpr, "p15,0,%0,c7,c8,0") /* AddrTrans CurState PL1 Read */ 529ARMREG_WRITE_INLINE(dccmvac, "p15,0,%0,c7,c10,1") /* Data Clean MVA to PoC */ 530ARMREG_WRITE_INLINE(dccsw, "p15,0,%0,c7,c10,2") /* Data Clean Set/Way */ 531ARMREG_WRITE_INLINE(dsb, "p15,0,%0,c7,c10,4") /* Data Synchronization Barrier */ 532ARMREG_WRITE_INLINE(dmb, "p15,0,%0,c7,c10,5") /* Data Memory Barrier */ 533ARMREG_WRITE_INLINE(dccmvau, "p15,0,%0,c7,c14,1") /* Data Clean MVA to PoU */ 534ARMREG_WRITE_INLINE(dccimvac, "p15,0,%0,c7,c14,1") /* Data Clean&Inv MVA to PoC */ 535ARMREG_WRITE_INLINE(dccisw, "p15,0,%0,c7,c14,2") /* Data Clean&Inv Set/Way */ 536/* cp15 c7 PA to VA translation */ 537 538/* 539 * N.B: Cortex-A8 TRM says these are used for both non-secure and secure 540 * states. Cortex-A5 TRM says these are used only for secure state. (4-7) 541 * ARM11 MPCore says to use 0-3. Which one is right for everything? 542 */ 543ARMREG_WRITE_INLINE(va2pa_pr_ns,"p15,0,%0,c7,c8,0") /* VA to PA, Privileged Read */ 544ARMREG_WRITE_INLINE(va2pa_pw_ns,"p15,0,%0,c7,c8,1") /* VA to PA, Privileged Write */ 545ARMREG_WRITE_INLINE(va2pa_ur_ns,"p15,0,%0,c7,c8,2") /* VA to PA, User Read */ 546ARMREG_WRITE_INLINE(va2pa_uw_ns,"p15,0,%0,c7,c8,3") /* VA to PA, User Write */ 547 548ARMREG_WRITE_INLINE(va2pa_pr_s,"p15,0,%0,c7,c8,4") /* VA to PA, Privileged Read */ 549ARMREG_WRITE_INLINE(va2pa_pw_s,"p15,0,%0,c7,c8,5") /* VA to PA, Privileged Write */ 550ARMREG_WRITE_INLINE(va2pa_ur_s,"p15,0,%0,c7,c8,6") /* VA to PA, User Read */ 551ARMREG_WRITE_INLINE(va2pa_uw_s,"p15,0,%0,c7,c8,7") /* VA to PA, User Write */ 552 553/* cp15 c8 registers */ 554ARMREG_WRITE_INLINE(tlbiallis, "p15,0,%0,c8,c3,0") /* Invalidate entire unified TLB, inner shareable */ 555ARMREG_WRITE_INLINE(tlbimvais, "p15,0,%0,c8,c3,1") /* Invalidate unified TLB by MVA, inner shareable */ 556ARMREG_WRITE_INLINE(tlbiasidis, "p15,0,%0,c8,c3,2") /* Invalidate unified TLB by ASID, inner shareable */ 557ARMREG_WRITE_INLINE(tlbimvaais, "p15,0,%0,c8,c3,3") /* Invalidate unified TLB by MVA, all ASID, inner shareable */ 558ARMREG_WRITE_INLINE(itlbiall, "p15,0,%0,c8,c5,0") /* Invalidate entire instruction TLB */ 559ARMREG_WRITE_INLINE(itlbimva, "p15,0,%0,c8,c5,1") /* Invalidate instruction TLB by MVA */ 560ARMREG_WRITE_INLINE(itlbiasid, "p15,0,%0,c8,c5,2") /* Invalidate instruction TLB by ASID */ 561ARMREG_WRITE_INLINE(dtlbiall, "p15,0,%0,c8,c6,0") /* Invalidate entire data TLB */ 562ARMREG_WRITE_INLINE(dtlbimva, "p15,0,%0,c8,c6,1") /* Invalidate data TLB by MVA */ 563ARMREG_WRITE_INLINE(dtlbiasid, "p15,0,%0,c8,c6,2") /* Invalidate data TLB by ASID */ 564ARMREG_WRITE_INLINE(tlbiall, "p15,0,%0,c8,c7,0") /* Invalidate entire unified TLB */ 565ARMREG_WRITE_INLINE(tlbimva, "p15,0,%0,c8,c7,1") /* Invalidate unified TLB by MVA */ 566ARMREG_WRITE_INLINE(tlbiasid, "p15,0,%0,c8,c7,2") /* Invalidate unified TLB by ASID */ 567ARMREG_WRITE_INLINE(tlbimvaa, "p15,0,%0,c8,c7,3") /* Invalidate unified TLB by MVA, all ASID */ 568/* cp15 c9 registers */ 569ARMREG_READ_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 570ARMREG_WRITE_INLINE(pmcr, "p15,0,%0,c9,c12,0") /* PMC Control Register */ 571ARMREG_READ_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 572ARMREG_WRITE_INLINE(pmcntenset, "p15,0,%0,c9,c12,1") /* PMC Count Enable Set */ 573ARMREG_READ_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 574ARMREG_WRITE_INLINE(pmcntenclr, "p15,0,%0,c9,c12,2") /* PMC Count Enable Clear */ 575ARMREG_READ_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 576ARMREG_WRITE_INLINE(pmovsr, "p15,0,%0,c9,c12,3") /* PMC Overflow Flag Status */ 577ARMREG_READ_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 578ARMREG_WRITE_INLINE(pmccntr, "p15,0,%0,c9,c13,0") /* PMC Cycle Counter */ 579ARMREG_READ_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ 580ARMREG_WRITE_INLINE(pmuserenr, "p15,0,%0,c9,c14,0") /* PMC User Enable */ 581/* cp15 c13 registers */ 582ARMREG_READ_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ 583ARMREG_WRITE_INLINE(contextidr, "p15,0,%0,c13,c0,1") /* Context ID Register */ 584ARMREG_READ_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 585ARMREG_WRITE_INLINE(tpidrprw, "p15,0,%0,c13,c0,4") /* PL1 only Thread ID Register */ 586/* cp14 c12 registers */ 587ARMREG_READ_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ 588ARMREG_WRITE_INLINE(vbar, "p15,0,%0,c12,c0,0") /* Vector Base Address Register */ 589/* cp15 c14 registers */ 590/* cp15 Global Timer Registers */ 591ARMREG_READ_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ 592ARMREG_WRITE_INLINE(cnt_frq, "p15,0,%0,c14,c0,0") /* Counter Frequency Register */ 593ARMREG_READ_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ 594ARMREG_WRITE_INLINE(cntk_ctl, "p15,0,%0,c14,c1,0") /* Timer PL1 Control Register */ 595ARMREG_READ_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ 596ARMREG_WRITE_INLINE(cntp_tval, "p15,0,%0,c14,c2,0") /* PL1 Physical TimerValue Register */ 597ARMREG_READ_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ 598ARMREG_WRITE_INLINE(cntp_ctl, "p15,0,%0,c14,c2,1") /* PL1 Physical Timer Control Register */ 599ARMREG_READ_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ 600ARMREG_WRITE_INLINE(cntv_tval, "p15,0,%0,c14,c3,0") /* Virtual TimerValue Register */ 601ARMREG_READ_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ 602ARMREG_WRITE_INLINE(cntv_ctl, "p15,0,%0,c14,c3,1") /* Virtual Timer Control Register */ 603ARMREG_READ64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ 604ARMREG_WRITE64_INLINE(cntp_ct, "p15,0,%Q0,%R0,c14") /* Physical Count Register */ 605ARMREG_READ64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ 606ARMREG_WRITE64_INLINE(cntv_ct, "p15,1,%Q0,%R0,c14") /* Virtual Count Register */ 607ARMREG_READ64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ 608ARMREG_WRITE64_INLINE(cntp_cval, "p15,2,%Q0,%R0,c14") /* PL1 Physical Timer CompareValue Register */ 609ARMREG_READ64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ 610ARMREG_WRITE64_INLINE(cntv_cval, "p15,3,%Q0,%R0,c14") /* PL1 Virtual Timer CompareValue Register */ 611/* cp15 c15 registers */ 612ARMREG_READ_INLINE(cbar, "p15,4,%0,c15,c0,0") /* Configuration Base Address Register */ 613ARMREG_READ_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 614ARMREG_WRITE_INLINE(pmcrv6, "p15,0,%0,c15,c12,0") /* PMC Control Register (armv6) */ 615ARMREG_READ_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 616ARMREG_WRITE_INLINE(pmccntrv6, "p15,0,%0,c15,c12,1") /* PMC Cycle Counter (armv6) */ 617 618#endif /* !__ASSEMBLER__ */ 619 620#endif /* !MACHINE_ARMREG_H */