1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * AIC-6915 (10/100 Ethernet) registers File: aic6915.h 5 * 6 ********************************************************************* 7 * 8 * Copyright 2002 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and conditions. 13 * Subject to these conditions, you may download, copy, install, 14 * use, modify and distribute modified or unmodified copies of 15 * this software in source and/or binary form. No title or ownership 16 * is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions as 20 * they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products 25 * derived from this software without the prior written 26 * permission of Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND 33 * IN PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, 34 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 36 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 37 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 38 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE), 40 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 ********************************************************************* */ 42 43#ifndef _AIC6915_H_ 44#define _AIC6915_H_ 45 46/* 47 * Register and bit definitions for the Adaptec AIC-6915 10/100 48 * Ethernet controller ("Starfire"). 49 * 50 * Reference: 51 * AIC-6915 Ethernet LAN Controller Programmer's Manual 52 * Stock No. 512130-00, Rev. A 53 * Adaptec, Inc., Milpitas CA 95035, September 1998 54 */ 55 56#define K_PCI_VENDOR_ADAPTEC 0x9004 57#define K_PCI_ID_AIC6915 0x6915 58 59#define _DD_MAKEMASK1(n) (1 << (n)) 60#define _DD_MAKEMASK(v,n) ((((1)<<(v))-1) << (n)) 61#define _DD_MAKEVALUE(v,n) ((v) << (n)) 62#define _DD_GETVALUE(v,n,m) (((v) & (m)) >> (n)) 63 64 65/* Offsets in the comments below are for accesses via PCI memory 66 space, but register identifiers are relative to 0x50000 in that 67 space. The subspaces at 0x50000-0x500FF (Adaptec's 68 "Internal_Functional_Registers") also appear at 0x0000 - 0x00FF in 69 i/o and config spaces, with indirect I/O for other registers. */ 70 71#define K_AIC_REG_OFFSET 0x00050000 72 73 74/* Registers 0x00000 - 0x3ffff are EPROM expansion space (not used) */ 75 76/* Registers 0x40000 - 0x4ffff are external registers (not supported) */ 77 78/* Registers 0x50000 - 0x50040 are PCI configuration registers (shadow) */ 79 80/* Registers 0x50040 - 0x5006f are additional PCI registers */ 81 82#define R_PCIDeviceConfig 0x0040 83#define R_BacControl 0x0044 84#define R_PCIMonitor1 0x0048 85#define R_PCIMonitor2 0x004C 86 87/* Power Management Capability */ 88#define R_PMC 0x0050 89#define R_PMCSR 0x0054 90#define R_PMEEvent 0x0058 91 92#define R_EEPROMControlStatus 0x0060 93#define R_PCIComplianceTesting 0x0064 94#define R_IndirectioAddress 0x0068 95#define R_IndirectioDataPort 0x006C 96 97/* Registers 0x50070 - 0x500ff are Ethernet functional registers */ 98 99/* General Ethernet Functional Registers */ 100#define R_GeneralEthernetCtrl 0x0070 101#define R_TimersCtrl 0x0074 102#define R_CurrentTime 0x0078 103#define R_InterruptStatus 0x0080 104#define R_ShadowInterruptStatus 0x0084 105#define R_InterruptEn 0x0088 106#define R_GPIO 0x008C 107 108/* Transmit Registers */ 109#define R_TxDescQueueCtrl 0x0090 110#define R_HiPrTxDescQueueBaseAddr 0x0094 111#define R_LoPrTxDescQueueBaseAddr 0x0098 112#define R_TxDescQueueHighAddr 0x009C 113#define R_TxDescQueueProducerIndex 0x00A0 114#define R_TxDescQueueConsumerIndex 0x00A4 115#define R_TxDmaStatus1 0x00A8 116#define R_TxDmaStatus2 0x00AC 117#define R_TxFrameCtrl 0x00B0 118 119/* Completion Queue Registers */ 120#define R_CompletionQueueHighAddr 0x00B4 121#define R_TxCompletionQueueCtrl 0x00B8 122#define R_RxCompletionQueue1Ctrl 0x00BC 123#define R_RxCompletionQueue2Ctrl 0x00C0 124#define R_CompletionQueueConsumerIndex 0x00C4 125#define R_CompletionQueueProducerIndex 0x00C8 126#define R_RxHiPrCompletionPtrs 0x00CC 127 128/* Receive Registers */ 129#define R_RxDmaCtrl 0x00D0 130#define R_RxDescQueue1Ctrl 0x00D4 131#define R_RxDescQueue2Ctrl 0x00D8 132#define R_RxDescQueueHighAddress 0x00DC 133#define R_RxDescQueue1LowAddress 0x00E0 134#define R_RxDescQueue2LowAddress 0x00E4 135#define R_RxDescQueue1Ptrs 0x00E8 136#define R_RxDescQueue2Ptrs 0x00EC 137#define R_RxDmaStatus 0x00F0 138#define R_RxAddressFilteringCtrl 0x00F4 139 140/* Registers 0x50100 - 0x50fff are PCI extra registers */ 141 142/* PCI Diagnostic Registers */ 143#define R_PCITargetStatus 0x0100 144#define R_PCIMasterStatus1 0x0104 145#define R_PCIMasterStatus2 0x0108 146#define R_PCIDmaLowHostAddr 0x010C 147#define R_BacDmaDiagnostic0 0x0110 148#define R_BacDmaDiagnostic1 0x0114 149#define R_BacDmaDiagnostic2 0x0118 150#define R_BacDmaDiagnostic3 0x011C 151 152#define R_MacAddr1 0x0120 153#define R_MacAddr2 0x0124 154 155/* PCI CardBus Registers */ 156#define R_FunctionEvent 0x0130 157#define R_FunctionEventMask 0x0134 158#define R_FunctionPresentState 0x0138 159#define R_ForceFunction 0x013C 160 161/* Registers 0x51000 - 0x51fff are serial EEPROM */ 162 163/* Registers 0x52000 - 0x53fff are MII registers */ 164 165#define R_MIIRegistersAccessPort 0x2000 166 167#define PHY_REGISTERS 32 168 169#define M_MiiDataValid (1 << 31) 170#define M_MiiBusy (1 << 30) 171#define S_MiiRegDataPort 0 172#define M_MiiRegDataPort (0xFFFF << S_MiiRegDataPort) 173 174/* Registers 0x54000 - 0x54fff are Ethernet extra registers */ 175 176#define R_TestMode 0x4000 177#define R_RxFrameProcessorCtrl 0x4004 178#define R_TxFrameProcessorCtrl 0x4008 179 180/* Registers 0x55000 - 0x55fff are MAC registers */ 181 182#define R_MacConfig1 0x5000 183#define R_MacConfig2 0x5004 184#define R_BkToBkIPG 0x5008 185#define R_NonBkToBkIPG 0x500C 186#define R_ColRetry 0x5010 187#define R_MaxLength 0x5014 188#define R_TxNibbleCnt 0x5018 189#define R_TxByteCnt 0x501C 190#define R_ReTxCnt 0x5020 191#define R_RandomNumGen 0x5024 192#define R_MskRandomNum 0x5028 193#define R_TotalTxCnt 0x5034 194#define R_RxByteCnt 0x5040 195#define R_TxPauseTimer 0x5060 196#define R_VLANType 0x5064 197#define R_MIIStatus 0x5070 198 199/* Registers 0x56000 - 0x56fff are address filtering */ 200 201#define R_PerfectAddressBase 0x6000 202 203#define PERFECT_ADDRESS_ENTRIES 16 204#define PERFECT_ADDRESS_STRIDE 0x10 205 206/* Hash and VLAN Tables are interleaved (Table 7-108) */ 207#define R_HashAddressBase 0x6100 208 209#define HASH_TABLE_STRIDE 0x10 210#define HASH_TABLE_ROWS 32 211#define HASH_BIT_OFFSET 0x0 212#define HASH_PRIORITY_OFFSET 0x4 213#define HASH_VLAN_OFFSET 0x8 214 215/* Registers 0x57000 - 0x57fff are the statistics register file */ 216 217#define R_StatisticsBase 0x7000 218 219#define R_TransmitOKFrames 0x7000 220#define R_SingleCollisionFrames 0x7004 221#define R_MultipleCollisionFrames 0x7008 222#define R_TransmitCRCErrors 0x700C 223#define R_TransmitOKOctets 0x7010 224#define R_TransmitDeferredFrames 0x7014 225#define R_TransmitLateCollision 0x7018 226#define R_TransmitPauseFrames 0x701C 227#define R_TransmitControlFrames 0x7020 228#define R_TransmitExcessiveCollisions 0x7024 229#define R_TransmitExcessiveDeferral 0x7028 230#define R_MulticastTransmitOKFrames 0x702C 231#define R_BroadcastTransmitOKFrames 0x7030 232#define R_FramesLostInternalTransmit 0x7034 233 234#define R_ReceiveOKFrames 0x7038 235#define R_ReceiveCRCErrors 0x703C 236#define R_AlignmentErrors 0x7040 237#define R_ReceiveOKOctets 0x7044 238#define R_PauseFramesReceivedOK 0x7048 239#define R_ControlFramesReceivedOK 0x704C 240#define R_UnknownControlFramesReceived 0x7050 241#define R_ReceiveFramesTooLong 0x7054 242#define R_ReceiveFramesTooShort 0x7058 243#define R_ReceiveFramesJabberError 0x705C 244#define R_ReceiveFramesFragments 0x7060 245#define R_ReceivePackets_64 0x7064 246#define R_ReceivePackets_65_127 0x7068 247#define R_ReceivePackets_128_255 0x706C 248#define R_ReceivePackets_256_511 0x7070 249#define R_ReceivePackets_512_1023 0x7074 250#define R_ReceivePackets_1024_1518 0x7078 251#define R_FramesLostInternalReceive 0x707C 252 253#define R_TransmitFIFOUnderflow 0x7080 254 255#define STATISTICS_COUNT 33 256 257/* Registers 0x58000 - 0x59fff are tx frame processor instruction memory */ 258 259#define R_TxGfpMem 0x8000 260 261/* Registers 0x5a000 - 0x5bfff are rx frame processor instruction memory */ 262 263#define R_RxGfpMem 0xA000 264 265/* Registers 0x5c000 - 0x5dfff are Ethernet FIFO access */ 266 267#define R_EthernetFIFO 0xC000 268 269/* Registers 0x5e000 - 0x5ffff are reserved */ 270 271 272/* 0x0040 PCI Device Config Register */ 273 274#define M_EnDpeInt (1 << 31) 275#define M_EnSseInt (1 << 30) 276#define M_EnRmaInt (1 << 29) 277#define M_EnRtaInt (1 << 28) 278#define M_EnStaInt (1 << 27) 279#define M_EnDprInt (1 << 24) 280#define M_IntEnable (1 << 23) 281#define S_ExternalRegCsWidth 20 282#define M_ExternalRegCsWidth (0x7 << S_ExternalRegCsWidth) 283#define M_StopMWrOnCacheLineDis (1 << 19) 284#define S_EpromCsWidth 16 285#define M_EpromCsWidth (0x7 << S_EpromCsWidth) 286#define M_EnBeLogic (1 << 15) 287#define M_LatencyStopOnCacheLine (1 << 14) 288#define M_PCIMstDmaEn (1 << 13) 289#define M_StopOnCachelineEn (1 << 12) 290#define S_FifoThreshold 8 291#define M_FifoThreshold (0xF << S_FifoThreshold) 292#define M_MemRdCmdEn (1 << 7) 293#define M_StopOnPerr (1 << 6) 294#define M_AbortOnAddrParityErr (1 << 5) 295#define M_EnIncrement (1 << 4) 296#define M_System64 (1 << 2) 297#define M_Force64 (1 << 1) 298#define M_SoftReset (1 << 0) 299 300/* 0x0044 BAC Control Register */ 301 302#define S_DescSwapMode 6 303#define M_DescSwapMode (0x3 << S_DescSwapMode) 304#define S_DataSwapMode 4 305#define M_DataSwapMode (0x3 << S_DataSwapMode) 306#define M_SingleDmaMode (1 << 3) 307#define M_PreferTxDmaReq (1 << 2) 308#define M_PreferRxDmaReq (1 << 1) 309#define M_BacDmaEn (1 << 0) 310 311#define V_DataSwapMode_LE (0x0 << S_DataSwapMode) 312#define V_DataSwapMode_BE (0x1 << S_DataSwapMode) 313 314/* 0x0048 PCI Monitor1 Register */ 315 316#define S_PCIBusMaxLatency 24 317#define M_PCIBusMaxLatency (0xFF << S_PCIBusMaxLatency) 318#define S_PCIIntMaxLatency 16 319#define M_PCIIntMaxLatency (0xFF << S_PCIIntMaxLatency) 320#define S_PCISlaveBusUtilization 0 321#define M_PCISlaveBusUtilization (0xFFFF << S_PCISlaveBusUtilization) 322 323/* 0x004C PCI Monitor2 Register */ 324 325#define S_PCIMasterBusUtilization 16 326#define M_PCIMasterBusUtilization (0xFFFF << S_PCIMasterBusUtilization) 327#define S_ActiveTransferCount 0 328#define M_ActiveTransferCount (0xFFFF << S_ActiveTransferCount) 329 330 331/* 0x0070 General Ethernet Control Register */ 332 333#define M_SetSoftInt (1 << 8) 334#define M_TxGfpEn (1 << 5) 335#define M_RxGfpEn (1 << 4) 336#define M_TxDmaEn (1 << 3) 337#define M_RxDmaEn (1 << 2) 338#define M_TransmitEn (1 << 1) 339#define M_ReceiveEn (1 << 0) 340 341/* 0x0074 Timers Control Register */ 342 343#define M_EarlyRxQ1IntDelayDiasable (1 << 31) 344#define M_RxQ1DoneIntDelayDisable (1 << 30) 345#define M_EarlyRxQ2IntDelayDisable (1 << 29) 346#define M_RxQ2DoneIntDelayDisable (1 << 28) 347#define M_TimeStampResolution (1 << 26) 348#define M_GeneralTimerResolution (1 << 25) 349#define M_OneShotMode (1 << 24) 350#define S_GeneralTimerInterval 16 351#define M_GeneralTimerInterval (0xFF << S_GeneralTimerInterval) 352#define M_TxFrameCompleteIntDelayDisable (1 << 15) 353#define M_TxQueueDoneIntDelayDisable (1 << 14) 354#define M_TxDmaDoneIntDelayDisable (1 << 13) 355#define M_RxHiPrBypass (1 << 12) 356#define M_Timer10X (1 << 11) 357#define S_SmallRxFrame 9 358#define M_SmallRxFrame (0x3 << S_SmallRxFrame) 359#define M_SmallFrameBypass (1 << 8) 360#define S_IntMaskMode 5 361#define M_IntMaskMode (0x3 << S_IntMaskMode) 362#define S_IntMaskPeriod 0 363#define M_IntMaskPeriod (0x1F << S_IntMaskPeriod) 364 365/* 0x0078 Current Time Register */ 366 367#define M_CurrentTime 0xFFFFFFFF 368 369/* 0x0080 Interrupt Status Register */ 370/* 0x0084 Shadow Interrupt Status Register */ 371/* 0x0088 Interrupt En Register (data sheet appends "En") */ 372 373#define M_GPIOInt_3 (1 << 31) 374#define M_GPIOInt_2 (1 << 30) 375#define M_GPIOInt_1 (1 << 29) 376#define M_GPIOInt_0 (1 << 28) 377#define M_GPIOInt (M_GPIOInt_3 | M_GPIOInt_2 | \ 378 M_GPIOInt_1 | M_GPIOInt_0) 379#define M_StatisticWrapInt (1 << 27) 380#define M_AbnormalInterrupt (1 << 25) 381#define M_GeneralTimerInt (1 << 24) 382#define M_SoftInt (1 << 23) 383#define M_RxCompletionQueue1Int (1 << 22) 384#define M_TxCompletionQueueInt (1 << 21) 385#define M_PCIInt (1 << 20) 386#define M_DmaErrInt (1 << 19) 387#define M_TxDataLowInt (1 << 18) 388#define M_RxCompletionQueue2Int (1 << 17) 389#define M_RxQ1LowBuffersInt (1 << 16) 390#define M_NormalInterrupt (1 << 15) 391#define M_TxFrameCompleteInt (1 << 14) 392#define M_TxDMADoneInt (1 << 13) 393#define M_TxQueueDoneInt (1 << 12) 394#define M_EarlyRxQ2Int (1 << 11) 395#define M_EarlyRxQ1Int (1 << 10) 396#define M_RxQ2DoneInt (1 << 9) 397#define M_RxQ1DoneInt (1 << 8) 398#define M_RxGfpNoResponseInt (1 << 7) 399#define M_RxQ2LowBuffersInt (1 << 6) 400#define M_NoTxChecksumInt (1 << 5) 401#define M_TxLowPrMismatchInt (1 << 4) 402#define M_TxHiPrMismatchInt (1 << 3) 403#define M_GfpRxInt (1 << 2) 404#define M_GfpTxInt (1 << 1) 405#define M_PCIPadInt (1 << 0) 406 407/* 0x008C GPIO Register */ 408 409#define M_GPIOCtrl_3 (1 << 27) 410#define M_GPIOCtrl_2 (1 << 26) 411#define M_GPIOCtrl_1 (1 << 25) 412#define M_GPIOCtrl_0 (1 << 24) 413#define M_GPIOCtrl (M_GPIOCtrl_3 | M_GPIOCtrl_2 | \ 414 M_GPIOCtrl_1 | M_GPIOCtrl_0) 415#define M_GPIOOutMode_3 (1 << 19) 416#define M_GPIOOutMode_2 (1 << 18) 417#define M_GPIOOutMode_1 (1 << 17) 418#define M_GPIOOutMode_0 (1 << 16) 419#define M_GPIOOutMode (M_GPIOOutMode_3 | M_GPIOOutMode_2 | \ 420 M_GPIOOutMode_1 | M_GPIOOutMode_0) 421#define M_GPIOInpMode_3 (3 << 14) 422#define M_GPIOInpMode_2 (3 << 12) 423#define M_GPIOInpMode_1 (3 << 10) 424#define M_GPIOInpMode_0 (3 << 8) 425#define M_GPIOInpMode (M_GPIOInpMode_3 | M_GPIOInpMode_2 | \ 426 M_GPIOInpMode_1 | M_GPIOInpMode_0) 427#define V_GPIOInpMode(x,n) ((x) << (8+2*(n))) 428#define G_GPIOInpMode(x,n) (((x) >> (8+2*(n))) & 0x3) 429#define K_GPIOInpMode_Normal 0 430#define K_GPIOInpMode_IntHi 1 431#define K_GPIOInpMode_IntLo 2 432#define K_GPIOInpMode_Change 3 433#define M_GPIOData_3 (1 << 27) 434#define M_GPIOData_2 (1 << 26) 435#define M_GPIOData_1 (1 << 25) 436#define M_GPIOData_0 (1 << 24) 437#define M_GPIOData (M_GPIOData_3 | M_GPIOData_2 | \ 438 M_GPIOData_1 | M_GPIOData_0) 439 440/* 0x0090 Tx DescQueue Ctrl Register (see 7-46) */ 441 442#define S_TxHighPriorityFifoThreshold 24 443#define M_TxHighPriorityFifoThreshold (0xFF << S_TxHighPriorityFifoThreshold) 444#define S_SkipLength 16 445#define M_SkipLength (0x1F << S_SkipLength) 446#define S_TxDmaBurstSize 8 447#define M_TxDmaBurstSize (0x3F << S_TxDmaBurstSize) 448#define M_TxDescQueue64bitAddr (1 << 7) 449#define S_MinFrameDescSpacing 4 450#define M_MinFrameDescSpacing (0x7 << S_MinFrameDescSpacing) 451#define M_DisableTxDmaCompletion (1 << 3) 452#define S_TxDescType 0 453#define M_TxDescType (0x7 << S_TxDescType) 454 455/* 0x0094 HiPr Tx DescQueue Base Addr Register */ 456/* 0x0098 LoPr Tx DescQueue Base Addr Register */ 457 458#define S_TxDescQueueBaseAddress 0 /* bit-aligned */ 459#define M_TxDescQueueBaseAddress 0xFFFFFF00 460 461/* 0x00A0 Tx DescQueue Producer Index Register */ 462 463#define S_HiPrTxProducerIndex 16 464#define M_HiPrTxProducerIndex (0x7FF << S_HiPrTxProducerIndex) 465#define S_LoPrTxProducerIndex 0 466#define M_LoPrTxProducerIndex (0x7FF << S_LoPrTxProducerIndex) 467 468 469/* 0x00A4 Tx DescQueue Consumer Index Register */ 470 471#define S_HiPrTxConsumerIndex 16 472#define M_HiPrTxConsumerIndex (0x7FF << S_HiPrTxConsumerIndex) 473#define S_LoPrTxConsumerIndex 0 474#define M_LoPrTxConsumerIndex (0x7FF << S_LoPrTxConsumerIndex) 475 476/* 0x00B0 Tx Frame Ctrl/Status Register */ 477 478#define S_TxFrameStates 16 479#define M_TxFrameStates (0x1FF << S_TxFrameStates) 480#define S_TxDebugConfigBits 9 481#define M_TxDebugConfigBits (0x7F << S_TxDebugConfigBits) 482#define M_DmaCompletionAfterTransmitComplete (1 << 8) 483#define S_TransmitThreshold 0 484#define M_TransmitThreshold (0xFF << S_TransmitThreshold) 485 486/* 0x00B8 Tx Completion Queue Ctrl Register */ 487 488#define S_TxCompletionBaseAddress 0 /* bit-aligned */ 489#define M_TxCompletionBaseAddress 0xFFFFFF00 490#define M_TxCompletion64bitAddress (1 << 7) 491#define M_TxCompletionProducerWe (1 << 6) 492#define M_TxCompletionSize (1 << 5) 493#define M_CommonQueueMode (1 << 4) 494#define S_TxCompletionQueueThreshold 0 495#define M_TxCompletionQueueThreshold (0xF << S_TxCompletionQueueThreshold) 496 497 498/* 0x00BC Rx Completion Queue 1 Ctrl Register */ 499/* 0x00C0 Rx Completion Queue 2 Ctrl Register */ 500 501#define S_RxCompletionBaseAddress 0 /* bit-aligned */ 502#define M_RxCompletionBaseAddress 0xFFFFFF00 503#define M_RxCompletion64bitAddress (1 << 7) 504#define M_RxCompletionProducerWe (1 << 6) 505#define S_RxCompletionType 4 506#define M_RxCompletionType (0x3 << S_RxCompletionType) 507#define S_RxCompletionThreshold 0 508#define M_RxCompletionThreshold (0xF << S_RxCompletionQueueThreshold) 509 510/* 0x00C4 Completion Queue Consumer Index Register */ 511 512#define M_TxCompletionThresholdMode (1 << 31) 513#define S_TxCompletionConsumerIndex 16 514#define M_TxCompletionConsumerIndex (0x3FF << S_TxCompletionConsumerIndex) 515#define V_TxCompletionConsumerIndex(x) ((x) << S_TxCompletionConsumerIndex) 516#define G_TxCompletionConsumerIndex(x) (((x) & M_TxCompletionConsumerIndex) \ 517 >> S_TxCompletionConsumerIndex) 518#define M_RxCompletionQ1ThresholdMode (1 << 15) 519#define S_RxCompletionQ1ConsumerIndex 0 520#define M_RxCompletionQ1ConsumerIndex (0x3FF << S_RxCompletionQ1ConsumerIndex) 521#define V_RxCompletionQ1ConsumerIndex(x) ((x) << S_RxCompletionQ1ConsumerIndex) 522#define G_RxCompletionQ1ConsumerIndex(x) (((x) & M_RxCompletionQ1ConsumerIndex)\ 523 >> S_RxCompletionQ1ConsumerIndex) 524 525/* 0x00C8 Completion Queue Producer Index Register */ 526 527#define S_TxCompletionProducerIndex 16 528#define M_TxCompletionProducerIndex (0x3FF << S_TxCompletionProducerIndex) 529#define V_TxCompletionProducerIndex(x) ((x) << S_TxCompletionProducerIndex) 530#define G_TxCompletionProducerIndex(x) (((x) & M_TxCompletionProducerIndex) \ 531 >> S_TxCompletionProducerIndex) 532#define S_RxCompletionQ1ProducerIndex 0 533#define M_RxCompletionQ1ProducerIndex (0x3FF << S_RxCompletionQ1ProducerIndex) 534#define V_RxCompletionQ1ProducerIndex(x) ((x) << S_RxCompletionQ1ProducerIndex) 535#define G_RxCompletionQ1ProducerIndex(x) (((x) & M_RxCompletionQ1ProducerIndex)\ 536 >> S_RxCompletionQ1ProducerIndex) 537 538/* 0x00CC Rx Hi Pr Completion Ptrs Register */ 539 540#define S_RxCompletionQ2ProducerIndex 16 541#define M_RxCompletionQ2ProducerIndex (0x3FF << S_RxCompletionQ2ProducerIndex) 542#define M_RxCompletionQ2ThresholdMode (1 << 15) 543#define S_RxCompletionQ2ConsumerIndex 0 544#define M_RxCompletionQ2ConsumerIndex (0x3FF << S_RxCompletionQ2ConsumerIndex) 545 546/* 0x00D0 Rx DMA Ctrl Register */ 547 548#define M_RxReportBadFrames (1 << 31) 549#define M_RxDmaShortFrames (1 << 30) 550#define M_RxDmaBadFrames (1 << 29) 551#define M_RxDmaCrcErrorFrames (1 << 28) 552#define M_RxDmaControlFrame (1 << 27) 553#define M_RxDmaPauseFrame (1 << 26) 554 555#define S_RxChecksumMode 24 556#define M_RxChecksumMode (0x3 << S_RxChecksumMode) 557#define K_RxChecksumMode_None 0 558#define K_RxChecksumMode_TCP 1 559#define K_RxChecksumMode_TCP_UDP 2 560 561#define M_RxCompletionQ2Enable (1 << 23) 562 563#define S_RxDmaQueueMode 20 564#define M_RxDmaQueueMode (0x7 << S_RxDmaQueueMode) 565#define K_RxDmaQueueMode_Q1Only 0 566#define K_RxDmaQueueMode_Q2FP 1 567#define K_RxDmaQueueMode_Q2Short 2 568#define K_RxDmaQueueMode_Q2Priority 3 569#define K_RxDmaQueueMode_SplitIP 4 570 571#define M_RxUseBackupQueue (1 << 19) 572#define M_RxDmaCrc (1 << 18) 573#define S_RxEarlyIntThreshold 12 574#define M_RxEarlyIntThreshold (0x1F << S_RxEarlyIntThreshold) 575#define S_RxHighPriorityThreshold 8 576#define M_RxHighPriorityThreshold (0xF << S_RxHighPriorityThreshold) 577#define M_RxFpTestMode (1 << 7) 578#define S_RxBurstSize 0 579#define M_RxBurstSize (0x7F << S_RxBurstSize) 580 581/* 0x00D4 Rx DescQueue1 Ctrl Register */ 582/* 0x00D8 Rx DescQueue2 Ctrl Register */ 583 584#define S_RxBufferLength 16 585#define M_RxBufferLength (0xFFFF << S_RxBufferLength) 586#define M_RxDescEntries (1 << 14) 587#define M_RxConsumerWe (1 << 7) 588#define S_RxMinDescriptorsThreshold 0 589#define M_RxMinDescriptorsThreshold (0x7F << S_RxMinDescriptorsThreshold) 590 591/* 0x00D4 Rx DescQueue1 Ctrl Register (only) */ 592 593#define M_RxPrefetchDescriptorsMode (1 << 15) 594#define M_RxVariableSizeQueues (1 << 13) 595#define M_Rx64BitBufferAddresses (1 << 12) 596#define M_Rx64BitDescQueueAddress (1 << 11) 597#define S_RxDescSpacing 8 598#define M_RxDescSpacing (0x7 << S_RxDescSpacing) 599 600/* 0x00E0 Rx DescQueue1 Low Address Register */ 601/* 0x00E4 Rx DescQueue2 Low Address Register */ 602 603#define S_RxDescQueueLowAddress 0 /* bit-aligned */ 604#define M_RxDescQueueLowAddress 0xFFFFFF00 605 606/* 0x00E8 Rx DescQueue1 Ptrs */ 607/* 0x00EC Rx DescQueue2 Ptrs */ 608 609#define S_RxDescConsumer 16 610#define M_RxDescConsumer (0x7FF << S_RxDescConsumer) 611#define S_RxDescProducer 0 612#define M_RxDescProducer (0x7FF << S_RxDescProducer) 613 614/* 0x00F4 Rx Address Filtering Ctrl Register */ 615 616#define S_PerfectAddressPriority 16 617#define M_PerfectAddressPriority (0xFFFF << S_PerfectAddressPriority) 618#define S_MinVlanPriority 13 619#define M_MinVlanPriority (0x7 << S_MinVlanPriority) 620#define M_PassMulticastExceptBroadcast (1 << 12) 621#define S_WakeupMode 10 622#define M_WakeupMode (3 << S_WakeupMode) 623#define S_VlanMode 8 624#define M_VlanMode (3 << S_VlanMode) 625 626#define S_PerfectFilteringMode 6 627#define M_PerfectFilteringMode (3 << S_PerfectFilteringMode) 628#define K_PerfectFiltering_Off 0 629#define K_PerfectFiltering_16 1 630#define K_PerfectFiltering_16Inv 2 631#define K_PerfectFiltering_Vlan 3 632 633#define S_HashFilteringMode 4 634#define M_HashFilteringMode (3 << S_HashFilteringMode) 635#define K_HashFiltering_Off 0 636#define K_HashFiltering_VlanMcast 1 637#define K_HashFiltering_AllMcast 2 638#define K_HashFiltering_All 3 639 640#define M_HashPriorityEnable (1 << 3) 641#define M_PassBroadcast (1 << 2) 642#define M_PassMulticast (1 << 1) 643#define M_PromiscuousMode (1 << 0) 644 645 646/* 0x5000 Mac Config1 Register */ 647 648#define M_SoftRst (1 << 15) 649#define M_MIILoopBack (1 << 14) 650#define S_TestMode 12 651#define M_TestMode (0x3 << S_TestMode) 652#define M_TxFlowEn (1 << 11) 653#define M_RxFlowEn (1 << 10) 654#define M_PreambleDetectCount (1 << 9) 655#define M_PassAllRxPackets (1 << 8) 656#define M_PurePreamble (1 << 7) 657#define M_LengthCheck (1 << 6) 658#define M_NoBackoff (1 << 5) 659#define M_DelayCRC (1 << 4) 660#define M_TxHalfDuplexJam (1 << 3) 661#define M_PadEn (1 << 2) 662#define M_FullDuplex (1 << 1) 663#define M_HugeFrame (1 << 0) 664 665/* 0x5004 MacConfig2 Register */ 666 667#define M_TxCRCerr (1 << 15) 668#define M_TxIslCRCerr (1 << 14) 669#define M_RxCRCerr (1 << 13) 670#define M_RxIslCRCerr (1 << 12) 671#define M_TXCF (1 << 11) 672#define M_CtlSoftRst (1 << 10) 673#define M_RxSoftRst (1 << 9) 674#define M_TxSoftRst (1 << 8) 675#define M_RxISLEn (1 << 7) 676#define M_BackPressureNoBackOff (1 << 6) 677#define M_AutoVlanPad (1 << 5) 678#define M_MandatoryVLANPad (1 << 4) 679#define M_TxISLAppen (1 << 3) 680#define M_TxISLCrcEn M_TxISLAppen 681#define M_TxISLEn (1 << 2) 682 683/* 0x5008 BkToBkIPG Register */ 684 685#define S_IPGT 0 686#define M_IPGT (0x7F << S_IPGT) 687#define K_IPGT_FDX 0x15 688#define K_IPGT_HDX 0x11 689 690/* 0x500C NonBkToBkIPG Register */ 691 692#define S_IPGR1 8 693#define M_IPGR1 (0x7F << S_IPGR1) 694#define S_IPGR2 0 695#define M_IPGR2 (0x7F << M_IPGR2) 696 697/* 0x5010 ColRetry Register */ 698 699#define S_LateColWin 8 700#define M_LateColWin (0x3F << S_LateColWin) 701#define S_MaxRetry 0 702#define M_MaxRetry (0xF << S_MaxRetry) 703 704/* 0x5014 MaxLength Register */ 705 706#define S_MaxPacketLength 0 707#define M_MaxPacketLength (0xFFFF << S_MaxPacketLength) 708 709/* 0x5024 RandomNumGen Register */ 710 711#define S_RandomNumGen 0 712#define M_RandomNumGen (0x3FF << S_RandomNumGen) 713 714/* 0x5028 MakRandomNum Register */ 715 716#define S_MskRandomNum 0 717#define M_MskRandomNum (0x3FF << S_MskRandomNum) 718 719/* 0x5060 TxPauseTimer Register */ 720 721#define S_TxPauseTimer 0 722#define M_TxPauseTimer (0xFFFF << S_TxPauseTimer) 723 724/* 0x5064 VLAN Type Register */ 725 726#define S_VLANType 0 727#define M_VLANType (0xFFFF << S_VLANType) 728 729/* 0x5070 MIIStatus Register */ 730 731#define M_MIIStatus_MIILinkFail (1 << 4) 732#define M_MIIStatus_NotValid (1 << 3) 733#define M_MIIStatus_Scan (1 << 2) 734#define M_MIIStatus_MiiDataValid (1 << 1) 735#define M_MIIStatus_MiiBusy (1 << 0) 736 737#endif /* _AIC6915_H_ */ 738