1/* ********************************************************************* 2 * PowerPC CPU support 3 * 4 * Exception Handler File: exception.S 5 * 6 * Author: Mitch Lichtenberg 7 * 8 ********************************************************************* 9 * 10 * Copyright 2000,2001,2002,2003 11 * Broadcom Corporation. All rights reserved. 12 * 13 * This software is furnished under license and may be used and 14 * copied only in accordance with the following terms and 15 * conditions. Subject to these conditions, you may download, 16 * copy, install, use, modify and distribute modified or unmodified 17 * copies of this software in source and/or binary form. No title 18 * or ownership is transferred hereby. 19 * 20 * 1) Any source code used, modified or distributed must reproduce 21 * and retain this copyright notice and list of conditions 22 * as they appear in the source file. 23 * 24 * 2) No right is granted to use any trade name, trademark, or 25 * logo of Broadcom Corporation. The "Broadcom Corporation" 26 * name may not be used to endorse or promote products derived 27 * from this software without the prior written permission of 28 * Broadcom Corporation. 29 * 30 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 31 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 32 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 33 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 34 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 35 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 38 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 39 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 40 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 41 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 42 * THE POSSIBILITY OF SUCH DAMAGE. 43 ********************************************************************* */ 44 45 46#include "ppcdefs.h" 47#include "exception.h" 48#include "ppcmacros.h" 49#include "cpu_config.h" /* for definition of HAZARD and ERET */ 50#include "bsp_config.h" 51 52/* ********************************************************************* 53 * Macros 54 ********************************************************************* */ 55 56 57/* ********************************************************************* 58 * Data 59 ********************************************************************* */ 60 61 .data 62 63 64/* ********************************************************************* 65 * Code 66 ********************************************************************* */ 67 68 .text 69 70 71/* ********************************************************************* 72 * _exc_restart() 73 * 74 * Restart the firmware at the boot address 75 * 76 * Input parameters: 77 * nothing 78 * 79 * Return value: 80 * nothing 81 ********************************************************************* */ 82 83LEAF(_exc_restart) 84 85 b CPUCFG_CPURESTART 86 87END(_exc_restart) 88 89/* ********************************************************************* 90 * _exc_entry(k0) 91 * 92 * Main exception entry point. 93 * 94 * Input parameters: 95 * k0 - exception type 96 * 97 * Return value: 98 * ... 99 ********************************************************************* */ 100 101LEAF(_exc_entry) 102 103 /* 104 * For now, we're going to build the exception frame 105 * on the stack. This is ugly, since the stack might be 106 * the problem in the first place... 107 * 108 * r1 is our stack pointer. 109 */ 110 111 subi r1,r1,EXCEPTION_SIZE 112 113 stw r0,XGR_R0(r1) 114 115 mfmsr r0 116 stw r0,XGR_MSR(r1) 117 mflr r0 118 stw r0,XGR_LR(r1) 119 mfctr r0 120 stw r0,XGR_CTR(r1) 121 mfxer r0 122 stw r0,XSPR_XER(r1) 123 mfspr r0,SPR_SRR0 124 stw r0,XSPR_SRR0(r1) 125 mfspr r0,SPR_SRR1 126 stw r0,XSPR_SRR1(r1) 127 mfspr r0,SPR_DSISR 128 stw r0,XSPR_DSISR(r1) 129 130 stw r1,XGR_R1(r1) 131 stw r2,XGR_R2(r1) 132 stw r3,XGR_R3(r1) 133 stw r4,XGR_R4(r1) 134 stw r5,XGR_R5(r1) 135 stw r6,XGR_R6(r1) 136 stw r7,XGR_R7(r1) 137 stw r8,XGR_R8(r1) 138 stw r9,XGR_R9(r1) 139 stw r10,XGR_R10(r1) 140 stw r11,XGR_R11(r1) 141 stw r12,XGR_R12(r1) 142 stw r13,XGR_R13(r1) 143 stw r14,XGR_R14(r1) 144 stw r15,XGR_R15(r1) 145 stw r16,XGR_R16(r1) 146 stw r17,XGR_R17(r1) 147 stw r18,XGR_R18(r1) 148 stw r19,XGR_R19(r1) 149 stw r20,XGR_R20(r1) 150 stw r21,XGR_R21(r1) 151 stw r22,XGR_R22(r1) 152 stw r23,XGR_R23(r1) 153 stw r24,XGR_R24(r1) 154 stw r25,XGR_R25(r1) 155 stw r26,XGR_R26(r1) 156 stw r27,XGR_R27(r1) 157 stw r28,XGR_R28(r1) 158 stw r29,XGR_R29(r1) 159 stw r30,XGR_R30(r1) 160 stw r31,XGR_R31(r1) 161 162 /* 163 * Okay, the exception code was stored in r0 and the original r0 164 * was stored in SPRG1. The original LR was stored 165 * in SPRG0. Fix things up. 166 */ 167 168 mfspr r0,SPR_SPRG0 169 mtlr r0 170 stw r0,XGR_LR(r1) 171 lwz r3,XGR_R0(r1) 172 mfspr r0,SPR_SPRG1 173 stw r0,XGR_R0(r1) 174 mr r4,r1 175 176 /* 177 * Reenable address translation, was disabled by the 178 * exception mechanism. 179 */ 180 181 mfmsr r0 182 ori r0,r0,(M_MSR_IR|M_MSR_DR) 183 mtmsr r0 184 185 /* 186 * R3 (arg1) is the exception vector number, and 187 * R4 (arg2) is the exception frame (stack pointer). 188 */ 189 190 bl cfe_exception 191 192 193 /* 194 * Stack pointer should still be valid. Restore everything. 195 */ 196 197 198 lwz r0,XGR_MSR(r1) 199 mtmsr r0 200 201 lwz r0,XGR_LR(r1) 202 mtlr r0 203 204 lwz r0,XGR_CTR(r1) 205 mtctr r0 206 207 lwz r0,XSPR_XER(r1) 208 mtxer r0 209 210 lwz r1,XGR_R1(r1) 211 lwz r2,XGR_R2(r1) 212 lwz r3,XGR_R3(r1) 213 lwz r4,XGR_R4(r1) 214 lwz r5,XGR_R5(r1) 215 lwz r6,XGR_R6(r1) 216 lwz r7,XGR_R7(r1) 217 lwz r8,XGR_R8(r1) 218 lwz r9,XGR_R9(r1) 219 lwz r10,XGR_R10(r1) 220 lwz r11,XGR_R11(r1) 221 lwz r12,XGR_R12(r1) 222 lwz r13,XGR_R13(r1) 223 lwz r14,XGR_R14(r1) 224 lwz r15,XGR_R15(r1) 225 lwz r16,XGR_R16(r1) 226 lwz r17,XGR_R17(r1) 227 lwz r18,XGR_R18(r1) 228 lwz r19,XGR_R19(r1) 229 lwz r20,XGR_R20(r1) 230 lwz r21,XGR_R21(r1) 231 lwz r22,XGR_R22(r1) 232 lwz r23,XGR_R23(r1) 233 lwz r24,XGR_R24(r1) 234 lwz r25,XGR_R25(r1) 235 lwz r26,XGR_R26(r1) 236 lwz r27,XGR_R27(r1) 237 lwz r28,XGR_R28(r1) 238 lwz r29,XGR_R29(r1) 239 lwz r30,XGR_R30(r1) 240 lwz r31,XGR_R31(r1) 241 242 lwz r0,XGR_R0(r1) 243 244 rfi 245 246 247END(_exc_entry) 248 249 250 251LEAF(_exc_continue) 252 253 mfmsr r0 /* set the RI bit in MSR to make us recoverable */ 254 LDCONST(r4,M_MSR_RI) 255 or r4,r4,r0 256 mtmsr r4 257 258 mtspr SPR_SRR0,r3 259 rfi 260 261END(_exc_continue) 262 263 264 265/* ********************************************************************* 266 * End 267 ********************************************************************* */ 268 269 270