1/*  *********************************************************************
2    *  PPC Board Support Package
3    *
4    *  Board-specific initialization		File: BMW_INIT.S
5    *
6    *  This module contains the assembly-language part of the init
7    *  code for this board support package.  The routine
8    *  "board_earlyinit" lives here.
9    *
10    *  This board support package is for the MPC8245 BMW board
11    *
12    *  Author:  Mitch Lichtenberg
13    *
14    *********************************************************************
15    *
16    *  Copyright 2000,2001,2002,2003
17    *  Broadcom Corporation. All rights reserved.
18    *
19    *  This software is furnished under license and may be used and
20    *  copied only in accordance with the following terms and
21    *  conditions.  Subject to these conditions, you may download,
22    *  copy, install, use, modify and distribute modified or unmodified
23    *  copies of this software in source and/or binary form.  No title
24    *  or ownership is transferred hereby.
25    *
26    *  1) Any source code used, modified or distributed must reproduce
27    *     and retain this copyright notice and list of conditions
28    *     as they appear in the source file.
29    *
30    *  2) No right is granted to use any trade name, trademark, or
31    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
32    *     name may not be used to endorse or promote products derived
33    *     from this software without the prior written permission of
34    *     Broadcom Corporation.
35    *
36    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
37    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
38    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
39    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
40    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
41    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
42    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
44    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
45    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
46    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
47    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
48    *     THE POSSIBILITY OF SUCH DAMAGE.
49    ********************************************************************* */
50
51
52#include "ppcdefs.h"
53#include "ppcmacros.h"
54#include "bsp_config.h"
55#include "bmw.h"
56#include "init_engine.h"
57#include "mpc824x.h"
58#include "sdram_spd.h"
59
60/*  *********************************************************************
61    *  Global Offset Table
62    ********************************************************************* */
63
64#if CFG_RELOC
65BEGIN_GOT()
66GOT_ENTRY(board_draminittab)
67END_GOT()
68#endif
69
70		.text
71
72/*  *********************************************************************
73    *  Macros
74    ********************************************************************* */
75
76#define DRAM_BASE	0
77
78/*  *********************************************************************
79    *  BOARD_EARLYINIT()
80    *
81    *  Initialize board registers.  This is the earliest
82    *  time the BSP gets control.  This routine cannot assume that
83    *  memory is operational, and therefore all code in this routine
84    *  must run from registers only.  The lr register must not
85    *  be modified, as it contains the return address.
86    *
87    *  This routine will be called from uncached space, before
88    *  the caches are initialized.
89    *
90    *  Among other things, this is where the GPIO registers get
91    *  programmed to make on-board LEDs function, or other startup
92    *  that has to be done before anything will work.
93    *
94    *  Input parameters:
95    *  	   nothing
96    *
97    *  Return value:
98    *  	   nothing
99    ********************************************************************* */
100
101LEAF(board_earlyinit)
102
103
104	blr
105
106END(board_earlyinit)
107
108
109/*  *********************************************************************
110    *  BOARD_DRAM_INIT
111    *
112    *  Initialize DRAM controller.
113    *
114    *  Input parameters:
115    *  	   nothing
116    *
117    *  Return value:
118    *  	   r3 - dram size in megabytes
119    ********************************************************************* */
120
121#define PCICW32(addr, data) LDCONST(r3, (addr)); LDCONST(r4, (data)); bl pci_conf_write_32
122
123#ifndef CFG_DRAM_ECC
124#define CFG_DRAM_ECC	0
125#endif
126
127#if CFG_DRAM_ECC
128#define MCCR1_ECC_BITS M_MCCR1_PCKEN
129#define MCCR2_ECC_BITS (M_MCCR2_WRPARCHK | M_MCCR2_INLPARNOECC | M_MCCR2_RMWPAR)
130#define MCCR3_ECC_BITS 0
131#define MCCR4_ECC_BITS M_MCCR4_BUFTYPE0
132#else
133#define MCCR1_ECC_BITS 0
134#define MCCR2_ECC_BITS 0
135#define MCCR3_ECC_BITS 0
136#define MCCR4_ECC_BITS M_MCCR4_BUFTYPE1
137#endif
138
139#define MC_MCCR_BSTOPRE 0x79
140
141/* Default memory configuration
142
143 This is the memory configuration that will be used if the SPD results
144 in an error.
145
146 Memory is specified in terms of the physical SDRAM architecture, such
147 as the number of rows and columns of the memory devices, as well as
148 the number of physical banks (chip selects). Due to the design of
149 both the MPC8245 and the BMW subsystem the parameter limits are as
150 follows:
151
152      SDRAM memory rows: 12 - 13        (SPD parameter #3)
153   SDRAM memory columns:  8 - 11        (SPD parameter #4)
154   SDRAM physical banks:  1 - 2         (SPD parameter #5)
155
156 The number of logical banks is fixed at 4.
157
158 Configurations tested:
159
160  Size   Rows   Columns  Banks
161 ------ ------- ------- -------
162  64MB       12       9       1
163 128MB       12       9       2
164 256MB       12      10       2
165
166 */
167
168#define SDRAM_ROWS      12
169#define SDRAM_COLUMNS    9
170#define SDRAM_BANKS      1
171
172/*
173  Calculate the size of a SDRAM physical bank in Megabytes. This size
174  is num_logical_banks * memory_module_bit_width * 2^(rows+columns) bits.
175  num_logical_banks is always 4 (2^2)
176  memory_module_bit_width is always 64 (2^6)
177  bits_per_byte is 8 (2^3)
178
179  2^(rows+columns)*(2^2)*(2^6)/(2^20 * 2^3) = 2^(rows+columns-15)
180
181*/
182
183#define SDRAM_BANK_SIZE  (1<<(SDRAM_ROWS + SDRAM_COLUMNS - 15))
184
185
186
187/* Set up MPC8245 memory configuration constants
188
189   Memory controller parameters are encoded from sdram_spd
190
191   Board info is encoded in 32 bits:
192
193   00000000001111111111222222222233
194   01234567890123456789012345678901
195   --------------------------------
196   ----------------slbrmmmm--------
197
198   s    SPD Probe Result
199         1 = SPD error
200         0 = SPD success
201   l    Logical banks
202         0 = 2 logical banks
203         1 = 4 logical banks
204   b    Physical banks
205         0 = 1 physical banks
206         1 = 2 physical banks
207   r    Device row addresses
208         0 = 4096 row addresses
209         1 = 8192 row addresses
210   m    Physical bank size in 64MB units
211         1 = 64MB
212         2 = 128MB
213         4 = 256MB
214         4 = 512MB
215 */
216
217#define MC1_ROW13_BANKBITS 0xAAAA
218
219#define MC2_REFINT_ROW12   0x3a5        /* Refresh Values are conservative */
220#define MC2_REFINT_ROW13   0x1d2
221
222#define MC_MSAR1_64   0x4000
223#define MC_XSAR1_64   0x0000
224#define MC_MEAR1_64   0x7f3f
225#define MC_XEAR1_64   0x0000
226#define BANK_SIZE_64      64
227
228#define MC_MSAR1_128  0x8000
229#define MC_XSAR1_128  0x0000
230#define MC_MEAR1_128  0xff7f
231#define MC_XEAR1_128  0x0000
232#define BANK_SIZE_128    128
233
234#define MC_MSAR1_256  0x0000
235#define MC_XSAR1_256  0x0100
236#define MC_MEAR1_256  0xffff
237#define MC_XEAR1_256  0x0100
238#define BANK_SIZE_256    256
239
240#define MC_MSAR1_512  0x0000
241#define MC_XSAR1_512  0x0200
242#define MC_MEAR1_512  0xffff
243#define MC_XEAR1_512  0x0301
244#define BANK_SIZE_512    512
245
246#if SDRAM_ROWS == 13
247#define MC1_BANKBITS MC1_ROW13_BANKBITS
248#define MEM_DEFAULT_ROW SPD_MEM_CONF_ROW
249#elif SDRAM_ROWS == 12
250#define MC1_BANKBITS 0x0000
251#define MEM_DEFAULT_ROW 0
252#else
253#error "SDRAM_ROWS must be 12 or 13"
254#endif /* SDRAM_ROWS */
255
256#if SDRAM_BANKS == 2
257#define MEM_DEFAULT_BANK SPD_MEM_CONF_BANK
258#elif SDRAM_BANKS == 1
259#define MEM_DEFAULT_BANK 0
260#else
261#error "SDRAM_BANKS must be 1 or 2"
262#endif /* SDRAM_BANKS */
263
264#define MEM_DEFAULT_SZ ((SDRAM_BANK_SIZE & 0x03C0)<<2)
265#define MEM_CONF_DEFAULT \
266  (SPD_MEM_CONF_LBNK|MEM_DEFAULT_ROW|MEM_DEFAULT_BANK|MEM_DEFAULT_SZ)
267
268LEAF(board_dram_init)
269
270	mflr	r29
271
272	/* LOAD_GOT trashes LR, but we saved it above. */
273	LOAD_GOT(GOT_REG)
274
275       	/*
276	 * Set up on-chip peripherals
277	 */
278
279 	PCICW32(MPC_EUMBBAR,A_BMW_EUMBBAR_VAL)
280
281
282	/*
283	 * Setup chip-select regions
284	 */
285
286	/* 0x84000000 */
287	PCICW32(MPC_ERCR1,(M_ERCR12_EN | V_ERCR12_DBW(K_ERCR12_DBW_8BIT) | V_ERCR12_CTL(K_ERCR12_CTL_BASE)))
288	PCICW32(MPC_ERCR2,(M_ERCR12_EN | V_ERCR12_DBW(K_ERCR12_DBW_8BIT) | V_ERCR12_CTL(K_ERCR12_CTL_BASE)))
289
290	PCICW32(MPC_ERCR3,((A_BMW_XROM & M_ERCR34_SADDR) | V_ERCR34_SIZE(K_ERCR34_SIZE_64K)))
291	PCICW32(MPC_ERCR4,((A_BMW_DOC & M_ERCR34_SADDR) | V_ERCR34_SIZE(K_ERCR34_SIZE_8K)))
292
293        /*
294         * Probe SDRAM for size
295         */
296#include "sdram_spd.s"
297
298	cmpi	0, 0, r3, 0
299        bgt     set_mem_config
300set_mem_default:
301        LDCONST(r3, (MEM_CONF_DEFAULT|SPD_MEM_CONF_ERR))
302set_mem_config:
303        mr r6, r3
304
305      	/*
306	 * Initialize memory controller.
307	 */
308
309        LDCONST(r3, MPC_MCCR1)
310	LDCONST(r4, V_MCCR1_ROMNAL(8) | V_MCCR1_ROMFAL(11) | M_MCCR1_SREN |
311	        MCCR1_ECC_BITS)
312
313        /* Check for 8192 row device detected/configured */
314        andi.   r7, r6, SPD_MEM_CONF_ROW
315        beq     set_mem_row_4096
316
317        /* 8192 rows */
318set_mem_row_8192:
319	ori	r4, r4, MC1_ROW13_BANKBITS
320        bl pci_conf_write_32
321
322        LDCONST(r3, MPC_MCCR2)
323	LDCONST(r4, V_MCCR2_TSWAIT(0) | V_MCCR2_ASRISE(8) | V_MCCR2_ASFALL(4) |
324		MCCR2_ECC_BITS |
325		V_MCCR2_REFINT(MC2_REFINT_ROW13))
326        bl pci_conf_write_32
327        b set_mem_row_done
328
329set_mem_row_4096:
330        bl pci_conf_write_32
331
332        LDCONST(r3, MPC_MCCR2)
333	LDCONST(r4, V_MCCR2_TSWAIT(0) | V_MCCR2_ASRISE(8) | V_MCCR2_ASFALL(4) |
334		MCCR2_ECC_BITS |
335		V_MCCR2_REFINT(MC2_REFINT_ROW12))
336        bl pci_conf_write_32
337
338set_mem_row_done:
339	PCICW32(MPC_MCCR3,V_MCCR3_BSTOPRE(((MC_MCCR_BSTOPRE >> 4) & 0x0F)) |
340		V_MCCR3_REFREC(8))
341
342	PCICW32(MPC_MCCR4,V_MCCR4_PRETOACT(3) | V_MCCR4_ACTOPRE(5) |
343		V_MCCR4_ACTORW(3) |
344		M_MCCR4_EXTROM |
345		M_MCCR4_DBUS_SIZE |
346                MCCR4_ECC_BITS |
347		V_MCCR4_BSTOPRE01((MC_MCCR_BSTOPRE >> 8) & 3) |
348		V_MCCR4_SDMODE(0x2) |
349		V_MCCR4_SDMODE_CAS(0x022) |
350		V_MCCR4_BSTOPRE69(MC_MCCR_BSTOPRE & 0x0F))
351#if CFG_DRAM_ECC
352	PCICW32(MPC_ERREN1,xxx)
353#endif
354
355        /* Set memory starting and ending addresses for banks 1 and 2
356
357           Register usage for this section:
358
359           r3:  scratch, arg1
360           r4:  scratch, arg2
361           r6:  SPD flags
362           r7:  SPD Bank size flags
363           r16: Bank size in MB - must not be modified by calls.
364
365        */
366
367        andi.   r7, r6, SPD_MEM_CONF_SZ
368
369bank_size_512:
370
371	cmpli	0, 0, r7, SPD_MEM_CONF_512
372        bne     bank_size_256
373
374        /* 512MB Bank */
375	PCICW32(MPC_MSAR1,  MC_MSAR1_512)
376	PCICW32(MPC_XMSAR1, MC_XSAR1_512)
377	PCICW32(MPC_MEAR1,  MC_MEAR1_512)
378	PCICW32(MPC_XMEAR1, MC_XEAR1_512)
379        LDCONST(r16, BANK_SIZE_512)
380
381        b       bank_size_done
382
383bank_size_256:
384
385	cmpli	0, 0, r7, SPD_MEM_CONF_256
386        bne     bank_size_128
387
388        /* 256MB Bank */
389	PCICW32(MPC_MSAR1,  MC_MSAR1_256)
390	PCICW32(MPC_XMSAR1, MC_XSAR1_256)
391	PCICW32(MPC_MEAR1,  MC_MEAR1_256)
392	PCICW32(MPC_XMEAR1, MC_XEAR1_256)
393        LDCONST(r16, BANK_SIZE_256)
394
395        b       bank_size_done
396
397bank_size_128:
398
399	cmpli	0, 0, r7, SPD_MEM_CONF_128
400        bne     bank_size_64
401
402        /* 128MB Bank */
403	PCICW32(MPC_MSAR1,  MC_MSAR1_128)
404	PCICW32(MPC_XMSAR1, MC_XSAR1_128)
405	PCICW32(MPC_MEAR1,  MC_MEAR1_128)
406	PCICW32(MPC_XMEAR1, MC_XEAR1_128)
407        LDCONST(r16, BANK_SIZE_128)
408
409        b       bank_size_done
410
411bank_size_64:
412
413        /* 64MB Bank */
414	PCICW32(MPC_MSAR1,  MC_MSAR1_64)
415	PCICW32(MPC_XMSAR1, MC_XSAR1_64)
416	PCICW32(MPC_MEAR1,  MC_MEAR1_64)
417	PCICW32(MPC_XMEAR1, MC_XEAR1_64)
418        LDCONST(r16, BANK_SIZE_64)
419
420bank_size_done:
421
422        /* Physical banks 4-7 are not used */
423	PCICW32(MPC_MSAR2,0xc0804000)
424	PCICW32(MPC_XMSAR2,0x01010101)
425	PCICW32(MPC_MEAR2,0xffbf7f3f)
426	PCICW32(MPC_XMEAR2,0x01010101)
427
428        /* Set the number of physical banks */
429        li      r4, 0x01                /* Enable the first bank by default */
430        andi.   r3, r6, SPD_MEM_CONF_BANK
431        beq     set_mem_num_bank
432	ori	r4, r4, 0x02		/* Enable the second banks, too */
433        add     r16, r16, r16           /* total memory size is 2 * bank size */
434set_mem_num_bank:
435        LDCONST(r3, MPC_MBEN)
436        bl      pci_conf_write_8
437
438	LDADDR(r6,board_draminittab)
439	bl	init_engine
440
441        mr      r3, r16
442	mtlr	r29
443
444	blr
445
446END(board_dram_init)
447
448
449
450/*  *********************************************************************
451    *  BOARD_SETLEDS(x)
452    *
453    *  Set LEDs for boot-time progress indication.  Not used if
454    *  the board does not have progress LEDs.  This routine
455    *  must not call any other routines.
456    *
457    *  Input parameters:
458    *  	   r3 - LED value (8 bits per character, 4 characters)
459    *
460    *  Return value:
461    *  	   nothing
462    *
463    *  Registers used:
464    *  	   r3,r5,r6
465    ********************************************************************* */
466
467
468LEAF(board_setleds)
469#if 1
470	LDCONST(r5,A_BMW_LED)
471
472
473	rlwinm	r3,r3,8,0,31
474	stb	r3,3(r5)
475	sync
476
477	rlwinm	r3,r3,8,0,31
478	stb	r3,2(r5)
479	sync
480
481	rlwinm	r3,r3,8,0,31
482	stb	r3,1(r5)
483	sync
484
485	rlwinm	r3,r3,8,0,31
486	stb	r3,0(r5)
487	sync
488
489#endif
490
491	blr
492
493END(board_setleds)
494
495
496
497/*  *********************************************************************
498    *  Initialization table for memory controller.
499    *
500    *  This table is processsed by the "init_engine" to
501    *  orchestrate writes to PCI space and CPU MSRs.
502    ********************************************************************* */
503
504#define DRAM_BASE	0
505
506board_draminittab:
507
508	IET_PCI8(MPC_ODCR,0x7f)
509
510	IET_DELAY(0x10000)
511	IET_PCI32X(MPC_MCCR1,0xFFFFFFFF,M_MCCR1_MEMGO)
512	IET_DELAY(0x30000)
513
514	/*
515	 * Done with memory controller.
516	 */
517
518	/*
519	 * setup BATs
520	 */
521
522	/* BAT 0 : SDRAM */
523	IET_IBAT(0,(DRAM_BASE | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
524		   (DRAM_BASE | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_MEMCOHERENCE))
525	IET_DBAT(0,(DRAM_BASE | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
526		   (DRAM_BASE | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_MEMCOHERENCE))
527
528        /* BAT 1 : DOC */
529	IET_IBAT(1,(0x70000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
530		   (0x70000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
531	IET_DBAT(1,(0x70000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
532		   (0x70000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
533
534        /* BAT 2 : PCI, EUMBAR */
535	IET_IBAT(2,(0x80000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
536		   (0x80000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
537	IET_DBAT(2,(0x80000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
538		   (0x80000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
539
540        /* BAT 3 : FLASH, PLD */
541	IET_IBAT(3,(0xF0000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
542		   (0xF0000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
543	IET_DBAT(3,(0xF0000000 | V_BATU_BL(K_BATU_BL_256M) | M_BATU_VS | M_BATU_VP),
544		   (0xF0000000 | V_BATL_PP(K_BATL_PP_RDWR) | M_BATL_INHIBIT))
545
546
547	IET_ENABBATS()
548
549	IET_ENABDCACHE()
550
551	IET_EOT()
552
553
554/*  *********************************************************************
555    *  Random little routines to read/write MSRs
556    ********************************************************************* */
557
558	.globl read_hid1
559read_hid1:
560
561	mfspr r3,SPR_HID1
562	blr
563
564	.globl read_hid0
565read_hid0:
566
567	mfspr r3,SPR_HID0
568	blr
569
570	.globl write_hid0
571write_hid0:
572
573	isync
574	mtspr SPR_HID0,r3
575	sync
576	isync
577	eieio
578	blr
579
580	.globl read_msr
581read_msr:
582
583	mfmsr r3
584	blr
585
586	.globl write_msr
587write_msr:
588
589	isync
590	mtmsr r3
591	sync
592	isync
593	eieio
594	blr
595
596        .globl pci_write_32
597pci_conf_write_32:
598
599        LDCONST(r5,A_MPC_CONFIG_ADDR)
600	stwbrx	r3,0,r5
601	sync
602	LDCONST(r5,A_MPC_CONFIG_DATA)
603	stwbrx	r4,0,r5
604	sync
605        blr
606
607        .globl pci_write_8
608pci_conf_write_8:
609
610        LDCONST(r5,A_MPC_CONFIG_ADDR)
611	stwbrx	r3,0,r5
612	sync
613	LDCONST(r5,A_MPC_CONFIG_DATA)
614	stb	r4,0(r5)
615	sync
616        blr
617
618	.globl eumbbar_read
619eumbbar_read:
620
621        lis     r4, A_BMW_EUMBBAR_VAL>>16
622        sync
623        lwbrx   r3, r3, r4
624        blr
625
626
627	.globl eumbbar_write
628eumbbar_write:
629
630        lis     r5, A_BMW_EUMBBAR_VAL>>16
631        stwbrx  r4, r3, r5
632        sync
633        blr
634