1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * Register Definitions File: sb1250_regs.h 5 * 6 * This module contains the addresses of the on-chip peripherals 7 * on the SB1250. 8 * 9 * SB1250 specification level: 01/02/2002 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49#ifndef _SB1250_REGS_H 50#define _SB1250_REGS_H 51 52#include "sb1250_defs.h" 53 54 55/* ********************************************************************* 56 * Some general notes: 57 * 58 * For the most part, when there is more than one peripheral 59 * of the same type on the SOC, the constants below will be 60 * offsets from the base of each peripheral. For example, 61 * the MAC registers are described as offsets from the first 62 * MAC register, and there will be a MAC_REGISTER() macro 63 * to calculate the base address of a given MAC. 64 * 65 * The information in this file is based on the SB1250 SOC 66 * manual version 0.2, July 2000. 67 ********************************************************************* */ 68 69 70/* ********************************************************************* 71 * Memory Controller Registers 72 ********************************************************************* */ 73 74/* 75 * XXX: can't remove MC base 0 if 112x, since it's used by other macros, 76 * since there is one reg there (but it could get its addr/offset constant). 77 */ 78 79#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ 80#define A_MC_BASE_0 0x0010051000 81#define A_MC_BASE_1 0x0010052000 82#define MC_REGISTER_SPACING 0x1000 83 84#define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) 85#define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) 86 87#define R_MC_CONFIG 0x0000000100 88#define R_MC_DRAMCMD 0x0000000120 89#define R_MC_DRAMMODE 0x0000000140 90#define R_MC_TIMING1 0x0000000160 91#define R_MC_TIMING2 0x0000000180 92#define R_MC_CS_START 0x00000001A0 93#define R_MC_CS_END 0x00000001C0 94#define R_MC_CS_INTERLEAVE 0x00000001E0 95#define S_MC_CS_STARTEND 16 96 97#define R_MC_CSX_BASE 0x0000000200 98#define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ 99#define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ 100#define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ 101#define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ 102 103#define R_MC_CS0_ROW 0x0000000200 104#define R_MC_CS0_COL 0x0000000220 105#define R_MC_CS0_BA 0x0000000240 106#define R_MC_CS1_ROW 0x0000000260 107#define R_MC_CS1_COL 0x0000000280 108#define R_MC_CS1_BA 0x00000002A0 109#define R_MC_CS2_ROW 0x00000002C0 110#define R_MC_CS2_COL 0x00000002E0 111#define R_MC_CS2_BA 0x0000000300 112#define R_MC_CS3_ROW 0x0000000320 113#define R_MC_CS3_COL 0x0000000340 114#define R_MC_CS3_BA 0x0000000360 115#define R_MC_CS_ATTR 0x0000000380 116#define R_MC_TEST_DATA 0x0000000400 117#define R_MC_TEST_ECC 0x0000000420 118#define R_MC_MCLK_CFG 0x0000000500 119 120#endif /* 1250 & 112x */ 121 122/* ********************************************************************* 123 * L2 Cache Control Registers 124 ********************************************************************* */ 125 126#if SIBYTE_HDR_FEATURE_1250_112x /* This L2C only on 1250/112x */ 127 128#define A_L2_READ_TAG 0x0010040018 129#define A_L2_ECC_TAG 0x0010040038 130#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 131#define A_L2_READ_MISC 0x0010040058 132#endif /* 1250 PASS3 || 112x PASS1 */ 133#define A_L2_WAY_DISABLE 0x0010041000 134#define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) 135#define A_L2_MGMT_TAG_BASE 0x00D0000000 136 137#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 138#define A_L2_CACHE_DISABLE 0x0010042000 139#define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) 140#define A_L2_MISC_CONFIG 0x0010043000 141#endif /* 1250 PASS2 || 112x PASS1 */ 142 143/* Backward-compatibility definitions. */ 144/* XXX: discourage people from using these constants. */ 145#define A_L2_READ_ADDRESS A_L2_READ_TAG 146#define A_L2_EEC_ADDRESS A_L2_ECC_TAG 147 148#endif 149 150 151/* ********************************************************************* 152 * PCI Interface Registers 153 ********************************************************************* */ 154 155#if SIBYTE_HDR_FEATURE_1250_112x /* This PCI/HT only on 1250/112x */ 156#define A_PCI_TYPE00_HEADER 0x00DE000000 157#define A_PCI_TYPE01_HEADER 0x00DE000800 158#endif 159 160 161/* ********************************************************************* 162 * Ethernet DMA and MACs 163 ********************************************************************* */ 164 165#define A_MAC_BASE_0 0x0010064000 166#define A_MAC_BASE_1 0x0010065000 167#if SIBYTE_HDR_FEATURE_CHIP(1250) 168#define A_MAC_BASE_2 0x0010066000 169#endif /* 1250 */ 170 171#define MAC_SPACING 0x1000 172#define MAC_DMA_TXRX_SPACING 0x0400 173#define MAC_DMA_CHANNEL_SPACING 0x0100 174#define DMA_RX 0 175#define DMA_TX 1 176#define MAC_NUM_DMACHAN 2 /* channels per direction */ 177 178/* XXX: not correct; depends on SOC type. */ 179#define MAC_NUM_PORTS 3 180 181#define A_MAC_CHANNEL_BASE(macnum) \ 182 (A_MAC_BASE_0 + \ 183 MAC_SPACING*(macnum)) 184 185#define A_MAC_REGISTER(macnum,reg) \ 186 (A_MAC_BASE_0 + \ 187 MAC_SPACING*(macnum) + (reg)) 188 189 190#define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ 191 192#define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ 193 ((A_MAC_CHANNEL_BASE(macnum)) + \ 194 R_MAC_DMA_CHANNELS + \ 195 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 196 (MAC_DMA_CHANNEL_SPACING*(chan))) 197 198#define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ 199 (R_MAC_DMA_CHANNELS + \ 200 (MAC_DMA_TXRX_SPACING*(txrx)) + \ 201 (MAC_DMA_CHANNEL_SPACING*(chan))) 202 203#define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ 204 (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ 205 (reg)) 206 207#define R_MAC_DMA_REGISTER(txrx,chan,reg) \ 208 (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ 209 (reg)) 210 211/* 212 * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE 213 */ 214 215#define R_MAC_DMA_CONFIG0 0x00000000 216#define R_MAC_DMA_CONFIG1 0x00000008 217#define R_MAC_DMA_DSCR_BASE 0x00000010 218#define R_MAC_DMA_DSCR_CNT 0x00000018 219#define R_MAC_DMA_CUR_DSCRA 0x00000020 220#define R_MAC_DMA_CUR_DSCRB 0x00000028 221#define R_MAC_DMA_CUR_DSCRADDR 0x00000030 222#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 223#define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ 224#endif /* 1250 PASS3 || 112x PASS1 */ 225 226/* 227 * RMON Counters 228 */ 229 230#define R_MAC_RMON_TX_BYTES 0x00000000 231#define R_MAC_RMON_COLLISIONS 0x00000008 232#define R_MAC_RMON_LATE_COL 0x00000010 233#define R_MAC_RMON_EX_COL 0x00000018 234#define R_MAC_RMON_FCS_ERROR 0x00000020 235#define R_MAC_RMON_TX_ABORT 0x00000028 236/* Counter #6 (0x30) now reserved */ 237#define R_MAC_RMON_TX_BAD 0x00000038 238#define R_MAC_RMON_TX_GOOD 0x00000040 239#define R_MAC_RMON_TX_RUNT 0x00000048 240#define R_MAC_RMON_TX_OVERSIZE 0x00000050 241#define R_MAC_RMON_RX_BYTES 0x00000080 242#define R_MAC_RMON_RX_MCAST 0x00000088 243#define R_MAC_RMON_RX_BCAST 0x00000090 244#define R_MAC_RMON_RX_BAD 0x00000098 245#define R_MAC_RMON_RX_GOOD 0x000000A0 246#define R_MAC_RMON_RX_RUNT 0x000000A8 247#define R_MAC_RMON_RX_OVERSIZE 0x000000B0 248#define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 249#define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 250#define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 251#define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 252 253/* Updated to spec 0.2 */ 254#define R_MAC_CFG 0x00000100 255#define R_MAC_THRSH_CFG 0x00000108 256#define R_MAC_VLANTAG 0x00000110 257#define R_MAC_FRAMECFG 0x00000118 258#define R_MAC_EOPCNT 0x00000120 259#define R_MAC_FIFO_PTRS 0x00000128 260#define R_MAC_ADFILTER_CFG 0x00000200 261#define R_MAC_ETHERNET_ADDR 0x00000208 262#define R_MAC_PKT_TYPE 0x00000210 263#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 264#define R_MAC_ADMASK0 0x00000218 265#define R_MAC_ADMASK1 0x00000220 266#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 267#define R_MAC_HASH_BASE 0x00000240 268#define R_MAC_ADDR_BASE 0x00000280 269#define R_MAC_CHLO0_BASE 0x00000300 270#define R_MAC_CHUP0_BASE 0x00000320 271#define R_MAC_ENABLE 0x00000400 272#define R_MAC_STATUS 0x00000408 273#define R_MAC_INT_MASK 0x00000410 274#define R_MAC_TXD_CTL 0x00000420 275#define R_MAC_MDIO 0x00000428 276#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 277#define R_MAC_STATUS1 0x00000430 278#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 279#define R_MAC_DEBUG_STATUS 0x00000448 280 281#define MAC_HASH_COUNT 8 282#define MAC_ADDR_COUNT 8 283#define MAC_CHMAP_COUNT 4 284 285 286/* ********************************************************************* 287 * DUART Registers 288 ********************************************************************* */ 289 290 291#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ 292#define R_DUART_NUM_PORTS 2 293 294#define A_DUART 0x0010060000 295 296#define DUART_CHANREG_SPACING 0x100 297#define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) 298#define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) 299#endif /* 1250 & 112x */ 300 301#define R_DUART_MODE_REG_1 0x100 302#define R_DUART_MODE_REG_2 0x110 303#define R_DUART_STATUS 0x120 304#define R_DUART_CLK_SEL 0x130 305#define R_DUART_CMD 0x150 306#define R_DUART_RX_HOLD 0x160 307#define R_DUART_TX_HOLD 0x170 308 309#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 310#define R_DUART_FULL_CTL 0x140 311#define R_DUART_OPCR_X 0x180 312#define R_DUART_AUXCTL_X 0x190 313#endif /* 1250 PASS2 || 112x PASS1 || 1480*/ 314 315 316/* 317 * The IMR and ISR can't be addressed with A_DUART_CHANREG, 318 * so use this macro instead. 319 */ 320 321#define R_DUART_AUX_CTRL 0x310 322#define R_DUART_ISR_A 0x320 323#define R_DUART_IMR_A 0x330 324#define R_DUART_ISR_B 0x340 325#define R_DUART_IMR_B 0x350 326#define R_DUART_OUT_PORT 0x360 327#define R_DUART_OPCR 0x370 328#define R_DUART_IN_PORT 0x380 329 330#define R_DUART_SET_OPR 0x3B0 331#define R_DUART_CLEAR_OPR 0x3C0 332 333#define DUART_IMRISR_SPACING 0x20 334 335#if SIBYTE_HDR_FEATURE_1250_112x /* This MC only on 1250 & 112x */ 336#define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) 337#define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) 338 339#define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) 340#define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) 341#endif /* 1250 & 112x */ 342 343 344 345 346/* 347 * These constants are the absolute addresses. 348 */ 349 350#define A_DUART_MODE_REG_1_A 0x0010060100 351#define A_DUART_MODE_REG_2_A 0x0010060110 352#define A_DUART_STATUS_A 0x0010060120 353#define A_DUART_CLK_SEL_A 0x0010060130 354#define A_DUART_CMD_A 0x0010060150 355#define A_DUART_RX_HOLD_A 0x0010060160 356#define A_DUART_TX_HOLD_A 0x0010060170 357 358#define A_DUART_MODE_REG_1_B 0x0010060200 359#define A_DUART_MODE_REG_2_B 0x0010060210 360#define A_DUART_STATUS_B 0x0010060220 361#define A_DUART_CLK_SEL_B 0x0010060230 362#define A_DUART_CMD_B 0x0010060250 363#define A_DUART_RX_HOLD_B 0x0010060260 364#define A_DUART_TX_HOLD_B 0x0010060270 365 366#define A_DUART_INPORT_CHNG 0x0010060300 367#define A_DUART_AUX_CTRL 0x0010060310 368#define A_DUART_ISR_A 0x0010060320 369#define A_DUART_IMR_A 0x0010060330 370#define A_DUART_ISR_B 0x0010060340 371#define A_DUART_IMR_B 0x0010060350 372#define A_DUART_OUT_PORT 0x0010060360 373#define A_DUART_OPCR 0x0010060370 374#define A_DUART_IN_PORT 0x0010060380 375#define A_DUART_ISR 0x0010060390 376#define A_DUART_IMR 0x00100603A0 377#define A_DUART_SET_OPR 0x00100603B0 378#define A_DUART_CLEAR_OPR 0x00100603C0 379#define A_DUART_INPORT_CHNG_A 0x00100603D0 380#define A_DUART_INPORT_CHNG_B 0x00100603E0 381 382#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 383#define A_DUART_FULL_CTL_A 0x0010060140 384#define A_DUART_FULL_CTL_B 0x0010060240 385 386#define A_DUART_OPCR_A 0x0010060180 387#define A_DUART_OPCR_B 0x0010060280 388 389#define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 390#endif /* 1250 PASS2 || 112x PASS1 */ 391 392 393/* ********************************************************************* 394 * Synchronous Serial Registers 395 ********************************************************************* */ 396 397 398#if SIBYTE_HDR_FEATURE_1250_112x /* sync serial only on 1250/112x */ 399 400#define A_SER_BASE_0 0x0010060400 401#define A_SER_BASE_1 0x0010060800 402#define SER_SPACING 0x400 403 404#define SER_DMA_TXRX_SPACING 0x80 405 406#define SER_NUM_PORTS 2 407 408#define A_SER_CHANNEL_BASE(sernum) \ 409 (A_SER_BASE_0 + \ 410 SER_SPACING*(sernum)) 411 412#define A_SER_REGISTER(sernum,reg) \ 413 (A_SER_BASE_0 + \ 414 SER_SPACING*(sernum) + (reg)) 415 416 417#define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ 418 419#define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ 420 ((A_SER_CHANNEL_BASE(sernum)) + \ 421 R_SER_DMA_CHANNELS + \ 422 (SER_DMA_TXRX_SPACING*(txrx))) 423 424#define A_SER_DMA_REGISTER(sernum,txrx,reg) \ 425 (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ 426 (reg)) 427 428 429/* 430 * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE 431 */ 432 433#define R_SER_DMA_CONFIG0 0x00000000 434#define R_SER_DMA_CONFIG1 0x00000008 435#define R_SER_DMA_DSCR_BASE 0x00000010 436#define R_SER_DMA_DSCR_CNT 0x00000018 437#define R_SER_DMA_CUR_DSCRA 0x00000020 438#define R_SER_DMA_CUR_DSCRB 0x00000028 439#define R_SER_DMA_CUR_DSCRADDR 0x00000030 440 441#define R_SER_DMA_CONFIG0_RX 0x00000000 442#define R_SER_DMA_CONFIG1_RX 0x00000008 443#define R_SER_DMA_DSCR_BASE_RX 0x00000010 444#define R_SER_DMA_DSCR_COUNT_RX 0x00000018 445#define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 446#define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 447#define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 448 449#define R_SER_DMA_CONFIG0_TX 0x00000080 450#define R_SER_DMA_CONFIG1_TX 0x00000088 451#define R_SER_DMA_DSCR_BASE_TX 0x00000090 452#define R_SER_DMA_DSCR_COUNT_TX 0x00000098 453#define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 454#define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 455#define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 456 457#define R_SER_MODE 0x00000100 458#define R_SER_MINFRM_SZ 0x00000108 459#define R_SER_MAXFRM_SZ 0x00000110 460#define R_SER_ADDR 0x00000118 461#define R_SER_USR0_ADDR 0x00000120 462#define R_SER_USR1_ADDR 0x00000128 463#define R_SER_USR2_ADDR 0x00000130 464#define R_SER_USR3_ADDR 0x00000138 465#define R_SER_CMD 0x00000140 466#define R_SER_TX_RD_THRSH 0x00000160 467#define R_SER_TX_WR_THRSH 0x00000168 468#define R_SER_RX_RD_THRSH 0x00000170 469#define R_SER_LINE_MODE 0x00000178 470#define R_SER_DMA_ENABLE 0x00000180 471#define R_SER_INT_MASK 0x00000190 472#define R_SER_STATUS 0x00000188 473#define R_SER_STATUS_DEBUG 0x000001A8 474#define R_SER_RX_TABLE_BASE 0x00000200 475#define SER_RX_TABLE_COUNT 16 476#define R_SER_TX_TABLE_BASE 0x00000300 477#define SER_TX_TABLE_COUNT 16 478 479/* RMON Counters */ 480#define R_SER_RMON_TX_BYTE_LO 0x000001C0 481#define R_SER_RMON_TX_BYTE_HI 0x000001C8 482#define R_SER_RMON_RX_BYTE_LO 0x000001D0 483#define R_SER_RMON_RX_BYTE_HI 0x000001D8 484#define R_SER_RMON_TX_UNDERRUN 0x000001E0 485#define R_SER_RMON_RX_OVERFLOW 0x000001E8 486#define R_SER_RMON_RX_ERRORS 0x000001F0 487#define R_SER_RMON_RX_BADADDR 0x000001F8 488 489#endif /* 1250/112x */ 490 491/* ********************************************************************* 492 * Generic Bus Registers 493 ********************************************************************* */ 494 495#define IO_EXT_CFG_COUNT 8 496 497#define A_IO_EXT_BASE 0x0010061000 498#define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) 499 500#define A_IO_EXT_CFG_BASE 0x0010061000 501#define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 502#define A_IO_EXT_START_ADDR_BASE 0x0010061200 503#define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 504#define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 505 506#define IO_EXT_REGISTER_SPACING 8 507#define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) 508#define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) 509 510#define R_IO_EXT_CFG 0x0000 511#define R_IO_EXT_MULT_SIZE 0x0100 512#define R_IO_EXT_START_ADDR 0x0200 513#define R_IO_EXT_TIME_CFG0 0x0600 514#define R_IO_EXT_TIME_CFG1 0x0700 515 516 517#define A_IO_INTERRUPT_STATUS 0x0010061A00 518#define A_IO_INTERRUPT_DATA0 0x0010061A10 519#define A_IO_INTERRUPT_DATA1 0x0010061A18 520#define A_IO_INTERRUPT_DATA2 0x0010061A20 521#define A_IO_INTERRUPT_DATA3 0x0010061A28 522#define A_IO_INTERRUPT_ADDR0 0x0010061A30 523#define A_IO_INTERRUPT_ADDR1 0x0010061A40 524#define A_IO_INTERRUPT_PARITY 0x0010061A50 525#define A_IO_PCMCIA_CFG 0x0010061A60 526#define A_IO_PCMCIA_STATUS 0x0010061A70 527#define A_IO_DRIVE_0 0x0010061300 528#define A_IO_DRIVE_1 0x0010061308 529#define A_IO_DRIVE_2 0x0010061310 530#define A_IO_DRIVE_3 0x0010061318 531#define A_IO_DRIVE_BASE A_IO_DRIVE_0 532#define IO_DRIVE_REGISTER_SPACING 8 533#define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) 534#define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) 535 536#define R_IO_INTERRUPT_STATUS 0x0A00 537#define R_IO_INTERRUPT_DATA0 0x0A10 538#define R_IO_INTERRUPT_DATA1 0x0A18 539#define R_IO_INTERRUPT_DATA2 0x0A20 540#define R_IO_INTERRUPT_DATA3 0x0A28 541#define R_IO_INTERRUPT_ADDR0 0x0A30 542#define R_IO_INTERRUPT_ADDR1 0x0A40 543#define R_IO_INTERRUPT_PARITY 0x0A50 544#define R_IO_PCMCIA_CFG 0x0A60 545#define R_IO_PCMCIA_STATUS 0x0A70 546 547/* ********************************************************************* 548 * GPIO Registers 549 ********************************************************************* */ 550 551#define A_GPIO_CLR_EDGE 0x0010061A80 552#define A_GPIO_INT_TYPE 0x0010061A88 553#define A_GPIO_INPUT_INVERT 0x0010061A90 554#define A_GPIO_GLITCH 0x0010061A98 555#define A_GPIO_READ 0x0010061AA0 556#define A_GPIO_DIRECTION 0x0010061AA8 557#define A_GPIO_PIN_CLR 0x0010061AB0 558#define A_GPIO_PIN_SET 0x0010061AB8 559 560#define A_GPIO_BASE 0x0010061A80 561 562#define R_GPIO_CLR_EDGE 0x00 563#define R_GPIO_INT_TYPE 0x08 564#define R_GPIO_INPUT_INVERT 0x10 565#define R_GPIO_GLITCH 0x18 566#define R_GPIO_READ 0x20 567#define R_GPIO_DIRECTION 0x28 568#define R_GPIO_PIN_CLR 0x30 569#define R_GPIO_PIN_SET 0x38 570 571/* ********************************************************************* 572 * SMBus Registers 573 ********************************************************************* */ 574 575#define A_SMB_XTRA_0 0x0010060000 576#define A_SMB_XTRA_1 0x0010060008 577#define A_SMB_FREQ_0 0x0010060010 578#define A_SMB_FREQ_1 0x0010060018 579#define A_SMB_STATUS_0 0x0010060020 580#define A_SMB_STATUS_1 0x0010060028 581#define A_SMB_CMD_0 0x0010060030 582#define A_SMB_CMD_1 0x0010060038 583#define A_SMB_START_0 0x0010060040 584#define A_SMB_START_1 0x0010060048 585#define A_SMB_DATA_0 0x0010060050 586#define A_SMB_DATA_1 0x0010060058 587#define A_SMB_CONTROL_0 0x0010060060 588#define A_SMB_CONTROL_1 0x0010060068 589#define A_SMB_PEC_0 0x0010060070 590#define A_SMB_PEC_1 0x0010060078 591 592#define A_SMB_0 0x0010060000 593#define A_SMB_1 0x0010060008 594#define SMB_REGISTER_SPACING 0x8 595#define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) 596#define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) 597 598#define R_SMB_XTRA 0x0000000000 599#define R_SMB_FREQ 0x0000000010 600#define R_SMB_STATUS 0x0000000020 601#define R_SMB_CMD 0x0000000030 602#define R_SMB_START 0x0000000040 603#define R_SMB_DATA 0x0000000050 604#define R_SMB_CONTROL 0x0000000060 605#define R_SMB_PEC 0x0000000070 606 607/* ********************************************************************* 608 * Timer Registers 609 ********************************************************************* */ 610 611/* 612 * Watchdog timers 613 */ 614 615#define A_SCD_WDOG_0 0x0010020050 616#define A_SCD_WDOG_1 0x0010020150 617#define SCD_WDOG_SPACING 0x100 618#define SCD_NUM_WDOGS 2 619#define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) 620#define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) 621 622#define R_SCD_WDOG_INIT 0x0000000000 623#define R_SCD_WDOG_CNT 0x0000000008 624#define R_SCD_WDOG_CFG 0x0000000010 625 626#define A_SCD_WDOG_INIT_0 0x0010020050 627#define A_SCD_WDOG_CNT_0 0x0010020058 628#define A_SCD_WDOG_CFG_0 0x0010020060 629 630#define A_SCD_WDOG_INIT_1 0x0010020150 631#define A_SCD_WDOG_CNT_1 0x0010020158 632#define A_SCD_WDOG_CFG_1 0x0010020160 633 634/* 635 * Generic timers 636 */ 637 638#define A_SCD_TIMER_0 0x0010020070 639#define A_SCD_TIMER_1 0x0010020078 640#define A_SCD_TIMER_2 0x0010020170 641#define A_SCD_TIMER_3 0x0010020178 642#define SCD_NUM_TIMERS 4 643#define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) 644#define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) 645 646#define R_SCD_TIMER_INIT 0x0000000000 647#define R_SCD_TIMER_CNT 0x0000000010 648#define R_SCD_TIMER_CFG 0x0000000020 649 650#define A_SCD_TIMER_INIT_0 0x0010020070 651#define A_SCD_TIMER_CNT_0 0x0010020080 652#define A_SCD_TIMER_CFG_0 0x0010020090 653 654#define A_SCD_TIMER_INIT_1 0x0010020078 655#define A_SCD_TIMER_CNT_1 0x0010020088 656#define A_SCD_TIMER_CFG_1 0x0010020098 657 658#define A_SCD_TIMER_INIT_2 0x0010020170 659#define A_SCD_TIMER_CNT_2 0x0010020180 660#define A_SCD_TIMER_CFG_2 0x0010020190 661 662#define A_SCD_TIMER_INIT_3 0x0010020178 663#define A_SCD_TIMER_CNT_3 0x0010020188 664#define A_SCD_TIMER_CFG_3 0x0010020198 665 666#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 667#define A_SCD_SCRATCH 0x0010020C10 668#endif /* 1250 PASS2 || 112x PASS1 */ 669 670#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 671#define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 672#define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 673#define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 674#endif 675 676/* ********************************************************************* 677 * System Control Registers 678 ********************************************************************* */ 679 680#define A_SCD_SYSTEM_REVISION 0x0010020000 681#define A_SCD_SYSTEM_CFG 0x0010020008 682#define A_SCD_SYSTEM_MANUF 0x0010038000 683 684/* ********************************************************************* 685 * System Address Trap Registers 686 ********************************************************************* */ 687 688#define A_ADDR_TRAP_INDEX 0x00100200B0 689#define A_ADDR_TRAP_REG 0x00100200B8 690#define A_ADDR_TRAP_UP_0 0x0010020400 691#define A_ADDR_TRAP_UP_1 0x0010020408 692#define A_ADDR_TRAP_UP_2 0x0010020410 693#define A_ADDR_TRAP_UP_3 0x0010020418 694#define A_ADDR_TRAP_DOWN_0 0x0010020420 695#define A_ADDR_TRAP_DOWN_1 0x0010020428 696#define A_ADDR_TRAP_DOWN_2 0x0010020430 697#define A_ADDR_TRAP_DOWN_3 0x0010020438 698#define A_ADDR_TRAP_CFG_0 0x0010020440 699#define A_ADDR_TRAP_CFG_1 0x0010020448 700#define A_ADDR_TRAP_CFG_2 0x0010020450 701#define A_ADDR_TRAP_CFG_3 0x0010020458 702#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 703#define A_ADDR_TRAP_REG_DEBUG 0x0010020460 704#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 705 706#define ADDR_TRAP_SPACING 8 707#define NUM_ADDR_TRAP 4 708#define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING)) 709#define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING)) 710#define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING)) 711 712 713/* ********************************************************************* 714 * System Interrupt Mapper Registers 715 ********************************************************************* */ 716 717#define A_IMR_CPU0_BASE 0x0010020000 718#define A_IMR_CPU1_BASE 0x0010022000 719#define IMR_REGISTER_SPACING 0x2000 720#define IMR_REGISTER_SPACING_SHIFT 13 721 722#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) 723#define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) 724 725#define R_IMR_INTERRUPT_DIAG 0x0010 726#define R_IMR_INTERRUPT_LDT 0x0018 727#define R_IMR_INTERRUPT_MASK 0x0028 728#define R_IMR_INTERRUPT_TRACE 0x0038 729#define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 730#define R_IMR_LDT_INTERRUPT_SET 0x0048 731#define R_IMR_LDT_INTERRUPT 0x0018 732#define R_IMR_LDT_INTERRUPT_CLR 0x0020 733#define R_IMR_MAILBOX_CPU 0x00c0 734#define R_IMR_ALIAS_MAILBOX_CPU 0x1000 735#define R_IMR_MAILBOX_SET_CPU 0x00C8 736#define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 737#define R_IMR_MAILBOX_CLR_CPU 0x00D0 738#define R_IMR_INTERRUPT_STATUS_BASE 0x0100 739#define R_IMR_INTERRUPT_STATUS_COUNT 7 740#define R_IMR_INTERRUPT_MAP_BASE 0x0200 741#define R_IMR_INTERRUPT_MAP_COUNT 64 742 743/* 744 * these macros work together to build the address of a mailbox 745 * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1) 746 * for mbox_0_set_cpu2 returns 0x00100240C8 747 */ 748#define A_MAILBOX_REGISTER(reg,cpu) \ 749 (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg) 750 751/* ********************************************************************* 752 * System Performance Counter Registers 753 ********************************************************************* */ 754 755#define A_SCD_PERF_CNT_CFG 0x00100204C0 756#define A_SCD_PERF_CNT_0 0x00100204D0 757#define A_SCD_PERF_CNT_1 0x00100204D8 758#define A_SCD_PERF_CNT_2 0x00100204E0 759#define A_SCD_PERF_CNT_3 0x00100204E8 760 761#define SCD_NUM_PERF_CNT 4 762#define SCD_PERF_CNT_SPACING 8 763#define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING)) 764 765/* ********************************************************************* 766 * System Bus Watcher Registers 767 ********************************************************************* */ 768 769#define A_SCD_BUS_ERR_STATUS 0x0010020880 770#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) 771#define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 772#define A_BUS_ERR_STATUS_DEBUG 0x00100208D0 773#endif /* 1250 PASS2 || 112x PASS1 */ 774#define A_BUS_ERR_DATA_0 0x00100208A0 775#define A_BUS_ERR_DATA_1 0x00100208A8 776#define A_BUS_ERR_DATA_2 0x00100208B0 777#define A_BUS_ERR_DATA_3 0x00100208B8 778#define A_BUS_L2_ERRORS 0x00100208C0 779#define A_BUS_MEM_IO_ERRORS 0x00100208C8 780 781/* ********************************************************************* 782 * System Debug Controller Registers 783 ********************************************************************* */ 784 785#define A_SCD_JTAG_BASE 0x0010000000 786 787/* ********************************************************************* 788 * System Trace Buffer Registers 789 ********************************************************************* */ 790 791#define A_SCD_TRACE_CFG 0x0010020A00 792#define A_SCD_TRACE_READ 0x0010020A08 793#define A_SCD_TRACE_EVENT_0 0x0010020A20 794#define A_SCD_TRACE_EVENT_1 0x0010020A28 795#define A_SCD_TRACE_EVENT_2 0x0010020A30 796#define A_SCD_TRACE_EVENT_3 0x0010020A38 797#define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 798#define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 799#define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 800#define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 801#define A_SCD_TRACE_EVENT_4 0x0010020A60 802#define A_SCD_TRACE_EVENT_5 0x0010020A68 803#define A_SCD_TRACE_EVENT_6 0x0010020A70 804#define A_SCD_TRACE_EVENT_7 0x0010020A78 805#define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 806#define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 807#define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 808#define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 809 810#define TRACE_REGISTER_SPACING 8 811#define TRACE_NUM_REGISTERS 8 812#define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \ 813 (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \ 814 (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING))) 815#define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \ 816 (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \ 817 (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING))) 818 819/* ********************************************************************* 820 * System Generic DMA Registers 821 ********************************************************************* */ 822 823#define A_DM_0 0x0010020B00 824#define A_DM_1 0x0010020B20 825#define A_DM_2 0x0010020B40 826#define A_DM_3 0x0010020B60 827#define DM_REGISTER_SPACING 0x20 828#define DM_NUM_CHANNELS 4 829#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) 830#define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) 831 832#define R_DM_DSCR_BASE 0x0000000000 833#define R_DM_DSCR_COUNT 0x0000000008 834#define R_DM_CUR_DSCR_ADDR 0x0000000010 835#define R_DM_DSCR_BASE_DEBUG 0x0000000018 836 837#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 838#define A_DM_PARTIAL_0 0x0010020ba0 839#define A_DM_PARTIAL_1 0x0010020ba8 840#define A_DM_PARTIAL_2 0x0010020bb0 841#define A_DM_PARTIAL_3 0x0010020bb8 842#define DM_PARTIAL_REGISTER_SPACING 0x8 843#define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING)) 844#endif /* 1250 PASS3 || 112x PASS1 */ 845 846#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 847#define A_DM_CRC_0 0x0010020b80 848#define A_DM_CRC_1 0x0010020b90 849#define DM_CRC_REGISTER_SPACING 0x10 850#define DM_CRC_NUM_CHANNELS 2 851#define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) 852#define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) 853 854#define R_CRC_DEF_0 0x00 855#define R_CTCP_DEF_0 0x08 856#endif /* 1250 PASS3 || 112x PASS1 */ 857 858/* ********************************************************************* 859 * Physical Address Map 860 ********************************************************************* */ 861 862#if SIBYTE_HDR_FEATURE_1250_112x 863#define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) 864#define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) 865#define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) 866#define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) 867#define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) 868#define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) 869#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) 870#define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) 871#define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) 872#define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) 873#define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) 874#define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) 875#define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) 876#define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) 877#define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) 878#define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) 879#define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) 880#define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) 881#define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) 882#define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) 883#define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) 884#define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) 885#define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) 886#define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) 887#define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) 888 889#define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) 890#define PHYS_L2CACHE_NUM_WAYS 4 891#define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) 892#define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) 893#define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) 894#define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) 895#define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) 896#endif 897 898 899#endif 900