1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * MAC constants and macros File: sb1250_mac.h 5 * 6 * This module contains constants and macros for the SB1250's 7 * ethernet controllers. 8 * 9 * SB1250 specification level: User's manual 1/02/02 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003,2004 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48 49#ifndef _SB1250_MAC_H 50#define _SB1250_MAC_H 51 52#include "sb1250_defs.h" 53 54/* ********************************************************************* 55 * Ethernet MAC Registers 56 ********************************************************************* */ 57 58/* 59 * MAC Configuration Register (Table 9-13) 60 * Register: MAC_CFG_0 61 * Register: MAC_CFG_1 62 * Register: MAC_CFG_2 63 */ 64 65 66#define M_MAC_RESERVED0 _SB_MAKEMASK1(0) 67#define M_MAC_TX_HOLD_SOP_EN _SB_MAKEMASK1(1) 68#define M_MAC_RETRY_EN _SB_MAKEMASK1(2) 69#define M_MAC_RET_DRPREQ_EN _SB_MAKEMASK1(3) 70#define M_MAC_RET_UFL_EN _SB_MAKEMASK1(4) 71#define M_MAC_BURST_EN _SB_MAKEMASK1(5) 72 73#define S_MAC_TX_PAUSE _SB_MAKE64(6) 74#define M_MAC_TX_PAUSE_CNT _SB_MAKEMASK(3,S_MAC_TX_PAUSE) 75#define V_MAC_TX_PAUSE_CNT(x) _SB_MAKEVALUE(x,S_MAC_TX_PAUSE) 76 77#define K_MAC_TX_PAUSE_CNT_512 0 78#define K_MAC_TX_PAUSE_CNT_1K 1 79#define K_MAC_TX_PAUSE_CNT_2K 2 80#define K_MAC_TX_PAUSE_CNT_4K 3 81#define K_MAC_TX_PAUSE_CNT_8K 4 82#define K_MAC_TX_PAUSE_CNT_16K 5 83#define K_MAC_TX_PAUSE_CNT_32K 6 84#define K_MAC_TX_PAUSE_CNT_64K 7 85 86#define V_MAC_TX_PAUSE_CNT_512 V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512) 87#define V_MAC_TX_PAUSE_CNT_1K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K) 88#define V_MAC_TX_PAUSE_CNT_2K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K) 89#define V_MAC_TX_PAUSE_CNT_4K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K) 90#define V_MAC_TX_PAUSE_CNT_8K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K) 91#define V_MAC_TX_PAUSE_CNT_16K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K) 92#define V_MAC_TX_PAUSE_CNT_32K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K) 93#define V_MAC_TX_PAUSE_CNT_64K V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K) 94 95#define M_MAC_RESERVED1 _SB_MAKEMASK(8,9) 96 97#define M_MAC_AP_STAT_EN _SB_MAKEMASK1(17) 98 99#if SIBYTE_HDR_FEATURE_CHIP(1480) 100#define M_MAC_TIMESTAMP _SB_MAKEMASK1(18) 101#endif 102#define M_MAC_DRP_ERRPKT_EN _SB_MAKEMASK1(19) 103#define M_MAC_DRP_FCSERRPKT_EN _SB_MAKEMASK1(20) 104#define M_MAC_DRP_CODEERRPKT_EN _SB_MAKEMASK1(21) 105#define M_MAC_DRP_DRBLERRPKT_EN _SB_MAKEMASK1(22) 106#define M_MAC_DRP_RNTPKT_EN _SB_MAKEMASK1(23) 107#define M_MAC_DRP_OSZPKT_EN _SB_MAKEMASK1(24) 108#define M_MAC_DRP_LENERRPKT_EN _SB_MAKEMASK1(25) 109 110#define M_MAC_RESERVED3 _SB_MAKEMASK(6,26) 111 112#define M_MAC_BYPASS_SEL _SB_MAKEMASK1(32) 113#define M_MAC_HDX_EN _SB_MAKEMASK1(33) 114 115#define S_MAC_SPEED_SEL _SB_MAKE64(34) 116#define M_MAC_SPEED_SEL _SB_MAKEMASK(2,S_MAC_SPEED_SEL) 117#define V_MAC_SPEED_SEL(x) _SB_MAKEVALUE(x,S_MAC_SPEED_SEL) 118#define G_MAC_SPEED_SEL(x) _SB_GETVALUE(x,S_MAC_SPEED_SEL,M_MAC_SPEED_SEL) 119 120#define K_MAC_SPEED_SEL_10MBPS 0 121#define K_MAC_SPEED_SEL_100MBPS 1 122#define K_MAC_SPEED_SEL_1000MBPS 2 123#define K_MAC_SPEED_SEL_RESERVED 3 124 125#define V_MAC_SPEED_SEL_10MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS) 126#define V_MAC_SPEED_SEL_100MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS) 127#define V_MAC_SPEED_SEL_1000MBPS V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS) 128#define V_MAC_SPEED_SEL_RESERVED V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED) 129 130#define M_MAC_TX_CLK_EDGE_SEL _SB_MAKEMASK1(36) 131#define M_MAC_LOOPBACK_SEL _SB_MAKEMASK1(37) 132#define M_MAC_FAST_SYNC _SB_MAKEMASK1(38) 133#define M_MAC_SS_EN _SB_MAKEMASK1(39) 134 135#define S_MAC_BYPASS_CFG _SB_MAKE64(40) 136#define M_MAC_BYPASS_CFG _SB_MAKEMASK(2,S_MAC_BYPASS_CFG) 137#define V_MAC_BYPASS_CFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_CFG) 138#define G_MAC_BYPASS_CFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_CFG,M_MAC_BYPASS_CFG) 139 140#define K_MAC_BYPASS_GMII 0 141#define K_MAC_BYPASS_ENCODED 1 142#define K_MAC_BYPASS_SOP 2 143#define K_MAC_BYPASS_EOP 3 144 145#define M_MAC_BYPASS_16 _SB_MAKEMASK1(42) 146#define M_MAC_BYPASS_FCS_CHK _SB_MAKEMASK1(43) 147 148#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 149#define M_MAC_RX_CH_SEL_MSB _SB_MAKEMASK1(44) 150#endif /* 1250 PASS2 || 112x PASS1 || 1480*/ 151 152#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 153#define M_MAC_SPLIT_CH_SEL _SB_MAKEMASK1(45) 154#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 155 156#define S_MAC_BYPASS_IFG _SB_MAKE64(46) 157#define M_MAC_BYPASS_IFG _SB_MAKEMASK(8,S_MAC_BYPASS_IFG) 158#define V_MAC_BYPASS_IFG(x) _SB_MAKEVALUE(x,S_MAC_BYPASS_IFG) 159#define G_MAC_BYPASS_IFG(x) _SB_GETVALUE(x,S_MAC_BYPASS_IFG,M_MAC_BYPASS_IFG) 160 161#define K_MAC_FC_CMD_DISABLED 0 162#define K_MAC_FC_CMD_ENABLED 1 163#define K_MAC_FC_CMD_ENAB_FALSECARR 2 164 165#define V_MAC_FC_CMD_DISABLED V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED) 166#define V_MAC_FC_CMD_ENABLED V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED) 167#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR) 168 169#define M_MAC_FC_SEL _SB_MAKEMASK1(54) 170 171#define S_MAC_FC_CMD _SB_MAKE64(55) 172#define M_MAC_FC_CMD _SB_MAKEMASK(2,S_MAC_FC_CMD) 173#define V_MAC_FC_CMD(x) _SB_MAKEVALUE(x,S_MAC_FC_CMD) 174#define G_MAC_FC_CMD(x) _SB_GETVALUE(x,S_MAC_FC_CMD,M_MAC_FC_CMD) 175 176#define S_MAC_RX_CH_SEL _SB_MAKE64(57) 177#define M_MAC_RX_CH_SEL _SB_MAKEMASK(7,S_MAC_RX_CH_SEL) 178#define V_MAC_RX_CH_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_SEL) 179#define G_MAC_RX_CH_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_SEL,M_MAC_RX_CH_SEL) 180 181 182/* 183 * MAC Enable Registers 184 * Register: MAC_ENABLE_0 185 * Register: MAC_ENABLE_1 186 * Register: MAC_ENABLE_2 187 */ 188 189#define M_MAC_RXDMA_EN0 _SB_MAKEMASK1(0) 190#define M_MAC_RXDMA_EN1 _SB_MAKEMASK1(1) 191#define M_MAC_TXDMA_EN0 _SB_MAKEMASK1(4) 192#define M_MAC_TXDMA_EN1 _SB_MAKEMASK1(5) 193 194#define M_MAC_PORT_RESET _SB_MAKEMASK1(8) 195 196#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x)) 197#define M_MAC_RX_ENABLE _SB_MAKEMASK1(10) 198#define M_MAC_TX_ENABLE _SB_MAKEMASK1(11) 199#define M_MAC_BYP_RX_ENABLE _SB_MAKEMASK1(12) 200#define M_MAC_BYP_TX_ENABLE _SB_MAKEMASK1(13) 201#endif 202 203/* 204 * MAC reset information register (1280/1255) 205 */ 206#if SIBYTE_HDR_FEATURE_CHIP(1480) 207#define M_MAC_RX_CH0_PAUSE_ON _SB_MAKEMASK1(8) 208#define M_MAC_RX_CH1_PAUSE_ON _SB_MAKEMASK1(16) 209#define M_MAC_TX_CH0_PAUSE_ON _SB_MAKEMASK1(24) 210#define M_MAC_TX_CH1_PAUSE_ON _SB_MAKEMASK1(32) 211#endif 212 213/* 214 * MAC DMA Control Register 215 * Register: MAC_TXD_CTL_0 216 * Register: MAC_TXD_CTL_1 217 * Register: MAC_TXD_CTL_2 218 */ 219 220#define S_MAC_TXD_WEIGHT0 _SB_MAKE64(0) 221#define M_MAC_TXD_WEIGHT0 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT0) 222#define V_MAC_TXD_WEIGHT0(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT0) 223#define G_MAC_TXD_WEIGHT0(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT0,M_MAC_TXD_WEIGHT0) 224 225#define S_MAC_TXD_WEIGHT1 _SB_MAKE64(4) 226#define M_MAC_TXD_WEIGHT1 _SB_MAKEMASK(4,S_MAC_TXD_WEIGHT1) 227#define V_MAC_TXD_WEIGHT1(x) _SB_MAKEVALUE(x,S_MAC_TXD_WEIGHT1) 228#define G_MAC_TXD_WEIGHT1(x) _SB_GETVALUE(x,S_MAC_TXD_WEIGHT1,M_MAC_TXD_WEIGHT1) 229 230/* 231 * MAC Fifo Threshhold registers (Table 9-14) 232 * Register: MAC_THRSH_CFG_0 233 * Register: MAC_THRSH_CFG_1 234 * Register: MAC_THRSH_CFG_2 235 */ 236 237#define S_MAC_TX_WR_THRSH _SB_MAKE64(0) 238#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 239/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 240/* #define M_MAC_TX_WR_THRSH _SB_MAKEMASK(6,S_MAC_TX_WR_THRSH) */ 241#endif /* up to 1250 PASS1 */ 242#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 243#define M_MAC_TX_WR_THRSH _SB_MAKEMASK(7,S_MAC_TX_WR_THRSH) 244#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 245#define V_MAC_TX_WR_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_WR_THRSH) 246#define G_MAC_TX_WR_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_WR_THRSH,M_MAC_TX_WR_THRSH) 247 248#define S_MAC_TX_RD_THRSH _SB_MAKE64(8) 249#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1) 250/* XXX: Can't enable, as it has the same name as a pass2+ define below. */ 251/* #define M_MAC_TX_RD_THRSH _SB_MAKEMASK(6,S_MAC_TX_RD_THRSH) */ 252#endif /* up to 1250 PASS1 */ 253#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 254#define M_MAC_TX_RD_THRSH _SB_MAKEMASK(7,S_MAC_TX_RD_THRSH) 255#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 256#define V_MAC_TX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RD_THRSH) 257#define G_MAC_TX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RD_THRSH,M_MAC_TX_RD_THRSH) 258 259#define S_MAC_TX_RL_THRSH _SB_MAKE64(16) 260#define M_MAC_TX_RL_THRSH _SB_MAKEMASK(4,S_MAC_TX_RL_THRSH) 261#define V_MAC_TX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_TX_RL_THRSH) 262#define G_MAC_TX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_TX_RL_THRSH,M_MAC_TX_RL_THRSH) 263 264#define S_MAC_RX_PL_THRSH _SB_MAKE64(24) 265#define M_MAC_RX_PL_THRSH _SB_MAKEMASK(6,S_MAC_RX_PL_THRSH) 266#define V_MAC_RX_PL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_PL_THRSH) 267#define G_MAC_RX_PL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_PL_THRSH,M_MAC_RX_PL_THRSH) 268 269#define S_MAC_RX_RD_THRSH _SB_MAKE64(32) 270#define M_MAC_RX_RD_THRSH _SB_MAKEMASK(6,S_MAC_RX_RD_THRSH) 271#define V_MAC_RX_RD_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RD_THRSH) 272#define G_MAC_RX_RD_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RD_THRSH,M_MAC_RX_RD_THRSH) 273 274#define S_MAC_RX_RL_THRSH _SB_MAKE64(40) 275#define M_MAC_RX_RL_THRSH _SB_MAKEMASK(6,S_MAC_RX_RL_THRSH) 276#define V_MAC_RX_RL_THRSH(x) _SB_MAKEVALUE(x,S_MAC_RX_RL_THRSH) 277#define G_MAC_RX_RL_THRSH(x) _SB_GETVALUE(x,S_MAC_RX_RL_THRSH,M_MAC_RX_RL_THRSH) 278 279#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 280#define S_MAC_ENC_FC_THRSH _SB_MAKE64(56) 281#define M_MAC_ENC_FC_THRSH _SB_MAKEMASK(6,S_MAC_ENC_FC_THRSH) 282#define V_MAC_ENC_FC_THRSH(x) _SB_MAKEVALUE(x,S_MAC_ENC_FC_THRSH) 283#define G_MAC_ENC_FC_THRSH(x) _SB_GETVALUE(x,S_MAC_ENC_FC_THRSH,M_MAC_ENC_FC_THRSH) 284#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 285 286/* 287 * MAC Frame Configuration Registers (Table 9-15) 288 * Register: MAC_FRAME_CFG_0 289 * Register: MAC_FRAME_CFG_1 290 * Register: MAC_FRAME_CFG_2 291 */ 292 293/* XXXCGD: ??? Unused in pass2? */ 294#define S_MAC_IFG_RX _SB_MAKE64(0) 295#define M_MAC_IFG_RX _SB_MAKEMASK(6,S_MAC_IFG_RX) 296#define V_MAC_IFG_RX(x) _SB_MAKEVALUE(x,S_MAC_IFG_RX) 297#define G_MAC_IFG_RX(x) _SB_GETVALUE(x,S_MAC_IFG_RX,M_MAC_IFG_RX) 298 299#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 300#define S_MAC_PRE_LEN _SB_MAKE64(0) 301#define M_MAC_PRE_LEN _SB_MAKEMASK(6,S_MAC_PRE_LEN) 302#define V_MAC_PRE_LEN(x) _SB_MAKEVALUE(x,S_MAC_PRE_LEN) 303#define G_MAC_PRE_LEN(x) _SB_GETVALUE(x,S_MAC_PRE_LEN,M_MAC_PRE_LEN) 304#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 305 306#define S_MAC_IFG_TX _SB_MAKE64(6) 307#define M_MAC_IFG_TX _SB_MAKEMASK(6,S_MAC_IFG_TX) 308#define V_MAC_IFG_TX(x) _SB_MAKEVALUE(x,S_MAC_IFG_TX) 309#define G_MAC_IFG_TX(x) _SB_GETVALUE(x,S_MAC_IFG_TX,M_MAC_IFG_TX) 310 311#define S_MAC_IFG_THRSH _SB_MAKE64(12) 312#define M_MAC_IFG_THRSH _SB_MAKEMASK(6,S_MAC_IFG_THRSH) 313#define V_MAC_IFG_THRSH(x) _SB_MAKEVALUE(x,S_MAC_IFG_THRSH) 314#define G_MAC_IFG_THRSH(x) _SB_GETVALUE(x,S_MAC_IFG_THRSH,M_MAC_IFG_THRSH) 315 316#define S_MAC_BACKOFF_SEL _SB_MAKE64(18) 317#define M_MAC_BACKOFF_SEL _SB_MAKEMASK(4,S_MAC_BACKOFF_SEL) 318#define V_MAC_BACKOFF_SEL(x) _SB_MAKEVALUE(x,S_MAC_BACKOFF_SEL) 319#define G_MAC_BACKOFF_SEL(x) _SB_GETVALUE(x,S_MAC_BACKOFF_SEL,M_MAC_BACKOFF_SEL) 320 321#define S_MAC_LFSR_SEED _SB_MAKE64(22) 322#define M_MAC_LFSR_SEED _SB_MAKEMASK(8,S_MAC_LFSR_SEED) 323#define V_MAC_LFSR_SEED(x) _SB_MAKEVALUE(x,S_MAC_LFSR_SEED) 324#define G_MAC_LFSR_SEED(x) _SB_GETVALUE(x,S_MAC_LFSR_SEED,M_MAC_LFSR_SEED) 325 326#define S_MAC_SLOT_SIZE _SB_MAKE64(30) 327#define M_MAC_SLOT_SIZE _SB_MAKEMASK(10,S_MAC_SLOT_SIZE) 328#define V_MAC_SLOT_SIZE(x) _SB_MAKEVALUE(x,S_MAC_SLOT_SIZE) 329#define G_MAC_SLOT_SIZE(x) _SB_GETVALUE(x,S_MAC_SLOT_SIZE,M_MAC_SLOT_SIZE) 330 331#define S_MAC_MIN_FRAMESZ _SB_MAKE64(40) 332#define M_MAC_MIN_FRAMESZ _SB_MAKEMASK(8,S_MAC_MIN_FRAMESZ) 333#define V_MAC_MIN_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MIN_FRAMESZ) 334#define G_MAC_MIN_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MIN_FRAMESZ,M_MAC_MIN_FRAMESZ) 335 336#define S_MAC_MAX_FRAMESZ _SB_MAKE64(48) 337#define M_MAC_MAX_FRAMESZ _SB_MAKEMASK(16,S_MAC_MAX_FRAMESZ) 338#define V_MAC_MAX_FRAMESZ(x) _SB_MAKEVALUE(x,S_MAC_MAX_FRAMESZ) 339#define G_MAC_MAX_FRAMESZ(x) _SB_GETVALUE(x,S_MAC_MAX_FRAMESZ,M_MAC_MAX_FRAMESZ) 340 341/* 342 * These constants are used to configure the fields within the Frame 343 * Configuration Register. 344 */ 345 346#define K_MAC_IFG_RX_10 _SB_MAKE64(0) /* See table 176, not used */ 347#define K_MAC_IFG_RX_100 _SB_MAKE64(0) 348#define K_MAC_IFG_RX_1000 _SB_MAKE64(0) 349 350#define K_MAC_IFG_TX_10 _SB_MAKE64(20) 351#define K_MAC_IFG_TX_100 _SB_MAKE64(20) 352#define K_MAC_IFG_TX_1000 _SB_MAKE64(8) 353 354#define K_MAC_IFG_THRSH_10 _SB_MAKE64(4) 355#define K_MAC_IFG_THRSH_100 _SB_MAKE64(4) 356#define K_MAC_IFG_THRSH_1000 _SB_MAKE64(0) 357 358#define K_MAC_SLOT_SIZE_10 _SB_MAKE64(0) 359#define K_MAC_SLOT_SIZE_100 _SB_MAKE64(0) 360#define K_MAC_SLOT_SIZE_1000 _SB_MAKE64(0) 361 362#define V_MAC_IFG_RX_10 V_MAC_IFG_RX(K_MAC_IFG_RX_10) 363#define V_MAC_IFG_RX_100 V_MAC_IFG_RX(K_MAC_IFG_RX_100) 364#define V_MAC_IFG_RX_1000 V_MAC_IFG_RX(K_MAC_IFG_RX_1000) 365 366#define V_MAC_IFG_TX_10 V_MAC_IFG_TX(K_MAC_IFG_TX_10) 367#define V_MAC_IFG_TX_100 V_MAC_IFG_TX(K_MAC_IFG_TX_100) 368#define V_MAC_IFG_TX_1000 V_MAC_IFG_TX(K_MAC_IFG_TX_1000) 369 370#define V_MAC_IFG_THRSH_10 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10) 371#define V_MAC_IFG_THRSH_100 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100) 372#define V_MAC_IFG_THRSH_1000 V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000) 373 374#define V_MAC_SLOT_SIZE_10 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10) 375#define V_MAC_SLOT_SIZE_100 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100) 376#define V_MAC_SLOT_SIZE_1000 V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000) 377 378#define K_MAC_MIN_FRAMESZ_FIFO _SB_MAKE64(9) 379#define K_MAC_MIN_FRAMESZ_DEFAULT _SB_MAKE64(64) 380#define K_MAC_MAX_FRAMESZ_DEFAULT _SB_MAKE64(1518) 381#define K_MAC_MAX_FRAMESZ_JUMBO _SB_MAKE64(9216) 382 383#define V_MAC_MIN_FRAMESZ_FIFO V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO) 384#define V_MAC_MIN_FRAMESZ_DEFAULT V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT) 385#define V_MAC_MAX_FRAMESZ_DEFAULT V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT) 386#define V_MAC_MAX_FRAMESZ_JUMBO V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO) 387 388/* 389 * MAC VLAN Tag Registers (Table 9-16) 390 * Register: MAC_VLANTAG_0 391 * Register: MAC_VLANTAG_1 392 * Register: MAC_VLANTAG_2 393 */ 394 395#define S_MAC_VLAN_TAG _SB_MAKE64(0) 396#define M_MAC_VLAN_TAG _SB_MAKEMASK(32,S_MAC_VLAN_TAG) 397#define V_MAC_VLAN_TAG(x) _SB_MAKEVALUE(x,S_MAC_VLAN_TAG) 398#define G_MAC_VLAN_TAG(x) _SB_GETVALUE(x,S_MAC_VLAN_TAG,M_MAC_VLAN_TAG) 399 400#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) 401#define S_MAC_TX_PKT_OFFSET _SB_MAKE64(32) 402#define M_MAC_TX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_TX_PKT_OFFSET) 403#define V_MAC_TX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_PKT_OFFSET) 404#define G_MAC_TX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_PKT_OFFSET,M_MAC_TX_PKT_OFFSET) 405 406#define S_MAC_TX_CRC_OFFSET _SB_MAKE64(40) 407#define M_MAC_TX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_TX_CRC_OFFSET) 408#define V_MAC_TX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_TX_CRC_OFFSET) 409#define G_MAC_TX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_TX_CRC_OFFSET,M_MAC_TX_CRC_OFFSET) 410 411#define M_MAC_CH_BASE_FC_EN _SB_MAKEMASK1(48) 412#endif /* 1250 PASS3 || 112x PASS1 */ 413 414/* 415 * MAC Status Registers (Table 9-17) 416 * Also used for the MAC Interrupt Mask Register (Table 9-18) 417 * Register: MAC_STATUS_0 418 * Register: MAC_STATUS_1 419 * Register: MAC_STATUS_2 420 * Register: MAC_INT_MASK_0 421 * Register: MAC_INT_MASK_1 422 * Register: MAC_INT_MASK_2 423 */ 424 425/* 426 * Use these constants to shift the appropriate channel 427 * into the CH0 position so the same tests can be used 428 * on each channel. 429 */ 430 431#define S_MAC_RX_CH0 _SB_MAKE64(0) 432#define S_MAC_RX_CH1 _SB_MAKE64(8) 433#define S_MAC_TX_CH0 _SB_MAKE64(16) 434#define S_MAC_TX_CH1 _SB_MAKE64(24) 435 436#define S_MAC_TXCHANNELS _SB_MAKE64(16) /* this is 1st TX chan */ 437#define S_MAC_CHANWIDTH _SB_MAKE64(8) /* bits between channels */ 438 439/* 440 * These are the same as RX channel 0. The idea here 441 * is that you'll use one of the "S_" things above 442 * and pass just the six bits to a DMA-channel-specific ISR 443 */ 444#define M_MAC_INT_CHANNEL _SB_MAKEMASK(8,0) 445#define M_MAC_INT_EOP_COUNT _SB_MAKEMASK1(0) 446#define M_MAC_INT_EOP_TIMER _SB_MAKEMASK1(1) 447#define M_MAC_INT_EOP_SEEN _SB_MAKEMASK1(2) 448#define M_MAC_INT_HWM _SB_MAKEMASK1(3) 449#define M_MAC_INT_LWM _SB_MAKEMASK1(4) 450#define M_MAC_INT_DSCR _SB_MAKEMASK1(5) 451#define M_MAC_INT_ERR _SB_MAKEMASK1(6) 452#define M_MAC_INT_DZERO _SB_MAKEMASK1(7) /* only for TX channels */ 453#define M_MAC_INT_DROP _SB_MAKEMASK1(7) /* only for RX channels */ 454 455/* 456 * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see 457 * also DMA_TX/DMA_RX in sb_regs.h). 458 */ 459#define S_MAC_STATUS_CH_OFFSET(ch,txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH) 460 461#define M_MAC_STATUS_CHANNEL(ch,txrx) _SB_MAKEVALUE(_SB_MAKEMASK(8,0),S_MAC_STATUS_CH_OFFSET(ch,txrx)) 462#define M_MAC_STATUS_EOP_COUNT(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 463#define M_MAC_STATUS_EOP_TIMER(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 464#define M_MAC_STATUS_EOP_SEEN(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 465#define M_MAC_STATUS_HWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_HWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 466#define M_MAC_STATUS_LWM(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_LWM,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 467#define M_MAC_STATUS_DSCR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DSCR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 468#define M_MAC_STATUS_ERR(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_ERR,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 469#define M_MAC_STATUS_DZERO(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DZERO,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 470#define M_MAC_STATUS_DROP(ch,txrx) _SB_MAKEVALUE(M_MAC_INT_DROP,S_MAC_STATUS_CH_OFFSET(ch,txrx)) 471#define M_MAC_STATUS_OTHER_ERR _SB_MAKEVALUE(_SB_MAKEMASK(7,0),40) 472 473 474#define M_MAC_RX_UNDRFL _SB_MAKEMASK1(40) 475#define M_MAC_RX_OVRFL _SB_MAKEMASK1(41) 476#define M_MAC_TX_UNDRFL _SB_MAKEMASK1(42) 477#define M_MAC_TX_OVRFL _SB_MAKEMASK1(43) 478#define M_MAC_LTCOL_ERR _SB_MAKEMASK1(44) 479#define M_MAC_EXCOL_ERR _SB_MAKEMASK1(45) 480#define M_MAC_CNTR_OVRFL_ERR _SB_MAKEMASK1(46) 481#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 482#define M_MAC_SPLIT_EN _SB_MAKEMASK1(47) /* interrupt mask only */ 483#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 484 485#define S_MAC_COUNTER_ADDR _SB_MAKE64(47) 486#define M_MAC_COUNTER_ADDR _SB_MAKEMASK(5,S_MAC_COUNTER_ADDR) 487#define V_MAC_COUNTER_ADDR(x) _SB_MAKEVALUE(x,S_MAC_COUNTER_ADDR) 488#define G_MAC_COUNTER_ADDR(x) _SB_GETVALUE(x,S_MAC_COUNTER_ADDR,M_MAC_COUNTER_ADDR) 489 490#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 491#define M_MAC_TX_PAUSE_ON _SB_MAKEMASK1(52) 492#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 493 494/* 495 * MAC Fifo Pointer Registers (Table 9-19) [Debug register] 496 * Register: MAC_FIFO_PTRS_0 497 * Register: MAC_FIFO_PTRS_1 498 * Register: MAC_FIFO_PTRS_2 499 */ 500 501#define S_MAC_TX_WRPTR _SB_MAKE64(0) 502#define M_MAC_TX_WRPTR _SB_MAKEMASK(6,S_MAC_TX_WRPTR) 503#define V_MAC_TX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_WRPTR) 504#define G_MAC_TX_WRPTR(x) _SB_GETVALUE(x,S_MAC_TX_WRPTR,M_MAC_TX_WRPTR) 505 506#define S_MAC_TX_RDPTR _SB_MAKE64(8) 507#define M_MAC_TX_RDPTR _SB_MAKEMASK(6,S_MAC_TX_RDPTR) 508#define V_MAC_TX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_TX_RDPTR) 509#define G_MAC_TX_RDPTR(x) _SB_GETVALUE(x,S_MAC_TX_RDPTR,M_MAC_TX_RDPTR) 510 511#define S_MAC_RX_WRPTR _SB_MAKE64(16) 512#define M_MAC_RX_WRPTR _SB_MAKEMASK(6,S_MAC_RX_WRPTR) 513#define V_MAC_RX_WRPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_WRPTR) 514#define G_MAC_RX_WRPTR(x) _SB_GETVALUE(x,S_MAC_RX_WRPTR,M_MAC_TX_WRPTR) 515 516#define S_MAC_RX_RDPTR _SB_MAKE64(24) 517#define M_MAC_RX_RDPTR _SB_MAKEMASK(6,S_MAC_RX_RDPTR) 518#define V_MAC_RX_RDPTR(x) _SB_MAKEVALUE(x,S_MAC_RX_RDPTR) 519#define G_MAC_RX_RDPTR(x) _SB_GETVALUE(x,S_MAC_RX_RDPTR,M_MAC_TX_RDPTR) 520 521/* 522 * MAC Fifo End Of Packet Count Registers (Table 9-20) [Debug register] 523 * Register: MAC_EOPCNT_0 524 * Register: MAC_EOPCNT_1 525 * Register: MAC_EOPCNT_2 526 */ 527 528#define S_MAC_TX_EOP_COUNTER _SB_MAKE64(0) 529#define M_MAC_TX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_TX_EOP_COUNTER) 530#define V_MAC_TX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_TX_EOP_COUNTER) 531#define G_MAC_TX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_TX_EOP_COUNTER,M_MAC_TX_EOP_COUNTER) 532 533#define S_MAC_RX_EOP_COUNTER _SB_MAKE64(8) 534#define M_MAC_RX_EOP_COUNTER _SB_MAKEMASK(6,S_MAC_RX_EOP_COUNTER) 535#define V_MAC_RX_EOP_COUNTER(x) _SB_MAKEVALUE(x,S_MAC_RX_EOP_COUNTER) 536#define G_MAC_RX_EOP_COUNTER(x) _SB_GETVALUE(x,S_MAC_RX_EOP_COUNTER,M_MAC_RX_EOP_COUNTER) 537 538/* 539 * MAC Recieve Address Filter Exact Match Registers (Table 9-21) 540 * Registers: MAC_ADDR0_0 through MAC_ADDR7_0 541 * Registers: MAC_ADDR0_1 through MAC_ADDR7_1 542 * Registers: MAC_ADDR0_2 through MAC_ADDR7_2 543 */ 544 545/* No bitfields */ 546 547/* 548 * MAC Receive Address Filter Mask Registers 549 * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1 550 * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1 551 * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1 552 */ 553 554/* No bitfields */ 555 556/* 557 * MAC Recieve Address Filter Hash Match Registers (Table 9-22) 558 * Registers: MAC_HASH0_0 through MAC_HASH7_0 559 * Registers: MAC_HASH0_1 through MAC_HASH7_1 560 * Registers: MAC_HASH0_2 through MAC_HASH7_2 561 */ 562 563/* No bitfields */ 564 565/* 566 * MAC Transmit Source Address Registers (Table 9-23) 567 * Register: MAC_ETHERNET_ADDR_0 568 * Register: MAC_ETHERNET_ADDR_1 569 * Register: MAC_ETHERNET_ADDR_2 570 */ 571 572/* No bitfields */ 573 574/* 575 * MAC Packet Type Configuration Register 576 * Register: MAC_TYPE_CFG_0 577 * Register: MAC_TYPE_CFG_1 578 * Register: MAC_TYPE_CFG_2 579 */ 580 581#define S_TYPECFG_TYPESIZE _SB_MAKE64(16) 582 583#define S_TYPECFG_TYPE0 _SB_MAKE64(0) 584#define M_TYPECFG_TYPE0 _SB_MAKEMASK(16,S_TYPECFG_TYPE0) 585#define V_TYPECFG_TYPE0(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE0) 586#define G_TYPECFG_TYPE0(x) _SB_GETVALUE(x,S_TYPECFG_TYPE0,M_TYPECFG_TYPE0) 587 588#define S_TYPECFG_TYPE1 _SB_MAKE64(0) 589#define M_TYPECFG_TYPE1 _SB_MAKEMASK(16,S_TYPECFG_TYPE1) 590#define V_TYPECFG_TYPE1(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE1) 591#define G_TYPECFG_TYPE1(x) _SB_GETVALUE(x,S_TYPECFG_TYPE1,M_TYPECFG_TYPE1) 592 593#define S_TYPECFG_TYPE2 _SB_MAKE64(0) 594#define M_TYPECFG_TYPE2 _SB_MAKEMASK(16,S_TYPECFG_TYPE2) 595#define V_TYPECFG_TYPE2(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE2) 596#define G_TYPECFG_TYPE2(x) _SB_GETVALUE(x,S_TYPECFG_TYPE2,M_TYPECFG_TYPE2) 597 598#define S_TYPECFG_TYPE3 _SB_MAKE64(0) 599#define M_TYPECFG_TYPE3 _SB_MAKEMASK(16,S_TYPECFG_TYPE3) 600#define V_TYPECFG_TYPE3(x) _SB_MAKEVALUE(x,S_TYPECFG_TYPE3) 601#define G_TYPECFG_TYPE3(x) _SB_GETVALUE(x,S_TYPECFG_TYPE3,M_TYPECFG_TYPE3) 602 603/* 604 * MAC Receive Address Filter Control Registers (Table 9-24) 605 * Register: MAC_ADFILTER_CFG_0 606 * Register: MAC_ADFILTER_CFG_1 607 * Register: MAC_ADFILTER_CFG_2 608 */ 609 610#define M_MAC_ALLPKT_EN _SB_MAKEMASK1(0) 611#define M_MAC_UCAST_EN _SB_MAKEMASK1(1) 612#define M_MAC_UCAST_INV _SB_MAKEMASK1(2) 613#define M_MAC_MCAST_EN _SB_MAKEMASK1(3) 614#define M_MAC_MCAST_INV _SB_MAKEMASK1(4) 615#define M_MAC_BCAST_EN _SB_MAKEMASK1(5) 616#define M_MAC_DIRECT_INV _SB_MAKEMASK1(6) 617#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 618#define M_MAC_ALLMCAST_EN _SB_MAKEMASK1(7) 619#endif /* 1250 PASS2 || 112x PASS1 || 1480 */ 620 621#define S_MAC_IPHDR_OFFSET _SB_MAKE64(8) 622#define M_MAC_IPHDR_OFFSET _SB_MAKEMASK(8,S_MAC_IPHDR_OFFSET) 623#define V_MAC_IPHDR_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_IPHDR_OFFSET) 624#define G_MAC_IPHDR_OFFSET(x) _SB_GETVALUE(x,S_MAC_IPHDR_OFFSET,M_MAC_IPHDR_OFFSET) 625 626#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480) 627#define S_MAC_RX_CRC_OFFSET _SB_MAKE64(16) 628#define M_MAC_RX_CRC_OFFSET _SB_MAKEMASK(8,S_MAC_RX_CRC_OFFSET) 629#define V_MAC_RX_CRC_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_CRC_OFFSET) 630#define G_MAC_RX_CRC_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_CRC_OFFSET,M_MAC_RX_CRC_OFFSET) 631 632#define S_MAC_RX_PKT_OFFSET _SB_MAKE64(24) 633#define M_MAC_RX_PKT_OFFSET _SB_MAKEMASK(8,S_MAC_RX_PKT_OFFSET) 634#define V_MAC_RX_PKT_OFFSET(x) _SB_MAKEVALUE(x,S_MAC_RX_PKT_OFFSET) 635#define G_MAC_RX_PKT_OFFSET(x) _SB_GETVALUE(x,S_MAC_RX_PKT_OFFSET,M_MAC_RX_PKT_OFFSET) 636 637#define M_MAC_FWDPAUSE_EN _SB_MAKEMASK1(32) 638#define M_MAC_VLAN_DET_EN _SB_MAKEMASK1(33) 639 640#define S_MAC_RX_CH_MSN_SEL _SB_MAKE64(34) 641#define M_MAC_RX_CH_MSN_SEL _SB_MAKEMASK(8,S_MAC_RX_CH_MSN_SEL) 642#define V_MAC_RX_CH_MSN_SEL(x) _SB_MAKEVALUE(x,S_MAC_RX_CH_MSN_SEL) 643#define G_MAC_RX_CH_MSN_SEL(x) _SB_GETVALUE(x,S_MAC_RX_CH_MSN_SEL,M_MAC_RX_CH_MSN_SEL) 644#endif /* 1250 PASS3 || 112x PASS1 || 1480 */ 645 646/* 647 * MAC Receive Channel Select Registers (Table 9-25) 648 */ 649 650/* no bitfields */ 651 652/* 653 * MAC MII Management Interface Registers (Table 9-26) 654 * Register: MAC_MDIO_0 655 * Register: MAC_MDIO_1 656 * Register: MAC_MDIO_2 657 */ 658 659#define S_MAC_MDC 0 660#define S_MAC_MDIO_DIR 1 661#define S_MAC_MDIO_OUT 2 662#define S_MAC_GENC 3 663#define S_MAC_MDIO_IN 4 664 665#define M_MAC_MDC _SB_MAKEMASK1(S_MAC_MDC) 666#define M_MAC_MDIO_DIR _SB_MAKEMASK1(S_MAC_MDIO_DIR) 667#define M_MAC_MDIO_DIR_INPUT _SB_MAKEMASK1(S_MAC_MDIO_DIR) 668#define M_MAC_MDIO_OUT _SB_MAKEMASK1(S_MAC_MDIO_OUT) 669#define M_MAC_GENC _SB_MAKEMASK1(S_MAC_GENC) 670#define M_MAC_MDIO_IN _SB_MAKEMASK1(S_MAC_MDIO_IN) 671 672#endif 673