1/*  *********************************************************************
2    *  SB1250 Board Support Package
3    *
4    *  Interrupt Mapper definitions		File: sb1250_int.h
5    *
6    *  This module contains constants for manipulating the SB1250's
7    *  interrupt mapper and definitions for the interrupt sources.
8    *
9    *  SB1250 specification level:  User's manual 1/02/02
10    *
11    *********************************************************************
12    *
13    *  Copyright 2000,2001,2002,2003,2004
14    *  Broadcom Corporation. All rights reserved.
15    *
16    *  This software is furnished under license and may be used and
17    *  copied only in accordance with the following terms and
18    *  conditions.  Subject to these conditions, you may download,
19    *  copy, install, use, modify and distribute modified or unmodified
20    *  copies of this software in source and/or binary form.  No title
21    *  or ownership is transferred hereby.
22    *
23    *  1) Any source code used, modified or distributed must reproduce
24    *     and retain this copyright notice and list of conditions
25    *     as they appear in the source file.
26    *
27    *  2) No right is granted to use any trade name, trademark, or
28    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
29    *     name may not be used to endorse or promote products derived
30    *     from this software without the prior written permission of
31    *     Broadcom Corporation.
32    *
33    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
34    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
35    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
36    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
37    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
38    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
39    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
41    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
42    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
43    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
44    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
45    *     THE POSSIBILITY OF SUCH DAMAGE.
46    ********************************************************************* */
47
48
49#ifndef _SB1250_INT_H
50#define _SB1250_INT_H
51
52#include "sb1250_defs.h"
53
54/*  *********************************************************************
55    *  Interrupt Mapper Constants
56    ********************************************************************* */
57
58/*
59 * Interrupt sources (Table 4-8, UM 0.2)
60 *
61 * First, the interrupt numbers.
62 */
63
64#define K_INT_SOURCES               64
65
66#define K_INT_WATCHDOG_TIMER_0      0
67#define K_INT_WATCHDOG_TIMER_1      1
68#define K_INT_TIMER_0               2
69#define K_INT_TIMER_1               3
70#define K_INT_TIMER_2               4
71#define K_INT_TIMER_3               5
72#define K_INT_SMB_0                 6
73#define K_INT_SMB_1                 7
74#define K_INT_UART_0                8
75#define K_INT_UART_1                9
76#define K_INT_SER_0                 10
77#define K_INT_SER_1                 11
78#define K_INT_PCMCIA                12
79#define K_INT_ADDR_TRAP             13
80#define K_INT_PERF_CNT              14
81#define K_INT_TRACE_FREEZE          15
82#define K_INT_BAD_ECC               16
83#define K_INT_COR_ECC               17
84#define K_INT_IO_BUS                18
85#define K_INT_MAC_0                 19
86#define K_INT_MAC_1                 20
87#define K_INT_MAC_2                 21
88#define K_INT_DM_CH_0               22
89#define K_INT_DM_CH_1               23
90#define K_INT_DM_CH_2               24
91#define K_INT_DM_CH_3               25
92#define K_INT_MBOX_0                26
93#define K_INT_MBOX_1                27
94#define K_INT_MBOX_2                28
95#define K_INT_MBOX_3                29
96#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
97#define K_INT_CYCLE_CP0_INT	    30
98#define K_INT_CYCLE_CP1_INT	    31
99#endif /* 1250 PASS2 || 112x PASS1 */
100#define K_INT_GPIO_0                32
101#define K_INT_GPIO_1                33
102#define K_INT_GPIO_2                34
103#define K_INT_GPIO_3                35
104#define K_INT_GPIO_4                36
105#define K_INT_GPIO_5                37
106#define K_INT_GPIO_6                38
107#define K_INT_GPIO_7                39
108#define K_INT_GPIO_8                40
109#define K_INT_GPIO_9                41
110#define K_INT_GPIO_10               42
111#define K_INT_GPIO_11               43
112#define K_INT_GPIO_12               44
113#define K_INT_GPIO_13               45
114#define K_INT_GPIO_14               46
115#define K_INT_GPIO_15               47
116#define K_INT_LDT_FATAL             48
117#define K_INT_LDT_NONFATAL          49
118#define K_INT_LDT_SMI               50
119#define K_INT_LDT_NMI               51
120#define K_INT_LDT_INIT              52
121#define K_INT_LDT_STARTUP           53
122#define K_INT_LDT_EXT               54
123#define K_INT_PCI_ERROR             55
124#define K_INT_PCI_INTA              56
125#define K_INT_PCI_INTB              57
126#define K_INT_PCI_INTC              58
127#define K_INT_PCI_INTD              59
128#define K_INT_SPARE_2               60
129#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
130#define K_INT_MAC_0_CH1		    61
131#define K_INT_MAC_1_CH1		    62
132#define K_INT_MAC_2_CH1		    63
133#endif /* 1250 PASS2 || 112x PASS1 */
134
135/*
136 * Mask values for each interrupt
137 */
138
139#define M_INT_WATCHDOG_TIMER_0      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
140#define M_INT_WATCHDOG_TIMER_1      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
141#define M_INT_TIMER_0               _SB_MAKEMASK1(K_INT_TIMER_0)
142#define M_INT_TIMER_1               _SB_MAKEMASK1(K_INT_TIMER_1)
143#define M_INT_TIMER_2               _SB_MAKEMASK1(K_INT_TIMER_2)
144#define M_INT_TIMER_3               _SB_MAKEMASK1(K_INT_TIMER_3)
145#define M_INT_SMB_0                 _SB_MAKEMASK1(K_INT_SMB_0)
146#define M_INT_SMB_1                 _SB_MAKEMASK1(K_INT_SMB_1)
147#define M_INT_UART_0                _SB_MAKEMASK1(K_INT_UART_0)
148#define M_INT_UART_1                _SB_MAKEMASK1(K_INT_UART_1)
149#define M_INT_SER_0                 _SB_MAKEMASK1(K_INT_SER_0)
150#define M_INT_SER_1                 _SB_MAKEMASK1(K_INT_SER_1)
151#define M_INT_PCMCIA                _SB_MAKEMASK1(K_INT_PCMCIA)
152#define M_INT_ADDR_TRAP             _SB_MAKEMASK1(K_INT_ADDR_TRAP)
153#define M_INT_PERF_CNT              _SB_MAKEMASK1(K_INT_PERF_CNT)
154#define M_INT_TRACE_FREEZE          _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
155#define M_INT_BAD_ECC               _SB_MAKEMASK1(K_INT_BAD_ECC)
156#define M_INT_COR_ECC               _SB_MAKEMASK1(K_INT_COR_ECC)
157#define M_INT_IO_BUS                _SB_MAKEMASK1(K_INT_IO_BUS)
158#define M_INT_MAC_0                 _SB_MAKEMASK1(K_INT_MAC_0)
159#define M_INT_MAC_1                 _SB_MAKEMASK1(K_INT_MAC_1)
160#define M_INT_MAC_2                 _SB_MAKEMASK1(K_INT_MAC_2)
161#define M_INT_DM_CH_0               _SB_MAKEMASK1(K_INT_DM_CH_0)
162#define M_INT_DM_CH_1               _SB_MAKEMASK1(K_INT_DM_CH_1)
163#define M_INT_DM_CH_2               _SB_MAKEMASK1(K_INT_DM_CH_2)
164#define M_INT_DM_CH_3               _SB_MAKEMASK1(K_INT_DM_CH_3)
165#define M_INT_MBOX_0                _SB_MAKEMASK1(K_INT_MBOX_0)
166#define M_INT_MBOX_1                _SB_MAKEMASK1(K_INT_MBOX_1)
167#define M_INT_MBOX_2                _SB_MAKEMASK1(K_INT_MBOX_2)
168#define M_INT_MBOX_3                _SB_MAKEMASK1(K_INT_MBOX_3)
169#define M_INT_MBOX_ALL              _SB_MAKEMASK(4,K_INT_MBOX_0)
170#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
171#define M_INT_CYCLE_CP0_INT	    _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
172#define M_INT_CYCLE_CP1_INT	    _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
173#endif /* 1250 PASS2 || 112x PASS1 */
174#define M_INT_GPIO_0                _SB_MAKEMASK1(K_INT_GPIO_0)
175#define M_INT_GPIO_1                _SB_MAKEMASK1(K_INT_GPIO_1)
176#define M_INT_GPIO_2                _SB_MAKEMASK1(K_INT_GPIO_2)
177#define M_INT_GPIO_3                _SB_MAKEMASK1(K_INT_GPIO_3)
178#define M_INT_GPIO_4                _SB_MAKEMASK1(K_INT_GPIO_4)
179#define M_INT_GPIO_5                _SB_MAKEMASK1(K_INT_GPIO_5)
180#define M_INT_GPIO_6                _SB_MAKEMASK1(K_INT_GPIO_6)
181#define M_INT_GPIO_7                _SB_MAKEMASK1(K_INT_GPIO_7)
182#define M_INT_GPIO_8                _SB_MAKEMASK1(K_INT_GPIO_8)
183#define M_INT_GPIO_9                _SB_MAKEMASK1(K_INT_GPIO_9)
184#define M_INT_GPIO_10               _SB_MAKEMASK1(K_INT_GPIO_10)
185#define M_INT_GPIO_11               _SB_MAKEMASK1(K_INT_GPIO_11)
186#define M_INT_GPIO_12               _SB_MAKEMASK1(K_INT_GPIO_12)
187#define M_INT_GPIO_13               _SB_MAKEMASK1(K_INT_GPIO_13)
188#define M_INT_GPIO_14               _SB_MAKEMASK1(K_INT_GPIO_14)
189#define M_INT_GPIO_15               _SB_MAKEMASK1(K_INT_GPIO_15)
190#define M_INT_LDT_FATAL             _SB_MAKEMASK1(K_INT_LDT_FATAL)
191#define M_INT_LDT_NONFATAL          _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
192#define M_INT_LDT_SMI               _SB_MAKEMASK1(K_INT_LDT_SMI)
193#define M_INT_LDT_NMI               _SB_MAKEMASK1(K_INT_LDT_NMI)
194#define M_INT_LDT_INIT              _SB_MAKEMASK1(K_INT_LDT_INIT)
195#define M_INT_LDT_STARTUP           _SB_MAKEMASK1(K_INT_LDT_STARTUP)
196#define M_INT_LDT_EXT               _SB_MAKEMASK1(K_INT_LDT_EXT)
197#define M_INT_PCI_ERROR             _SB_MAKEMASK1(K_INT_PCI_ERROR)
198#define M_INT_PCI_INTA              _SB_MAKEMASK1(K_INT_PCI_INTA)
199#define M_INT_PCI_INTB              _SB_MAKEMASK1(K_INT_PCI_INTB)
200#define M_INT_PCI_INTC              _SB_MAKEMASK1(K_INT_PCI_INTC)
201#define M_INT_PCI_INTD              _SB_MAKEMASK1(K_INT_PCI_INTD)
202#define M_INT_SPARE_2               _SB_MAKEMASK1(K_INT_SPARE_2)
203#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
204#define M_INT_MAC_0_CH1		    _SB_MAKEMASK1(K_INT_MAC_0_CH1)
205#define M_INT_MAC_1_CH1		    _SB_MAKEMASK1(K_INT_MAC_1_CH1)
206#define M_INT_MAC_2_CH1		    _SB_MAKEMASK1(K_INT_MAC_2_CH1)
207#endif /* 1250 PASS2 || 112x PASS1 */
208
209/*
210 * Interrupt mappings
211 */
212
213#define K_INT_MAP_I0	0		/* interrupt pins on processor */
214#define K_INT_MAP_I1	1
215#define K_INT_MAP_I2	2
216#define K_INT_MAP_I3	3
217#define K_INT_MAP_I4	4
218#define K_INT_MAP_I5	5
219#define K_INT_MAP_NMI	6		/* nonmaskable */
220#define K_INT_MAP_DINT	7		/* debug interrupt */
221
222/*
223 * LDT Interrupt Set Register (table 4-5)
224 */
225
226#define S_INT_LDT_INTMSG	      0
227#define M_INT_LDT_INTMSG              _SB_MAKEMASK(3,S_INT_LDT_INTMSG)
228#define V_INT_LDT_INTMSG(x)           _SB_MAKEVALUE(x,S_INT_LDT_INTMSG)
229#define G_INT_LDT_INTMSG(x)           _SB_GETVALUE(x,S_INT_LDT_INTMSG,M_INT_LDT_INTMSG)
230
231#define K_INT_LDT_INTMSG_FIXED	      0
232#define K_INT_LDT_INTMSG_ARBITRATED   1
233#define K_INT_LDT_INTMSG_SMI	      2
234#define K_INT_LDT_INTMSG_NMI	      3
235#define K_INT_LDT_INTMSG_INIT	      4
236#define K_INT_LDT_INTMSG_STARTUP      5
237#define K_INT_LDT_INTMSG_EXTINT	      6
238#define K_INT_LDT_INTMSG_RESERVED     7
239
240#define M_INT_LDT_EDGETRIGGER         0
241#define M_INT_LDT_LEVELTRIGGER        _SB_MAKEMASK1(3)
242
243#define M_INT_LDT_PHYSICALDEST        0
244#define M_INT_LDT_LOGICALDEST         _SB_MAKEMASK1(4)
245
246#define S_INT_LDT_INTDEST             5
247#define M_INT_LDT_INTDEST             _SB_MAKEMASK(10,S_INT_LDT_INTDEST)
248#define V_INT_LDT_INTDEST(x)          _SB_MAKEVALUE(x,S_INT_LDT_INTDEST)
249#define G_INT_LDT_INTDEST(x)          _SB_GETVALUE(x,S_INT_LDT_INTDEST,M_INT_LDT_INTDEST)
250
251#define S_INT_LDT_VECTOR              13
252#define M_INT_LDT_VECTOR              _SB_MAKEMASK(8,S_INT_LDT_VECTOR)
253#define V_INT_LDT_VECTOR(x)           _SB_MAKEVALUE(x,S_INT_LDT_VECTOR)
254#define G_INT_LDT_VECTOR(x)           _SB_GETVALUE(x,S_INT_LDT_VECTOR,M_INT_LDT_VECTOR)
255
256/*
257 * Vector format (Table 4-6)
258 */
259
260#define M_LDTVECT_RAISEINT		0x00
261#define M_LDTVECT_RAISEMBOX             0x40
262
263
264#endif	/* 1250/112x */
265