1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * MEMC definitions File: sbmemc.h 5 * 6 * Constants and macros pertaining to SiliconBackplane 7 * based MEMC cores 8 * 9 ********************************************************************* 10 * 11 * Copyright 2003,2004 12 * Broadcom Corporation. All rights reserved. 13 * 14 * This software is furnished under license and may be used and 15 * copied only in accordance with the following terms and 16 * conditions. Subject to these conditions, you may download, 17 * copy, install, use, modify and distribute modified or unmodified 18 * copies of this software in source and/or binary form. No title 19 * or ownership is transferred hereby. 20 * 21 * 1) Any source code used, modified or distributed must reproduce 22 * and retain this copyright notice and list of conditions 23 * as they appear in the source file. 24 * 25 * 2) No right is granted to use any trade name, trademark, or 26 * logo of Broadcom Corporation. The "Broadcom Corporation" 27 * name may not be used to endorse or promote products derived 28 * from this software without the prior written permission of 29 * Broadcom Corporation. 30 * 31 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 32 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 33 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 34 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 35 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 36 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 39 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 40 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 41 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 42 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 43 * THE POSSIBILITY OF SUCH DAMAGE. 44 ********************************************************************* */ 45 46 47#ifndef _SBMEMC_H 48#define _SBMEMC_H 49 50#define MEMC_CONTROL 0x00 51#define MEMC_CONFIG 0x04 52#define MEMC_REFRESH 0x08 53#define MEMC_BISTSTAT 0x0c /* unused */ 54#define MEMC_MODEBUF 0x10 55#define MEMC_BKCLS 0x14 /* unused */ 56#define MEMC_PRIORINV 0x18 /* unused */ 57#define MEMC_DRAMTIM 0x1c 58#define MEMC_INTSTAT 0x20 /* unused */ 59#define MEMC_INTMASK 0x24 /* unused */ 60#define MEMC_INTINFO 0x28 /* unused */ 61#define MEMC_NCDLCTL 0x30 62#define MEMC_RDNCDLCOR 0x34 63#define MEMC_WRNCDLCOR 0x38 64#define MEMC_MISCDLYCTL 0x3c 65#define MEMC_DQSGATENCDL 0x40 66#define MEMC_SPARE 0x44 /* unused */ 67#define MEMC_TPADDR 0x48 /* unused */ 68#define MEMC_TPDATA 0x4c /* unused */ 69#define MEMC_BARRIER 0x50 /* unused */ 70#define MEMC_CORE 0x54 /* unused */ 71 72 73/* MEMC Core Init values (OCP ID 0x80f) */ 74 75/* For sdr: */ 76#define MEMC_SD_CONFIG_INIT 0x0004a000 77#define MEMC_SD_DRAMTIM2_INIT 0x000754d8 /* CAS latency 2 */ 78#define MEMC_SD_DRAMTIM3_INIT 0x000754da /* CAS latency 3 */ 79#define MEMC_SD_RDNCDLCOR_INIT 0x00000000 80#define MEMC_SD_WRNCDLCOR_INIT 0x49351200 81#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 */ 82#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b 83#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 */ 84#define MEMC_SD_CONTROL_INIT0 0x00000002 /* SeqEn */ 85#define MEMC_SD_CONTROL_INIT1 0x00000008 /* PreCmd */ 86#define MEMC_SD_CONTROL_INIT2 0x00000004 /* RefCmd */ 87#define MEMC_SD_CONTROL_INIT3 0x00000010 /* MRSCmd */ 88#define MEMC_SD_CONTROL_INIT4 0x00000001 /* DRAMAccEn */ 89#define MEMC_SD_MODEBUF_INIT 0x00000000 90#define MEMC_SD_REFRESH_INIT 0x0000840f 91 92#if defined(SDRM16X16X2) 93/* This is for 64 MB as 16M X 16 X 2 (e.g., bcm95365rr) */ 94#define MEMC_GEOMETRY 95#define MEMC_SDR_INIT 0x0008 96#define MEMC_SDR_MODE 0x23 97#define MEMC_SDR_NCDL 0x00000000 /* was 0x00020032 */ 98#define MEMC_SDR1_NCDL 0x00000000 /* was 0x0002020f */ 99#elif defined(SDRM4X32X1) 100/* This is for 16 MB as 4M X 32 X 1 */ 101#define MEMC_GEOMETRY 102#define MEMC_SDR_INIT 0x0000 103#define MEMC_SDR_MODE 0x32 104#define MEMC_SDR_NCDL 0x00000000 /* was 0x00020032 */ 105#define MEMC_SDR1_NCDL 0x00000000 /* was 0x0002020f */ 106#elif defined(SDRM8X8X4) 107/* Default: 32MB as 8M x 8 x 4 */ 108#define MEMC_GEOMETRY 109#define MEMC_SDR_INIT 0x0008 110#define MEMC_SDR_MODE 0x32 111#define MEMC_SDR_NCDL 0x00020032 112#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 */ 113#elif defined(SDRM32X8X4) 114/* This is for 128 MB as 32M X 8 X 4 */ 115#define MEMC_GEOMETRY 116#define MEMC_SDR_INIT 0x0010 /* 1024 columns */ 117#define MEMC_SDR_MODE 0x32 /* CAS 3, Burst 4 */ 118#define MEMC_SDR_NCDL 0x00000000 /* was 0x00020032 */ 119#define MEMC_SDR1_NCDL 0x00000000 /* was 0x0002020f */ 120#elif defined(SDRM8X16X2) 121/* This is for 32 MB as 8M X 16 X 2 */ 122#define MEMC_GEOMETRY 123#define MEMC_SDR_INIT 0x0008 /* 512 columns */ 124#define MEMC_SDR_MODE 0x32 /* 0x30 = CAS 3, 0x02 = Burst Length 4 */ 125#define MEMC_SDR_NCDL 0x00000000 /* was 0x00020032 */ 126#define MEMC_SDR1_NCDL 0x00000000 /* was 0x0002020f */ 127#endif 128 129 130/* For ddr: */ 131#define MEMC_CONFIG_INIT 0x00048000 132#define MEMC_DRAMTIM2_INIT 0x000754d8 /* CL = 2 */ 133#define MEMC_DRAMTIM25_INIT 0x000754d9 /* CL = 2.5 */ 134#define MEMC_RDNCDLCOR_INIT 0x00000000 135#define MEMC_WRNCDLCOR_INIT 0x49351200 136#define MEMC_1_WRNCDLCOR_INIT 0x14500200 137#define MEMC_DQSGATENCDL_INIT 0x00030000 138#define MEMC_MISCDLYCTL_INIT 0x21061c1b 139#define MEMC_1_MISCDLYCTL_INIT 0x21021400 140#define MEMC_NCDLCTL_INIT 0x00002001 141#define MEMC_CONTROL_INIT0 0x00000002 142#define MEMC_CONTROL_INIT1 0x00000008 143#define MEMC_MODEBUF_INIT0 0x00004000 144#define MEMC_CONTROL_INIT2 0x00000010 145#define MEMC_MODEBUF_INIT1 0x00000100 146#define MEMC_CONTROL_INIT3 0x00000010 147#define MEMC_CONTROL_INIT4 0x00000008 148#define MEMC_REFRESH_INIT 0x0000840f 149#define MEMC_CONTROL_INIT5 0x00000004 150#define MEMC_MODEBUF_INIT2 0x00000000 151#define MEMC_CONTROL_INIT6 0x00000010 152#define MEMC_CONTROL_INIT7 0x00000001 153 154#if defined(DDRM16X16X2) 155/* This is for 64 MB as 16M X 16 X 2 */ 156#define MEMC_GEOMETRY 157#define MEMC_DDR_INIT 0x0009 158#define MEMC_DDR_MODE 0x62 159#define MEMC_DDR_NCDL 0x00000000 /* was 0005050a */ 160#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 */ 161#elif defined(DDRM32X16X2) 162/* This is for 128 MB as 32M X 16 X 2 (e.g., bcm95836cpci) */ 163#define MEMC_GEOMETRY 164#define MEMC_DDR_INIT 0x0011 /* for full 128MB */ 165#define MEMC_DDR_MODE 0x62 166#define MEMC_DDR_NCDL 0x00000000 /* was 0x0005050a */ 167#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 */ 168#elif defined(DDRM64X16X2) 169/* This is for 256 MB as 64M X 16 X 2 (e.g., bcm95836cpci Rev 2) */ 170#define MEMC_GEOMETRY 171#define MEMC_DDR_INIT 0x0011 /* for full 256MB (adds row) */ 172#define MEMC_DDR_MODE 0x62 173#define MEMC_DDR_NCDL 0x00000000 174#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 */ 175#endif 176 177#ifndef MEMC_GEOMETRY 178#error "sbmemc: geometry must be defined" 179#endif 180 181/* mask for sdr/ddr calibration registers */ 182#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff 183#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff 184#define MEMC_DQSGATENCDL_G_MASK 0x000000ff 185 186/* masks for miscdlyctl registers */ 187#define MEMC_MISC_SM_MASK 0x30000000 188#define MEMC_MISC_SM_SHIFT 28 189#define MEMC_MISC_SD_MASK 0x0f000000 190#define MEMC_MISC_SD_SHIFT 24 191 192/* hw threshhold for calculating wr/rd for sdr memc */ 193#define MEMC_CD_THRESHOLD 128 194 195/* Low bit of init register says if memc is ddr or sdr */ 196#define MEMC_CONFIG_DDR 0x00000001 197 198#endif /* _SBMEMC_H */ 199