1/*  *********************************************************************
2    *  Broadcom Common Firmware Environment (CFE)
3    *
4    *  PCI core definitions                  	File: sb_pci.c
5    *
6    *********************************************************************
7    *
8    *  Copyright 2003
9    *  Broadcom Corporation. All rights reserved.
10    *
11    *  This software is furnished under license and may be used and
12    *  copied only in accordance with the following terms and
13    *  conditions.  Subject to these conditions, you may download,
14    *  copy, install, use, modify and distribute modified or unmodified
15    *  copies of this software in source and/or binary form.  No title
16    *  or ownership is transferred hereby.
17    *
18    *  1) Any source code used, modified or distributed must reproduce
19    *     and retain this copyright notice and list of conditions
20    *     as they appear in the source file.
21    *
22    *  2) No right is granted to use any trade name, trademark, or
23    *     logo of Broadcom Corporation.  The "Broadcom Corporation"
24    *     name may not be used to endorse or promote products derived
25    *     from this software without the prior written permission of
26    *     Broadcom Corporation.
27    *
28    *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
29    *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
30    *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
31    *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
32    *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
33    *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
34    *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35    *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
36    *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
37    *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
38    *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
39    *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
40    *     THE POSSIBILITY OF SUCH DAMAGE.
41    ********************************************************************* */
42
43#ifndef _SBPCI_H_
44#define _SBPCI_H_
45
46/*
47 * Register and bit definitions for the PCI core (OCP ID 0x804)
48 *
49 * The PCI core can be operated in either host or device (aka client)
50 * mode.  Interpretations of some registers are different in the two
51 * modes.  In host mode, the core serves as the PCI host bridge for
52 * the internal CPU.  In device mode, there is an external master
53 * responsible for PCI configuration and the bcm47xx appears as a PCI
54 * device. Some derivative parts the same core but in device mode only.
55 *
56 * In addition to the registers in enumeration space, the PCI core
57 * provides an extended set of PCI configuration registers accessible
58 * only to the system host via PCI configuration cycles.
59 */
60
61#define K_PCI_VENDOR_BROADCOM  0x14e4
62
63/* PCI Enumeration Space (Section 10.4) */
64
65#define R_PCI_CONTROL           0x000    /* not device mode */
66#define R_BIST_STATUS           0x00C
67#define R_PCI_ARB_CONTROL       0x010
68#define R_INT_STATUS            0x020
69#define R_INT_MASK              0x024
70#define R_SB_TO_PCI_MAILBOX     0x028
71
72#define R_BROADCAST_ADDRESS     0x050
73#define R_BROADCAST_DATA        0x054
74
75#define R_GPIO_INPUT            0x060    /* BCM440x */
76#define R_GPIO_OUTPUT           0x064    /* BCM440x */
77#define R_GPIO_OUT_EN           0x068    /* BCM440x */
78#define R_GPIO_CONTROL          0x06C    /* BCM440x */
79
80#define R_SB_TO_PCI_TRANSLATION0 0x100
81#define R_SB_TO_PCI_TRANSLATION1 0x104
82#define R_SB_TO_PCI_TRANSLATION2 0x108   /* undocumented for BCM440x */
83
84/* SPROM Shadow Area */
85#define SROM_OFFSET              0x800
86#define SROM_SIZE                0x100
87
88
89/* PCI Configuration Registers */
90
91/* Standard Configuration Registers (Section 10.5.1, see pci.h) */
92
93/* Power Managment Capability (Section 10.5.2) */
94
95#define PCI_PMC_REG            0x40
96#define PCI_PMCSR_REG          0x44
97#define PCI_PMDATA_REG         0x48
98
99/* Device Specific Configuration Space Registers (10.5.3) */
100
101#define PCI_PCIBAR0WINDOW_REG  0x80
102#define PCI_PCIBAR1WINDOW_REG  0x84
103#define PCI_SPROMCONTROL_REG   0x88
104#define PCI_BAR1BURSTCTRL_REG  0x8C
105#define PCI_PCIINTSTATUS_REG   0x90
106#define PCI_PCIINTMASK_REG     0x94
107#define PCI_SBMAILBOX_REG      0x98
108#define PCI_BACKPLANEADDR_REG  0xA0
109#define PCI_BACKPLANEDATA_REG  0xA4
110
111/* Extended PCI Configuration Space (XXX reconcile with above) */
112
113#define R_PCI_BAR0_WINDOW       0x080
114#define R_PCI_BAR1_WINDOW       0x084
115#define R_BAR1_BURST_CONTROL    0x08C
116#define R_PCI_INT_STATUS        0x090
117#define R_PCI_INT_MASK          0x094
118#define R_PCI_TO_SB_MAILBOX     0x098
119
120#define R_BACKPLANE_ADDRESS     0x0A0
121#define R_BACKPLANE_DATA        0x0A4
122
123
124/* PCI Core Enumeration Space Registers */
125
126/* PCICTL: PCI Control Register (0x000, R/W) */
127
128#define M_PCICTL_OE             _DD_MAKEMASK1(0)        /* PCIResetOutputEn */
129#define M_PCICTL_RO             _DD_MAKEMASK1(1)        /* PCIResetOutput */
130#define M_PCICTL_CE             _DD_MAKEMASK1(2)        /* PCIClockOutputEn */
131#define M_PCICTL_CO             _DD_MAKEMASK1(3)        /* PCIClockOutput */
132
133/* PCIARB: PCI Arbiter Control Register (0x010, R/W) */
134
135#define M_PCIARB_IA             _DD_MAKEMASK1(0)        /* InternalArbiter */
136#define M_PCIARB_EA             _DD_MAKEMASK1(1)        /* ExternalArbiter */
137
138#define S_PCIARB_PI             2                       /* ParkID */
139#define M_PCIARB_PI             _DD_MAKEMASK(2,S_PCIARB_PI)
140#define V_PCIARB_PI(x)          _DD_MAKEVALUE(x,S_PCIARB_PI)
141#define G_PCIARB_PI(x)          _DD_GETVALUE(x,S_PCIARB_PI,M_PCIARB_PI)
142#define K_ARB_PARK_GNT0         0x0
143#define K_ARB_PARK_GNT1         0x1
144#define K_ARB_PARK_INT          0x2
145#define K_ARB_PARK_LAST         0x3
146
147/* ISR: Interrupt Status Register (0x020, R/W) */
148/* IMR: Interrupt Mask Register   (0x024, R/W) */
149
150#define M_PCIINT_PA             _DD_MAKEMASK1(0)        /* PCIIntA */
151#define M_PCIINT_PB             _DD_MAKEMASK1(1)        /* PCIIntB */
152#define M_PCIINT_PS             _DD_MAKEMASK1(2)        /* PCISerr */
153#define M_PCIINT_PP             _DD_MAKEMASK1(3)        /* PCIPerr */
154#define M_PCIINT_PM             _DD_MAKEMASK1(4)        /* PCIPME */
155
156#define S_PCIINT_F0             8                       /* Function0 */
157#define M_PCIINT_F0             _DD_MAKEMASK(2,S_PCIINT_F0)
158#define V_PCIINT_F0(x)          _DD_MAKEVALUE(x,S_PCIINT_F0)
159#define G_PCIINT_F0(x)          _DD_GETVALUE(x,S_PCIINT_F0,M_PCIINT_F0)
160
161#define S_PCIINT_F1             10                      /* Function1 */
162#define M_PCIINT_F1             _DD_MAKEMASK(2,S_PCIINT_F1)
163#define V_PCIINT_F1(x)          _DD_MAKEVALUE(x,S_PCIINT_F1)
164#define G_PCIINT_F1(x)          _DD_GETVALUE(x,S_PCIINT_F1,M_PCIINT_F1)
165
166#define S_PCIINT_F2             12                      /* Function2 */
167#define M_PCIINT_F2             _DD_MAKEMASK(2,S_PCIINT_F2)
168#define V_PCIINT_F2(x)          _DD_MAKEVALUE(x,S_PCIINT_F2)
169#define G_PCIINT_F2(x)          _DD_GETVALUE(x,S_PCIINT_F2,M_PCIINT_F2)
170
171#define S_PCIINT_F3             14                      /* Function3 */
172#define M_PCIINT_F3             _DD_MAKEMASK(2,S_PCIINT_F3)
173#define V_PCIINT_F3(x)          _DD_MAKEVALUE(x,S_PCIINT_F3)
174#define G_PCIINT_F3(x)          _DD_GETVALUE(x,S_PCIINT_F3,M_PCIINT_F3)
175
176/* SBMBOX: System Backplane to PCI Mailbox Register (0x028, WO) */
177
178#define S_SBMBOX_F0             8                      /* Function0 */
179#define M_SBMBOX_F0             _DD_MAKEMASK(2,S_SBMBOX_F0)
180#define V_SBMBOX_F0(x)          _DD_MAKEVALUE(x,S_SBMBOX_F0)
181#define G_SBMBOX_F0(x)          _DD_GETVALUE(x,S_SBMBOX_F0,M_SBMBOX_F0)
182
183#define S_SBMBOX_F1             10                      /* Function1 */
184#define M_SBMBOX_F1             _DD_MAKEMASK(2,S_SBMBOX_F1)
185#define V_SBMBOX_F1(x)          _DD_MAKEVALUE(x,S_SBMBOX_F1)
186#define G_SBMBOX_F1(x)          _DD_GETVALUE(x,S_SBMBOX_F1,M_SBMBOX_F1)
187
188#define S_SBMBOX_F2             12                      /* Function2 */
189#define M_SBMBOX_F2             _DD_MAKEMASK(2,S_SBMBOX_F2)
190#define V_SBMBOX_F2(x)          _DD_MAKEVALUE(x,S_SBMBOX_F2)
191#define G_SBMBOX_F2(x)          _DD_GETVALUE(x,S_SBMBOX_F2,M_SBMBOX_F2)
192
193#define S_SBMBOX_F3             14                      /* Function3 */
194#define M_SBMBOX_F3             _DD_MAKEMASK(2,S_SBMBOX_F3)
195#define V_SBMBOX_F3(x)          _DD_MAKEVALUE(x,S_SBMBOX_F3)
196#define G_SBMBOX_F3(x)          _DD_GETVALUE(x,S_SBMBOX_F3,M_SBMBOX_F3)
197
198/* SBXLAT: System Backplane to PCI Translation 0 Register (0x100, R/W) */
199/* SBXLAT: System Backplane to PCI Translation 1 Register (0x104, R/W) */
200/* SBXLAT: System Backplane to PCI Translation 2 Register (0x108, R/W) */
201
202#define S_SBXLAT_AT             0                       /* AccessType */
203#define M_SBXLAT_AT             _DD_MAKEMASK(2,S_SBXLAT_AT)
204#define V_SBXLAT_AT(x)          _DD_MAKEVALUE(x,S_SBXLAT_AT)
205#define G_SBXLAT_AT(x)          _DD_GETVALUE(x,S_SBXLAT_AT,M_SBXLAT_AT)
206#define K_AT_RW                 0
207#define K_AT_IO_RW              1
208#define K_AT_CFG0_RW            2
209#define K_AT_CFG1_RW            3
210
211#define M_SBXLAT_PE             _DD_MAKEMASK1(2)        /* PrefetchEn */
212#define M_SBXLAT_WB             _DD_MAKEMASK1(3)        /* WriteBurstEn */
213
214/* SBXLAT0,1 span 64MB */
215#define S_SBXLAT_UA             26                      /* UpperAddress */
216#define M_SBXLAT_UA             _DD_MAKEMASK(6,S_SBXLAT_UA)
217#define V_SBXLAT_UA(x)          _DD_MAKEVALUE(x,S_SBXLAT_UA)
218#define G_SBXLAT_UA(x)          _DD_GETVALUE(x,S_SBXLAT_UA,M_SBXLAT_UA)
219
220/* SBXLAT2 spans 1GB */
221#define S_SBXLAT2_UA            30                      /* UpperAddress */
222#define M_SBXLAT2_UA            _DD_MAKEMASK(2,S_SBXLAT2_UA)
223#define V_SBXLAT2_UA(x)         _DD_MAKEVALUE(x,S_SBXLAT2_UA)
224#define G_SBXLAT2_UA(x)         _DD_GETVALUE(x,S_SBXLAT2_UA,M_SBXLAT2_UA)
225
226
227/* Device Specific PCI Configuration Registers */
228
229/* SPROMCTL: SPROM Control Register (0x88, R/W) */
230
231#define S_SPROMCTL_SS           0                       /* SPROMSize */
232#define M_SPROMCTL_SS           _DD_MAKEMASK(2,S_SPROMCTL_SS)
233#define V_SPROMCTL_SS(x)        _DD_MAKEVALUE(x,S_SPROMCTL_SS)
234#define G_SPROMCTL_SS(x)        _DD_GETVALUE(x,S_SPROMCTL_SS,M_SPROMCTL_SS)
235#define K_SPROM_SIZE_128        0
236#define K_SPROM_SIZE_512        1
237#define K_SPROM_SIZE_2048       2
238
239#define M_SPROMCTL_SB           _DD_MAKEMASK1(2)        /* SPROMBlank */
240#define M_SPROMCTL_SL           _DD_MAKEMASK1(3)        /* SPROMLocked */
241#define M_SPROMCTL_SW           _DD_MAKEMASK1(4)        /* SPROMWriteEn */
242
243/* BAR1BURST: Bar 1 Burst Control Register (0x8C, R/W) */
244
245#define M_BAR1BURST_WB          _DD_MAKEMASK1(0)        /* WriteBufferEn */
246#define M_BAR1BURST_PE          _DD_MAKEMASK1(1)        /* PrefetchEn */
247#define M_BAR1BURST_ET          _DD_MAKEMASK1(4)        /* TransactionTimer */
248
249/* SBISR: PCI Interrupt Status Register (0x90, R/W) */
250/* SBIMR: PCI Interrupt Mask Register   (0x94, R/W) */
251
252#define S_SBINT_BM              0                       /* SBMailbox */
253#define M_SBINT_BM              _DD_MAKEMASK(2,S_SBINT_BM)
254#define V_SBINT_BM(x)           _DD_MAKEVALUE(x,S_SBINT_BM)
255#define G_SBINT_BM(x)           _DD_GETVALUE(x,S_SBINT_BM,M_SBINT_BM)
256
257#define M_SBINT_SB               _DD_MAKEMASK1(2)        /* SBError */
258
259/* The following on PCI 2.3 versions (Rev >= 6) only. */
260#define S_SBINT_IM              8                       /* SBIntMask */
261#define M_SBINT_IM              _DD_MAKEMASK(8,S_SBINT_IM)
262#define V_SBINT_IM(x)           _DD_MAKEVALUE(x,S_SBINT_IM)
263#define G_SBINT_IM(x)           _DD_GETVALUE(x,S_SBINT_IM,M_SBINT_IM)
264
265/* PCIMBOX: PCI to System Backplane Mailbox Register (0x98, WO) */
266
267#define S_PCIMBOX_BM            0                       /* SBMailbox */
268#define M_PCIMBOX_BM            _DD_MAKEMASK(2,S_PCIMBOX_BM)
269#define V_PCIMBOX_BM(x)         _DD_MAKEVALUE(x,S_PCIMBOX_BM)
270#define G_PCIMBOX_BM(x)         _DD_GETVALUE(x,S_PCIMBOX_BM,M_PCIMBOX_BM)
271
272#endif /* _SBPCI_H_ */
273