1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * Ethernet MAC definitions File: sb_mac.h 5 * 6 ********************************************************************* 7 * 8 * Copyright 2003 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and 13 * conditions. Subject to these conditions, you may download, 14 * copy, install, use, modify and distribute modified or unmodified 15 * copies of this software in source and/or binary form. No title 16 * or ownership is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions 20 * as they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products derived 25 * from this software without the prior written permission of 26 * Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 40 * THE POSSIBILITY OF SUCH DAMAGE. 41 42 ********************************************************************* */ 43 44#ifndef _SBMAC_H_ 45#define _SBMAC_H_ 46 47/* 48 * Register and bit definitions for the 10/100 MACs and associated DMA 49 * engines (OCP ID 0x806) 50 */ 51 52 53/* Ethernet 10/100 Core (Section 5, Table 102) */ 54 55#define R_DEV_CONTROL 0x000 56#define R_BIST_STATUS 0x00C 57#define R_WAKEUP_LENGTH 0x010 58#define R_INT_STATUS 0x020 59#define R_INT_MASK 0x024 60#define R_GP_TIMER 0x028 61#define R_ENET_FT_ADDR 0x090 62#define R_ENET_FT_DATA 0x094 63#define R_EMAC_XMT_MAX_BURST 0x0A0 64#define R_EMAC_RCV_MAX_BURST 0x0A4 65#define R_EMAC_CONTROL 0x0A8 66#define R_INT_RECV_LAZY 0x100 67 68/* Core DMA Engine Registers (Section 3) */ 69 70#define R_XMT_CONTROL 0x200 71#define R_XMT_ADDR 0x204 72#define R_XMT_PTR 0x208 73#define R_XMT_STATUS 0x20C 74#define R_RCV_CONTROL 0x210 75#define R_RCV_ADDR 0x214 76#define R_RCV_PTR 0x218 77#define R_RCV_STATUS 0x21C 78 79/* EMAC Registers */ 80 81#define R_RCV_CONFIG 0x400 82#define R_RCV_MAX_LENGTH 0x404 83#define R_XMT_MAX_LENGTH 0x408 84#define R_MII_STATUS_CONTROL 0x410 85#define R_MII_DATA 0x414 86#define R_ENET_INT_MASK 0x418 87#define R_ENET_INT_STATUS 0x41C 88#define R_CAM_DATA_L 0x420 89#define R_CAM_DATA_H 0x424 90#define R_CAM_CONTROL 0x428 91#define R_ENET_CONTROL 0x42C 92#define R_XMT_CONTROL1 0x430 93#define R_XMT_WATERMARK 0x434 94#define R_MIB_CONTROL 0x438 95#define R_MIB_COUNTERS 0x500 /* Block base address */ 96 97/* Also, Core Configuration Space Registers at 0xF00 (see sbbp.h) */ 98 99 100/* Ethernet PHY MII (Section 5, Table 103) */ 101 102#define R_BMCR 0x00 103#define R_BMSR 0x01 104#define R_PHYIDR1 0x02 105#define R_PHYIDR2 0x03 106#define R_ANAR 0x04 107#define R_ANLPAR 0x05 108#define R_ANER 0x06 109#define R_NEXT_PAGE 0x07 110#define R_LP_NEXT_PAGE 0x08 111 112#define R_100X_AUX_CONTROL 0x10 113#define R_100X_AUX_STATUS 0x11 114#define R_100X_RCV_ERROR_CTR 0x12 115#define R_100X_CARR_SENSE_CTR 0x13 116#define R_100X_DISCONNECT_CRT 0x14 117#define R_AUX_CTL_STATUS 0x18 118#define R_AUX_STATUS_SUMMARY 0x19 119#define R_INTERRUPT 0x1A 120#define R_AUX_MODE_2 0x1B 121#define R_10BT_T_ERR_GEN_STAT 0x1C 122#define R_AUX_MODE 0x1D 123#define R_AUX_MULTI_PHY 0x1E 124 125 126/* Ethernet MAC Registers */ 127 128/* DVCTL: Device Control Register (0x000, R/W) */ 129 130#define M_DVCTL_PM _DD_MAKEMASK1(7) /* PatMatchEn */ 131#define M_DVCTL_IP _DD_MAKEMASK1(10) /* InternalEPHY */ 132#define M_DVCTL_ER _DD_MAKEMASK1(15) /* EPHYReset */ 133#define M_DVCTL_MP _DD_MAKEMASK1(16) /* MIIPHYModeEn */ 134#define M_DVCTL_CO _DD_MAKEMASK1(17) /* ClkOutputEn */ 135 136#define S_DVCTL_PA 18 /* PHYAddrReg */ 137#define M_DVCTL_PA _DD_MAKEMASK(5,S_DVCTL_PA) 138#define V_DVCTL_PA(x) _DD_MAKEVALUE(x,S_DVCTL_PA) 139#define G_DVCTL_PA(x) _DD_GETVALUE(x,S_DVCTL_PA,M_DVCTL_PA) 140 141/* BIST: Built-In Self Test Register (0x00C, RO) */ 142 143#define S_BIST_BS 0 /* BISTStatus */ 144#define M_BIST_BS _DD_MAKEMASK(2,S_BIST_BS) 145#define V_BIST_BS(x) _DD_MAKEVALUE(x,S_BIST_BS) 146#define G_BIST_BS(x) _DD_GETVALUE(x,S_BIST_BS,M_BIST_BS) 147 148/* WKUP: Wakeup Length Register (0x010, R/W) */ 149 150#define S_WKUP_P0 0 /* Pattern0 */ 151#define M_WKUP_P0 _DD_MAKEMASK(7,S_WKUP_P0) 152#define V_WKUP_P0(x) _DD_MAKEVALUE(x,S_WKUP_P0) 153#define G_WKUP_P0(x) _DD_GETVALUE(x,S_WKUP_P0,M_WKUP_P0) 154 155#define M_WKUP_D0 _DD_MAKEMASK1(7) /* Disable0 */ 156 157#define S_WKUP_P1 0 /* Pattern1 */ 158#define M_WKUP_P1 _DD_MAKEMASK(7,S_WKUP_P1) 159#define V_WKUP_P1(x) _DD_MAKEVALUE(x,S_WKUP_P1) 160#define G_WKUP_P1(x) _DD_GETVALUE(x,S_WKUP_P1,M_WKUP_P1) 161 162#define M_WKUP_D1 _DD_MAKEMASK1(15) /* Disable1 */ 163 164#define S_WKUP_P2 0 /* Pattern2 */ 165#define M_WKUP_P2 _DD_MAKEMASK(7,S_WKUP_P2) 166#define V_WKUP_P2(x) _DD_MAKEVALUE(x,S_WKUP_P2) 167#define G_WKUP_P2(x) _DD_GETVALUE(x,S_WKUP_P2,M_WKUP_P2) 168 169#define M_WKUP_D2 _DD_MAKEMASK1(23) /* Disable2 */ 170 171#define S_WKUP_P3 0 /* Pattern3 */ 172#define M_WKUP_P3 _DD_MAKEMASK(7,S_WKUP_P3) 173#define V_WKUP_P3(x) _DD_MAKEVALUE(x,S_WKUP_P3) 174#define G_WKUP_P3(x) _DD_GETVALUE(x,S_WKUP_P3,M_WKUP_P3) 175 176#define M_WKUP_D3 _DD_MAKEMASK1(31) /* Disable3 */ 177 178/* ISR: Interrupt Status Register (0x020, R/W) */ 179/* IMR: Interrupt Mask Register (0x024, R/W) */ 180 181#define M_INT_PM _DD_MAKEMASK1(6) /* PME */ 182#define M_INT_TO _DD_MAKEMASK1(7) /* TimeOut */ 183#define M_INT_DE _DD_MAKEMASK1(10) /* DescErr */ 184#define M_INT_DA _DD_MAKEMASK1(11) /* DataErr */ 185#define M_INT_DP _DD_MAKEMASK1(12) /* DescProtoErr */ 186#define M_INT_RU _DD_MAKEMASK1(13) /* RcvDescUf */ 187#define M_INT_RO _DD_MAKEMASK1(14) /* RcvFIFOOf */ 188#define M_INT_XU _DD_MAKEMASK1(15) /* XmtFIFOUf */ 189#define M_INT_RI _DD_MAKEMASK1(16) /* RcvInt */ 190#define M_INT_XI _DD_MAKEMASK1(24) /* XmtInt */ 191#define M_INT_EI _DD_MAKEMASK1(26) /* EMACInterrupt */ 192#define M_INT_IW _DD_MAKEMASK1(27) /* IntMIIWrite */ 193#define M_INT_IR _DD_MAKEMASK1(28) /* IntMIIRead */ 194 195/* EMCTL: Ethernet MAC Control Register (0x0A8, R/W) */ 196 197#define M_EMCTL_CC _DD_MAKEMASK1(0) /* CRCCheckXmt */ 198#define M_EMCTL_EP _DD_MAKEMASK1(2) /* EPHYPowerDown */ 199#define M_EMCTL_ED _DD_MAKEMASK1(3) /* EPHYEnergyDetect */ 200 201#define S_EMCTL_LC 5 /* LEDControl */ 202#define M_EMCTL_LC _DD_MAKEMASK(3,S_EMCTL_LC) 203#define V_EMCTL_LC(x) _DD_MAKEVALUE(x,S_EMCTL_LC) 204#define G_EMCTL_LC(x) _DD_GETVALUE(x,S_EMCTL_LC,M_EMCTL_LC) 205 206/* EMFLOW: Ethernet MAC Flow Control Register (0x0AC, R/W) */ 207 208#define S_EMFLOW_RF 0 /* RcvFlowControl */ 209#define M_EMFLOW_RF _DD_MAKEMASK(8,S_EMFLOW_RF) 210#define V_EMFLOW_RF(x) _DD_MAKEVALUE(x,S_EMFLOW_RF) 211#define G_EMFLOW_RF(x) _DD_GETVALUE(x,S_EMFLOWL_RF,M_EFLOW_RF) 212 213#define M_EMFLOW_PE _DD_MAKEMASK1(15) /* PauseEn */ 214 215 216/* INTLZY: Interrupt Receive Lazy Timeout Register (0x100, R/W) */ 217 218#define S_INTLZY_TO 0 /* TimeOut */ 219#define M_INTLZY_TO _DD_MAKEMASK(24,S_INTLZY_TO) 220#define V_INTLZY_TO(x) _DD_MAKEVALUE(x,S_INTLZY_TO) 221#define G_INTLZY_TO(x) _DD_GETVALUE(x,S_INTLZY_TO,M_INTLZY_TO) 222 223#define S_INTLZY_FC 24 /* FrameCount */ 224#define M_INTLZY_FC _DD_MAKEMASK(8,S_INTLZY_FC) 225#define V_INTLZY_FC(x) _DD_MAKEVALUE(x,S_INTLZY_FC) 226#define G_INTLZY_FC(x) _DD_GETVALUE(x,S_INTLZY_FC,M_INTLZY_FC) 227 228 229/* RCFG: Receiver Configuration Register (0x400, R/W) */ 230 231#define M_RCFG_DB _DD_MAKEMASK1(0) /* DisB */ 232#define M_RCFG_AM _DD_MAKEMASK1(1) /* AccMult */ 233#define M_RCFG_RD _DD_MAKEMASK1(2) /* RcvDisableTx */ 234#define M_RCFG_PR _DD_MAKEMASK1(3) /* Prom */ 235#define M_RCFG_LB _DD_MAKEMASK1(4) /* Lpbk */ 236#define M_RCFG_EF _DD_MAKEMASK1(5) /* EnFlow */ 237#define M_RCFG_UF _DD_MAKEMASK1(6) /* UniFlow */ 238#define M_RCFG_RF _DD_MAKEMASK1(7) /* RejectFilter */ 239 240 241/* MIICTL: MII Status/Control Register (0x410, R/W) */ 242 243#define S_MIICTL_MD 0 /* MDC */ 244#define M_MIICTL_MD _DD_MAKEMASK(7,S_MIICTL_MD) 245#define V_MIICTL_MD(x) _DD_MAKEVALUE(x,S_MIICTL_MD) 246#define G_MIICTL_MD(x) _DD_GETVALUE(x,S_MIICTL_MD,M_MIICTL_MD) 247 248#define M_MIICTL_PR _DD_MAKEMASK1(7) /* PreEn */ 249 250/* MIIDATA: MII Data Register (0x414, R/W) */ 251 252#define S_MIIDATA_D 0 /* Data */ 253#define M_MIIDATA_D _DD_MAKEMASK(16,S_MIIDATA_D) 254#define V_MIIDATA_D(x) _DD_MAKEVALUE(x,S_MIIDATA_D) 255#define G_MIIDATA_D(x) _DD_GETVALUE(x,S_MIIDATA_D,M_MIIDATA_D) 256 257#define S_MIIDATA_TA 16 /* Turnaround */ 258#define M_MIIDATA_TA _DD_MAKEMASK(2,S_MIIDATA_TA) 259#define V_MIIDATA_TA(x) _DD_MAKEVALUE(x,S_MIIDATA_TA) 260#define G_MIIDATA_TA(x) _DD_GETVALUE(x,S_MIIDATA_TA,M_MIIDATA_TA) 261#define K_TA_VALID 0x2 262 263#define S_MIIDATA_RA 18 /* RegAddr */ 264#define M_MIIDATA_RA _DD_MAKEMASK(5,S_MIIDATA_RA) 265#define V_MIIDATA_RA(x) _DD_MAKEVALUE(x,S_MIIDATA_RA) 266#define G_MIIDATA_RA(x) _DD_GETVALUE(x,S_MIIDATA_RA,M_MIIDATA_RA) 267 268#define S_MIIDATA_PM 23 /* PhysMedia */ 269#define M_MIIDATA_PM _DD_MAKEMASK(5,S_MIIDATA_PM) 270#define V_MIIDATA_PM(x) _DD_MAKEVALUE(x,S_MIIDATA_PM) 271#define G_MIIDATA_PM(x) _DD_GETVALUE(x,S_MIIDATA_PM,M_MIIDATA_PM) 272 273#define S_MIIDATA_OP 28 /* Opcode */ 274#define M_MIIDATA_OP _DD_MAKEMASK(2,S_MIIDATA_OP) 275#define V_MIIDATA_OP(x) _DD_MAKEVALUE(x,S_MIIDATA_OP) 276#define G_MIIDATA_OP(x) _DD_GETVALUE(x,S_MIIDATA_OP,M_MIIDATA_OP) 277#define K_MII_OP_WRITE 0x1 278#define K_MII_OP_READ 0x2 279 280#define S_MIIDATA_SB 30 /* StartBits */ 281#define M_MIIDATA_SB _DD_MAKEMASK(2,S_MIIDATA_SB) 282#define V_MIIDATA_SB(x) _DD_MAKEVALUE(x,S_MIIDATA_SB) 283#define G_MIIDATA_SB(x) _DD_GETVALUE(x,S_MIIDATA_SB,M_MIIDATA_SB) 284#define K_MII_START 0x1 285 286/* EIMR: Ethernet Interrupt Mask Register (0x418, R/W) */ 287/* EISR: Ethernet Interrupt Status Register (0x41C, R/W) */ 288 289#define M_EINT_MI _DD_MAKEMASK1(0) /* MIIInt */ 290#define M_EINT_MB _DD_MAKEMASK1(1) /* MIBInt */ 291#define M_EINT_FM _DD_MAKEMASK1(2) /* FlowInt */ 292 293/* CAM: CAM Data Low Register (0x420, R/W) */ 294 295#define S_CAM_CD_L 0 /* CAMDataL */ 296#define M_CAM_CD_L _DD_MAKEMASK(32,S_CAM_CD_L) 297#define V_CAM_CD_L(x) _DD_MAKEVALUE(x,S_CAM_CD_L) 298#define G_CAM_CD_L(x) _DD_GETVALUE(x,S_CAM_CD_L,M_CAM_CD_L) 299 300/* CAM: CAM Data High Register (0x424, R/W) */ 301 302#define S_CAM_CD_H 0 /* CAMDataH */ 303#define M_CAM_CD_H _DD_MAKEMASK(16,S_CAM_CD_H) 304#define V_CAM_CD_H(x) _DD_MAKEVALUE(x,S_CAM_CD_H) 305#define G_CAM_CD_H(x) _DD_GETVALUE(x,S_CAM_CD_H,M_CAM_CD_H) 306 307#define M_CAM_VB _DD_MAKEMASK1(16) /* ValidBit */ 308 309/* CAMCTL: CAM Control Register (0x428, R/W) */ 310 311#define M_CAMCTL_CE _DD_MAKEMASK1(0) /* CAMEnable */ 312#define M_CAMCTL_MS _DD_MAKEMASK1(1) /* MaskSelect */ 313#define M_CAMCTL_CR _DD_MAKEMASK1(2) /* CAMRead */ 314#define M_CAMCTL_CW _DD_MAKEMASK1(3) /* CAMWrite */ 315 316#define S_CAMCTL_IX 16 /* Index */ 317#define M_CAMCTL_IX _DD_MAKEMASK(6,S_CAMCTL_IX) 318#define V_CAMCTL_IX(x) _DD_MAKEVALUE(x,S_CAMCTL_IX) 319#define G_CAMCTL_IX(x) _DD_GETVALUE(x,S_CAMCTL_IX,M_CAMCTL_IX) 320 321#define M_CAMCTL_CB _DD_MAKEMASK1(31) /* CAMBusy */ 322 323/* ECTL: Ethernet Control Register (0x42C, R/W) */ 324 325#define M_ECTL_EE _DD_MAKEMASK1(0) /* EMACEnable */ 326#define M_ECTL_ED _DD_MAKEMASK1(1) /* EMACDisable */ 327#define M_ECTL_ES _DD_MAKEMASK1(2) /* EMACSoftReset */ 328#define M_ECTL_EP _DD_MAKEMASK1(3) /* ExtPHYSelect */ 329 330/* TCTL: Transmit Control Register (0x430, R/W) */ 331 332#define M_TCTL_FD _DD_MAKEMASK1(0) /* FullDuplex */ 333#define M_TCTL_FM _DD_MAKEMASK1(1) /* FlowMode */ 334#define M_TCTL_SB _DD_MAKEMASK1(2) /* SingleBackoffEn */ 335#define M_TCTL_SS _DD_MAKEMASK1(3) /* SmSlotTime */ 336 337/* MIBCTL: MIB Control Register (0x438, R/W) */ 338 339#define M_MIBCTL_RO _DD_MAKEMASK1(0) /* RO */ 340 341 342/* DMA Control Registers */ 343 344/* XCTL: Transmit Channel Control Register (0x200, R/W) */ 345 346#define M_XCTL_XE _DD_MAKEMASK1(0) /* XmtEn */ 347#define M_XCTL_SE _DD_MAKEMASK1(1) /* SuspEn */ 348#define M_XCTL_LE _DD_MAKEMASK1(2) /* LoopbackEn */ 349#define M_XCTL_FP _DD_MAKEMASK1(3) /* FairPriority */ 350 351/* XADDR: Transmit Descriptor Table Address Register (0x204, R/W) */ 352 353#define S_XADDR_BA 12 /* BaseAddr */ 354#define M_XADDR_BA _DD_MAKEMASK(20,S_XADDR_BA) 355#define V_XADDR_BA(x) _DD_MAKEVALUE(x,S_XADDR_BA) 356#define G_XADDR_BA(x) _DD_GETVALUE(x,S_XADDR_BA,M_XADDR_BA) 357 358/* XPTR: Transmit Descriptor Table Pointer Register (0x208, R/W) */ 359 360#define S_XPTR_LD 0 /* LastDscr */ 361#define M_XPTR_LD _DD_MAKEMASK(12,S_XPTR_LD) 362#define V_XPTR_LD(x) _DD_MAKEVALUE(x,S_XPTR_LD) 363#define G_XPTR_LD(x) _DD_GETVALUE(x,S_XPTR_LD,M_XPTR_LD) 364 365/* XSTAT: Transmit Channel Status Register (0x20C, RO) */ 366 367#define S_XSTAT_CD 0 /* CurrDscr */ 368#define M_XSTAT_CD _DD_MAKEMASK(12,S_XSTAT_CD) 369#define V_XSTAT_CD(x) _DD_MAKEVALUE(x,S_XSTAT_CD) 370#define G_XSTAT_CD(x) _DD_GETVALUE(x,S_XSTAT_CD,M_XSTAT_CD) 371 372#define S_XSTAT_XS 12 /* XmtState */ 373#define M_XSTAT_XS _DD_MAKEMASK(4,S_XSTAT_XS) 374#define V_XSTAT_XS(x) _DD_MAKEVALUE(x,S_XSTAT_XS) 375#define G_XSTAT_XS(x) _DD_GETVALUE(x,S_XSTAT_XS,M_XSTAT_XS) 376#define K_XS_DISABLED 0x0 377#define K_XS_ACTIVE 0x1 378#define K_XS_IDLE_WAIT 0x2 379#define K_XS_STOPPED 0x3 380#define K_XS_SUSPEND_PENDING 0x4 381 382#define S_XSTAT_XE 16 /* XmtErr */ 383#define M_XSTAT_XE _DD_MAKEMASK(4,S_XSTAT_XE) 384#define V_XSTAT_XE(x) _DD_MAKEVALUE(x,S_XSTAT_XE) 385#define G_XSTAT_XE(x) _DD_GETVALUE(x,S_XSTAT_XE,M_XSTAT_XE) 386#define K_XE_NONE 0x0 387#define K_XE_DSCR_PROTOCOL 0x1 388#define K_XE_FIFO_UNDERRUN 0x2 389#define K_XE_DATA_TRANSFER 0x3 390#define K_XE_DSCR_READ 0x4 391 392/* RCTL: Receive Channel Control Register (0x210, R/W) */ 393 394#define M_RCTL_RE _DD_MAKEMASK1(0) /* RcvEn */ 395 396#define S_RCTL_RO 1 /* RcvOffset */ 397#define M_RCTL_RO _DD_MAKEMASK(7,S_RCTL_RO) 398#define V_RCTL_RO(x) _DD_MAKEVALUE(x,S_RCTL_RO) 399#define G_RCTL_RO(x) _DD_GETVALUE(x,S_RCTL_RO,M_RCTL_RO) 400 401#define M_RCTL_FM _DD_MAKEMASK1(8) /* FIFOMode */ 402 403/* RADDR: Receive Descriptor Table Address Register (0x214, R/W) */ 404 405#define S_RADDR_BA 12 /* BaseAddr */ 406#define M_RADDR_BA _DD_MAKEMASK(20,S_RADDR_BA) 407#define V_RADDR_BA(x) _DD_MAKEVALUE(x,S_RADDR_BA) 408#define G_RADDR_BA(x) _DD_GETVALUE(x,S_RADDR_BA,M_RADDR_BA) 409 410/* RPTR: Receive Descriptor Table Pointer Register (0x218, R/W) */ 411 412#define S_RPTR_LD 0 /* LastDscr */ 413#define M_RPTR_LD _DD_MAKEMASK(12,S_RPTR_LD) 414#define V_RPTR_LD(x) _DD_MAKEVALUE(x,S_RPTR_LD) 415#define G_RPTR_LD(x) _DD_GETVALUE(x,S_RPTR_LD,M_RPTR_LD) 416 417/* RSTAT: Receive Channel Status Register (0x21C, RO) */ 418 419#define S_RSTAT_CD 0 /* CurrDscr */ 420#define M_RSTAT_CD _DD_MAKEMASK(12,S_RSTAT_CD) 421#define V_RSTAT_CD(x) _DD_MAKEVALUE(x,S_RSTAT_CD) 422#define G_RSTAT_CD(x) _DD_GETVALUE(x,S_RSTAT_CD,M_RSTAT_CD) 423 424#define S_RSTAT_RS 12 /* RcvState */ 425#define M_RSTAT_RS _DD_MAKEMASK(4,S_RSTAT_RS) 426#define V_RSTAT_RS(x) _DD_MAKEVALUE(x,S_RSTAT_RS) 427#define G_RSTAT_RS(x) _DD_GETVALUE(x,S_RSTAT_RS,M_RSTAT_RS) 428#define K_RS_DISABLED 0x0 429#define K_RS_ACTIVE 0x1 430#define K_RS_IDLE_WAIT 0x2 431#define K_RS_STOPPED 0x3 432 433#define S_RSTAT_RE 16 /* RcvErr */ 434#define M_RSTAT_RE _DD_MAKEMASK(4,S_RSTAT_RE) 435#define V_RSTAT_RE(x) _DD_MAKEVALUE(x,S_RSTAT_RE) 436#define G_RSTAT_RE(x) _DD_GETVALUE(x,S_RSTAT_RE,M_RSTAT_RE) 437#define K_RE_NONE 0x0 438#define K_RE_DSCR_PROTOCOL 0x1 439#define K_RE_FIFO_OVERFLOW 0x2 440#define K_RE_DATA_TRANSFER 0x3 441#define K_RE_DSCR_READ 0x4 442 443 444/* DMA Descriptor Structure (Table 66) */ 445 446/* Word 0: Flags and Count */ 447 448#define S_DSCR0_BC 0 /* BufCount */ 449#define M_DSCR0_BC _DD_MAKEMASK(13,S_DSCR0_BC) 450#define V_DSCR0_BC(x) _DD_MAKEVALUE(x,S_DSCR0_BC) 451#define G_DSCR0_BC(x) _DD_GETVALUE(x,S_DSCR0_BC,M_DSCR0_BC) 452 453#define S_DSCR0_FL 20 /* Flags */ 454#define M_DSCR0_FL _DD_MAKEMASK(8,S_DSCR0_FL) 455#define V_DSCR0_FL(x) _DD_MAKEVALUE(x,S_DSCR0_FL) 456#define G_DSCR0_FL(x) _DD_GETVALUE(x,S_DSCR0_FL,M_DSCR0_FL) 457 458#define M_DSCR0_ET _DD_MAKEMASK1(28) /* EOT */ 459#define M_DSCR0_IC _DD_MAKEMASK1(29) /* IOC */ 460#define M_DSCR0_EF _DD_MAKEMASK1(30) /* EOF */ 461#define M_DSCR0_SF _DD_MAKEMASK1(31) /* SOF */ 462 463/* Word 1: Data Buffer Pointer */ 464 465#define S_DSCR1_DB 0 /* DataBufPtr */ 466#define M_DSCR1_DB _DD_MAKEMASK(32, S_DSCR1_DB) 467#define V_DSCR1_DB(x) _DD_MAKEVALUE(x,S_DSCR1_DB) 468#define G_DSCR1_DB(x) _DD_GETVALUE(x,S_DSCR1_DB,M_DSCR1_DB) 469 470 471/* DMA Receive Headers (Table 67) */ 472 473#define S_RCVHDR0_CD 0 /* FrameLen (!) */ 474#define M_RCVHDR0_CD _DD_MAKEMASK(16,S_RCVHDR0_CD) 475#define V_RCVHDR0_CD(x) _DD_MAKEVALUE(x,S_RCVHDR0_CD) 476#define G_RCVHDR0_CD(x) _DD_GETVALUE(x,S_RCVHDR0_CD,M_RCVHDR0_CD) 477 478#define S_RCVHDR0_DC 24 /* DescrCnt */ 479#define M_RCVHDR0_DC _DD_MAKEMASK(4,S_RCVHDR0_DC) 480#define V_RCVHDR0_DC(x) _DD_MAKEVALUE(x,S_RCVHDR0_DC) 481#define G_RCVHDR0_DC(x) _DD_GETVALUE(x,S_RCVHDR0_DC,M_RCVHDR0_DC) 482 483/* The presence of these flags can depend on which version of the core you have. */ 484#define M_RCVHDR0_L _DD_MAKEMASK1(27) /* Last */ 485#define M_RCVHDR0_F _DD_MAKEMASK1(26) /* First */ 486#define M_RCVHDR0_W _DD_MAKEMASK1(25) /* Wrap */ 487#define M_RCVHDR0_MISS _DD_MAKEMASK1(23) /* Miss */ 488#define M_RCVHDR0_BRDCAST _DD_MAKEMASK1(22) /* Broadcast */ 489#define M_RCVHDR0_MULT _DD_MAKEMASK1(21) /* Multicast */ 490#define M_RCVHDR0_LG _DD_MAKEMASK1(20) /* Large */ 491#define M_RCVHDR0_NO _DD_MAKEMASK1(19) /* NonOctet Aligned */ 492#define M_RCVHDR0_RXER _DD_MAKEMASK1(18) /* Symbol Error */ 493#define M_RCVHDR0_CRC _DD_MAKEMASK1(17) /* CRC */ 494#define M_RCVHDR0_OV _DD_MAKEMASK1(16) /* Overflow */ 495#define M_RCVHDR0_ERRORS (M_RCVHDR0_NO | M_RCVHDR0_RXER | M_RCVHDR0_CRC \ 496 | M_RCVHDR0_OV) 497 498 499/* Offsets of MIB counters in Statistics Block (Table 161) 500 Registers are 16 bits except as noted. */ 501 502#define TX_GD_OCTETS 0x500 /* 32 bits */ 503#define TX_GD_PKTS 0x504 504#define TX_ALL_OCTETS 0x508 /* 32 bits */ 505#define TX_ALL_PKTS 0x50C 506#define TX_BRDCAST 0x510 507#define TX_MULT 0x514 508#define TX_64 0x518 509#define TX_65_127 0x51C 510#define TX_128_255 0x520 511#define TX_256_511 0x524 512#define TX_512_1023 0x528 513#define TX_1024_MAX 0x52C 514#define TX_JAB 0x530 515#define TX_OVR 0x534 516#define TX_FRAG 0x538 517#define TX_UNDERRUN 0x53C 518#define TX_COL 0x540 519#define TX_1_COL 0x544 520#define TX_M_COL 0x548 521#define TX_EX_COL 0x54C 522#define TX_LATE 0x550 523#define TX_DEF 0x554 524#define TX_CRS 0x558 525#define TX_PAUS 0x55C 526 527#define RX_GD_OCTETS 0x580 /* 32 bits */ 528#define RX_GD_PKTS 0x584 529#define RX_ALL_OCTETS 0x588 /* 32 bits */ 530#define RX_ALL_PKTS 0x58C 531#define RX_BRDCAST 0x590 532#define RX_MULT 0x594 533#define RX_64 0x598 534#define RX_65_127 0x59C 535#define RX_128_255 0x5A0 536#define RX_256_511 0x5A4 537#define RX_512_1023 0x5A8 538#define RX_1024_MAX 0x5AC 539#define RX_JAB 0x5B0 540#define RX_OVR 0x5B4 541#define RX_FRAG 0x5B8 542#define RX_DROP 0x5BC 543#define RX_CRC_ALIGN 0x5C0 544#define RX_UND 0x5C4 545#define RX_CRC 0x5C8 546#define RX_ALIGN 0x5CC 547#define RX_SYM 0x5D0 548#define RX_PAUSE 0x5D4 549#define RX_CNTRL 0x5D8 550 551 552/* In the default mapping, the top 4K of the BAR0 window maps into the 553 SPROM. Note that access latency is high and the corresponding code 554 must be prepared to avoid or deal with bus errors caused by PCI 555 timeouts. */ 556 557#define SPROM_BASE 0x1000 558 559#define SPROM_MAC_ADDR 0x4E /* 6 bytes */ 560#define SPROM_PHY_ADDR 90 /* 2 bytes, bits [4:0] (undoc) */ 561 562#endif /* _SBMAC_H_ */ 563