1/* ********************************************************************* 2 * Broadcom Common Firmware Environment (CFE) 3 * 4 * Silicon Backplane definitions File: sb_chipc.h 5 * 6 ********************************************************************* 7 * 8 * Copyright 2003 9 * Broadcom Corporation. All rights reserved. 10 * 11 * This software is furnished under license and may be used and 12 * copied only in accordance with the following terms and 13 * conditions. Subject to these conditions, you may download, 14 * copy, install, use, modify and distribute modified or unmodified 15 * copies of this software in source and/or binary form. No title 16 * or ownership is transferred hereby. 17 * 18 * 1) Any source code used, modified or distributed must reproduce 19 * and retain this copyright notice and list of conditions 20 * as they appear in the source file. 21 * 22 * 2) No right is granted to use any trade name, trademark, or 23 * logo of Broadcom Corporation. The "Broadcom Corporation" 24 * name may not be used to endorse or promote products derived 25 * from this software without the prior written permission of 26 * Broadcom Corporation. 27 * 28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 40 * THE POSSIBILITY OF SUCH DAMAGE. 41 ********************************************************************* */ 42 43#ifndef _SBCHIPC_H_ 44#define _SBCHIPC_H_ 45 46/* 47 * Register and bit definitions for the Chip Common control 48 * registers (OCP ID 0x800). 49 */ 50 51 52/* Chip Common Core (Section 9) */ 53 54/* Control and Interrupt Registers (Section 9.2.1) */ 55#define R_CHIPID 0x000 56#define R_CORECAPABILITIES 0x004 57#define R_CORECONTROL 0x008 58#define R_INTSTATUS 0x020 59#define R_INTMASK 0x024 60#define R_SFLASHCONTROL 0x040 61#define R_SFLASHADDRESS 0x044 62#define R_SFLASHDATA 0x048 63#define R_BROADCASTADDRESS 0x050 64#define R_BROADCASTDATA 0x054 65 66/* GPIO Registers (Section 9.2.2) */ 67#define R_GPIOINPUT 0x060 68#define R_GPIOOUTPUT 0x064 69#define R_GPIOOUTEN 0x068 70#define R_GPIOCONTROL 0x06C 71#define R_GPIOINTPOLARITY 0x070 72#define R_GPIOINTMASK 0x074 73#define R_WATCHDOGCOUNTER 0x080 74/* Backward compatibility aliases */ 75#define R_WATCHDOGCNTR R_WATCHDOGCOUNTER 76 77/* Clock Control Registers (Section 9.2.3) */ 78#define R_CLOCKCONTROLN 0x090 79#define R_CLOCKCONTROLM0 0x094 80#define R_CLOCKCONTROLM1 0x098 81#define R_CLOCKCONTROLM2 0x09C 82#define R_CLOCKCONTROLM3 0x0A0 83#define R_UARTCLOCKDIV 0x0A4 84/* Backward compatibility aliases */ 85#define R_CLOCKCONTROLSB R_CLOCKCONTROLM0 86#define R_CLOCKCONTROLPCI R_CLOCKCONTROLM1 87#define R_CLOCKCONTROLMII R_CLOCKCONTROLM2 88#define R_CLOCKCONTROLCPU R_CLOCKCONTROLM3 89 90/* External Interface Bus Control Registers (Section 9.2.4) */ 91#define R_CS01CONFIG 0x100 92#define R_CS01MEMWAITCNT 0x104 93#define R_CS01ATTRWAITCNT 0x108 94#define R_CS01IOWAITCNT 0x10C 95#define R_CS23CONFIG 0x110 96#define R_CS23MEMWAITCNT 0x114 97#define R_CS23ATTRWAITCNT 0x118 98#define R_CS23IOWAITCNT 0x11C 99#define R_CS4CONFIG 0x120 100#define R_CS4WAITCNT 0x124 101#define R_PARALLELFLASHCONFIG 0x128 102#define R_PARALLELFLASHWAITCNT 0x12C 103 104/* UART Registers (Section 9.2.5) - see ns16550.h */ 105 106/* System Backplane Configuration Register (Section 9.2.6) */ 107#define R_FLAGSTATUS 0xFE8 108 109/* JTAG Backplane Access Registers (Section 9.2.7) */ 110#define R_JTAG_ADDRESS_WR 0x30 111#define R_JTAG_ADDRESS_RD 0x31 112#define R_JTAG_DATA_WR 0x32 113#define R_JTAG_DATA_RD 0x33 114#define R_JTAG_CONTROL_WR 0x34 115#define R_JTAG_CONTROL_RD 0x35 116 117 118/* CHIPID: ChipID Register (0x000, RO) */ 119 120#define S_CHIPID_CI 0 /* ChipID */ 121#define M_CHIPID_CI _DD_MAKEMASK(16,S_CHIPID_CI) 122#define V_CHIPID_CI(x) _DD_MAKEVALUE(x,S_CHIPID_CI) 123#define G_CHIPID_CI(x) _DD_GETVALUE(x,S_CHIPID_CI,M_CHIPID_CI) 124 125#define S_CHIPID_RI 16 /* RevisionID */ 126#define M_CHIPID_RI _DD_MAKEMASK(4,S_CHIPID_RI) 127#define V_CHIPID_RI(x) _DD_MAKEVALUE(x,S_CHIPID_RI) 128#define G_CHIPID_RI(x) _DD_GETVALUE(x,S_CHIPID_RI,M_CHIPID_RI) 129 130#define S_CHIPID_PO 20 /* PackageOption */ 131#define M_CHIPID_PO _DD_MAKEMASK(4,S_CHIPID_PO) 132#define V_CHIPID_PO(x) _DD_MAKEVALUE(x,S_CHIPID_PO) 133#define G_CHIPID_PO(x) _DD_GETVALUE(x,S_CHIPID_PO,M_CHIPID_PO) 134 135/* CORECAP: Core Capabilities Register (0x004, RO) */ 136 137#define S_CORECAP_UP 0 /* UARTsPresent */ 138#define M_CORECAP_UP _DD_MAKEMASK(2,S_CORECAP_UP) 139#define V_CORECAP_UP(x) _DD_MAKEVALUE(x,S_CORECAP_UP) 140#define G_CORECAP_UP(x) _DD_GETVALUE(x,S_CORECAP_UP,M_CORECAP_UP) 141 142#define M_CORECAP_EM _DD_MAKEMASK1(2) /* EndianMode */ 143 144#define S_CORECAP_CS 3 /* UARTClkSel */ 145#define M_CORECAP_CS _DD_MAKEMASK(2,S_CORECAP_CS) 146#define V_CORECAP_CS(x) _DD_MAKEVALUE(x,S_CORECAP_CS) 147#define G_CORECAP_CS(x) _DD_GETVALUE(x,S_CORECAP_CS,M_CORECAP_CS) 148#define K_CS_EXTERNAL 0x0 149#define K_CS_INTERNAL 0x1 150 151#define M_CORECAP_UG _DD_MAKEMASK1(5) /* UARTGPIOs */ 152#define M_CORECAP_EB _DD_MAKEMASK1(6) /* ExtBusPresent */ 153 154#define S_CORECAP_FT 8 /* FlashType */ 155#define M_CORECAP_FT _DD_MAKEMASK(3,S_CORECAP_FT) 156#define V_CORECAP_FT(x) _DD_MAKEVALUE(x,S_CORECAP_FT) 157#define G_CORECAP_FT(x) _DD_GETVALUE(x,S_CORECAP_FT,M_CORECAP_FT) 158#define K_FT_NONE 0x0 159#define K_FT_STM_SERIAL 0x1 160#define K_FT_ATMEL_SERIAL 0x2 161#define K_FT_PARALLEL 0x7 162 163#define S_CORECAP_PL 16 /* PLLCtlPresent */ 164#define M_CORECAP_PL _DD_MAKEMASK(2,S_CORECAP_PL) 165#define V_CORECAP_PL(x) _DD_MAKEVALUE(x,S_CORECAP_PL) 166#define G_CORECAP_PL(x) _DD_GETVALUE(x,S_CORECAP_PL,M_CORECAP_PL) 167#define K_PLL_NONE 0x0 168#define K_PLL_TYPE1 0x1 169#define K_PLL_TYPE2 0x2 170#define K_PLL_TYPE3 0x3 171/* Backward compatibility aliases */ 172#define K_PL_NONE 0x0 173#define K_PL_4710 0x1 174#define K_PL_4704 0x2 175#define K_PL_5365 0x3 176 177/* CORECTL: Core Control Register (0x008, R/W) */ 178 179#define M_CORECTL_CO _DD_MAKEMASK1(0) /* UARTClkOverride */ 180#define M_CORECTL_SE _DD_MAKEMASK1(1) /* SyncClkOutEn */ 181 182/* INTSTAT: Int Status Register (0x020, R/W) */ 183 184#define M_INTSTAT_GI _DD_MAKEMASK1(0) /* GPIOInt */ 185#define M_INTSTAT_EI _DD_MAKEMASK1(1) /* ExtInt */ 186#define M_INTSTAT_WD _DD_MAKEMASK1(2) /* WDReset */ 187 188/* INTMASK: Int Mask Register (0x024, R/W) */ 189 190#define M_INTMASK_EI _DD_MAKEMASK1(1) /* ExtInt */ 191 192/* SFLASHCTL: SFlash Control Register (0x040, R/W) */ 193 194#define S_SFLASHCTL_OC 0 /* Opcode */ 195#define M_SFLASHCTL_OC _DD_MAKEMASK(8,S_SFLASHCTL_OC) 196#define V_SFLASHCTL_OC(x) _DD_MAKEVALUE(x,S_SFLASHCTL_OC) 197#define G_SFLASHCTL_OC(x) _DD_GETVALUE(x,S_SFLASHCTL_OC,M_SFLASHCTL_OC) 198 199#define S_SFLASHCTL_AC 8 /* Action */ 200#define M_SFLASHCTL_AC _DD_MAKEMASK(8,S_SFLASHCTL_AC) 201#define V_SFLASHCTL_AC(x) _DD_MAKEVALUE(x,S_SFLASHCTL_AC) 202#define G_SFLASHCTL_AC(x) _DD_GETVALUE(x,S_SFLASHCTL_AC,M_SFLASHCTL_AC) 203 204#define M_SFLASHCTL_AB _DD_MAKEMASK1(32) /* Start/Busy */ 205 206/* SFLASHADDR: SFlash Address Register (0x44, R/W) */ 207 208/* SFLASHDATA: SFlash Data Register (0x48, R/W) */ 209 210/* BCASTADDR: Broadcast Address Register (0x050, R/W) */ 211 212/* BCASTDATA: Broadcast Data Register (0x054, R/W) */ 213 214 215/* ... GPIO ... */ 216 217/* WDOG: Watchdog Counter Register (0x080, R/W) */ 218 219 220/* CCN: Clock Control N Register (0x090, R/W, buffered) */ 221 222#define S_CCN_N1 0 /* N1Control */ 223#define M_CCN_N1 _DD_MAKEMASK(6,S_CCN_N1) 224#define V_CCN_N1(x) _DD_MAKEVALUE(x,S_CCN_N1) 225#define G_CCN_N1(x) _DD_GETVALUE(x,S_CCN_N1,M_CCN_N1) 226 227#define S_CCN_N2 8 /* N2Control */ 228#define M_CCN_N2 _DD_MAKEMASK(5,S_CCN_N2) 229#define V_CCN_N2(x) _DD_MAKEVALUE(x,S_CCN_N2) 230#define G_CCN_N2(x) _DD_GETVALUE(x,S_CCN_N2,M_CCN_N2) 231 232/* CCM0: Clock Control M0 Register (0x094, R/W, buffered) */ 233/* CCM1: Clock Control M1 Register (0x098, R/W, buffered) */ 234/* CCM2: Clock Control M2 Register (0x09C, R/W, buffered) */ 235/* CCM3: Clock Control M3 Register (0x0A0, R/W, buffered) */ 236 237#define S_CCM_M1 0 /* M1Control */ 238#define M_CCM_M1 _DD_MAKEMASK(6,S_CCM_M1) 239#define V_CCM_M1(x) _DD_MAKEVALUE(x,S_CCM_M1) 240#define G_CCM_M1(x) _DD_GETVALUE(x,S_CCM_M1,M_CCM_M1) 241 242#define S_CCM_M2 8 /* M2Control */ 243#define M_CCM_M2 _DD_MAKEMASK(5,S_CCM_M2) 244#define V_CCM_M2(x) _DD_MAKEVALUE(x,S_CCM_M2) 245#define G_CCM_M2(x) _DD_GETVALUE(x,S_CCM_M2,M_CCM_M2) 246 247#define S_CCM_M3 16 /* M3Control */ 248#define M_CCM_M3 _DD_MAKEMASK(6,S_CCM_M3) 249#define V_CCM_M3(x) _DD_MAKEVALUE(x,S_CCM_M3) 250#define G_CCM_M3(x) _DD_GETVALUE(x,S_CCM_M3,M_CCM_M3) 251 252#define S_CCM_MM 24 /* MuxControl */ 253#define M_CCM_MM _DD_MAKEMASK(5,S_CCM_MM) 254#define V_CCM_MM(x) _DD_MAKEVALUE(x,S_CCM_MM) 255#define G_CCM_MM(x) _DD_GETVALUE(x,S_CCM_MM,M_CCM_MM) 256/* Backward compatibility aliases */ 257#define S_CCM_MC S_CCM_MM 258#define M_CCM_MC M_CCM_MM 259#define V_CCM_MC V_CCM_MM 260#define G_CCM_MC G_CCM_MM 261 262/* UARTDIV: UART Clock Div Register (0xA4, R/W) */ 263 264#define S_UARTDIV_CD 0 /* ClkDiv */ 265#define M_UARTDIV_CD _DD_MAKEMASK(6,S_UARTDIV_CD) 266#define V_UARTDIV_CD(x) _DD_MAKEVALUE(x,S_UARTDIV_CD) 267#define G_UARTDIV_CD(x) _DD_GETVALUE(x,S_UARTDIV_CD,M_UARTDIV_CD) 268 269/* CSO1CONFIG: CS01 Configuration Register (0x100, R/W) */ 270/* CSO1CONFIG: CS23 Configuration Register (0x110, R/W) */ 271/* CS4CONFIG: CS4 Configuration Register (0x120, R/W) */ 272 273#define M_CS_EN _DD_MAKEMASK1(0) /* Enable */ 274 275#define S_CS_EM 1 /* ExtIfMode */ 276#define M_CS_EM _DD_MAKEMASK(3,S_CS_EM) 277#define V_CS_EM(x) _DD_MAKEVALUE(x,S_CS_EM) 278#define G_CS_EM(x) _DD_GETVALUE(x,S_CS_EM,M_CS_EM) 279 280#define M_CS_DS _DD_MAKEMASK1(4) /* DestSize */ 281 282#define S_CS_CD 5 /* ClkDivider */ 283#define M_CS_CD _DD_MAKEMASK(2,S_CS_CD) 284#define V_CS_CD(x) _DD_MAKEVALUE(x,S_CS_CD) 285#define G_CS_CD(x) _DD_GETVALUE(x,S_CS_CD,M_CS_CD) 286 287#define M_CS_CE _DD_MAKEMASK1(7) /* ClkEnable */ 288#define M_CS_SB _DD_MAKEMASK1(8) /* Size/ByteStrobe */ 289 290/* CSO1MEMWAITCNT: CS01 Memory Wait Count Register (0x104, R/W) */ 291/* CS23MEMWAITCNT: CS23 Memory Wait Count Register (0x114, R/W) */ 292/* CS4MEMWAITCNT: CS4 Memory Wait Count Register (0x124, R/W) */ 293 294/* CS01ATTRWAITCNT: CS01 Attribute Wait Count Register (0x108, R/W) */ 295/* CS23ATTRWAITCNT: CS23 Attribute Wait Count Register (0x118, R/W) */ 296/* CS4ATTRWAITCNT: CS4 Attribute Wait Count Register (0x128, R/W) */ 297 298/* CS01IOWAITCNT: CS01 I/O Wait Count Register (0x10C, R/W) */ 299/* CS23IOWAITCNT: CS23 I/O Wait Count Register (0x11C, R/W) */ 300/* CS4IOWAITCNT: CS4 I/O Wait Count Register (0x12C, R/W) */ 301 302#define S_CS_W0 0 /* WaitCount0 */ 303#define M_CS_W0 _DD_MAKEMASK(6,S_CS_W0) 304#define V_CS_W0(x) _DD_MAKEVALUE(x,S_CS_W0) 305#define G_CS_W0(x) _DD_GETVALUE(x,S_CS_W0,M_CS_W0) 306 307#define S_CS_W1 8 /* WaitCount1 */ 308#define M_CS_W1 _DD_MAKEMASK(5,S_CS_W1) 309#define V_CS_W1(x) _DD_MAKEVALUE(x,S_CS_W1) 310#define G_CS_W1(x) _DD_GETVALUE(x,S_CS_W1,M_CS_W1) 311 312#define S_CS_W2 16 /* WaitCount2 */ 313#define M_CS_W2 _DD_MAKEMASK(5,S_CS_W2) 314#define V_CS_W2(x) _DD_MAKEVALUE(x,S_CS_W2) 315#define G_CS_W2(x) _DD_GETVALUE(x,S_CS_W2,M_CS_W2) 316 317#define S_CS_W3 24 /* WaitCount0 */ 318#define M_CS_W3 _DD_MAKEMASK(5,S_CS_W3) 319#define V_CS_W3(x) _DD_MAKEVALUE(x,S_CS_W3) 320#define G_CS_W3(x) _DD_GETVALUE(x,S_CS_W3,M_CS_W3) 321 322#endif /* _SBCHIPC_H_ */ 323