1/* ********************************************************************* 2 * SB1250 Board Support Package 3 * 4 * BCM91125CPCI Definitions File: bcm91125cpci.h 5 * 6 * This file contains I/O, chip select, and GPIO assignments 7 * for the BCM91125CPCI board. 8 * 9 * Author: Mitch Lichtenberg 10 * 11 ********************************************************************* 12 * 13 * Copyright 2000,2001,2002,2003 14 * Broadcom Corporation. All rights reserved. 15 * 16 * This software is furnished under license and may be used and 17 * copied only in accordance with the following terms and 18 * conditions. Subject to these conditions, you may download, 19 * copy, install, use, modify and distribute modified or unmodified 20 * copies of this software in source and/or binary form. No title 21 * or ownership is transferred hereby. 22 * 23 * 1) Any source code used, modified or distributed must reproduce 24 * and retain this copyright notice and list of conditions 25 * as they appear in the source file. 26 * 27 * 2) No right is granted to use any trade name, trademark, or 28 * logo of Broadcom Corporation. The "Broadcom Corporation" 29 * name may not be used to endorse or promote products derived 30 * from this software without the prior written permission of 31 * Broadcom Corporation. 32 * 33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR 34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED 35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR 36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT 37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN 38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT, 39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF 45 * THE POSSIBILITY OF SUCH DAMAGE. 46 ********************************************************************* */ 47 48/* 49 * I/O Address assignments for the bcm91125cpci board 50 * 51 * Summary of address map: 52 * 53 * Address Size CSel Description 54 * --------------- ---- ------ -------------------------------- 55 * 0x1FC00000 16MB CS0 Boot ROM 56 * 0x1EC00000 16MB CS1 Alternate Boot ROM 57 * CS2 Unused 58 * CS3 Unused 59 * 0x1D0A0000 64KB CS4 LED display 60 * CS5 Unused 61 * 0x11000000 64KB CS6 CompactFlash/PCMCIA 62 * CS7 Unused 63 * 64 * GPIO assignments 65 * 66 * GPIO# Direction Description 67 * ------- --------- ------------------------------------------ 68 * GPIO0 Output Debug LED 69 * GPIO1 Input Boot Mode 70 * GPIO2 Input NMI (interrupt) 71 * GPIO3 Input RTC Interrupt (interrupt) 72 * GPIO4 Input PHY Interrupt (interrupt) 73 * GPIO5 Input Temperature Sensor Alert (interrupt) 74 * GPIO6 N/A PCMCIA interface 75 * GPIO7 N/A PCMCIA interface 76 * GPIO8 N/A PCMCIA interface 77 * GPIO9 N/A PCMCIA interface 78 * GPIO10 N/A PCMCIA interface 79 * GPIO11 N/A PCMCIA interface 80 * GPIO12 N/A PCMCIA interface 81 * GPIO13 N/A PCMCIA interface 82 * GPIO14 N/A PCMCIA interface 83 * GPIO15 N/A PCMCIA interface 84 * 85 * SMBus assignments: 86 * 87 * Chan Dev Description 88 * ---- ------ ------------------------------------------ 89 * 0 0x2A Temperature Sensor 90 * 1 0x68 ST Micro M41T81 Real-time clock 91 * 0 0x54 SPD for DIMM slot 0 92 * 0 0x50 Microchip 24LC128 SMBus EEPROM (400KHz capable) 93 */ 94 95/* ********************************************************************* 96 * Macros 97 ********************************************************************* */ 98 99#define __MB (1024*1024) 100#define __KB (1024) 101#define __K64 65536 102#define NUM64K(x) (((x)+(__K64-1))/__K64) 103 104 105/* ********************************************************************* 106 * GPIO pins 107 ********************************************************************* */ 108 109#define GPIO_DEBUG_LED 0 110#define GPIO_BOOT_MODE 1 111#define GPIO_NONMASKABLE_INT 2 112#define GPIO_RTC_INTERRUPT 3 113#define GPIO_PHY_INTERRUPT 4 114#define GPIO_TEMP_SENSOR_INT 5 115 116#define M_GPIO_DEBUG_LED _SB_MAKEMASK1(GPIO_DEBUG_LED) 117#define M_GPIO_BOOT_MODE _SB_MAKEMASK1(GPIO_BOOT_MODE) 118 119#define GPIO_INTERRUPT_MASK ((V_GPIO_INTR_TYPEX(GPIO_PHY_INTERRUPT,K_GPIO_INTR_LEVEL))) 120 121#define GPIO_OUTPUT_MASK (M_GPIO_DEBUG_LED) 122 123/* ********************************************************************* 124 * Generic Bus 125 ********************************************************************* */ 126 127/* 128 * Boot ROM: non-multiplexed, byte width, no parity, no ack 129 * XXX: These are the (very slow) default parameters. This can be sped up! 130 * Boot rom: 16MB Intel StrataFlash 131 */ 132#define BOOTROM_CS 0 133#define BOOTROM_PHYS 0x1FC00000 /* address of boot ROM (CS0) */ 134#define BOOTROM_SIZE NUM64K(16*__MB) /* size of boot ROM */ 135#define BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 136 V_IO_ALE_TO_CS(2) | \ 137 V_IO_CS_WIDTH(24) | \ 138 V_IO_RDY_SMPLE(1) 139#define BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 140 V_IO_WRITE_WIDTH(7) | \ 141 V_IO_IDLE_CYCLE(6) | \ 142 V_IO_CS_TO_OE(0) | \ 143 V_IO_OE_TO_CS(0) 144#define BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 145 146/* 147 * Alternate Boot ROM: non-multiplexed, byte width, no parity, no ack 148 * XXX: These are the (very slow) default parameters. This can be sped up! 149 * Boot rom: 512KB AMD PLCC 150 */ 151#define ALT_BOOTROM_CS 1 152#define ALT_BOOTROM_PHYS 0x1EC00000 /* address of alternate boot ROM (CS1) */ 153#define ALT_BOOTROM_SIZE NUM64K(512*__KB) /* size of alternate boot ROM */ 154#define ALT_BOOTROM_TIMING0 V_IO_ALE_WIDTH(4) | \ 155 V_IO_ALE_TO_CS(2) | \ 156 V_IO_CS_WIDTH(24) | \ 157 V_IO_RDY_SMPLE(1) 158#define ALT_BOOTROM_TIMING1 V_IO_ALE_TO_WRITE(7) | \ 159 V_IO_WRITE_WIDTH(7) | \ 160 V_IO_IDLE_CYCLE(6) | \ 161 V_IO_CS_TO_OE(0) | \ 162 V_IO_OE_TO_CS(0) 163#define ALT_BOOTROM_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 164 165 166/* 167 * LEDs: non-multiplexed, byte width, no parity, no ack 168 */ 169#define LEDS_CS 4 170#define LEDS_PHYS 0x1D0A0000 171#define LEDS_SIZE NUM64K(4) 172#define LEDS_TIMING0 V_IO_ALE_WIDTH(4) | \ 173 V_IO_ALE_TO_CS(2) | \ 174 V_IO_CS_WIDTH(13) | \ 175 V_IO_RDY_SMPLE(1) 176#define LEDS_TIMING1 V_IO_ALE_TO_WRITE(2) | \ 177 V_IO_WRITE_WIDTH(8) | \ 178 V_IO_IDLE_CYCLE(6) | \ 179 V_IO_CS_TO_OE(0) | \ 180 V_IO_OE_TO_CS(0) 181#define LEDS_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX 182 183 184/* 185 * PCMCIA: this information was derived from chapter 12, table 12-5 186 */ 187#define PCMCIA_CS 6 188#define PCMCIA_PHYS 0x11000000 189#define PCMCIA_SIZE NUM64K(64*__MB) 190#define PCMCIA_TIMING0 V_IO_ALE_WIDTH(3) | \ 191 V_IO_ALE_TO_CS(1) | \ 192 V_IO_CS_WIDTH(17) | \ 193 V_IO_RDY_SMPLE(1) 194#define PCMCIA_TIMING1 V_IO_ALE_TO_WRITE(8) | \ 195 V_IO_WRITE_WIDTH(8) | \ 196 V_IO_IDLE_CYCLE(2) | \ 197 V_IO_CS_TO_OE(0) | \ 198 V_IO_OE_TO_CS(0) 199#define PCMCIA_CONFIG V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2) 200 201 202/* ********************************************************************* 203 * SMBus 204 ********************************************************************* */ 205 206#define TEMPSENSOR_SMBUS_CHAN 0 207#define TEMPSENSOR_SMBUS_DEV 0x2A 208#define EEPROM0_SMBUS_CHAN 0 209#define EEPROM0_SMBUS_DEV 0x50 210#define M41T81_SMBUS_CHAN 1 211#define M41T81_SMBUS_DEV 0x68 212 213#define SODIMM1_SMBUS_CHAN 0 214#define SODIMM1_SMBUS_DEV 0x54 215