1/* 2 * Copyright (c) 2014 ETH Zurich. 3 * All rights reserved. 4 * 5 * This file is distributed under the terms in the attached LICENSE file. 6 * If you do not find this file, copies can be found by writing to: 7 * ETH Zurich D-INFK, Universitaetsstrasse 6, CH-8092 Zurich. Attn: Systems Group. 8 */ 9 10#ifndef DMA_MGR_DEBUG_H_ 11#define DMA_MGR_DEBUG_H_ 12 13 14/* 15 * Debug output switches 16 */ 17#define DEBUG_ENABLED 0 18#define DEBUG_SVC_ENABLED 1 19#define DEBUG_DS_ENABLED 1 20 21 22/* 23 * -------------------------------------------------------------------------- 24 * Debug output generation 25 */ 26#if DEBUG_ENABLED 27#define DEBUGPRINT(x...) debug_printf(x) 28#else 29#define DEBUGPRINT(x... ) 30#endif 31#if DEBUG_SVC_ENABLED 32#define SVC_DEBUG(x...) DEBUGPRINT("svc | " x) 33#else 34#define SVC_DEBUG(x...) 35#endif 36#if DEBUG_DS_ENABLED 37#define DS_DEBUG(x...) DEBUGPRINT("ds | " x) 38#else 39#define DS_DEBUG(x...) 40#endif 41 42 43#define ERRPRINT(x...) debug_printf(x) 44#define SVC_ERR(x...) ERRPRINT("svc | ERROR: " x) 45#define DS_ERR(x...) ERRPRINT("ds | ERROR: " x) 46 47#endif /* DMA_MGR_DEBUG_H_ */ 48