1/* 2 * clock.c 3 * 4 * Copyright(c) 2010 Texas Instruments. All rights reserved. 5 * 6 * Texas Instruments, <www.ti.com> 7 * Richard Woodruff <r-woodruff2@ti.com> 8 * Rajendra Nayak <rnayak@ti.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 14 * * Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * * Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in 18 * the documentation and/or other materials provided with the 19 * distribution. 20 * * Neither the name Texas Instruments nor the names of its 21 * contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 */ 36 37#include <aboot/aboot.h> 38#include <aboot/io.h> 39#include <omap4/hw.h> 40 41 42//#include <omap4/clocks.h> 43 44#define LDELAY 12000000 45 46#define PLL_STOP 1 /* PER & IVA */ 47#define PLL_MN_POWER_BYPASS 4 48#define PLL_LOW_POWER_BYPASS 5 /* MPU, IVA & CORE */ 49#define PLL_FAST_RELOCK_BYPASS 6 /* CORE */ 50#define PLL_LOCK 7 /* MPU, IVA, CORE & PER */ 51 52#define BIT0 (1<<0) 53#define BIT16 (1<<16) 54#define BIT17 (1<<17) 55#define BIT18 (1<<18) 56 57#define CONFIG_OMAP4_SDC 1 58 59/* clk sel is 12M / 13M / 16.8M / 19.2M / 26M / 27M / 38.4M */ 60/* we only support 38.4M here */ 61 62/* #define CONFIG_MPU_1000 1 */ 63/* #define CONFIG_MPU_800 1 */ 64#define CONFIG_MPU_600 1 65 66struct dpll_param mpu_dpll_param = { 67#ifdef CONFIG_MPU_600 68 0x7d, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 69#elif CONFIG_MPU_800 /* 796.8MHz */ 70 0xa6, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 71#elif CONFIG_MPU_1000 72 0x69, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 73#else /* 332.8MHz */ 74 0x1a, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 75#endif 76}; 77 78const struct dpll_param per_dpll_param = { 79 0x14, 0x00, 0x08, 0x06, 0x0c, 0x09, 0x04, 0x05, 80}; 81 82struct dpll_param iva_dpll_param = { 83#ifdef CONFIG_OMAP4_SDC 84 0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 85#else 86 0x61, 0x03, 0x00, 0x00, 0x04, 0x07, 0x00, 0x00, 87#endif 88}; 89 90struct dpll_param core_dpll_param_ddr400mhz = { 91 0x7d, 0x05, 0x01, 0x05, 0x08, 0x04, 0x06, 0x05, 92}; 93 94struct dpll_param abe_dpll_param = { 95#ifdef CONFIG_OMAP4_SDC 96 0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 97#else 98 0x40, 0x18, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 99#endif 100}; 101 102struct dpll_param usb_dpll_param = { 103#ifdef CONFIG_OMAP4_SDC 104 0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 105#else 106 0x32, 0x1, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 107#endif 108}; 109 110typedef struct dpll_param dpll_param; 111 112static void configure_mpu_dpll(dpll_param *dpll_param_p) 113{ 114 /* Unlock the MPU dpll */ 115 sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_MN_POWER_BYPASS); 116 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_MPU, LDELAY); 117 118 /* Disable DPLL autoidle */ 119 sr32(CM_AUTOIDLE_DPLL_MPU, 0, 3, 0x0); 120 121 /* Set M,N,M2 values */ 122 sr32(CM_CLKSEL_DPLL_MPU, 8, 11, dpll_param_p->m); 123 sr32(CM_CLKSEL_DPLL_MPU, 0, 6, dpll_param_p->n); 124 sr32(CM_DIV_M2_DPLL_MPU, 0, 5, dpll_param_p->m2); 125 sr32(CM_DIV_M2_DPLL_MPU, 8, 1, 0x1); 126 127 /* Lock the mpu dpll */ 128 sr32(CM_CLKMODE_DPLL_MPU, 0, 3, PLL_LOCK | 0x10); 129 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_MPU, LDELAY); 130} 131 132static void configure_iva_dpll(dpll_param *dpll_param_p) 133{ 134 /* Unlock the IVA dpll */ 135 sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_MN_POWER_BYPASS); 136 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_IVA, LDELAY); 137 138 /* CM_BYPCLK_DPLL_IVA = CORE_X2_CLK/2 */ 139 sr32(CM_BYPCLK_DPLL_IVA, 0, 2, 0x1); 140 141 /* Disable DPLL autoidle */ 142 sr32(CM_AUTOIDLE_DPLL_IVA, 0, 3, 0x0); 143 144 /* Set M,N,M4,M5 */ 145 sr32(CM_CLKSEL_DPLL_IVA, 8, 11, dpll_param_p->m); 146 sr32(CM_CLKSEL_DPLL_IVA, 0, 7, dpll_param_p->n); 147 sr32(CM_DIV_M4_DPLL_IVA, 0, 5, dpll_param_p->m4); 148 sr32(CM_DIV_M4_DPLL_IVA, 8, 1, 0x1); 149 sr32(CM_DIV_M5_DPLL_IVA, 0, 5, dpll_param_p->m5); 150 sr32(CM_DIV_M5_DPLL_IVA, 8, 1, 0x1); 151 152 /* Lock the iva dpll */ 153 sr32(CM_CLKMODE_DPLL_IVA, 0, 3, PLL_LOCK); 154 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_IVA, LDELAY); 155} 156 157static void configure_per_dpll(const dpll_param *dpll_param_p) 158{ 159 /* Unlock the PER dpll */ 160 sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_MN_POWER_BYPASS); 161 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_PER, LDELAY); 162 163 /* Disable autoidle */ 164 sr32(CM_AUTOIDLE_DPLL_PER, 0, 3, 0x0); 165 166 sr32(CM_CLKSEL_DPLL_PER, 8, 11, dpll_param_p->m); 167 sr32(CM_CLKSEL_DPLL_PER, 0, 6, dpll_param_p->n); 168 sr32(CM_DIV_M2_DPLL_PER, 0, 5, dpll_param_p->m2); 169 sr32(CM_DIV_M2_DPLL_PER, 8, 1, 0x1); 170 sr32(CM_DIV_M3_DPLL_PER, 0, 5, dpll_param_p->m3); 171 sr32(CM_DIV_M3_DPLL_PER, 8, 1, 0x1); 172 sr32(CM_DIV_M4_DPLL_PER, 0, 5, dpll_param_p->m4); 173 sr32(CM_DIV_M4_DPLL_PER, 8, 1, 0x1); 174 sr32(CM_DIV_M5_DPLL_PER, 0, 5, dpll_param_p->m5); 175 sr32(CM_DIV_M5_DPLL_PER, 8, 1, 0x1); 176 sr32(CM_DIV_M6_DPLL_PER, 0, 5, dpll_param_p->m6); 177 sr32(CM_DIV_M6_DPLL_PER, 8, 1, 0x1); 178 sr32(CM_DIV_M7_DPLL_PER, 0, 5, dpll_param_p->m7); 179 sr32(CM_DIV_M7_DPLL_PER, 8, 1, 0x1); 180 181 /* Lock the per dpll */ 182 sr32(CM_CLKMODE_DPLL_PER, 0, 3, PLL_LOCK); 183 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_PER, LDELAY); 184} 185 186static void configure_abe_dpll(dpll_param *dpll_param_p) 187{ 188 /* Select sys_clk as ref clk for ABE dpll */ 189 sr32(CM_ABE_PLL_REF_CLKSEL, 0, 32, 0x0); 190 191 /* Unlock the ABE dpll */ 192 sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_MN_POWER_BYPASS); 193 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_ABE, LDELAY); 194 195 /* Disable autoidle */ 196 sr32(CM_AUTOIDLE_DPLL_ABE, 0, 3, 0x0); 197 198 sr32(CM_CLKSEL_DPLL_ABE, 8, 11, dpll_param_p->m); 199 sr32(CM_CLKSEL_DPLL_ABE, 0, 6, dpll_param_p->n); 200 201 /* Force DPLL CLKOUTHIF to stay enabled */ 202 sr32(CM_DIV_M2_DPLL_ABE, 0, 32, 0x500); 203 sr32(CM_DIV_M2_DPLL_ABE, 0, 5, dpll_param_p->m2); 204 sr32(CM_DIV_M2_DPLL_ABE, 8, 1, 0x1); 205 /* Force DPLL CLKOUTHIF to stay enabled */ 206 sr32(CM_DIV_M3_DPLL_ABE, 0, 32, 0x100); 207 sr32(CM_DIV_M3_DPLL_ABE, 0, 5, dpll_param_p->m3); 208 sr32(CM_DIV_M3_DPLL_ABE, 8, 1, 0x1); 209 210 /* Lock the abe dpll */ 211 sr32(CM_CLKMODE_DPLL_ABE, 0, 3, PLL_LOCK); 212 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_ABE, LDELAY); 213} 214 215static void configure_usb_dpll(dpll_param *dpll_param_p) 216{ 217 /* Select the 60Mhz clock 480/8 = 60*/ 218 sr32(CM_CLKSEL_USB_60MHz, 0, 32, 0x1); 219 220 /* Unlock the USB dpll */ 221 sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_MN_POWER_BYPASS); 222 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_USB, LDELAY); 223 224 /* Disable autoidle */ 225 sr32(CM_AUTOIDLE_DPLL_USB, 0, 3, 0x0); 226 227 sr32(CM_CLKSEL_DPLL_USB, 8, 11, dpll_param_p->m); 228 sr32(CM_CLKSEL_DPLL_USB, 0, 6, dpll_param_p->n); 229 230 /* Force DPLL CLKOUT to stay active */ 231 sr32(CM_DIV_M2_DPLL_USB, 0, 32, 0x100); 232 sr32(CM_DIV_M2_DPLL_USB, 0, 5, dpll_param_p->m2); 233 sr32(CM_DIV_M2_DPLL_USB, 8, 1, 0x1); 234 sr32(CM_CLKDCOLDO_DPLL_USB, 8, 1, 0x1); 235 236 /* Lock the usb dpll */ 237 sr32(CM_CLKMODE_DPLL_USB, 0, 3, PLL_LOCK); 238 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_USB, LDELAY); 239 240 /* force enable the CLKDCOLDO clock */ 241 sr32(CM_CLKDCOLDO_DPLL_USB, 0, 32, 0x100); 242} 243 244void configure_core_dpll_no_lock(void) 245{ 246 dpll_param *dpll_param_p = &core_dpll_param_ddr400mhz; 247 248 /* Get the sysclk speed from cm_sys_clksel 249 * Set it to 38.4 MHz, in case ROM code is bypassed 250 */ 251 writel(0x7,CM_SYS_CLKSEL); 252 253 /* CORE_CLK=CORE_X2_CLK/2, L3_CLK=CORE_CLK/2, L4_CLK=L3_CLK/2 */ 254 sr32(CM_CLKSEL_CORE, 0, 32, 0x110); 255 256 /* Unlock the CORE dpll */ 257 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_MN_POWER_BYPASS); 258 wait_on_value(BIT0, 0, CM_IDLEST_DPLL_CORE, LDELAY); 259 260 /* Disable autoidle */ 261 sr32(CM_AUTOIDLE_DPLL_CORE, 0, 3, 0x0); 262 263 sr32(CM_CLKSEL_DPLL_CORE, 8, 11, dpll_param_p->m); 264 sr32(CM_CLKSEL_DPLL_CORE, 0, 6, dpll_param_p->n); 265 sr32(CM_DIV_M2_DPLL_CORE, 0, 5, dpll_param_p->m2); 266 sr32(CM_DIV_M3_DPLL_CORE, 0, 5, dpll_param_p->m3); 267 sr32(CM_DIV_M4_DPLL_CORE, 0, 5, dpll_param_p->m4); 268 sr32(CM_DIV_M5_DPLL_CORE, 0, 5, dpll_param_p->m5); 269 sr32(CM_DIV_M6_DPLL_CORE, 0, 5, dpll_param_p->m6); 270 sr32(CM_DIV_M7_DPLL_CORE, 0, 5, dpll_param_p->m7); 271} 272 273void lock_core_dpll(void) 274{ 275 /* Lock the core dpll */ 276 sr32(CM_CLKMODE_DPLL_CORE, 0, 3, PLL_LOCK); 277 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); 278} 279 280void lock_core_dpll_shadow(void) 281{ 282 dpll_param *dpll_param_p = &core_dpll_param_ddr400mhz; 283 u32 temp; 284 temp = readl(CM_MEMIF_CLKSTCTRL); 285 temp &= (~3); 286 temp |= 2; 287 writel(temp, CM_MEMIF_CLKSTCTRL); 288 289 while(readl(CM_MEMIF_EMIF_1_CLKCTRL) & 0x30000) 290 ; 291 292 while(readl(CM_MEMIF_EMIF_2_CLKCTRL) & 0x30000) 293 ; 294 295 /* Lock the core dpll using freq update method */ 296 /*(CM_CLKMODE_DPLL_CORE) */ 297 writel(0x0A, 0x4A004120); 298 299 /* CM_SHADOW_FREQ_CONFIG1: DLL_OVERRIDE = 1(hack), DLL_RESET = 1, 300 * DPLL_CORE_M2_DIV =1, DPLL_CORE_DPLL_EN = 0x7, FREQ_UPDATE = 1 301 */ 302 writel(0x70D | (dpll_param_p->m2 << 11), 0x4A004260); 303 304 /* Wait for Freq_Update to get cleared: CM_SHADOW_FREQ_CONFIG1 */ 305 while((readl(0x4A004260) & 0x1) == 0x1) 306 ; 307 308 /* Wait for DPLL to Lock : CM_IDLEST_DPLL_CORE */ 309 wait_on_value(BIT0, 1, CM_IDLEST_DPLL_CORE, LDELAY); 310 //lock_core_dpll(); 311 312 while(readl(CM_MEMIF_EMIF_1_CLKCTRL) & 0x30000) 313 ; 314 315 while(readl(CM_MEMIF_EMIF_2_CLKCTRL) & 0x30000) 316 ; 317 318 writel(temp|3, CM_MEMIF_CLKSTCTRL); 319} 320 321static void enable_all_clocks(void) 322{ 323 /* L4PER clocks */ 324 sr32(CM_L4PER_CLKSTCTRL, 0, 32, 0x2); 325 sr32(CM_L4PER_DMTIMER10_CLKCTRL, 0, 32, 0x2); 326 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER10_CLKCTRL, LDELAY); 327 sr32(CM_L4PER_DMTIMER11_CLKCTRL, 0, 32, 0x2); 328 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER11_CLKCTRL, LDELAY); 329 sr32(CM_L4PER_DMTIMER2_CLKCTRL, 0, 32, 0x2); 330 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER2_CLKCTRL, LDELAY); 331 sr32(CM_L4PER_DMTIMER3_CLKCTRL, 0, 32, 0x2); 332 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER3_CLKCTRL, LDELAY); 333 sr32(CM_L4PER_DMTIMER4_CLKCTRL, 0, 32, 0x2); 334 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER4_CLKCTRL, LDELAY); 335 sr32(CM_L4PER_DMTIMER9_CLKCTRL, 0, 32, 0x2); 336 wait_on_value(BIT17|BIT16, 0, CM_L4PER_DMTIMER9_CLKCTRL, LDELAY); 337 338 /* GPIO clocks */ 339 sr32(CM_L4PER_GPIO2_CLKCTRL, 0 ,32, 0x1); 340 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO2_CLKCTRL, LDELAY); 341 sr32(CM_L4PER_GPIO3_CLKCTRL, 0, 32, 0x1); 342 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO3_CLKCTRL, LDELAY); 343 sr32(CM_L4PER_GPIO4_CLKCTRL, 0, 32, 0x1); 344 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO4_CLKCTRL, LDELAY); 345 sr32(CM_L4PER_GPIO4_CLKCTRL, 8, 1, 0x1); 346 sr32(CM_L4PER_GPIO5_CLKCTRL, 0, 32, 0x1); 347 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO5_CLKCTRL, LDELAY); 348 sr32(CM_L4PER_GPIO6_CLKCTRL, 0, 32, 0x1); 349 wait_on_value(BIT17|BIT16, 0, CM_L4PER_GPIO6_CLKCTRL, LDELAY); 350 351 sr32(CM_L4PER_HDQ1W_CLKCTRL, 0, 32, 0x2); 352 353 /* I2C clocks */ 354 sr32(CM_L4PER_I2C1_CLKCTRL, 0, 32, 0x2); 355 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C1_CLKCTRL, LDELAY); 356 sr32(CM_L4PER_I2C2_CLKCTRL, 0, 32, 0x2); 357 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C2_CLKCTRL, LDELAY); 358 sr32(CM_L4PER_I2C3_CLKCTRL, 0, 32, 0x2); 359 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C3_CLKCTRL, LDELAY); 360 sr32(CM_L4PER_I2C4_CLKCTRL, 0, 32, 0x2); 361 wait_on_value(BIT17|BIT16, 0, CM_L4PER_I2C4_CLKCTRL, LDELAY); 362 363 sr32(CM_L4PER_MCBSP4_CLKCTRL, 0, 32, 0x2); 364 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCBSP4_CLKCTRL, LDELAY); 365 366 /* MCSPI clocks */ 367 sr32(CM_L4PER_MCSPI1_CLKCTRL, 0, 32, 0x2); 368 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI1_CLKCTRL, LDELAY); 369 sr32(CM_L4PER_MCSPI2_CLKCTRL, 0, 32, 0x2); 370 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI2_CLKCTRL, LDELAY); 371 sr32(CM_L4PER_MCSPI3_CLKCTRL, 0, 32, 0x2); 372 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI3_CLKCTRL, LDELAY); 373 sr32(CM_L4PER_MCSPI4_CLKCTRL, 0, 32, 0x2); 374 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MCSPI4_CLKCTRL, LDELAY); 375 376 /* MMC clocks */ 377 sr32(CM_L3INIT_HSMMC1_CLKCTRL, 0, 2, 0x2); 378 sr32(CM_L3INIT_HSMMC1_CLKCTRL, 24, 1, 0x1); 379 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC1_CLKCTRL, LDELAY); 380 sr32(CM_L3INIT_HSMMC2_CLKCTRL, 0, 2, 0x2); 381 sr32(CM_L3INIT_HSMMC2_CLKCTRL, 24, 1, 0x1); 382 //wait_on_value(BIT18|BIT17|BIT16, 0, CM_L3INIT_HSMMC2_CLKCTRL, LDELAY); 383 sr32(CM_L4PER_MMCSD3_CLKCTRL, 0, 32, 0x2); 384 wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD3_CLKCTRL, LDELAY); 385 sr32(CM_L4PER_MMCSD4_CLKCTRL, 0, 32, 0x2); 386 wait_on_value(BIT18|BIT17|BIT16, 0, CM_L4PER_MMCSD4_CLKCTRL, LDELAY); 387 sr32(CM_L4PER_MMCSD5_CLKCTRL, 0, 32, 0x2); 388 wait_on_value(BIT17|BIT16, 0, CM_L4PER_MMCSD5_CLKCTRL, LDELAY); 389 390 /* UART clocks */ 391 sr32(CM_L4PER_UART1_CLKCTRL, 0, 32, 0x2); 392 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART1_CLKCTRL, LDELAY); 393 sr32(CM_L4PER_UART2_CLKCTRL, 0, 32, 0x2); 394 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART2_CLKCTRL, LDELAY); 395 sr32(CM_L4PER_UART3_CLKCTRL, 0, 32, 0x2); 396 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART3_CLKCTRL, LDELAY); 397 sr32(CM_L4PER_UART4_CLKCTRL, 0, 32, 0x2); 398 wait_on_value(BIT17|BIT16, 0, CM_L4PER_UART4_CLKCTRL, LDELAY); 399 400 /* WKUP clocks */ 401 sr32(CM_WKUP_GPIO1_CLKCTRL, 0, 32, 0x1); 402 wait_on_value(BIT17|BIT16, 0, CM_WKUP_GPIO1_CLKCTRL, LDELAY); 403 sr32(CM_WKUP_TIMER1_CLKCTRL, 0, 32, 0x01000002); 404 wait_on_value(BIT17|BIT16, 0, CM_WKUP_TIMER1_CLKCTRL, LDELAY); 405 406 sr32(CM_WKUP_KEYBOARD_CLKCTRL, 0, 32, 0x2); 407 wait_on_value(BIT17|BIT16, 0, CM_WKUP_KEYBOARD_CLKCTRL, LDELAY); 408 409 sr32(CM_SDMA_CLKSTCTRL, 0, 32, 0x0); 410 sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3); 411 sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1); 412 wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_1_CLKCTRL, LDELAY); 413 sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1); 414 wait_on_value(BIT17|BIT16, 0, CM_MEMIF_EMIF_2_CLKCTRL, LDELAY); 415 sr32(CM_D2D_CLKSTCTRL, 0, 32, 0x3); 416 sr32(CM_L3_2_GPMC_CLKCTRL, 0, 32, 0x1); 417 wait_on_value(BIT17|BIT16, 0, CM_L3_2_GPMC_CLKCTRL, LDELAY); 418 sr32(CM_L3INSTR_L3_3_CLKCTRL, 0, 32, 0x1); 419 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_3_CLKCTRL, LDELAY); 420 sr32(CM_L3INSTR_L3_INSTR_CLKCTRL, 0, 32, 0x1); 421 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_L3_INSTR_CLKCTRL, LDELAY); 422 sr32(CM_L3INSTR_OCP_WP1_CLKCTRL, 0, 32, 0x1); 423 wait_on_value(BIT17|BIT16, 0, CM_L3INSTR_OCP_WP1_CLKCTRL, LDELAY); 424 425 /* WDT clocks */ 426 sr32(CM_WKUP_WDT2_CLKCTRL, 0, 32, 0x2); 427 wait_on_value(BIT17|BIT16, 0, CM_WKUP_WDT2_CLKCTRL, LDELAY); 428 429 /* Select DPLL PER CLOCK as source for SGX FCLK */ 430 sr32(CM_SGX_SGX_CLKCTRL, 24, 1, 0x1); 431 432 /* Enable clocks for USB fast boot to work */ 433 sr32(CM_L3INIT_USBPHY_CLKCTRL, 0, 32, 0x301); 434 sr32(CM_L3INIT_HSUSBOTG_CLKCTRL, 0, 32, 0x1); 435 436 return; 437} 438 439/* must be called from sram or flash */ 440void prcm_init(void) 441{ 442 u32 clk_index; 443 /* Get the sysclk speed from cm_sys_clksel 444 * Set the CM_SYS_CLKSEL in case ROM code has not set 445 */ 446 writel(0x7,CM_SYS_CLKSEL); 447 clk_index = readl(CM_SYS_CLKSEL); 448 if (!clk_index) 449 return; 450 451 /* Configure all DPLL's at 100% OPP */ 452 configure_mpu_dpll(&mpu_dpll_param); 453 configure_iva_dpll(&iva_dpll_param); 454 configure_per_dpll(&per_dpll_param); 455 configure_abe_dpll(&abe_dpll_param); 456 configure_usb_dpll(&usb_dpll_param); 457 458 enable_all_clocks(); 459} 460 461