1/****************************************************************************** 2* 3* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. 4* 5* Permission is hereby granted, free of charge, to any person obtaining a copy 6* of this software and associated documentation files (the "Software"), to deal 7* in the Software without restriction, including without limitation the rights 8* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9* copies of the Software, and to permit persons to whom the Software is 10* furnished to do so, subject to the following conditions: 11* 12* The above copyright notice and this permission notice shall be included in 13* all copies or substantial portions of the Software. 14* 15* Use of the Software is limited solely to applications: 16* (a) running on a Xilinx device, or 17* (b) that interact with a Xilinx device through a bus or interconnect. 18* 19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 23* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF 24* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 25* SOFTWARE. 26* 27* Except as contained in this notice, the name of the Xilinx shall not be used 28* in advertising or otherwise to promote the sale, use or other dealings in 29* this Software without prior written authorization from Xilinx. 30* 31****************************************************************************** 32* 33* Copyright (c) 2016, ETH Zurich. 34* All rights reserved. 35* 36* This file is distributed under the terms in the attached LICENSE file. 37* If you do not find this file, copies can be found by writing to: 38* ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group. 39* 40***************************************************************************** 41* 42* @file zynq7000_map.h 43* 44* This file contains the address definitions for the hard peripherals 45* attached to the ARM Cortex A9 core in the Zynq7000-series SoCs. 46* 47* Derived from lib/bsp/standalone/src/cortexa9/xparameters_ps.h in the Xilinx 48* 'embeddedsw' package. 49* 50******************************************************************************/ 51 52#ifndef _ZYNQ7000_MAP_H_ 53#define _ZYNQ7000_MAP_H_ 54 55#ifdef __cplusplus 56extern "C" { 57#endif 58 59/************************** Constant Definitions *****************************/ 60 61/* 62 * This block contains constant declarations for the peripherals 63 * within the hardblock 64 */ 65 66/* Canonical definitions for DDR MEMORY */ 67#define ZYNQ7_DDR_MEM_BASEADDR 0x00000000U 68#define ZYNQ7_DDR_MEM_HIGHADDR 0x3FFFFFFFU 69 70/* Canonical definitions for SLCR */ 71#define ZINQ7_XSLCR_NUM_INSTANCES 1U 72#define ZINQ7_XSLCR_0_DEVICE_ID 0U 73#define ZINQ7_XSLCR_0_BASEADDR ZINQ7_SYS_CTRL_BASEADDR 74 75/* Canonical definitions for SCU GIC */ 76#define ZINQ7_SCUGIC_NUM_INSTANCES 1U 77#define ZINQ7_SCUGIC_SINGLE_DEVICE_ID 0U 78#define ZINQ7_SCUGIC_CPU_BASEADDR (ZINQ7_SCU_PERIPH_BASE + 0x00000100U) 79#define ZINQ7_SCUGIC_DIST_BASEADDR (ZINQ7_SCU_PERIPH_BASE + 0x00001000U) 80#define ZINQ7_SCUGIC_ACK_BEFORE 0U 81 82/* Canonical definitions for Global Timer */ 83#define ZINQ7_GLOBAL_TMR_NUM_INSTANCES 1U 84#define ZINQ7_GLOBAL_TMR_DEVICE_ID 0U 85#define ZINQ7_GLOBAL_TMR_BASEADDR (ZINQ7_SCU_PERIPH_BASE + 0x00000200U) 86#define ZINQ7_GLOBAL_TMR_INTR ZINQ7_GLOBAL_TMR_INT_ID 87 88/* 89 * This block contains constant declarations for the peripherals 90 * within the hardblock. These have been put for bacwards compatibilty 91 */ 92 93#define ZINQ7_PERIPHERAL_BASEADDR 0xE0000000U 94#define ZINQ7_UART0_BASEADDR 0xE0000000U 95#define ZINQ7_UART1_BASEADDR 0xE0001000U 96#define ZINQ7_USB0_BASEADDR 0xE0002000U 97#define ZINQ7_USB1_BASEADDR 0xE0003000U 98#define ZINQ7_I2C0_BASEADDR 0xE0004000U 99#define ZINQ7_I2C1_BASEADDR 0xE0005000U 100#define ZINQ7_SPI0_BASEADDR 0xE0006000U 101#define ZINQ7_SPI1_BASEADDR 0xE0007000U 102#define ZINQ7_CAN0_BASEADDR 0xE0008000U 103#define ZINQ7_CAN1_BASEADDR 0xE0009000U 104#define ZINQ7_GPIO_BASEADDR 0xE000A000U 105#define ZINQ7_GEM0_BASEADDR 0xE000B000U 106#define ZINQ7_GEM1_BASEADDR 0xE000C000U 107#define ZINQ7_QSPI_BASEADDR 0xE000D000U 108#define ZINQ7_PARPORT_CRTL_BASEADDR 0xE000E000U 109#define ZINQ7_SDIO0_BASEADDR 0xE0100000U 110#define ZINQ7_SDIO1_BASEADDR 0xE0101000U 111#define ZINQ7_IOU_BUS_CFG_BASEADDR 0xE0200000U 112#define ZINQ7_NAND_BASEADDR 0xE1000000U 113#define ZINQ7_PARPORT0_BASEADDR 0xE2000000U 114#define ZINQ7_PARPORT1_BASEADDR 0xE4000000U 115#define ZINQ7_QSPI_LINEAR_BASEADDR 0xFC000000U 116#define ZINQ7_SYS_CTRL_BASEADDR 0xF8000000U /* AKA SLCR */ 117#define ZINQ7_TTC0_BASEADDR 0xF8001000U 118#define ZINQ7_TTC1_BASEADDR 0xF8002000U 119#define ZINQ7_DMAC0_SEC_BASEADDR 0xF8003000U 120#define ZINQ7_DMAC0_NON_SEC_BASEADDR 0xF8004000U 121#define ZINQ7_WDT_BASEADDR 0xF8005000U 122#define ZINQ7_DDR_CTRL_BASEADDR 0xF8006000U 123#define ZINQ7_DEV_CFG_APB_BASEADDR 0xF8007000U 124#define ZINQ7_AFI0_BASEADDR 0xF8008000U 125#define ZINQ7_AFI1_BASEADDR 0xF8009000U 126#define ZINQ7_AFI2_BASEADDR 0xF800A000U 127#define ZINQ7_AFI3_BASEADDR 0xF800B000U 128#define ZINQ7_OCM_BASEADDR 0xF800C000U 129#define ZINQ7_EFUSE_BASEADDR 0xF800D000U 130#define ZINQ7_CORESIGHT_BASEADDR 0xF8800000U 131#define ZINQ7_TOP_BUS_CFG_BASEADDR 0xF8900000U 132#define ZINQ7_SCU_PERIPH_BASE 0xF8F00000U 133#define ZINQ7_L2CC_BASEADDR 0xF8F02000U 134#define ZINQ7_SAM_RAM_BASEADDR 0xFFFC0000U 135#define ZINQ7_FPGA_AXI_S0_BASEADDR 0x40000000U 136#define ZINQ7_FPGA_AXI_S1_BASEADDR 0x80000000U 137#define ZINQ7_IOU_S_SWITCH_BASEADDR 0xE0000000U 138#define ZINQ7_PERIPH_APB_BASEADDR 0xF8000000U 139 140/* Shared Peripheral Interrupts (SPI) */ 141#define ZINQ7_CORE_PARITY0_INT_ID 32U 142#define ZINQ7_CORE_PARITY1_INT_ID 33U 143#define ZINQ7_L2CC_INT_ID 34U 144#define ZINQ7_OCMINTR_INT_ID 35U 145#define ZINQ7_ECC_INT_ID 36U 146#define ZINQ7_PMU0_INT_ID 37U 147#define ZINQ7_PMU1_INT_ID 38U 148#define ZINQ7_SYSMON_INT_ID 39U 149#define ZINQ7_DVC_INT_ID 40U 150#define ZINQ7_WDT_INT_ID 41U 151#define ZINQ7_TTC0_0_INT_ID 42U 152#define ZINQ7_TTC0_1_INT_ID 43U 153#define ZINQ7_TTC0_2_INT_ID 44U 154#define ZINQ7_DMA0_ABORT_INT_ID 45U 155#define ZINQ7_DMA0_INT_ID 46U 156#define ZINQ7_DMA1_INT_ID 47U 157#define ZINQ7_DMA2_INT_ID 48U 158#define ZINQ7_DMA3_INT_ID 49U 159#define ZINQ7_SMC_INT_ID 50U 160#define ZINQ7_QSPI_INT_ID 51U 161#define ZINQ7_GPIO_INT_ID 52U 162#define ZINQ7_USB0_INT_ID 53U 163#define ZINQ7_GEM0_INT_ID 54U 164#define ZINQ7_GEM0_WAKE_INT_ID 55U 165#define ZINQ7_SDIO0_INT_ID 56U 166#define ZINQ7_I2C0_INT_ID 57U 167#define ZINQ7_SPI0_INT_ID 58U 168#define ZINQ7_UART0_INT_ID 59U 169#define ZINQ7_CAN0_INT_ID 60U 170#define ZINQ7_FPGA0_INT_ID 61U 171#define ZINQ7_FPGA1_INT_ID 62U 172#define ZINQ7_FPGA2_INT_ID 63U 173#define ZINQ7_FPGA3_INT_ID 64U 174#define ZINQ7_FPGA4_INT_ID 65U 175#define ZINQ7_FPGA5_INT_ID 66U 176#define ZINQ7_FPGA6_INT_ID 67U 177#define ZINQ7_FPGA7_INT_ID 68U 178#define ZINQ7_TTC1_0_INT_ID 69U 179#define ZINQ7_TTC1_1_INT_ID 70U 180#define ZINQ7_TTC1_2_INT_ID 71U 181#define ZINQ7_DMA4_INT_ID 72U 182#define ZINQ7_DMA5_INT_ID 73U 183#define ZINQ7_DMA6_INT_ID 74U 184#define ZINQ7_DMA7_INT_ID 75U 185#define ZINQ7_USB1_INT_ID 76U 186#define ZINQ7_GEM1_INT_ID 77U 187#define ZINQ7_GEM1_WAKE_INT_ID 78U 188#define ZINQ7_SDIO1_INT_ID 79U 189#define ZINQ7_I2C1_INT_ID 80U 190#define ZINQ7_SPI1_INT_ID 81U 191#define ZINQ7_UART1_INT_ID 82U 192#define ZINQ7_CAN1_INT_ID 83U 193#define ZINQ7_FPGA8_INT_ID 84U 194#define ZINQ7_FPGA9_INT_ID 85U 195#define ZINQ7_FPGA10_INT_ID 86U 196#define ZINQ7_FPGA11_INT_ID 87U 197#define ZINQ7_FPGA12_INT_ID 88U 198#define ZINQ7_FPGA13_INT_ID 89U 199#define ZINQ7_FPGA14_INT_ID 90U 200#define ZINQ7_FPGA15_INT_ID 91U 201 202/* Private Peripheral Interrupts (PPI) */ 203#define ZINQ7_GLOBAL_TMR_INT_ID 27U /* SCU Global Timer interrupt */ 204#define ZINQ7_FIQ_INT_ID 28U /* FIQ from FPGA fabric */ 205#define ZINQ7_SCU_TMR_INT_ID 29U /* SCU Private Timer interrupt */ 206#define ZINQ7_SCU_WDT_INT_ID 30U /* SCU Private WDT interrupt */ 207#define ZINQ7_IRQ_INT_ID 31U /* IRQ from FPGA fabric */ 208 209#define ZINQ7_SCUTIMER_DEVICE_ID 0U 210#define ZINQ7_SCUWDT_DEVICE_ID 0U 211 212#ifdef __cplusplus 213} 214#endif 215 216#endif /* _ZYNQ7000_MAP_H_ */ 217