1/**
2 * \file
3 * \brief Architecture-specific registers code
4 */
5
6/*
7 * Copyright (c) 2015, ETH Zurich.
8 * Copyright (c) 2015, Hewlett Packard Enterprise Development LP.
9 * All rights reserved.
10 *
11 * This file is distributed under the terms in the attached LICENSE file.
12 * If you do not find this file, copies can be found by writing to:
13 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
14 */
15
16#ifndef ARCH_AARCH64_BARRELFISH_KPI_REGISTERS_H
17#define ARCH_AARCH64_BARRELFISH_KPI_REGISTERS_H
18
19#ifndef __ASSEMBLER__
20#include <stddef.h> // for offsetof
21#include <barrelfish/curdispatcher_arch.h> // XXX For curdispatcher()
22#include <barrelfish_kpi/types.h> // for lvaddr_t
23#endif
24
25//
26// Offsets of saved registers in save area.
27//
28#define X0_REG    0
29#define X1_REG    1
30#define X2_REG    2
31#define X3_REG    3
32#define X4_REG    4
33#define X5_REG    5
34#define X6_REG    6
35#define X7_REG    7
36#define X8_REG    8
37#define X9_REG    9
38#define X10_REG  10
39#define X11_REG  11
40#define X12_REG  12
41#define X13_REG  13
42#define X14_REG  14
43#define X15_REG  15
44#define X16_REG  16
45#define X17_REG  17
46#define X18_REG  18
47#define X19_REG  19
48#define X20_REG  20
49#define X21_REG  21
50#define X22_REG  22
51#define X23_REG  23
52#define X24_REG  24
53#define X25_REG  25
54#define X26_REG  26
55#define X27_REG  27
56#define X28_REG  28
57#define FP_REG   29
58#define LR_REG   30
59#define SP_REG   31
60#define PC_REG   32
61#define SPSR_REG 33
62
63#define PIC_REGISTER X10
64
65#define NUM_REGS 98     /* cpsr, x0-x30, sp, pc */
66#define NUM_FPU_REGS 0
67#define ARCH_NUMREGS NUM_REGS
68
69/// Register used in system calls to encode function and arg count
70#define SYSCALL_REG       0
71
72//
73// Helpers for pasting system reserved register names
74//
75#define REG_OFFSET_CONCAT(x)    x ## _REG
76#define REG_OFFSET(name)        REG_OFFSET_CONCAT(name)
77
78#define REG_NAME(ord)
79
80#ifndef __ASSEMBLER__
81
82union registers_aarch64 {
83    struct registers_aarch64_named {
84        uint64_t x0,  x1,  x2,  x3,  x4,  x5,  x6,  x7;
85        uint64_t x8,  x9,  x10, x11, x12, x13, x14, x15;
86        uint64_t x16, x17, x18, x19, x20, x21, x22, x23;
87        uint64_t x24, x25, x26, x27, x28, x29, x30;
88        uint64_t stack, pc, spsr;
89        uint64_t v[32][2];
90    } named;
91    struct registers_aarch64_syscall_args {
92        uint64_t arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7;
93        uint64_t x8,   x9,   x10,  x11,  x12,  x13,  x14,  x15;
94        uint64_t x16,  x17,  x18,  x19,  x20,  x21,  x22,  x23;
95        uint64_t x24,  x25,  x26,  x27,  x28,  x29,  x30;
96        uint64_t stack, pc, spsr;
97        uint64_t v[32][2];
98    } syscall_args;
99    uint64_t regs[sizeof(struct registers_aarch64_named) / sizeof(uint64_t)];
100};
101
102STATIC_ASSERT_SIZEOF(union registers_aarch64, NUM_REGS * sizeof(uint64_t));
103
104///< Opaque handle for the register state
105typedef union registers_aarch64 arch_registers_state_t;
106
107static inline void
108registers_set_entry(arch_registers_state_t *regs, lvaddr_t entry)
109{
110    regs->named.pc = (uint64_t)entry;
111}
112
113static inline void
114registers_set_param(arch_registers_state_t *regs, uint64_t param)
115{
116    regs->named.x0 = param;
117}
118
119static inline void
120registers_get_param(arch_registers_state_t *regs, uint64_t *param)
121{
122    *param = regs->named.x0;
123}
124
125static inline uint64_t
126registers_get_ip(arch_registers_state_t *regs)
127{
128    return regs->named.pc;
129}
130
131static inline uint64_t
132registers_get_sp(arch_registers_state_t *regs)
133{
134    return regs->named.stack;
135}
136
137#endif // __ASSEMBLER__
138
139#endif // ARCH_AARCH64_BARRELFISH_KPI_REGISTERS_H
140