1/* 2 * Copyright (c) 2016, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstr 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * zynq_uart.dev 11 * 12 * DESCRIPTION: Xilinx Zynq UART controller 13 * 14 * This is derived from: 15 * 16 * Zynq-7000 All Programmable SoC Technical Reference Manual (UG585) 17 * 18 */ 19 20device zynq_uart msbfirst (addr base) "Zynq UART" { 21 22 constants en_hi "Enable high" { 23 disabled_hi = 0b0 "disabled"; 24 enabled_hi = 0b1 "enabled"; 25 }; 26 27 constants en_lo "Enable low" { 28 enabled_lo = 0b0 "enabled"; 29 disabled_lo = 0b1 "disabled"; 30 }; 31 32 register CR addr (base, 0x0) "UART Control" { 33 _ 23; 34 stopbrk 1 rw "Stop transmitting break"; 35 startbrk 1 rw "Start transmitting break"; 36 torst 1 rw "Restart receiver timeout counter"; 37 tx_dis 1 rw type(en_lo) "Transmit disable"; 38 tx_en 1 rw type(en_hi) "Transmit enable"; 39 rx_dis 1 rw type(en_lo) "Receive disable"; 40 rx_en 1 rw type(en_hi) "Receive enable"; 41 txrst 1 rw "Software reset for Tx data path"; 42 rxrst 1 rw "Software reset for Rx data path"; 43 }; 44 45 constants chmode "Channel mode" { 46 normal = 0b00 "normal"; 47 echo = 0b01 "automatic echo"; 48 local_loop = 0b10 "local loopback"; 49 remote_loop = 0b11 "remote loopback"; 50 }; 51 52 constants stopbits "Number of stop bits" { 53 stop_1 = 0b00 "1 stop bit"; 54 stop_15 = 0b01 "1.5 stop bits"; 55 stop_2 = 0b10 "2 stop bits"; 56 }; 57 58 constants parity "Parity type" { 59 even = 0b000 "even"; 60 odd = 0b001 "odd"; 61 space = 0b010 "space"; 62 mark = 0b011 "mark"; 63 none0 = 0b100 "none"; 64 none1 = 0b101 "none"; 65 none2 = 0b110 "none"; 66 none3 = 0b111 "none"; 67 }; 68 69 constants length "Character length" { 70 bits_8_0 = 0b00 "8 bits"; 71 bits_8_1 = 0b01 "8 bits"; 72 bits_7 = 0b10 "7 bits"; 73 bits_6 = 0b11 "6 bits"; 74 }; 75 76 register MR addr (base, 0x4) "UART Mode" { 77 _ 20; 78 _ 1; 79 _ 1; 80 chmode 2 rw type(chmode) "Channel mode"; 81 nbstop 2 rw type(stopbits) "Number of stop bits"; 82 par 3 rw type(parity) "Parity type"; 83 chrl 2 rw type(length) "Character length"; 84 clksel 1 rw "Divide uart_ref_clk by 8"; 85 }; 86 87 register IER addr (base, 0x8) "Interrupt Enable" { 88 _ 19; 89 tovr 1 wo "Transmitter FIFO overflow"; 90 tnful 1 wo "Transmitter FIFO nearly full"; 91 ttrig 1 wo "Transmitter FIFO trigger"; 92 dmsi 1 wo "Delta modem status indicator"; 93 timeout 1 wo "Receiver timeout error"; 94 parity 1 wo "Receiver parity error"; 95 framing 1 wo "Receiver framing error"; 96 rovr 1 wo "Receiver overflow error"; 97 tful 1 wo "Transmitter FIFO full"; 98 tempty 1 wo "Transmitter FIFO empty"; 99 rful 1 wo "Receiver FIFO full"; 100 rempty 1 wo "Receiver FIFO empty"; 101 rtrig 1 wo "Receiver FIFO trigger"; 102 }; 103 104 register IDR addr (base, 0xC) "Interrupt Disable" { 105 _ 19; 106 tovr 1 wo "Transmitter FIFO overflow"; 107 tnful 1 wo "Transmitter FIFO nearly full"; 108 ttrig 1 wo "Transmitter FIFO trigger"; 109 dmsi 1 wo "Delta modem status indicator"; 110 timeout 1 wo "Receiver timeout error"; 111 parity 1 wo "Receiver parity error"; 112 framing 1 wo "Receiver framing error"; 113 rovr 1 wo "Receiver overflow error"; 114 tful 1 wo "Transmitter FIFO full"; 115 tempty 1 wo "Transmitter FIFO empty"; 116 rful 1 wo "Receiver FIFO full"; 117 rempty 1 wo "Receiver FIFO empty"; 118 rtrig 1 wo "Receiver FIFO trigger"; 119 }; 120 121 register IMR addr (base, 0x10) "Interrupt Mask" { 122 _ 19; 123 tovr 1 ro "Transmitter FIFO overflow"; 124 tnful 1 ro "Transmitter FIFO nearly full"; 125 ttrig 1 ro "Transmitter FIFO trigger"; 126 dmsi 1 ro "Delta modem status indicator"; 127 timeout 1 ro "Receiver timeout error"; 128 parity 1 ro "Receiver parity error"; 129 framing 1 ro "Receiver framing error"; 130 rovr 1 ro "Receiver overflow error"; 131 tful 1 ro "Transmitter FIFO full"; 132 tempty 1 ro "Transmitter FIFO empty"; 133 rful 1 ro "Receiver FIFO full"; 134 rempty 1 ro "Receiver FIFO empty"; 135 rtrig 1 ro "Receiver FIFO trigger"; 136 }; 137 138 register ISR addr (base, 0x14) "Channel Interrupt Status" { 139 _ 19; 140 tovr 1 rw1c "Transmitter FIFO overflow"; 141 tnful 1 rw1c "Transmitter FIFO nearly full"; 142 ttrig 1 rw1c "Transmitter FIFO trigger"; 143 dmsi 1 rw1c "Delta modem status indicator"; 144 timeout 1 rw1c "Receiver timeout error"; 145 parity 1 rw1c "Receiver parity error"; 146 framing 1 rw1c "Receiver framing error"; 147 rovr 1 rw1c "Receiver overflow error"; 148 tful 1 rw1c "Transmitter FIFO full"; 149 tempty 1 rw1c "Transmitter FIFO empty"; 150 rful 1 rw1c "Receiver FIFO full"; 151 rempty 1 rw1c "Receiver FIFO empty"; 152 rtrig 1 rw1c "Receiver FIFO trigger"; 153 }; 154 155 register BAUDGEN addr (base, 0x18) "Baud Rate Generator" { 156 _ 16; 157 CD 16 rw "Baud rate clock divisor value"; 158 }; 159 160 register RXTOUT addr (base, 0x1C) "Receiver Timeout" { 161 _ 24; 162 RTO 8 rw "Receiver timeout value"; 163 }; 164 165 register RXWM addr (base, 0x20) "Receiver FIFO Trigger Level" { 166 _ 26; 167 RTRIG 6 rw "Receiver FIFO trigger level"; 168 }; 169 170 register MODEMCR addr (base, 0x24) "Modem Control" { 171 _ 26; 172 FCM 1 rw type(en_hi) "Automatic flow control"; 173 _ 3; 174 RTS 1 rw type(en_lo) "Request to send software control"; 175 DTR 1 rw type(en_lo) "Data terminal ready"; 176 }; 177 178 register MODEMSR addr (base, 0x28) "Modem Status" { 179 _ 23; 180 FCMS 1 rw type(en_hi) "Flow control mode"; 181 DCD 1 ro type(en_lo) "Data carrier detect"; 182 RI 1 ro type(en_lo) "Ring indicator"; 183 DSR 1 ro type(en_lo) "Data set ready"; 184 CTS 1 ro type(en_lo) "Clear to send"; 185 DDCD 1 rw1c "Delta data carrier detect status"; 186 TERI 1 rw1c "Trailing edge ring indicator status"; 187 DDSR 1 rw1c "Delta data set ready status"; 188 DCTS 1 rw1c "Delta clear to send status"; 189 }; 190 191 register SR addr (base, 0x2C) "Channel Status" { 192 _ 17; 193 TNFUL 1 ro "Transmitter FIFO nearly full"; 194 TTRIG 1 ro "Transmitter FIFO >= TTRIG"; 195 FDELT 1 ro "Receiver FIFO >= FDEL"; 196 TACTIVE 1 ro "Transmitter active"; 197 RACTIVE 1 ro "Recevier active"; 198 _ 1; 199 _ 1; 200 _ 1; 201 _ 1; 202 _ 1; 203 TXFULL 1 ro "Transmitter FIFO full"; 204 TXEMPTY 1 ro "Transmitter FIFO empty"; 205 RXFULL 1 ro "Receiver FIFO full"; 206 RXEMPTY 1 ro "Receiver FIFO empty"; 207 RTRIG 1 ro "Receiver FIFO >= RTRIG"; 208 }; 209 210 register FIFO addr (base, 0x30) "Transmit and Receive FIFO" { 211 _ 24; 212 FIFO 8 rw; 213 }; 214 215 register BDIV addr (base, 0x34) "Baud Rate Divider" { 216 _ 24; 217 BDIV 8 rw "Baud rate divider value"; 218 }; 219 220 register FDEL addr (base, 0x38) "Flow Control Delay" { 221 _ 26; 222 BDIV 6 rw "RxFIFO trigger level for RTS deassertion"; 223 }; 224 225 register TTRIG addr (base, 0x44) "Transmitter FIFO Trigger Level" { 226 _ 26; 227 TTRIG 6 rw "Transmitter FIFO Trigger Level"; 228 }; 229}; 230