1/* 2 * Copyright (c) 2012, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * ti_i2c.dev 11 * 12 * DESCRIPTION: TI I2C controller registers. 13 * 14 * Section numbers refer to OMAP4460 ES1.x PUBLIC TRM vQ 15 * 16 * (I think the I2C controllers in the OMAP4460 match the standard TI I2C) -SG 17 */ 18 19device ti_i2c msbfirst (addr b) "TI I2C controller" { 20 // Tables 23-33 and 23-35 21 register revnb_lo ro addr(b, 0x0) "Revision number (low part)" type(uint16); 22 register revnb_hi ro addr(b, 0x4) "Revision number (high part)" type(uint16); 23 24 constants clkact "clock activity" { 25 clk_off = 0b00 "Both clocks can be off"; 26 clk_ocp = 0b01 "Only OCP clock must be kept active"; 27 clk_sys = 0b10 "Only system clock must be kept active"; 28 clk_act = 0b11 "Both clocks must be active"; 29 }; 30 31 constants idlemode "idle mode" { 32 idlemode_forceidle = 0b00 "Force Idle"; 33 idlemode_noidle = 0b01 "No Idle"; 34 idlemode_smartidle = 0b10 "Smart Idle"; 35 idlemode_smartwkup = 0b11 "Smart Idle & Wakeup"; 36 }; 37 38 // Table 23-37 39 register sysc rw addr(b, 0x10) "System Configuration" { 40 _ 6 rsvd; 41 clkactivity 2 type(clkact) "Clock activity selection"; 42 _ 3 rsvd; 43 idlemode 2 type(idlemode) "Idle mode selection"; 44 enawakeup 1 "Enable wakeup control"; 45 srst 1 "SoftReset"; 46 autoidle 1 "Autoidle"; 47 }; 48 49 // Tables 23-39 and 23-41 50 regtype irqstatus "interrupt status vector" { 51 _ 1 rsvd; 52 xdr 1 "Transmit draining"; 53 rdr 1 "Receive draining"; 54 bb 1 ro "Bus busy"; 55 rovr 1 "Receive overrun"; 56 xudf 1 "Transmit underflow"; 57 aas 1 "Address recognized as slave IRQ status"; 58 bf 1 "Bus free"; 59 aerr 1 "Access error"; 60 stc 1 "Start condition"; 61 gc 1 "General call"; 62 xrdy 1 "Transmit data ready"; 63 rrdy 1 "Receive data ready"; 64 ardy 1 "Register access ready"; 65 nack 1 "No acknowledgement"; 66 al 1 "Arbitration lost"; 67 }; 68 register irqstatus_raw rw addr(b, 0x24) "Per-event raw interrupt status vector" 69 type(irqstatus); 70 register irqstatus rw1c addr(b, 0x28) "Per-event enabled interrupt status vector" 71 type(irqstatus); 72 73 // Tables 23-43 and 23-45 74 regtype irqenable "interrupt enable vector" { 75 _ 1 rsvd; 76 xdr_ie 1 "Transmit draining"; 77 rdr_ie 1 "Receive draining"; 78 _ 1 rsvd; 79 // NOTE: rovr and xudf don't have _ie in OMAP TRM -SG 80 rovr_ie 1 "Receive overrun"; 81 xudf_ie 1 "Transmit underflow"; 82 aas_ie 1 "Address recognized as slave IRQ status"; 83 bf_ie 1 "Bus free"; 84 aerr_ie 1 "Access error"; 85 stc_ie 1 "Start condition"; 86 gc_ie 1 "General call"; 87 xrdy_ie 1 "Transmit data ready"; 88 rrdy_ie 1 "Receive data ready"; 89 ardy_ie 1 "Register access ready"; 90 nack_ie 1 "No acknowledgement"; 91 al_ie 1 "Arbitration lost"; 92 }; 93 register irqenable_set rw addr(b, 0x2C) "Per-event interrupt enable bit vector" 94 type(irqenable); 95 register irqenable_clr rw addr(b, 0x30) "Per-event interrupt clear bit vector" 96 type(irqenable); 97 98 regtype wakeupen "per-event wakeup enable" { 99 _ 1 rsvd; 100 xdr 1 "Transmit draining"; 101 rdr 1 "Receive draining"; 102 _ 1 rsvd; 103 rovr 1 "Receive overrun"; 104 xudf 1 "Transmit underflow"; 105 aas 1 "Address recognized as slave IRQ status"; 106 bf 1 "Bus free"; 107 _ 1 rsvd; 108 stc 1 "Start condition"; 109 gc 1 "General call"; 110 _ 1 rsvd; 111 drdy 1 "Receive/Transmit data ready"; 112 ardy 1 "Register access ready"; 113 nack 1 "No acknowledgement"; 114 al 1 "Arbitration lost"; 115 }; 116 117 // Table 23-47 118 register we rw addr(b, 0x34) "Wakeup enable vector" type(wakeupen); 119 120 // Tables 23-49, 23-51, 23-53, and 23-55 121 // NOTE: nomenclature doesn't match OMAP TRM 122 regtype dmaen "DMA enable" { 123 _ 15 rsvd; 124 en 1 "Enable DMA channel"; 125 }; 126 register dmarxenable_set addr(b, 0x38) "Per-event DMA RX enable" 127 type(dmaen); 128 register dmatxenable_set addr(b, 0x3C) "Per-event DMA TX enable" 129 type(dmaen); 130 register dmarxenable_clr addr(b, 0x40) "Per-event DMA RX enable clear" 131 type(dmaen); 132 register dmatxenable_clr addr(b, 0x44) "Per-event DMA TX enable clear" 133 type(dmaen); 134 135 // Tables 23-57 and 23-59 136 register dmarxwake_en addr(b, 0x48) "Per-event DMA RX wakeup enable" 137 type(wakeupen); 138 register dmatxwake_en addr(b, 0x4C) "Per-event DMA TX wakeup enable" 139 type(wakeupen); 140 141 // Table 23-61 142 register ie rw addr(b, 0x84) "Interrupt enable vector (legacy)" 143 type(irqenable); 144 145 // dummy constants for polling stat flags 146 constants irqstatus_flags width(16) "irqstatus bitmasks" { 147 irq_flag_xdr = 0x4000 "Transmit draining"; 148 irq_flag_rdr = 0x2000 "Receive draining"; 149 irq_flag_bb = 0x1000 "Bus busy"; 150 irq_flag_rovr = 0x0800 "Receive overrun"; 151 irq_flag_xudf = 0x0400 "Transmit underflow"; 152 irq_flag_aas = 0x0200 "Address recognized as slave IRQ status"; 153 irq_flag_bf = 0x0100 "Bus free"; 154 irq_flag_aerr = 0x0080 "Access error"; 155 irq_flag_stc = 0x0040 "Start condition"; 156 irq_flag_gc = 0x0020 "General call"; 157 irq_flag_xrdy = 0x0010 "Transmit data ready"; 158 irq_flag_rrdy = 0x0008 "Receive data ready"; 159 irq_flag_ardy = 0x0004 "Register access ready"; 160 irq_flag_nack = 0x0002 "No acknowledgement"; 161 irq_flag_al = 0x0001 "Arbitration lost"; 162 }; 163 164 // Table 23-63 165 register stat rw1c addr(b, 0x88) "Interrupt status vector (legacy)" 166 type(irqstatus); 167 168 // Table 23-65 169 register syss rw addr(b, 0x90) "System status" { 170 _ 15 rsvd; 171 rdone 1 rw "Reset done"; 172 }; 173 174 // Table 23-67 175 register buf rw addr(b, 0x94) "Buffer Configuration" { 176 rdma_en 1 "Receive DMA enable"; 177 rxfifo_clr 1 "Receive FIFO clear"; 178 rxtrsh 6 "Threshold value for FIFO buffer in RX mode"; 179 xdma_en 1 "Transmit DMA enable"; 180 txfifo_clr 1 "Transmit FIFO clear"; 181 txtrsh 6 "Threshold value for FIFO buffer in TX mode"; 182 }; 183 184 // Table 23-69 185 // NOTE: writing 0 to cnt equals to a transfer of 65536 bytes; this means 186 // that software has to disallow 0-byte transfers. -SG 187 register cnt rw addr(b, 0x98) "Data counter" type(uint16); 188 189 // Table 23-71 190 register data rw addr(b, 0x9C) "Data access" { 191 _ 8 rsvd; 192 data 8 "Transmit/Receive data FIFO endpoint"; 193 }; 194 195 // Table 23-73 196 constants opmode "Operation Mode" { 197 opmode_fs = 0b00 "I2C Fast/Standard Mode"; 198 opmode_hs = 0b01 "I2C High Speed Mode"; 199 opmode_sccb = 0b10 "SCCB Mode"; 200 }; 201 register con rw addr(b, 0xA4) "Configuration" { 202 en 1 "module enable"; 203 _ 1 rsvd; 204 opmode 2 type(opmode) "Operation mode selection"; 205 stb 1 "Start byte mode"; 206 mst 1 "Master/slave mode"; 207 trx 1 "Transmitter/Receiver mode"; 208 xsa 1 "Expand Slave Address"; 209 xoa0 1 "Expand Own address 0"; 210 xoa1 1 "Expand Own address 1"; 211 xoa2 1 "Expand Own address 2"; 212 xoa3 1 "Expand Own address 3"; 213 _ 2 rsvd; 214 stp 1 "Stop condition"; 215 stt 1 "Start condition"; 216 }; 217 218 // Table 23-75 219 register oa rw addr(b, 0xA8) "Own address" { 220 mcode 3 "Master Code"; 221 _ 3 rsvd; 222 oa 10 "Own addres"; 223 }; 224 225 // Table 23-77 226 register sa rw addr(b, 0xAC) "Slave address" { 227 _ 6 rsvd; 228 sa 10 "Slave address"; 229 }; 230 231 // Table 23-79 232 register psc rw addr(b, 0xB0) "Clock Prescaler" { 233 _ 8 rsvd; 234 psc 8 "Fast/Standard mode prescale sampling clock divider [/(psc+1)]"; 235 }; 236 237 // Tables 23-81 and 23-83 238 regtype scltime "SCL time" { 239 hsscl 8 "High Speed mode SCL time"; 240 scl 8 "Fast/Standard mode SCL time"; 241 }; 242 register scll rw addr(b, 0xB4) "SCL Low Time" type(scltime); 243 register sclh rw addr(b, 0xB8) "SCL High Time" type(scltime); 244 245 // Table 23-85 246 constants testmode "Test mode" { 247 test_functional = 0b00 "Functional mode (default)"; 248 test_loopback = 0b11 "Loop back mode select + SDA/SCL IO mode select"; 249 test_sclcnttest = 0b10 "Test of SCL counters"; 250 }; 251 register systest rw addr(b, 0xBC) "System Test" { 252 st_en 1 "System test enable"; 253 free 1 "Free running mode (on breakpoint)"; 254 tmode 2 type(testmode) "Test mode select"; 255 ssb 1 "Set status bits from 0 to 14"; 256 _ 2 rsvd; 257 scl_i_func 1 ro "SCL line input value"; 258 scl_o_func 1 ro "SCL line output value"; 259 sda_i_func 1 ro "SDA line input value"; 260 sda_o_func 1 ro "SDA line output value"; 261 sccb_e_o 1 rw "SCCB_E line sense output value"; 262 scl_i 1 ro "SCL line sense input value"; 263 scl_o 1 rw "SCL line drive output value"; 264 sda_i 1 ro "SDA line sense input value"; 265 sda_o 1 rw "SDA line drive output value"; 266 }; 267 268 // Table 23-87 269 register bufstat ro addr(b, 0xC0) "Buffer Status" { 270 fifodepth 2 "Internal FIFO buffers depth"; 271 rxstat 6 "RX buffer status"; 272 _ 2 rsvd; 273 txstat 6 "TX buffer status"; 274 }; 275 276 // Tables 23-89, 23-91, and 23-93 277 regtype ownaddr "own address" { 278 _ 6 rsvd; 279 oa 10 "Own address"; 280 }; 281 register oa1 addr(b, 0xC4) "Own Address 1" type(ownaddr); 282 register oa2 addr(b, 0xC8) "Own Address 2" type(ownaddr); 283 register oa3 addr(b, 0xCC) "Own Address 3" type(ownaddr); 284 285 // Table 23-95 286 register actoa ro addr(b, 0xD0) { 287 _ 12 rsvd; 288 oa3_act 1 "Own address 3 active"; 289 oa2_act 1 "Own address 2 active"; 290 oa1_act 1 "Own address 1 active"; 291 oa0_act 1 "Own address 0 active"; 292 }; 293 294 // Table 23-97 295 register sblock rw addr(b, 0xD4) "Clock Blocking Enable" { 296 _ 12 rsvd; 297 oa3_en 1 "Own address 3 clock blocking enable"; 298 oa2_en 1 "Own address 2 clock blocking enable"; 299 oa1_en 1 "Own address 1 clock blocking enable"; 300 oa0_en 1 "Own address 0 clock blocking enable"; 301 }; 302}; 303