1/* 2 * Copyright (c) 2012, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * sp804_pit.dev 11 * 12 * DESCRIPTION: Dual-Timer Module SP804 13 * 14 * This is derived from: 15 * 16 * ARM Dual-Timer Module (SP804) Technical Reference Manual 17 * (DDI0271_sp804_timer_trm.pdf) 18 * 19 */ 20 21 22device sp804_pit msbfirst ( addr base ) "Dual-Timer Module SP804" { 23 24 constants prescale "Possible Prescale Values" { 25 prescale0 = 0b00 "0 stages of prescale, clock divided by 1"; 26 prescale4 = 0b01 "4 stages of prescale, clock divided by 16"; 27 prescale8 = 0b10 "8 stages of prescale, clock divided by 256"; 28 }; 29 30 constants timer_size "Timer operation sizes" { 31 size_16bit = 0b0 "16-bit counter"; 32 size_32bit = 0b1 "32-bit counter"; 33 }; 34 35 constants timer_modes "Timer Running Mode" { 36 free = 0b0 "Counts once and then wraps to 0xffff"; 37 periodic = 0b1 "Reloads from load register at end of each count"; 38 }; 39 40 41 // 42 // timer 1 43 // 44 45 register Timer1Load addr(base, 0x0) "Load Register" type(uint32); 46 47 register Timer1Value ro addr(base, 0x4) "Current Value Register" type(uint32); 48 49 register Timer1Control addr(base, 0x8) "Control Register" { 50 _ 24 rsvd; 51 timer_en 1 rw "Enable Bit"; 52 timer_mode 1 rw "Mode Bit"; 53 int_enable 1 rw "Interrupt Enable Bit"; 54 _ 1 rsvd; 55 timer_pre 2 rw "Prescale Bits"; 56 timer_size 1 rw "Selects 16/32 bit mode"; 57 one_shot 1 rw "Selects one-shot or wrapping counter mode"; 58 }; 59 60 register Timer1IntClr wo addr(base, 0xc) "Interrupt Clear Register" type(uint32); 61 62 register Timer1RIS ro addr(base, 0x10) "Raw Interrupt Status Register" { 63 _ 31 rsvd; 64 ri_status 1 ro "Raw interrupt status from the counter"; 65 }; 66 67 register Timer1MIS ro addr(base, 0x14) "Masked Interrupt Status Register" { 68 _ 31 rsvd; 69 mi_status 1 ro "Masked interrupt status from the counter"; 70 }; 71 72 register Timer1BGLoad addr(base, 0x18) "Background Load Register" type(uint32); 73 74 // 75 // timer 2 76 // 77 78 register Timer2Load addr(base, 0x20) "Load Register" type(uint32); 79 80 register Timer2Value ro addr(base, 0x24) "Current Value Register" type(uint32); 81 82 register Timer2Control addr(base, 0x28) "Control Register" { 83 _ 24 rsvd; 84 timer_en 1 rw "Enable Bit"; 85 timer_mode 1 rw "Mode Bit"; 86 int_enable 1 rw "Interrupt Enable Bit"; 87 _ 1 rsvd; 88 timer_pre 2 rw "Prescale Bits"; 89 timer_size 1 rw "Selects 16/32 bit mode"; 90 one_shot 1 rw "Selects one-shot or wrapping counter mode"; 91 }; 92 93 register Timer2IntClr wo addr(base, 0x2c) "Interrupt Clear Register" type(uint32); 94 95 register Timer2RIS ro addr(base, 0x30) "Raw Interrupt Status Register" { 96 _ 31 rsvd; 97 ri_status 1 ro "Raw interrupt status from the counter"; 98 }; 99 100 register Timer2MIS ro addr(base, 0x34) "Masked Interrupt Status Register" { 101 _ 31 rsvd; 102 mi_status 1 ro "Masked interrupt status from the counter"; 103 }; 104 105 register Timer2BGLoad addr(base, 0x38) "Background Load Register" type(uint32); 106 };