1/* 2 * Copyright (c) 2007, 2008, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * rtl8029as.dev 11 * 12 * DESCRIPTION: RTL8029AS Realtek PCI Full-Duplex Ethernet Controller 13 * with built-in SRAM 14 * 15 * This is derived from the IC specification white paper from RealTek 16 * (RTL8029AS Preliminary LS009.0 1997.01.16). 17 */ 18 19device rtl8029as lsbfirst ( io base ) "RTL8029AS Ethernet Controller" 20{ 21 /* 22 * 5. REGISTER DESCRIPTIONS 23 * 24 * The registers in RTL8029AS controller can be roughly divided into 25 * two groups by their address and functions -- one for NE2000, the 26 * other for PCI Configuration Space. 27 */ 28 29 /* 30 * 5.1. Group 1: NE2000 Registers 31 * 32 * This group includes 4 pages of registers which are selected by 33 * bit PS0 & PS1 in the CR register. Each page contains 16 34 * registers. Besides those registers compatible with NE2000, the 35 * RTL8029AS controller defines some registers for software 36 * configuration and feature enhancement. 37 */ 38 39 constants rd "Remote read/write" { 40 notallowed = 0b000 "Not allowed"; 41 rrd = 0b001 "Remote read"; 42 rwr = 0b010 "Remote write"; 43 sp = 0b011 "Send packet"; 44 acrdma = 0b100 "Abort/Complete remote DMA"; 45 }; 46 47 constants ps "Page identification" { 48 ne2000p0 = 0b00 "NE2000 compatible page 0"; 49 ne2000p1 = 0b01 "NE2000 compatible page 1"; 50 ne2000p2 = 0b10 "NE2000 compatible page 2"; 51 rtl8029as = 0b11 "RTL8029AS configuration page 3"; 52 }; 53 space page0(addr) bytewise "NE2000 compatible page 0"; 54 space page1(addr) bytewise "NE2000 compatible page 1"; 55 space page2(addr) bytewise "NE2000 compatible page 2"; 56 space p2p0(addr) bytewise "Write page 0, read page 2"; 57 space rtlp(addr) bytewise "RTL8029AS configuration page 3"; 58 59 constants lpconf "Loopback configuration" { 60 normal = 0b00 "Normal operation"; 61 internal = 0b01 "Internal loopback"; 62 external = 0b10 "External loopback"; 63 external1 = 0b11 "External loopback"; 64 }; 65 66 /* Supported interrupts */ 67 regtype irq "Interrupts" { 68 prx 1 "Packet received correctly"; 69 ptx 1 "Packet transmitted correctly"; 70 rxe 1 "Packet receive error"; 71 txe 1 "Packet sent aborted (excessive collisions)"; 72 ovw 1 "Receive buffer exhausted"; 73 cnt 1 "MSB of one or more network tally counters is set"; 74 rdc 1 "Remote DMA operation completed"; 75 rst 1 "Reset state / Receive buffer overflow"; 76 }; 77 78 /* 79 * This register is used to select register pages, enable or disable 80 * remote DMA operation and issue commands. 81 */ 82 register cr rw io ( base, 0x0 ) "Command" { 83 stp 1 "Stop command"; 84 sta 1 "Start command"; 85 txp 1 "Transmit packet"; 86 rd 3 type(rd) "Remote read/write"; 87 ps 2 type(ps) "Page identification"; 88 }; 89 90 /* 91 * This register reflects the NIC status. The host reads it to 92 * determine the cause of an interrupt. Individual bits are cleared 93 * by writing a "1" into the corresponding bit. It must be cleared 94 * after power up. 95 * 96 * Type=R/W in Page0. 97 */ 98 register isr rw page0( 0x7 ) "Interrupt Status" type(irq); 99 100 /* 101 * All bits correspond to the bits in the ISR register. POWER UP=all 102 * 0s. Setting individual bits will enable the corresponding 103 * interrupts. 104 * 105 * Type=W in Page0, Type=R in Page2. 106 */ 107 register imr rw p2p0( 0xf ) "Interrupt Mask" type(irq); 108 109 /* Type=W in Page0, Type=R in Page2. */ 110 register dcr rw p2p0( 0xe ) "Data Configuration" { 111 wts 1 "Word transfer select"; 112 bos 1 "Byte order select"; 113 _ 1 mbz; 114 ls 1 "Loopback select"; 115 arm 1 "Auto-Initialize remote"; 116 ft 2 "FIFO threshold select"; 117 _ 1 mb1; 118 }; 119 120 /* Type=W in Page0, Type=R in Page2 */ 121 register tcr rw p2p0 ( 0xd ) "Transmit Configuration" { 122 crc 1 "Inhibit CRC generation"; 123 lb 2 type(lpconf) "Loopback configuration"; 124 atd 1 "Auto transmit disable"; 125 ofst 1 "Collision offset enable"; 126 _ 3 mb1; 127 }; 128 129 /* 130 * This register indicates the status of a packet transmission. 131 * 132 * Type=R in Page0. 133 */ 134 register tsr ro page0( 0x4 ) "Transmit Status" { 135 ptx 1 "Transmission completed"; 136 _ 1 mb1; 137 col 1 "Collision"; 138 abt 1 "Aborted (excessive collisions)"; 139 crs 1 "Carrier lost"; 140 _ 1 mbz; 141 cdh 1 "CD Heartbeat failed"; 142 owc 1 "Out of Window collision"; 143 }; 144 145 /* Type=W in Page0, Type=R in Page2. */ 146 register rcr rw p2p0( 0xc ) "Receive Configuration" { 147 sep 1 "Accept packets with receive errors"; 148 ar 1 "Accept length < 64 bytes"; 149 ab 1 "Accept broadcast destination address"; 150 am 1 "Accept multicast destination address"; 151 pro 1 "Promiscuous mode"; 152 mon 1 "Monitor mode"; 153 _ 2 mb1; 154 }; 155 156 /* Type=R in Page0. */ 157 register rsr ro page0( 0xc ) "Receive Status" { 158 prx 1 "Packet received correctly"; 159 crc 1 "CRC mismatch"; 160 fae 1 "Frame alignment error"; 161 _ 1 mbz; 162 mpa 1 "Missed packet"; 163 phy 1 "Physical destination error"; 164 dis 1 "Receiver disabled"; 165 dfr 1 "Deferring"; 166 }; 167 168 /* 169 * These two registers can be read to get the current local DMA 170 * address. 171 * 172 * Type=R in Page0. 173 */ 174 register clda ro page0 ( 0x1 ) "Current Local DMA" type(uint16); 175 176 /* 177 * The Page Start register sets the start page address of the 178 * receive buffer ring. 179 * 180 * Type=W in Page0, Type=R in Page 2. 181 */ 182 register pstart rw p2p0( 0x1 ) "Page Start" type(uint8); 183 184 /* 185 * PSTOP: Page Stop Register (02H; Type=W in Page0, Type=R in Page2) 186 * 187 * The Page Stop register sets the stop page address of the receive 188 * buffer ring. 189 */ 190 register pstop rw p2p0( 0x2 ) "Page Stop" type(uint8); 191 192 /* 193 * BNRY: Boundary Register (03H; Type=R/W in Page0) 194 * 195 * This register is used to prevent overwrite of the receive buffer 196 * ring. It is typically used as a pointer indicating the last receive 197 * buffer page the host has read. 198 */ 199 register bnry rw page0( 0x3 ) "Boundary" type(uint8); 200 201 /* 202 * TPSR: Transmit Page Start Register (04H; Type=W in Page0) 203 * 204 * This register sets the start page address of the packet to the 205 * transmitted. 206 */ 207 register tpsr wo also page0( 0x4 ) "Transmit Page Start" type(uint8); 208 209 /* 210 * TBCR0,1: Transmit Byte Count Registers (05H & 06H; Type=W in 211 * Page0) 212 * 213 * These two registers set the byte counts of the packet to be 214 * transmitted. 215 */ 216 register tbcr wo also page0( 0x5 ) "Transmit Byte Count" type(uint16); 217 218 /* 219 * NCR: Number of Collisions Register (05H; Type=R in Page0) 220 * 221 * The register records the number of collisions a node experiences 222 * during a packet transmission. 223 */ 224 register ncr ro page0( 0x5 ) "Number of Collisions" type(uint8); 225 226 /* 227 * FIFO: First In First Out Register (06H; Type=R in Page0) 228 * 229 * This register allows the host to examine the contents of the FIFO 230 * after loopback. 231 */ 232 register fifo ro page0( 0x6 ) "FIFO" type(uint8); 233 234 /* 235 * CRDA0,1: Current Remote DMA Address registers (08H & 09H; 236 * Type=R in Page0) 237 * 238 * These two registers contain the current address of remote 239 * DMA. 240 */ 241 register crda ro page0( 0x8 ) "Current Remote DMA Address" type(uint16); 242 243 /* 244 * RSAR0,1: Remote Start Address Registers (08H & 09H; Type=W in Page0) 245 * 246 * These two registers set the start address of remote DMA. 247 */ 248 register rsar wo also page0( 0x8 ) "Remote Start Address" type(uint16); 249 250 /* 251 * RBCR0,1: Remote Byte Count Registers (0AH & 0BH; Type=W in Page0) 252 * 253 * These two registers set the data byte counts of remote DMA. 254 */ 255 register rbcr wo also page0( 0xa ) "Remote Byte Count" type(uint16); 256 257 /* 258 * CNTR0: Frame Alignment Error Tally Counter Register (0DH; 259 * Type=R in Page0) 260 */ 261 register cntr0 ro page0( 0xd ) "Frame Alignment Error Tally Counter" type(uint8); 262 263 /* 264 * CNTR1: CRC Error Tally Counter Register (0EH; Type=R in Page0) 265 */ 266 register cntr1 ro page0( 0xe ) "CRC Error Tally Counter" type(uint8); 267 268 /* 269 * CNTR2: Missed Packet Tally Counter Register (0FH; Type=R in 270 * Page0) 271 */ 272 register cntr2 ro page0( 0xf ) "Missed Packet Tally Counter" type(uint8); 273 274 /* 275 * PAR0-5: Physical Address Registers (01H - 06H; Type=R/W in Page1) 276 * 277 * These registers contain my Ethernet node address and are used 278 * to compare the destination address of incoming packets for 279 * acceptation or rejection. 280 */ 281 regarray par rw page1( 0x1 )[6] "Physical Address" type(uint8); 282 283 /* 284 * CURR: Current Page Register (07H; Type=R/W in Page1) 285 * 286 * This register points to the page address of the first receive 287 * buffer page to be used for a packet reception. 288 */ 289 register curr rw page1 ( 0x7 ) "Current Page" type(uint8); 290 291 /* 292 * MAR0-7: Multicast Address Register (08H - 0FH; Type=R/W in 293 * Page1) 294 * 295 * These registers provide filtering bits of multicast addresses 296 * hashed by the CRC logic. 297 */ 298 regarray mar rw page1( 0x8 )[8] "Multicast Address" type(uint8); 299 300 /* 301 * 5.1.2.2. RTL8029AS Defined Registers 302 */ 303 304 /* 305 * Page 0 (PS1=0, PS0=0) 306 * 307 * Two registers are defined to contain the RTL8029AS chip ID and 308 * Read Sequence Command is NO LONGER supported in RTL8029AS. 309 * 310 * Address 0x0a reads ASCII "P", address 0x0b reads ASCII "C". 311 */ 312 regarray chipid ro page0( 0xa )[2] "RTL8029AS Chip ID" type(uint8); 313 314 /* 315 * Page 3 (PS1=1, PS0=1). 316 */ 317 318 constants mode "RTL8029AS operating mode" { 319 opnormal = 0b00 "Normal (DP8390 compatible)"; 320 autoload = 0b01 "Auto-load 9346"; 321 programming = 0b10 "9346 programming"; 322 configwrite = 0b11 "Config register write enable"; 323 }; 324 325 /* 9346CR: 9346 Command Register (01H; Type=R/W except Bit0=R) */ 326 register cr9346 rw also rtlp( 0x1 ) "9346 Command" { 327 eedo 1; 328 eedi 1; 329 eesk 1; 330 eecs 1; 331 _ 2; 332 eem 2 type(mode) "RTL8029AS operating mode"; 333 }; 334 335 /* CONFIG0: RTL8029AS Configuration Register 0 (03H; Type=R) */ 336 register config0 ro rtlp( 0x3 ) "RTL8029AS Configuration 0" { 337 _ 2 mbz; 338 bnc 1 "10Base2 thin cable connected"; 339 _ 5; 340 }; 341 342 constants bromsize "Boot ROM Size" { 343 nobrom = 0b00 "No Boot ROM"; 344 size8k = 0b01 "8K Boot ROM"; 345 size16k = 0b10 "16K Boot ROM"; 346 size32k = 0b11 "32K Boot ROM"; 347 }; 348 349 constants medium "Network Medium" { 350 auto = 0b00 "TP/CX auto-detect"; 351 tenbaset = 0b01 "10BaseT"; 352 tenbase5 = 0b10 "10Base5"; 353 tenbase2 = 0b11 "10Base2"; 354 }; 355 356 /* 357 * CONFIG2: RTL8029AS Configuration Register 2 (05H; Type=R except 358 * Bit[7:5]=R/W) 359 */ 360 register config2 rtlp( 0x5 ) "RTL8029AS Configuration 2" { 361 bs 2 ro type(bromsize) "Boot ROM size"; 362 _ 2; 363 pf 1 ro "Pause flag"; 364 fce 1 rw "Flow control enable"; 365 pl 2 rw type(medium) "Network medium select"; 366 }; 367 368 constants leds "LED Control" { 369 rxcol = 0b00 "RX and COL"; 370 rxlink = 0b01 "RX and LINK"; 371 crscol = 0b10 "CRS and COL"; 372 crslink = 0b11 "CRS and LINK"; 373 }; 374 375 /* 376 * CONFIG3: RTL8029AS Configuration Register 3 (06H; Type=R except 377 * Bit[6,2:1]=R/W) 378 */ 379 register config3 rw rtlp( 0x6 ) "RTL8029AS Configuration 3" { 380 _ 1; 381 pwrdn 1 "Power down mode"; 382 sleep 1 "Sleep mode"; 383 _ 1 mbz; 384 leds 2 type(leds) "LED control"; 385 fudup 1 "Full-duplex mode"; 386 _ 1; 387 }; 388 389 constants clock "Halt Clock Mode" { 390 running = 0x52 "Running"; /* ASCII code of 'R' */ 391 halted = 0x48 "Halted"; /* ASCII code of 'H' */ 392 }; 393 394 /* 395 * HLTCLK: Halt Clock Register (09H; Type=W) 396 * 397 * This is the only active one of Group1 registers when RTL8029AS 398 * is inactivated. Writing to this register is invalid if 399 * RTL8029AS is not in power down mode. (i.e., If PWRDN bit in 400 * CONFIG3 register is zero.) The data written to this register 401 * determines the RTL8029AS's power down mode. 402 */ 403 register hltclk wo rtlp( 0x9 ) "Halt Clock" type(uint8); 404 405 /* 8029ASID0,1: RTL8029AS ID = 8029H (0E,0FH; Type=R) */ 406 register asid ro rtlp( 0xe ) "8029AS ID" type(uint16); 407 408 /* 409 * 6.2.2 ID PROM Contents 410 * 411 * The RTL8029AS emulates the ID PROM of NE2000 internally. After 412 * 9346 is loaded, the contents of ID PROM are as follows. 413 * 414 * offset Byte contents 415 * ------ ------------- 416 * 00H Ethernet ID0 417 * 01H Ethernet ID1 418 * 02H Ethernet ID2 419 * 03H Ethernet ID3 420 * 04H Ethernet ID4 421 * 05H Ethernet ID5 422 * 06H PID0 423 * 07H PID1 424 * 08H PID2 425 * 09H PID3 426 * 0AH PID4 427 * 0BH PID5 428 * 0CH PID6 429 * 0DH PID7 430 * 0EH 57 (ASCII Code of "W") 431 * 0FH 57 (ASCII Code of "W") 432 * 10H Ethernet ID0 433 * 11H Ethernet ID1 434 * 12H Ethernet ID2 435 * 13H Ethernet ID3 436 * 14H Ethernet ID4 437 * 15H Ethernet ID5 438 * 16H PID0 439 * 17H PID1 440 * 18H PID2 441 * 19H PID3 442 * 1AH PID4 443 * 1BH PID5 444 * 1CH PID6 445 * 1DH PID7 446 * 1EH 42 (ASCII Code of "B") 447 * 1FH 42 (ASCII Code of "B") 448 */ 449 450 /* 451 * Remote DMA Port (10H - 17H) 452 * 453 * 454 * The ID PROM and Ethernet packet RAM contents can be read using 455 * these registers. Set the start address in RSAR and amount of 456 * bytes to transfer in RBCR. 457 * 458 * RAM start is at offset 0x4000. 459 */ 460 /* 461 regarray rdma rw rtlp( 0x10 )[8] "Remote DMA 0" type(uint8); 462 */ 463 register rdma32 rw rtlp( 0x10 ) "Remote DMA 32-bit" type(uint32); 464 register rdma16 rw also rtlp( 0x10 ) "Remote DMA 16-bit" type(uint16); 465 register rdma8 rw also rtlp( 0x10 ) "Remote DMA 8-bit" type(uint8); 466 467 /* 468 * Reset Port 469 * 470 * Ports in the range 0x18 - 0x1f are reset ports. We only index the 471 * last one here as the others are not used on QEMU. 472 * 473 * Reading from the reset port causes the card to be reset. 474 */ 475 register reset rc rtlp( 0x1f ) "Reset" type(uint8); 476}; 477