1/* 2 * Copyright (c) 2012, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr 6, CH-8092 Zurich. 7 * Attn: Systems Group. 8 */ 9 10/* 11 * pl390_gic.dev 12 * 13 * DESCRIPTION: PrimeCell PL390 Generic Interrupt Controller 14 * 15 * This is derived from: 16 * 17 * [1] PrimeCell Generic Interrupt Controller PL390 18 * (DDI0416B_gic_pl390_r0p0_trm.pdf) 19 * [2] ARM Cortex A9 MPCore TRM r2p0 20 * [3] ARM Generic Interrupt Controller v1.0 21 * 22 * Updated to work on PandaBoard according to [2] Table 3-1 23 * 24 * Register map for distributor: [3], chp 4.1.2 25 * Register map for CPU interface: [3], chp 4.1.3 26 */ 27 28device pl390_gic_dist msbfirst (addr dist_base) 29 "PrimeCell PL390 Generic Interrupt Controller Distributor" 30{ 31 // 32 // Distributor register map 33 // 34 register ICDDCR addr(dist_base, 0x0) "Distributor Control" { 35 _ 31 rsvd; 36 enable 1 rw "enable forwarding to CPU interface"; 37 }; 38 39 register ICDICTR ro addr(dist_base, 0x4) "Interrupt Controller Type" { 40 _ 16; 41 LSPI 5 "maximum number of lockable SPIs"; 42 TZ 1 "GIC implements Security Extensions"; 43 _ 2; 44 cpu_number 3 "number of implemented CPU interfaces"; 45 it_lines_num 5 "max. num. (N) interrupts supported 32(N+1)"; 46 }; 47 48 register ICDIIDR ro addr(dist_base, 0x8) "Distributor Implementer Ident." { 49 product_id 8 "Product identifier"; 50 rev_num 12 "Revision number"; 51 implementer 12 "JEP106 code of implementing company"; 52 }; 53 54 // Do not read 16 Bit values, only 32 bit ones, otherwise the 55 // Mackerel code will crash on the PandaBoard 56 regarray ICDISR addr(dist_base, 0x80) [32] "SPI Interrupt Security" 57 type(uint32); 58 regarray ICDISER addr(dist_base, 0x100) [32] "Interrupt Set-Enable" 59 type(uint32); 60 regarray ICDICER addr(dist_base, 0x180) [32] "Interrupt Clear-Enable" 61 type(uint32); 62 regarray ICDISPR addr(dist_base, 0x200) [32] "Interrupt Set-Pending" 63 type(uint32); 64 regarray ICDICPR addr(dist_base, 0x280) [32] "Interrupt Clear-Pending" 65 type(uint32); 66 regarray ICDABR ro addr(dist_base, 0x300) [32] "Interrupt Active Bit" 67 type(uint32); 68 69 regtype priority_reg "Interrupt priority register" { 70 prio_off3 8 rw "Priority, byte offset 3"; 71 prio_off2 8 rw "Priority, byte offset 2"; 72 prio_off1 8 rw "Priority, byte offset 1"; 73 prio_off0 8 rw "Priority, byte offset 0"; 74 }; 75 76 regarray ICDIPR addr(dist_base, 0x400) [31] "Priority Level" 77 type(priority_reg); 78 79 regtype cpu_targets_reg "CPU targets" { 80 targets_off3 8 rw "CPU targets, byte offset 3"; 81 targets_off2 8 rw "CPU targets, byte offset 2"; 82 targets_off1 8 rw "CPU targets, byte offset 1"; 83 targets_off0 8 rw "CPU targets, byte offset 0"; 84 }; 85 regarray ICDIPTR rw addr(dist_base, 0x800) [31] // only partly rw 86 "Interrupt Processor Targets" 87 type(cpu_targets_reg); 88 89 regtype conf_reg "Configuration registers" { 90 conf15 2 "Configuration 15"; 91 conf14 2 "Configuration 14"; 92 conf13 2 "Configuration 13"; 93 conf12 2 "Configuration 12"; 94 conf11 2 "Configuration 11"; 95 conf10 2 "Configuration 10"; 96 conf9 2 "Configuration 9"; 97 conf8 2 "Configuration 8"; 98 conf7 2 "Configuration 7"; 99 conf6 2 "Configuration 6"; 100 conf5 2 "Configuration 5"; 101 conf4 2 "Configuration 4"; 102 conf3 2 "Configuration 3"; 103 conf2 2 "Configuration 2"; 104 conf1 2 "Configuration 1"; 105 conf0 2 "Configuration 0"; 106 }; 107 regarray ICDICR rw addr(dist_base, 0xC00) [16] 108 "Interrupt Configuration Reigsters" 109 type(conf_reg); 110 111 register PPI_STATUS ro addr(dist_base, 0xd00) "PPI Status" { 112 _ 16; 113 ppi_status 16 "Status of PPI0 - PPI15"; 114 }; 115 116 regarray SPI_STATUS ro addr(dist_base, 0xd04) [30] "SPI Status" 117 type(uint32); 118 119 register ICDSGIR wo addr(dist_base, 0xf00) "Software Generated Interrupt" { 120 _ 6 mbz; 121 target_list_filter 2 "Target List Filter"; 122 cpu_target_list 8 "CPU Target List"; 123 SATT 1 "Secure Access Bit"; 124 _ 11 mbz; 125 SGIINTID 4 "SGI Interrupt ID"; 126 }; 127 128 register DIST_PERIPH_ID0 ro addr(dist_base, 0xfec) "Peripheral Ident. 0" { 129 _ 24; 130 part_number_0 8 "Part Number 0"; 131 }; 132 133 register DIST_PERIPH_ID1 ro addr(dist_base, 0xfe8) "Peripheral Ident. 1" { 134 _ 24; 135 jep106_id_3_0 4 "JEP106 identity code [3:0]"; 136 part_number_1 4 "Part Number 1"; 137 }; 138 139 register DIST_PERIPH_ID2 ro addr(dist_base, 0xfe4) "Peripheral Ident. 2" { 140 _ 24; 141 architecure 4 "Architecture vers. of GIC"; 142 jedec_used 1 "is ID allocated by JEDEC"; 143 jep106_id_6_4 3 "JEP106 identity code [6:4]"; 144 }; 145 146 register DIST_PERIPH_ID3 ro addr(dist_base, 0xfe0) "Peripheral Ident. 3" { 147 _ 24; 148 rev_and 4 "Revision of AND Gates"; 149 mod_number 4 "Modification Number"; 150 }; 151 152 register DIST_PERIPH_ID4 ro addr(dist_base, 0xfdc) "Peripheral Ident. 4" { 153 _ 24; 154 page_count 4 "# of 4KB blocks needed"; 155 jep106_c_code 4 "JEP106 continuation code"; 156 }; 157 158 register DIST_PERIPH_ID5 ro addr(dist_base, 0xfd8) "Peripheral Ident. 5" { 159 _ 24; 160 ppi_number_0 4 "LSBs of # of PPIs in FIC"; 161 sgi_number 4 "# of SGIs in GIC"; 162 }; 163 164 register DIST_PERIPH_ID6 ro addr(dist_base, 0xfd4) "Peripheral Ident. 6" { 165 _ 24; 166 spi_number_0 4 "LSBs of #SPIs GIC provides"; 167 ppi_number_1 4 "MSBs of #PPIs GIC provides"; 168 }; 169 170 register DIST_PERIPH_ID7 ro addr(dist_base, 0xfd0) "Peripheral Ident. 7" { 171 _ 24; 172 tz 1 "# secure states"; 173 priority 3 "# priority lvls GIC provides"; 174 spi_number_1 4 "MSBs of # SPIs GIC provides"; 175 }; 176 177 register DIST_PERIPH_ID8 ro addr(dist_base, 0xfc0) "Peripheral Ident. 8" { 178 _ 24; 179 identifier 1 "AMBA interface ID"; 180 if_type 2 "AMBA protocoll"; 181 cpu_if 3 "# of CPU interfaces"; 182 fiq_legacy 1 "Legacy FIQ signals supported"; 183 irq_legacy 1 "Legacy IRQ signals supported"; 184 }; 185 186 register DIST_COMPONENT_ID0 ro addr(dist_base, 0xffc) "PrimeCell Ident. 0" { 187 _ 24; 188 component_id 8; 189 }; 190 191 register DIST_COMPONENT_ID1 ro addr(dist_base, 0xff8) "PrimeCell Ident. 1" { 192 _ 24; 193 component_id 8; 194 }; 195 196 register DIST_COMPONENT_ID2 ro addr(dist_base, 0xff4) "PrimeCell Ident. 2" { 197 _ 24; 198 component_id 8; 199 }; 200 201 register DIST_COMPONENT_ID3 ro addr(dist_base, 0xff0) "PrimeCell Ident. 3" { 202 _ 24; 203 component_id 8; 204 }; 205}; 206