1/* 2 * Copyright (c) 2008, ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group. 7 */ 8 9/* 10 * pci_hdr1.dev 11 * 12 * DESCRIPTION: PCI Type 1 Configuration header 13 * 14 */ 15 16device pci_hdr1 msbfirst ( pci base ) "PCI Type 1 Configuration" { 17 18 register vendor_id ro pci( base, 0x00 ) "Vendor ID" type(uint16); 19 register device_id ro pci( base, 0x02 ) "Device ID" type(uint16); 20 21 register command rw pci( base, 0x04 ) "Command" { 22 _ 5; 23 int_dis 1 rw "Interrupt disable"; 24 back2back 1 ro "Fast back-to-back enable"; 25 serr 1 rw "SERR# enable"; 26 stepping 1 ro "IDSEL stepping/wait cycle control"; 27 parity 1 rw "Parity error response"; 28 vga_snoop 1 ro "VGA palette snoop enable"; 29 mem_inval 1 ro "Memory write and invalidate enable"; 30 special 1 ro "Special cycles"; 31 master 1 rw "Bus master"; 32 mem_space 1 rw "Memory space enable"; 33 io_space 1 rw "I/O space enable"; 34 }; 35 36 regtype statreg "Interface status" { 37 parity_err 1 rwc "Detected parity error"; 38 system_err 1 rwc "Signalled system error"; 39 rx_m_abrt 1 rwc "Received master abort"; 40 rx_t_abrt 1 rwc "Received target abort"; 41 sig_t_abrt 1 rwc "Signalled target abort"; 42 devsel 2 ro "DEVSEL timing"; 43 md_parity 1 rwc "Master data parity error"; 44 back2back 1 ro "Fast Back-to-Back enable"; 45 udf 1 ro "UDF supported"; 46 m66 1 ro "66MHz capable"; 47 caplist 1 ro "Capabilities list"; 48 intstat 1 ro "Interrupt status"; 49 _ 3; 50 }; 51 52 register status pci( base, 0x06 ) "Status" type(statreg); 53 register sec_stat pci (base, 0x1e) "Secondary status" type(statreg); 54 55 // 56 // Revision ID and Class code fall in the same 32-bit space. We 57 // allow access to the Revision ID as an 8-bit value, and the Class 58 // Code as a 32-bit value with the bottom 8 bits reserved, but we 59 // could I suppose combine them all into one register. 60 // 61 62 register rev_id ro pci( base, 0x08 ) "Revision ID" type(uint8); 63 64 constants classcode "Class code" { 65 bridge = 0x06 "Bridge device"; 66 }; 67 68 register class_code ro also pci( base, 0x08 ) "Class code" { 69 clss 8 type(classcode) "Class code"; 70 subclss 8 "Subclass code"; 71 prog_if 8 "Programming intf"; 72 _ 8; 73 }; 74 75 register cache_sz rw pci( base, 0x0c ) "Cache line size" type(uint8); 76 register latency rw pci( base, 0x0d ) "Master latency timer" type(uint8); 77 78 // 79 // Important stuff: whether this is actually a Type-0 header at 80 // all. This is currently duplicated into the Type-1 definition - 81 // when Mackerel gets a module system we can break this out into 82 // other files. 83 // 84 constants hdrtype "Configuration header types" { 85 nonbridge = 0 "non-bridge function"; 86 pci2pci = 1 "PCI-to-PCI bridge"; 87 cardbus = 2 "CardBus bridge"; 88 }; 89 90 register hdr_type ro pci( base, 0x0e ) "Header type" { 91 multi 1 "Multifunction device"; 92 fmt 7 type(hdrtype) "Configuration header format"; 93 }; 94 95 register bist pci( base, 0x0f ) "Built-in self-test" { 96 cap 1 ro "BIST capable"; 97 start 1 rw "Start BIST"; 98 _ 2; 99 comp 4 ro "Completion code"; 100 }; 101 102 // 103 // Base-Address registers. These are problematic for Mackerel, 104 // since you don't know exactly what the register is (32, 64, or IO) 105 // until you read it. And only then do you know where the next one 106 // might be. This is beyond Mackerel, and in all honesty probably 107 // should stay that way. 108 // 109 // As a compromise we define register types for each BAR, and give 110 // the BAR block as simply a set of 6 32-bit registers. PCI 111 // enumeration code can do the rest. 112 // 113 constants bardecoder "BAR decoder type" { 114 bar_32bit = 0b00 "32-bit decoder"; 115 bar_64bit = 0b10 "64-bit decoder"; 116 }; 117 118 regtype bar32 "32-bit memory base address" { 119 base 25 rw "Base address"; 120 _ 3; 121 prefetch 1 ro "Prefetchable"; 122 tpe 2 ro type(bardecoder) "Memory decoder type"; 123 space 1 ro "Memory space indicator"; 124 }; 125 regtype bar64 "64-bit memory base address" { 126 base 57 rw "Base address"; 127 _ 3; 128 prefetch 1 ro "Prefetchable"; 129 tpe 2 ro type(bardecoder) "Memory decoder type"; 130 space 1 ro "Memory space indicator"; 131 }; 132 regtype bario "I/O space base address" { 133 base 30 rw "Base address"; 134 _ 1; 135 space 1 ro "I/O space indicator"; 136 }; 137 138 register bar0 pci ( base, 0x10 ) "Base address 0" type(uint32); 139 register bar1 pci ( base, 0x14 ) "Base address 1" type(uint32); 140 141 register bcfg pci (base, 0x18) "Bus configuration register" { 142 sec_lat 8 "Secondary latency timer"; 143 sub_bus 8 "Subordinate bus number"; 144 sec_bus 8 "Secondary bus number"; 145 pri_bus 8 "Primary bus number"; 146 }; 147 148 // 149 // I/O base and limit registers 150 // 151 constants iobl_decode "I/O Base and limit decode type" { 152 io_16bit = 0b00 "16-bit I/O decode"; 153 io_32bit = 0b01 "32-bit I/O decode"; 154 }; 155 regtype iobl "I/O Base and limit" { 156 val 4 rw "Low bits of address"; 157 tpe 4 ro type(iobl_decode) "Decode type"; 158 }; 159 160 register io_base pci (base, 0x1c) "I/O base" type(iobl); 161 register io_limit pci (base, 0x1d) "I/O limit" type(iobl); 162 register io_base_upper pci (base, 0x30) "I/O base upper 16b" type(uint16); 163 register io_limit_upper pci (base, 0x32) "I/O limit upper 16b" type(uint16); 164 165 // 166 // Memory-mapped I/O base and limit registers 167 // 168 169 register membl pci (base, 0x20) "Memory base and limit" { 170 limit 16 "Limit"; 171 base 16 "Base"; 172 }; 173 174 // 175 // Prefetchable memory base and limit registers 176 // 177 constants pref_decode "Prefetchable memory base and limit decode type" { 178 mem_32bit = 0b00 "32-bit memory decode"; 179 mem_64bit = 0b01 "64-bit memory decode"; 180 }; 181 regtype prefbl "Prefetchable memory base and limit" { 182 val 12 rw "Low bits of address"; 183 tpe 4 ro type(iobl_decode) "Decode type"; 184 }; 185 register pref_base pci (base, 0x24) "Prefetchable memory base" type(prefbl); 186 register pref_limit pci (base, 0x26) "Prefetchable memory limit" type(prefbl); 187 register pref_base_upper pci (base, 0x28) "Prefetch base upper 32b" type(uint32); 188 register pref_limit_upper pci (base, 0x2C) "Prefetch limit upper 32b" type(uint32); 189 190 register cap_ptr ro pci(base, 0x34) "Capabilities ptr" type(uint8); 191 192 register rom_base rw pci(base, 0x38) "Expansion ROM base addr" { 193 base 21 "ROM Base address high bits"; 194 _ 10; 195 enable 1 "ROM address decoder enable"; 196 }; 197 198 register int_line rw pci(base, 0x3c) "Interrupt line" type(uint8); 199 register int_pin ro pci(base, 0x3d) "Interrupt ping" type(uint8); 200 201 register brdg_ctrl pci(base, 0x3e) "Bridge control" { 202 _ 4; 203 serr_dis 1 ro "Discard timer SERR# enable"; 204 tstat_dis 1 ro "Discard timer status"; 205 sectm_dis 1 ro "Secondary discard timeout"; 206 pritm_dis 1 ro "Primary discard timeout"; 207 back2back 1 ro "Fast back-to-back enable"; 208 sec_reset 1 rw "Secondary bus reset"; 209 mabort 1 rw "Master abort mode"; 210 _ 1; 211 vga 1 rw "VGA enable"; 212 isa 1 rw "ISA enable"; 213 serr_en 1 rw "SERR# enable"; 214 parity 1 rw "Parity error response"; 215 }; 216 217}; 218 219 220