1/*
2 * Copyright (c) 2007, 2008, ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, Universitaetstrasse 6, CH-8092 Zurich. Attn: Systems Group.
7 */
8
9/*
10 * pc16550d_uart.dev
11 *
12 * DESCRIPTION: PC16550D Universal Asynchronous Receiver Transmitter
13 *              with FIFOs
14 *
15 * This is derived from the IC specification white paper from National
16 * Semiconductor (TL/C/8652 and RRD-B30M75).
17 */
18
19device pc16550d lsbfirst ( io base ) "PC16550D UART" {
20  constants trigger_lvl "RCVR FIFO trigger level" {
21    bytes1  = 0b00      "Every byte";
22    bytes4  = 0b01      "Every 4th byte";
23    bytes8  = 0b10      "Every 8th byte";
24    bytes14 = 0b11      "Every 14th byte";
25  };
26
27  constants char_len "Character Length" {
28    bits5   = 0b00   "5 Bits";
29    bits6   = 0b01   "6 Bits";
30    bits7   = 0b10   "7 Bits";
31    bits8   = 0b11   "8 Bits";
32  };
33
34  constants irq_id "Interrupt ID" {
35    none    = 0b0001          "No interrupt pending";
36    rls     = 0b0110          "Receiver line status";
37    rda     = 0b0100          "Receiver data available";
38    cti     = 0b1100          "Character timeout";
39    thre    = 0b0010          "Transmitter holding register empty";
40    ms      = 0b0000          "Modem status";
41  };
42
43  constants divisor "Baud Rate Divisor" {
44    baud50          = 2304     "50 bps";
45    baud75          = 1536     "75 bps";
46    baud110         = 1047     "110 bps";
47    baud134_5       = 857      "134.5 bps";
48    baud150         = 768      "150 bps";
49    baud300         = 384      "300 bps";
50    baud600         = 192      "600 bps";
51    baud1200        = 96       "1200 bps";
52    baud1800        = 64       "1800 bps";
53    baud2000        = 58       "2000 bps";
54    baud2400        = 48       "2400 bps";
55    baud4800        = 24       "4800 bps";
56    baud7200        = 16       "7200 bps";
57    baud9600        = 12       "9600 bps";
58    baud19200       = 6        "19200 bps";
59    baud38400       = 3        "38400 bps";
60    baud57600       = 2        "57600 bps";
61    baud115200      = 1        "115200 bps";
62  };
63
64  register rbr ro io( base, 0x0 ) "Receiver buffer" type(uint8);
65  register thr wo also io( base , 0x0 ) "Transmitter holding" type(uint8);
66
67  register ier rw io ( base, 0x1 ) "Interrupt enable" {
68    erbfi         1  "Enable received data available interrupt";
69    etbei         1  "Enable transmitter holding register empty interrupt";
70    elsi          1  "Enable receiver line status interrupt";
71    edssi         1  "Enable modem status interrupt";
72    _             4  mbz;
73  };
74
75  register iir ro io ( base, 0x2 ) "Interrupt identification" {
76    iid           4  type(irq_id) "Interrupt ID";
77    _             2  mbz;
78    fifoe         2  "FIFOs enabled";
79  };
80
81  register fcr wo also io ( base, 0x2 ) "FIFO control" {
82    fifoe         1  "FIFO enable";
83    rfifo_reset   1  "RCVR FIFO reset";
84    xfifo_reset   1  "XMIT FIFO reset";
85    dma_mode      1  "DMA mode select";
86    _             2;
87    rtrigger      2  type(trigger_lvl)  "RCVR trigger";
88  };
89
90  register lcr rw io ( base, 0x3 ) "Line control" {
91    wls           2  type(char_len) "Word length select";
92    stb           1  "Number of stop bits";
93    pen           1  "Parity enable";
94    eps           1  "Even parity select";
95    sp            1  "Stick parity";
96    sb            1  "Set break";
97    dlab          1  "Divisor latch access";
98  };
99
100  register mcr rw io ( base, 0x4 ) "Modem control" {
101    dtr           1  "Data terminal ready";
102    rts           1  "Request to send";
103    out           2  "Out";
104    loop          1  "Loop";
105    _             3  mbz;
106  };
107
108  register lsr rw io ( base, 0x5 ) "Line status" {
109    dr            1  "Data ready";
110    oe            1  "Overrun error";
111    pe            1  "Parity error";
112    fe            1  "Framing error";
113    bi            1  "Break interrupt";
114    thre          1  "Transmitter holding register";
115    temt          1  "Transmitter empty";
116    erfifo        1  "Error in RCVR FIFO";
117  };
118
119  register msr rw io ( base, 0x6 ) "Modem status" {
120    dcts          1  "Delta clear to send";
121    ddsr          1  "Delta data set ready";
122    teri          1  "Trailing edge ring indicator";
123    ddcd          1  "Delta data carrier detect";
124    cts           1  "Clear to send";
125    dsr           1  "Data set ready";
126    ri            1  "Ring indicator";
127    dcd           1  "Data carrier detect";
128  };
129
130  register scr ro io( base , 0x7 ) "Scratch register" type(uint8);
131  register dl rw also io( base , 0x0 ) "Divisor latch" type(uint16);
132};
133