1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_wdtimer3_dsp.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_wdtimer3_dsp msbfirst ( addr base ) "" { 29 30 31 register wdt_widr ro addr(base, 0x0) "IP revision identifier" type(uint32); 32 33 constants emufree_status width(1) "" { 34 EMUFREE_0 = 0 "Timer counter frozen in emulation"; 35 EMUFREE_1 = 1 "Timer counter free-running in emulation"; 36 }; 37 38 constants idlemode_status width(2) "" { 39 IDLEMODE_0 = 0 "Force-idle mode: local target IDLE state follows (acknowledges) the system idle requests unconditionally, that is, regardless of the IP module internal requirements. Backup mode, for debug only."; 40 IDLEMODE_1 = 1 "No-idle mode: local target never enters IDLE state. Backup mode, for debug only."; 41 IDLEMODE_2 = 2 "Smart-idle mode: local target IDLE state eventually follows (acknowledges) the system idle requests, depending on the IP module internal requirements. IP module should not generate (IRQ- or DMA-request-related) wake-up events."; 42 IDLEMODE_3 = 3 "Smart-idle wake-up-capable mode: local target IDLE state eventually follows (acknowledges) the system idle requests, depending on the IP module internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP moduleswake-up output(s) is (are) implemented."; 43 }; 44 45 constants softreset_status width(1) "" { 46 SOFTRESET_0_r = 0 "Reset done, no pending action"; 47 SOFTRESET_0_w = 0 "No action"; 48 SOFTRESET_1_w = 1 "Initiate software reset."; 49 SOFTRESET_1_r = 1 "Reset (software or other) ongoing"; 50 }; 51 52 register wdt_wdsc addr(base, 0x10) "This register controls the various parameters of the L4 interface." { 53 _ 26 mbz; 54 emufree 1 rw type(emufree_status) "Emulation mode"; 55 idlemode 2 rw type(idlemode_status) "Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state."; 56 _ 1 mbz; 57 softreset 1 rw type(softreset_status) "Software reset. (Optional)"; 58 _ 1 mbz; 59 }; 60 61 constants resetdone_status width(1) "" { 62 RESETDONE_0_r = 0 "Internal module reset is ongoing."; 63 RESETDONE_1_r = 1 "Reset completed"; 64 }; 65 66 register wdt_wdst addr(base, 0x14) "This register provides status information about the module." { 67 _ 31 mbz; 68 resetdone 1 ro type(resetdone_status) "Internal module reset monitoring"; 69 }; 70 71 constants dly_it_flag_status width(1) "" { 72 DLY_IT_FLAG_0_r = 0 "No delay interrupt pending"; 73 DLY_IT_FLAG_0_w = 0 "Status unchanged"; 74 DLY_IT_FLAG_1_w = 1 "Status bit cleared"; 75 DLY_IT_FLAG_1_r = 1 "Delay interrupt pending"; 76 }; 77 78 constants ovf_it_flag_status width(1) "" { 79 OVF_IT_FLAG_0_r = 0 "No overflow interrupt pending"; 80 OVF_IT_FLAG_0_w = 0 "Status unchanged"; 81 OVF_IT_FLAG_1_w = 1 "Status bit cleared"; 82 OVF_IT_FLAG_1_r = 1 "Overflow interrupt pending"; 83 }; 84 85 register wdt_wisr addr(base, 0x18) "This register shows which interrupt events are pending inside the module." { 86 _ 30 mbz; 87 dly_it_flag 1 rw1c type(dly_it_flag_status) "Pending delay interrupt status."; 88 ovf_it_flag 1 rw1c type(ovf_it_flag_status) "Pending overflow interrupt status."; 89 }; 90 91 constants dly_it_ena_status width(1) "" { 92 DLY_IT_ENA_0 = 0 "Disable delay interrupt."; 93 DLY_IT_ENA_1 = 1 "Enable delay interrupt."; 94 }; 95 96 constants ovf_it_ena_status width(1) "" { 97 OVF_IT_ENA_0 = 0 "Disable overflow interrupt."; 98 OVF_IT_ENA_1 = 1 "Enable overflow interrupt."; 99 }; 100 101 register wdt_wier addr(base, 0x1C) "This register controls (enable/disable) the interrupt events." { 102 _ 30 mbz; 103 dly_it_ena 1 rw type(dly_it_ena_status) "Delay interrupt enable/disable"; 104 ovf_it_ena 1 rw type(ovf_it_ena_status) "Overflow interrupt enable/disable"; 105 }; 106 107 constants dly_wk_ena_status width(1) "" { 108 DLY_WK_ENA_0 = 0 "Disable delay wakeup."; 109 DLY_WK_ENA_1 = 1 "Enable delay wakeup."; 110 }; 111 112 constants ovf_wk_ena_status width(1) "" { 113 OVF_WK_ENA_0 = 0 "Disable overflow wakeup."; 114 OVF_WK_ENA_1 = 1 "Enable overflow wakeup."; 115 }; 116 117 register wdt_wwer addr(base, 0x20) "This register controls (enable/disable) the wake-up events." { 118 _ 30 mbz; 119 dly_wk_ena 1 rw type(dly_wk_ena_status) "Delay wake-up enable"; 120 ovf_wk_ena 1 rw type(ovf_wk_ena_status) "Overflow wake-up enable"; 121 }; 122 123 constants pre_status width(1) "" { 124 PRE_0 = 0 "Prescaler disabled"; 125 PRE_1 = 1 "Prescaler enabled"; 126 }; 127 128 register wdt_wclr addr(base, 0x24) "This register controls the prescaler stage of the counter." { 129 _ 26 mbz; 130 pre 1 rw type(pre_status) "Prescaler enable/disable configuration"; 131 ptv 3 rw "Prescaler value The timer counter is prescaled with the value: 2. Example: PTV = 3 -> counter increases value if started after 8 functional clock periods. On reset, it is loaded from PI_PTV_RESET_VALUE input port."; 132 _ 2 mbz; 133 }; 134 135 register wdt_wcrr rw addr(base, 0x28) "This register holds the value of the internal counter." type(uint32); 136 137 register wdt_wldr rw addr(base, 0x2C) "This register holds the timer load value." type(uint32); 138 139 register wdt_wtgr rw addr(base, 0x30) "Writing a different value than the one already written in this register does a watchdog counter reload." type(uint32); 140 141 constants w_pend_wdly_status width(1) "" { 142 W_PEND_WDLY_0_r = 0 "No register write pending"; 143 W_PEND_WDLY_1_r = 1 "Register write pending"; 144 }; 145 146 register wdt_wwps addr(base, 0x34) "This register contains the write posting bits for all writeable functional registers." { 147 _ 26 mbz; 148 w_pend_wdly 1 ro type(w_pend_wdly_status) "Write pending for register WDLY"; 149 w_pend_wspr 1 ro type(w_pend_wdly_status) "Write pending for register WSPR"; 150 w_pend_wtgr 1 ro type(w_pend_wdly_status) "Write pending for register WTGR"; 151 w_pend_wldr 1 ro type(w_pend_wdly_status) "Write pending for register WLDR"; 152 w_pend_wcrr 1 ro type(w_pend_wdly_status) "Write pending for register WCRR"; 153 w_pend_wclr 1 ro type(w_pend_wdly_status) "Write pending for register WCLR"; 154 }; 155 156 register wdt_wdly rw addr(base, 0x44) "This register holds the delay value that controls the internal pre-overflow event detection." type(uint32); 157 158 register wdt_wspr rw addr(base, 0x48) "This register holds the start-stop value that controls the internal start-stop FSM." type(uint32); 159 160 constants event_dly_status width(1) "" { 161 EVENT_DLY_0_r = 0 "No event pending"; 162 EVENT_DLY_0_w = 0 "No action"; 163 EVENT_DLY_1_w = 1 "Set event (debug)"; 164 EVENT_DLY_1_r = 1 "Event pending"; 165 }; 166 167 register wdt_wirqstatraw addr(base, 0x54) "IRQ unmasked status, status set per-event raw interrupt status vector, line 0. Raw status is set even if event is not enabled. Write 1 to set the (raw) status, mostly for debug." { 168 _ 30 mbz; 169 event_dly 1 rw type(event_dly_status) "Settable raw status for delay event"; 170 event_ovf 1 rw type(event_dly_status) "Settable raw status for overflow event"; 171 }; 172 173 constants event_dly_status1 width(1) "" { 174 EVENT_DLY_0_r_1 = 0 "No (enabled) event pending"; 175 EVENT_DLY_0_w_1 = 0 "No action"; 176 EVENT_DLY_1_w_1 = 1 "Clear (raw) event"; 177 EVENT_DLY_1_r_1 = 1 "Event pending"; 178 }; 179 180 register wdt_wirqstat addr(base, 0x58) "IRQ masked status, status clear per-event enabled interrupt status vector, line 0. Enabled status is not set unless event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled)." { 181 _ 30 mbz; 182 event_dly 1 rw1c type(event_dly_status1) "Clearable, enabled status for delay event"; 183 event_ovf 1 rw1c type(event_dly_status1) "Clearable, enabled status for overflow event"; 184 }; 185 186 constants enable_dly_status width(1) "" { 187 ENABLE_DLY_0_r = 0 "Interrupt disabled (masked)"; 188 ENABLE_DLY_0_w = 0 "No action"; 189 ENABLE_DLY_1_w = 1 "Enable interrupt."; 190 ENABLE_DLY_1_r = 1 "Interrupt enabled"; 191 }; 192 193 register wdt_wirqenset addr(base, 0x5C) "IRQ enable set per-event interrupt enable bit vector, line 0. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register." { 194 _ 30 mbz; 195 enable_dly 1 rw type(enable_dly_status) "Enable for delay event"; 196 enable_ovf 1 rw type(enable_dly_status) "Enable for overflow event"; 197 }; 198 199 constants enable_dly_status1 width(1) "" { 200 ENABLE_DLY_0_r_1 = 0 "Interrupt disabled (masked)"; 201 ENABLE_DLY_0_w_1 = 0 "No action"; 202 ENABLE_DLY_1_w_1 = 1 "Disable interrupt."; 203 ENABLE_DLY_1_r_1 = 1 "Interrupt enabled"; 204 }; 205 206 register wdt_wirqenclr addr(base, 0x60) "IRQ enable clear per-event interrupt enable bit vector, line 0. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register." { 207 _ 30 mbz; 208 enable_dly 1 rw1c type(enable_dly_status1) "Enable for delay event"; 209 enable_ovf 1 rw1c type(enable_dly_status1) "Enable for overflow event"; 210 }; 211 212 constants dly_wk_ena_status1 width(1) "" { 213 DLY_WK_ENA_0_1 = 0 "Disable delay wakeup"; 214 DLY_WK_ENA_1_1 = 1 "Enable delay wakeup"; 215 }; 216 217 constants ovf_wk_ena_status1 width(1) "" { 218 OVF_WK_ENA_0_1 = 0 "Disable overflow wakeup"; 219 OVF_WK_ENA_1_1 = 1 "Enable overflow wakeup"; 220 }; 221 222 register wdt_wirqwakeen addr(base, 0x64) "This register controls (enable/disable) the wake-up events." { 223 _ 30 mbz; 224 dly_wk_ena 1 rw type(dly_wk_ena_status1) "Enable delay wake-up"; 225 ovf_wk_ena 1 rw type(ovf_wk_ena_status1) "Enable overflow wakeup"; 226 }; 227};