1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_usbtllhs_ulpi.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_usbtllhs_ulpi msbfirst ( addr base ) "" { 29 30 31 register vendor_id_lo_i_0 ro addr(base, 0x0) "Lower byte of USB-IF-supplied 16-bit vendor ID Value is set for all channels. Default is Texas Instruments Vendor ID = 0x0451." type(uint8); 32 33 register vendor_id_lo_i_1 ro addr(base, 0x100) "Lower byte of USB-IF-supplied 16-bit vendor ID Value is set for all channels. Default is Texas Instruments Vendor ID = 0x0451." type(uint8); 34 35 register vendor_id_hi_i_0 ro addr(base, 0x1) "Upper byte of USB-IF-supplied 16-bit vendor ID Value is set for all channels. Default is Texas-Instruments Vendor ID = 0x0451." type(uint8); 36 37 register vendor_id_hi_i_1 ro addr(base, 0x101) "Upper byte of USB-IF-supplied 16-bit vendor ID Value is set for all channels. Default is Texas-Instruments Vendor ID = 0x0451." type(uint8); 38 39 register product_id_lo_i_0 ro addr(base, 0x2) "Lower byte of 16-bit product ID Value is set for all channels. Default is" type(uint8); 40 41 register product_id_lo_i_1 ro addr(base, 0x102) "Lower byte of 16-bit product ID Value is set for all channels. Default is" type(uint8); 42 43 register product_id_hi_i_0 ro addr(base, 0x3) "Upper byte of 16-bit product ID Value is set for all channels. Default is" type(uint8); 44 45 register product_id_hi_i_1 ro addr(base, 0x103) "Upper byte of 16-bit product ID Value is set for all channels. Default is" type(uint8); 46 47 constants suspendm_status width(1) "" { 48 SUSPENDM_0 = 0 "PHY is in low-power mode."; 49 SUSPENDM_1 = 1 "PHY is not in low-power mode."; 50 }; 51 52 constants reset_status width(1) "" { 53 RESET_0 = 0 "No ongoing reset/no action"; 54 RESET_1 = 1 "Ongoing reset/apply reset"; 55 }; 56 57 constants opmode_status width(2) "" { 58 OPMODE_0 = 0 "Normal operation"; 59 OPMODE_1 = 1 "Nondriving"; 60 OPMODE_3 = 3 "Reserved"; 61 OPMODE_2 = 2 "Disable bit-stuff and NRZI encoding"; 62 }; 63 64 constants termselect_status width(1) "" { 65 TERMSELECT_0 = 0 "HS termination enabled (other conditions)"; 66 TERMSELECT_1 = 1 "FS termination enabled (other conditions)"; 67 }; 68 69 constants xcvrselect_status width(2) "" { 70 XCVRSELECT_0 = 0 "Enable HS transceiver"; 71 XCVRSELECT_1 = 1 "Enable FS transceiver"; 72 XCVRSELECT_3 = 3 "Enable FS transceiver for LS packets (automatic FS preamble prepending)"; 73 XCVRSELECT_2 = 2 "Enable LS transceiver"; 74 }; 75 76 register function_ctrl_i_0 addr(base, 0x4) "Controls UTMI function settings of the PHY. Read/write address." { 77 _ 1 mbz; 78 suspendm 1 rw type(suspendm_status) "Active low PHY suspend: puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit."; 79 reset 1 rw type(reset_status) "Active high UTMI transceiver reset. Auto-cleared. Does not reset the ULPI interface or ULPI register set."; 80 opmode 2 rw type(opmode_status) "Select the required bit encoding style during transmit"; 81 termselect 1 rw type(termselect_status) "Controls the internal 1.5-kohm HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown."; 82 xcvrselect 2 rw type(xcvrselect_status) "Select the required transceiver speed."; 83 }; 84 85 register function_ctrl_i_1 addr(base, 0x104) "Controls UTMI function settings of the PHY. Read/write address." { 86 _ 1 mbz; 87 suspendm 1 rw type(suspendm_status) "Active low PHY suspend: puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit."; 88 reset 1 rw type(reset_status) "Active high UTMI transceiver reset. Auto-cleared. Does not reset the ULPI interface or ULPI register set."; 89 opmode 2 rw type(opmode_status) "Select the required bit encoding style during transmit"; 90 termselect 1 rw type(termselect_status) "Controls the internal 1.5-kohm HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown."; 91 xcvrselect 2 rw type(xcvrselect_status) "Select the required transceiver speed."; 92 }; 93 94 constants suspendm_status1 width(1) "" { 95 SUSPENDM_0_w = 0 "No effect on bit value"; 96 SUSPENDM_1_w = 1 "Set the bit to 1."; 97 }; 98 99 register function_ctrl_set_i_0 addr(base, 0x5) "Controls UTMI function settings of the PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See the field description at the read/write address of the same register." { 100 _ 1 mbz; 101 suspendm 1 rw type(suspendm_status1) "Active low PHY suspend: Puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit."; 102 reset 1 rw type(suspendm_status1) "Active high UTMI transceiver reset. Autocleared. Does not reset the ULPI interface or ULPI register set."; 103 opmode 2 rw type(suspendm_status1) "Select the required bit encoding style during transmit."; 104 termselect 1 rw type(suspendm_status1) "Controls the internal 1.5-kohm pullup resistor and 45-ohm HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown."; 105 xcvrselect 2 rw type(suspendm_status1) "Select the required transceiver speed."; 106 }; 107 108 register function_ctrl_set_i_1 addr(base, 0x105) "Controls UTMI function settings of the PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See the field description at the read/write address of the same register." { 109 _ 1 mbz; 110 suspendm 1 rw type(suspendm_status1) "Active low PHY suspend: Puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit."; 111 reset 1 rw type(suspendm_status1) "Active high UTMI transceiver reset. Autocleared. Does not reset the ULPI interface or ULPI register set."; 112 opmode 2 rw type(suspendm_status1) "Select the required bit encoding style during transmit."; 113 termselect 1 rw type(suspendm_status1) "Controls the internal 1.5-kohm pullup resistor and 45-ohm HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown."; 114 xcvrselect 2 rw type(suspendm_status1) "Select the required transceiver speed."; 115 }; 116 117 constants suspendm_status2 width(1) "" { 118 SUSPENDM_0_w_2 = 0 "No effect on bit value"; 119 SUSPENDM_1_w_2 = 1 "Clear the bit to 0."; 120 }; 121 122 register function_ctrl_clr_i_0 addr(base, 0x6) "Controls UTMI function settings of the PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See the field description at the read/write address of the same register." { 123 _ 1 mbz; 124 suspendm 1 rw type(suspendm_status2) "Active low PHY suspend: Puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit."; 125 reset 1 rw type(suspendm_status2) "Active high UTMI transceiver reset. Autocleared. Does not reset the ULPI interface or ULPI register set."; 126 opmode 2 rw type(suspendm_status2) "Select the required bit encoding style during transmit"; 127 termselect 1 rw type(suspendm_status2) "Controls the internal 1.5-kohm pull-up resistor and 45-ohm HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown."; 128 xcvrselect 2 rw type(suspendm_status2) "Select the required transceiver speed."; 129 }; 130 131 register function_ctrl_clr_i_1 addr(base, 0x106) "Controls UTMI function settings of the PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See the field description at the read/write address of the same register." { 132 _ 1 mbz; 133 suspendm 1 rw type(suspendm_status2) "Active low PHY suspend: Puts the ULPI bus in low-power mode. Automatically set back to 1 upon low-power mode exit."; 134 reset 1 rw type(suspendm_status2) "Active high UTMI transceiver reset. Autocleared. Does not reset the ULPI interface or ULPI register set."; 135 opmode 2 rw type(suspendm_status2) "Select the required bit encoding style during transmit"; 136 termselect 1 rw type(suspendm_status2) "Controls the internal 1.5-kohm pull-up resistor and 45-ohm HS terminations. Control over bus resistors changes depending on XcvrSelect, OpMode, DpPulldown and DmPulldown."; 137 xcvrselect 2 rw type(suspendm_status2) "Select the required transceiver speed."; 138 }; 139 140 constants interface_protect_disable_status width(1) "" { 141 INTERFACE_PROTECT_DISABLE_0 = 0 "Enables the interface protect circuit"; 142 INTERFACE_PROTECT_DISABLE_1 = 1 "Disables the interface protect circuit"; 143 }; 144 145 constants autoresume_status width(1) "" { 146 AUTORESUME_0 = 0 "AutoResume disabled"; 147 AUTORESUME_1 = 1 "AutoResume enabled"; 148 }; 149 150 constants clocksuspendm_status width(1) "" { 151 CLOCKSUSPENDM_0 = 0 "ULPI clock will stop during serial modes."; 152 CLOCKSUSPENDM_1 = 1 "ULPI clock will run during serial modes."; 153 }; 154 155 constants fslsserialmode_3pin_status width(1) "" { 156 FSLSSERIALMODE_3PIN_0 = 0 "ULPI is not in 3-pin mode."; 157 FSLSSERIALMODE_3PIN_1 = 1 "ULPI is in 3-pin serial mode."; 158 }; 159 160 constants fslsserialmode_6pin_status width(1) "" { 161 FSLSSERIALMODE_6PIN_0 = 0 "ULPI is not in 6-pin mode."; 162 FSLSSERIALMODE_6PIN_1 = 1 "ULPI is in 6-pin serial mode."; 163 }; 164 165 register interface_ctrl_i_0 addr(base, 0x7) "Enables alternative interfaces and PHY features. Read/write address." { 166 interface_protect_disable 1 rw type(interface_protect_disable_status) "Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data."; 167 _ 2 mbz; 168 autoresume 1 rw type(autoresume_status) "Enables the PHY to automatically drive resume signaling. On by default."; 169 clocksuspendm 1 rw type(clocksuspendm_status) "Active low clock suspend for serial modes (6-pin/3-pin)."; 170 _ 1 mbz; 171 fslsserialmode_3pin 1 rw type(fslsserialmode_3pin_status) "Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Auto-cleared when serial mode is exited."; 172 fslsserialmode_6pin 1 rw type(fslsserialmode_6pin_status) "Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Auto-cleared when serial mode is exited."; 173 }; 174 175 register interface_ctrl_i_1 addr(base, 0x107) "Enables alternative interfaces and PHY features. Read/write address." { 176 interface_protect_disable 1 rw type(interface_protect_disable_status) "Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data."; 177 _ 2 mbz; 178 autoresume 1 rw type(autoresume_status) "Enables the PHY to automatically drive resume signaling. On by default."; 179 clocksuspendm 1 rw type(clocksuspendm_status) "Active low clock suspend for serial modes (6-pin/3-pin)."; 180 _ 1 mbz; 181 fslsserialmode_3pin 1 rw type(fslsserialmode_3pin_status) "Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Auto-cleared when serial mode is exited."; 182 fslsserialmode_6pin 1 rw type(fslsserialmode_6pin_status) "Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Auto-cleared when serial mode is exited."; 183 }; 184 185 register interface_ctrl_set_i_0 addr(base, 0x8) "Enables alternative interfaces and PHY features. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." { 186 interface_protect_disable 1 rw type(suspendm_status1) "Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data."; 187 _ 2 mbz; 188 autoresume 1 rw type(suspendm_status1) "Enables the PHY to automatically drive resume signaling. On by default."; 189 clocksuspendm 1 rw type(suspendm_status1) "Active low clock suspend for serial modes (6-pin/3-pin)."; 190 _ 1 mbz; 191 fslsserialmode_3pin 1 rw type(suspendm_status1) "Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Autocleared when serial mode is exited."; 192 fslsserialmode_6pin 1 rw type(suspendm_status1) "Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Autocleared when serial mode is exited."; 193 }; 194 195 register interface_ctrl_set_i_1 addr(base, 0x108) "Enables alternative interfaces and PHY features. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." { 196 interface_protect_disable 1 rw type(suspendm_status1) "Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data."; 197 _ 2 mbz; 198 autoresume 1 rw type(suspendm_status1) "Enables the PHY to automatically drive resume signaling. On by default."; 199 clocksuspendm 1 rw type(suspendm_status1) "Active low clock suspend for serial modes (6-pin/3-pin)."; 200 _ 1 mbz; 201 fslsserialmode_3pin 1 rw type(suspendm_status1) "Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Autocleared when serial mode is exited."; 202 fslsserialmode_6pin 1 rw type(suspendm_status1) "Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Autocleared when serial mode is exited."; 203 }; 204 205 register interface_ctrl_clr_i_0 addr(base, 0x9) "Enables alternative interfaces and PHY features. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 206 interface_protect_disable 1 rw type(suspendm_status2) "Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data."; 207 _ 2 mbz; 208 autoresume 1 rw type(suspendm_status2) "Enables the PHY to automatically drive resume signaling. On by default."; 209 clocksuspendm 1 rw type(suspendm_status2) "Active low clock suspend for serial modes (6-pin/3-pin)."; 210 _ 1 mbz; 211 fslsserialmode_3pin 1 rw type(suspendm_status2) "Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Autocleared when serial mode is exited."; 212 fslsserialmode_6pin 1 rw type(suspendm_status2) "Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Autocleared when serial mode is exited."; 213 }; 214 215 register interface_ctrl_clr_i_1 addr(base, 0x109) "Enables alternative interfaces and PHY features. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 216 interface_protect_disable 1 rw type(suspendm_status2) "Controls circuitry built into the PHY for protecting the ULPI interface when the link 3-states stp and data."; 217 _ 2 mbz; 218 autoresume 1 rw type(suspendm_status2) "Enables the PHY to automatically drive resume signaling. On by default."; 219 clocksuspendm 1 rw type(suspendm_status2) "Active low clock suspend for serial modes (6-pin/3-pin)."; 220 _ 1 mbz; 221 fslsserialmode_3pin 1 rw type(suspendm_status2) "Sets the ULPI interface to 3-pin (FS/LS only) serial mode. Autocleared when serial mode is exited."; 222 fslsserialmode_6pin 1 rw type(suspendm_status2) "Sets the ULPI interface to 6-pin (FS/LS only) serial mode. Autocleared when serial mode is exited."; 223 }; 224 225 constants drvvbus_status width(1) "" { 226 DRVVBUS_0 = 0 "No action"; 227 DRVVBUS_1 = 1 "Drive VBUS."; 228 }; 229 230 constants chrgvbus_status width(1) "" { 231 CHRGVBUS_0 = 0 "No action"; 232 CHRGVBUS_1 = 1 "Charge VBUS."; 233 }; 234 235 constants dischrgvbus_status width(1) "" { 236 DISCHRGVBUS_0 = 0 "No action"; 237 DISCHRGVBUS_1 = 1 "Discharge VBUS."; 238 }; 239 240 constants dmpulldown_status width(1) "" { 241 DMPULLDOWN_0 = 0 "Pulldown resistor not connected to D-"; 242 DMPULLDOWN_1 = 1 "Pulldown resistor connected to D-"; 243 }; 244 245 constants dppulldown_status width(1) "" { 246 DPPULLDOWN_0 = 0 "Pulldown resistor not connected to D+"; 247 DPPULLDOWN_1 = 1 "Pulldown resistor connected to D+"; 248 }; 249 250 constants idpullup_status width(1) "" { 251 IDPULLUP_0 = 0 "Disable sampling of ID line."; 252 IDPULLUP_1 = 1 "Enable sampling of ID line."; 253 }; 254 255 register otg_ctrl_i_0 addr(base, 0xA) "Controls UTMI+ OTG functions of the PHY. Read/write address." { 256 _ 2 mbz; 257 drvvbus 1 rw type(drvvbus_status) "Drive 5 V on VBUS"; 258 chrgvbus 1 rw type(chrgvbus_status) "Charge VBUS through a resistor for VBUS-pulsing SRP."; 259 dischrgvbus 1 rw type(dischrgvbus_status) "Discharge VBUS through a resistor, until the session-end VBUS state is reached."; 260 dmpulldown 1 rw type(dmpulldown_status) "Enables the 15-kohm pulldown resistor on D-"; 261 dppulldown 1 rw type(dppulldown_status) "Enables the 15-kohm pulldown resistor on D+"; 262 idpullup 1 rw type(idpullup_status) "Pullup to the (OTG) ID line to allow its sampling"; 263 }; 264 265 register otg_ctrl_i_1 addr(base, 0x10A) "Controls UTMI+ OTG functions of the PHY. Read/write address." { 266 _ 2 mbz; 267 drvvbus 1 rw type(drvvbus_status) "Drive 5 V on VBUS"; 268 chrgvbus 1 rw type(chrgvbus_status) "Charge VBUS through a resistor for VBUS-pulsing SRP."; 269 dischrgvbus 1 rw type(dischrgvbus_status) "Discharge VBUS through a resistor, until the session-end VBUS state is reached."; 270 dmpulldown 1 rw type(dmpulldown_status) "Enables the 15-kohm pulldown resistor on D-"; 271 dppulldown 1 rw type(dppulldown_status) "Enables the 15-kohm pulldown resistor on D+"; 272 idpullup 1 rw type(idpullup_status) "Pullup to the (OTG) ID line to allow its sampling"; 273 }; 274 275 register otg_ctrl_set_i_0 addr(base, 0xB) "Controls UTMI+ OTG functions of the PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." { 276 _ 2 mbz; 277 drvvbus 1 rw type(suspendm_status1) "Drive 5 V on VBUS"; 278 chrgvbus 1 rw type(suspendm_status1) "Charge VBUS through a resistor for VBUS-pulsing SRP."; 279 dischrgvbus 1 rw type(suspendm_status1) "Discharge VBUS through a resistor, until the session-end VBUS state is reached."; 280 dmpulldown 1 rw type(suspendm_status1) "Enables the 15-kohm pulldown resistor on D-"; 281 dppulldown 1 rw type(suspendm_status1) "Enables the 15-kohm pulldown resistor on D+"; 282 idpullup 1 rw type(suspendm_status1) "Pullup to the (OTG) ID line to allow its sampling"; 283 }; 284 285 register otg_ctrl_set_i_1 addr(base, 0x10B) "Controls UTMI+ OTG functions of the PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." { 286 _ 2 mbz; 287 drvvbus 1 rw type(suspendm_status1) "Drive 5 V on VBUS"; 288 chrgvbus 1 rw type(suspendm_status1) "Charge VBUS through a resistor for VBUS-pulsing SRP."; 289 dischrgvbus 1 rw type(suspendm_status1) "Discharge VBUS through a resistor, until the session-end VBUS state is reached."; 290 dmpulldown 1 rw type(suspendm_status1) "Enables the 15-kohm pulldown resistor on D-"; 291 dppulldown 1 rw type(suspendm_status1) "Enables the 15-kohm pulldown resistor on D+"; 292 idpullup 1 rw type(suspendm_status1) "Pullup to the (OTG) ID line to allow its sampling"; 293 }; 294 295 register otg_ctrl_clr_i_0 addr(base, 0xC) "Controls UTMI+ OTG functions of the PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 296 _ 2 mbz; 297 drvvbus 1 rw type(suspendm_status2) "Drive 5 V on VBUS"; 298 chrgvbus 1 rw type(suspendm_status2) "Charge VBUS through a resistor for VBUS-pulsing SRP."; 299 dischrgvbus 1 rw type(suspendm_status2) "Discharge VBUS through a resistor, until the session-end VBUS state is reached."; 300 dmpulldown 1 rw type(suspendm_status2) "Enables the 15k pulldown resistor on D-"; 301 dppulldown 1 rw type(suspendm_status2) "Enables the 15kohm pulldown resistor on D+"; 302 idpullup 1 rw type(suspendm_status2) "Pullup to the (OTG) ID line to allow its sampling"; 303 }; 304 305 register otg_ctrl_clr_i_1 addr(base, 0x10C) "Controls UTMI+ OTG functions of the PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 306 _ 2 mbz; 307 drvvbus 1 rw type(suspendm_status2) "Drive 5 V on VBUS"; 308 chrgvbus 1 rw type(suspendm_status2) "Charge VBUS through a resistor for VBUS-pulsing SRP."; 309 dischrgvbus 1 rw type(suspendm_status2) "Discharge VBUS through a resistor, until the session-end VBUS state is reached."; 310 dmpulldown 1 rw type(suspendm_status2) "Enables the 15k pulldown resistor on D-"; 311 dppulldown 1 rw type(suspendm_status2) "Enables the 15kohm pulldown resistor on D+"; 312 idpullup 1 rw type(suspendm_status2) "Pullup to the (OTG) ID line to allow its sampling"; 313 }; 314 315 constants idgnd_rise_status width(1) "" { 316 IDGND_RISE_0_w = 0 "No effect on bit value"; 317 IDGND_RISE_1_w = 1 "Set the bit to 1"; 318 }; 319 320 register usb_int_en_rise_i_0 addr(base, 0xD) "Enables an interrupt event notification when the corresponding status bit changes from low to high. By default, all transitions are enabled. Read/write address." { 321 _ 3 mbz; 322 idgnd_rise 1 rw type(idgnd_rise_status) "Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50ms after IdPullup is set to 1."; 323 sessend_rise 1 rw type(idgnd_rise_status) "Generate an interrupt event notification when SessEnd changes from low to high."; 324 sessvalid_rise 1 rw type(idgnd_rise_status) "Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid."; 325 vbusvalid_rise 1 rw type(idgnd_rise_status) "Generate an interrupt event notification when VbusValid changes from low to high."; 326 hostdisconnect_rise 1 rw type(idgnd_rise_status) "Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 327 }; 328 329 register usb_int_en_rise_i_1 addr(base, 0x10D) "Enables an interrupt event notification when the corresponding status bit changes from low to high. By default, all transitions are enabled. Read/write address." { 330 _ 3 mbz; 331 idgnd_rise 1 rw type(idgnd_rise_status) "Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50ms after IdPullup is set to 1."; 332 sessend_rise 1 rw type(idgnd_rise_status) "Generate an interrupt event notification when SessEnd changes from low to high."; 333 sessvalid_rise 1 rw type(idgnd_rise_status) "Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid."; 334 vbusvalid_rise 1 rw type(idgnd_rise_status) "Generate an interrupt event notification when VbusValid changes from low to high."; 335 hostdisconnect_rise 1 rw type(idgnd_rise_status) "Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 336 }; 337 338 register usb_int_en_rise_set_i_0 addr(base, 0xE) "Enables an interrupt event notification when the corresponding status bit changes from low to high. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 339 _ 3 mbz; 340 idgnd_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50ms after IdPullup is set to 1."; 341 sessend_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when SessEnd changes from low to high."; 342 sessvalid_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid."; 343 vbusvalid_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when VbusValid changes from low to high."; 344 hostdisconnect_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 345 }; 346 347 register usb_int_en_rise_set_i_1 addr(base, 0x10E) "Enables an interrupt event notification when the corresponding status bit changes from low to high. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 348 _ 3 mbz; 349 idgnd_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50ms after IdPullup is set to 1."; 350 sessend_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when SessEnd changes from low to high."; 351 sessvalid_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid."; 352 vbusvalid_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when VbusValid changes from low to high."; 353 hostdisconnect_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 354 }; 355 356 register usb_int_en_rise_clr_i_0 addr(base, 0xF) "Enables an interrupt event notification when the corresponding status bit changes from low to high. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See the field description at the read/write address of the same register." { 357 _ 3 mbz; 358 idgnd_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1."; 359 sessend_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when SessEnd changes from low to high."; 360 sessvalid_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid."; 361 vbusvalid_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when VbusValid changes from low to high."; 362 hostdisconnect_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 363 }; 364 365 register usb_int_en_rise_clr_i_1 addr(base, 0x10F) "Enables an interrupt event notification when the corresponding status bit changes from low to high. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See the field description at the read/write address of the same register." { 366 _ 3 mbz; 367 idgnd_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1."; 368 sessend_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when SessEnd changes from low to high."; 369 sessvalid_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid."; 370 vbusvalid_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when VbusValid changes from low to high."; 371 hostdisconnect_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 372 }; 373 374 register usb_int_en_fall_i_0 addr(base, 0x10) "Enables an interrupt event notification when the corresponding status bit changes from high to low. By default, all transitions are enabled. Read/write address." { 375 _ 3 mbz; 376 idgnd_fall 1 rw "Generate an interrupt event notification when IdGnd changes from high to low. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1."; 377 sessend_fall 1 rw "Generate an interrupt event notification when SessEnd changes from high to low."; 378 sessvalid_fall 1 rw "Generate an interrupt event notification when SessValid changes from high to low. SessValid is the same as UTMI+ AValid."; 379 vbusvalid_fall 1 rw "Generate an interrupt event notification when VbusValid changes from high to low."; 380 hostdisconnect_fall 1 rw "Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 381 }; 382 383 register usb_int_en_fall_i_1 addr(base, 0x110) "Enables an interrupt event notification when the corresponding status bit changes from high to low. By default, all transitions are enabled. Read/write address." { 384 _ 3 mbz; 385 idgnd_fall 1 rw "Generate an interrupt event notification when IdGnd changes from high to low. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1."; 386 sessend_fall 1 rw "Generate an interrupt event notification when SessEnd changes from high to low."; 387 sessvalid_fall 1 rw "Generate an interrupt event notification when SessValid changes from high to low. SessValid is the same as UTMI+ AValid."; 388 vbusvalid_fall 1 rw "Generate an interrupt event notification when VbusValid changes from high to low."; 389 hostdisconnect_fall 1 rw "Generate an interrupt event notification when Hostdisconnect changes from high to low. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 390 }; 391 392 register usb_int_en_fall_set_i_0 addr(base, 0x11) "Enables an interrupt event notification when the corresponding status bit changes from high to low. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 393 _ 3 mbz; 394 idgnd_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1."; 395 sessend_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when SessEnd changes from low to high."; 396 sessvalid_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid."; 397 vbusvalid_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when VbusValid changes from low to high."; 398 hostdisconnect_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 399 }; 400 401 register usb_int_en_fall_set_i_1 addr(base, 0x111) "Enables an interrupt event notification when the corresponding status bit changes from high to low. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 402 _ 3 mbz; 403 idgnd_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1."; 404 sessend_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when SessEnd changes from low to high."; 405 sessvalid_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid."; 406 vbusvalid_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when VbusValid changes from low to high."; 407 hostdisconnect_rise 1 rw type(suspendm_status1) "Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 408 }; 409 410 register usb_int_en_fall_clr_i_0 addr(base, 0x12) "Enables an interrupt event notification when the corresponding status bit changes from high to low. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See field description at the read/write address of the same register." { 411 _ 3 mbz; 412 idgnd_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1."; 413 sessend_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when SessEnd changes from low to high."; 414 sessvalid_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid."; 415 vbusvalid_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when VbusValid changes from low to high."; 416 hostdisconnect_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 417 }; 418 419 register usb_int_en_fall_clr_i_1 addr(base, 0x112) "Enables an interrupt event notification when the corresponding status bit changes from high to low. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See field description at the read/write address of the same register." { 420 _ 3 mbz; 421 idgnd_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when IdGnd changes from low to high. Event is automatically masked if IdPullup bit is clear to 0 and for 50 ms after IdPullup is set to 1."; 422 sessend_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when SessEnd changes from low to high."; 423 sessvalid_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when SessValid changes from low to high. SessValid is the same as UTMI+ AValid."; 424 vbusvalid_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when VbusValid changes from low to high."; 425 hostdisconnect_rise 1 rw type(suspendm_status2) "Generate an interrupt event notification when Hostdisconnect changes from low to high. Applicable only in host mode (DpPulldown and DmPulldown both set to 1b)."; 426 }; 427 428 constants idgnd_status width(1) "" { 429 IDGND_1_r = 1 "ID pin is floating = OTG B = default peripheral"; 430 IDGND_0_r = 0 "ID pin is grounded = OTG A = default host"; 431 }; 432 433 constants sessend_status width(1) "" { 434 SESSEND_1_r = 1 "VBUS is below Session-End threshold."; 435 SESSEND_0_r = 0 "VBUS is above Session-End threshold."; 436 }; 437 438 constants sessvalid_status width(1) "" { 439 SESSVALID_1_r = 1 "VBUS is above Session-Valid threshold."; 440 SESSVALID_0_r = 0 "VBUS is below Session-Valid threshold."; 441 }; 442 443 constants vbusvalid_status width(1) "" { 444 VBUSVALID_1_r = 1 "VBUS is above Vbus-Valid threshold."; 445 VBUSVALID_0_r = 0 "VBUS is below Vbus-Valid threshold."; 446 }; 447 448 constants hostdisconnect_status width(1) "" { 449 HOSTDISCONNECT_1_r = 1 "Peripheral disconnected"; 450 HOSTDISCONNECT_0_r = 0 "Peripheral not disconnected or nonhost mode"; 451 }; 452 453 register usb_int_status_i_0 addr(base, 0x13) "Indicates the current value of the interrupt source signal." { 454 _ 3 mbz; 455 idgnd 1 ro type(idgnd_status) "Value of UTMI+ IdDig output. Undefined unless IdPullup = 1"; 456 sessend 1 ro type(sessend_status) "Current value of UTMI+ SessEnd output."; 457 sessvalid 1 ro type(sessvalid_status) "Current value of UTMI+ SessValid output. SessValid is the same as UTMI+ AValid."; 458 vbusvalid 1 ro type(vbusvalid_status) "Current value of UTMI+ VbusValid output."; 459 hostdisconnect 1 ro type(hostdisconnect_status) "Current value of UTMI+ Hostdisconnect output. Applicable only in host mode. Automatically reset to 0 when low-power mode is entered."; 460 }; 461 462 register usb_int_status_i_1 addr(base, 0x113) "Indicates the current value of the interrupt source signal." { 463 _ 3 mbz; 464 idgnd 1 ro type(idgnd_status) "Value of UTMI+ IdDig output. Undefined unless IdPullup = 1"; 465 sessend 1 ro type(sessend_status) "Current value of UTMI+ SessEnd output."; 466 sessvalid 1 ro type(sessvalid_status) "Current value of UTMI+ SessValid output. SessValid is the same as UTMI+ AValid."; 467 vbusvalid 1 ro type(vbusvalid_status) "Current value of UTMI+ VbusValid output."; 468 hostdisconnect 1 ro type(hostdisconnect_status) "Current value of UTMI+ Hostdisconnect output. Applicable only in host mode. Automatically reset to 0 when low-power mode is entered."; 469 }; 470 471 register usb_int_latch_i_0 addr(base, 0x14) "Set by unmasked changes on the corresponding status bits to generate the ULPI interrupt. Cleared upon read, and when low-power mode, serial mode, or carkit mode are entered." { 472 _ 3 mbz; 473 idgnd_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on IdGnd. Cleared when this register is read."; 474 sessend_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on SessEnd. Cleared when this register is read."; 475 sessvalid_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on SessValid. Cleared when this register is read. SessValid is the same as UTMI+ AValid."; 476 vbusvalid_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on VbusValid. Cleared when this register is read."; 477 hostdisconnect_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode."; 478 }; 479 480 register usb_int_latch_i_1 addr(base, 0x114) "Set by unmasked changes on the corresponding status bits to generate the ULPI interrupt. Cleared upon read, and when low-power mode, serial mode, or carkit mode are entered." { 481 _ 3 mbz; 482 idgnd_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on IdGnd. Cleared when this register is read."; 483 sessend_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on SessEnd. Cleared when this register is read."; 484 sessvalid_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on SessValid. Cleared when this register is read. SessValid is the same as UTMI+ AValid."; 485 vbusvalid_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on VbusValid. Cleared when this register is read."; 486 hostdisconnect_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode."; 487 }; 488 489 constants line_state_status width(2) "" { 490 LINE_STATE_3_r = 3 "SE1 (LS/FS), Invalid (HS/Chirp)"; 491 LINE_STATE_2_r = 2 "LS: J state, FS: K state, HS: Invalid, Chirp: !Squelch AND !HS_Differential_Receiver_Output"; 492 LINE_STATE_1_r = 1 "LS: K state, FS: J state, HS: !Squelch, Chirp: !Squelch AND HS_Differential_Receiver_Output"; 493 LINE_STATE_0_r = 0 "SE0 (LS/FS), Squelch (HS/Chirp)"; 494 }; 495 496 register debug_i_0 addr(base, 0x15) "Indicates the current value of various signals useful for debugging." { 497 _ 6 mbz; 498 line_state 2 ro type(line_state_status) "Current state of the USB line: D+ (bit 0) and D- (bit 1)."; 499 }; 500 501 register debug_i_1 addr(base, 0x115) "Indicates the current value of various signals useful for debugging." { 502 _ 6 mbz; 503 line_state 2 ro type(line_state_status) "Current state of the USB line: D+ (bit 0) and D- (bit 1)."; 504 }; 505 506 register scratch_register_i_0 rw addr(base, 0x16) "Register byte for register access testing purposes. Value has no functional effect on PHY. Read/write address." type(uint8); 507 508 register scratch_register_i_1 rw addr(base, 0x116) "Register byte for register access testing purposes. Value has no functional effect on PHY. Read/write address." type(uint8); 509 510 register scratch_register_set_i_0 rw addr(base, 0x17) "Register byte for register access testing purposes. Value has no functional effect on PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." type(uint8); 511 512 register scratch_register_set_i_1 rw addr(base, 0x117) "Register byte for register access testing purposes. Value has no functional effect on PHY. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." type(uint8); 513 514 register scratch_register_clr_i_0 rw addr(base, 0x18) "Register byte for register access testing purposes. Value has no functional effect on PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See field description at the read/write address of the same register." type(uint8); 515 516 register scratch_register_clr_i_1 rw addr(base, 0x118) "Register byte for register access testing purposes. Value has no functional effect on PHY. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See field description at the read/write address of the same register." type(uint8); 517 518 register extended_set_access_i_0 rw addr(base, 0x2F) "This address is used to access the extended register set; that is, addresses above 0x40." type(uint8); 519 520 register extended_set_access_i_1 rw addr(base, 0x12F) "This address is used to access the extended register set; that is, addresses above 0x40." type(uint8); 521 522 register utmi_vcontrol_en_i_0 addr(base, 0x30) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1 Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/write address. Lowest VCS_CTRL_WIDTH (HDL generic) bits are implemented, others are always-0, read-only. (UTMI standard is 4-bit.)" { 523 vc7_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 524 vc6_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 525 vc5_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 526 vc4_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 527 vc3_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 528 vc2_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 529 vc1_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 530 vc0_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 531 }; 532 533 register utmi_vcontrol_en_i_1 addr(base, 0x130) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1 Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/write address. Lowest VCS_CTRL_WIDTH (HDL generic) bits are implemented, others are always-0, read-only. (UTMI standard is 4-bit.)" { 534 vc7_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 535 vc6_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 536 vc5_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 537 vc4_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 538 vc3_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 539 vc2_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 540 vc1_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 541 vc0_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 542 }; 543 544 register utmi_vcontrol_en_set_i_0 addr(base, 0x31) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1 Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 545 vc7_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 546 vc6_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 547 vc5_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 548 vc4_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 549 vc3_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 550 vc2_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 551 vc1_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 552 vc0_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 553 }; 554 555 register utmi_vcontrol_en_set_i_1 addr(base, 0x131) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1 Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 556 vc7_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 557 vc6_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 558 vc5_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 559 vc4_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 560 vc3_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 561 vc2_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 562 vc1_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 563 vc0_en 1 rw "Enable alt_int assertion upon vcontrol_status bit change: Write 0x0: No effect on bit value Write 0x1: Set the bit to 1."; 564 }; 565 566 register utmi_vcontrol_en_clr_i_0 rw addr(base, 0x32) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." type(uint8); 567 568 register utmi_vcontrol_en_clr_i_1 rw addr(base, 0x132) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. Enables an interrupt notification when the corresponding vcontrol_status bit changes. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." type(uint8); 569 570 register utmi_vcontrol_status_i_0 rw addr(base, 0x33) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vcontrol vector byte is sent by the UTMI controller (other side of TLL) to its PHY (emulated here by the TLL). Alternatively, data can be also written directly into the register. Can contain any user-defined data. Vcontrol bit changes can be used to assert the ULPI ALT interrupt. Lowest VCS_CTRL_WIDTH (HDL generic) bits are implemented, others are always-0, read-only. (UTMI standard is 4-bit)." type(uint8); 571 572 register utmi_vcontrol_status_i_1 rw addr(base, 0x133) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vcontrol vector byte is sent by the UTMI controller (other side of TLL) to its PHY (emulated here by the TLL). Alternatively, data can be also written directly into the register. Can contain any user-defined data. Vcontrol bit changes can be used to assert the ULPI ALT interrupt. Lowest VCS_CTRL_WIDTH (HDL generic) bits are implemented, others are always-0, read-only. (UTMI standard is 4-bit)." type(uint8); 573 574 register utmi_vcontrol_latch_i_0 addr(base, 0x34) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. Set by unmasked changes on the corresponding vcontrol_status bits to generate the ULPI ALT interrupt. Cleared upon read, and when low-power mode, serial mode or carkit mode are entered. Lowest VCS_CTRL_WIDTH (HDL generic) bits are implemented, others are always-0, read-only. (UTMI standard is 4-bit.)" { 575 vc7_change 1 ro "Unmasked change on vcontrol_status bit"; 576 vc6_change 1 ro "Unmasked change on vcontrol_status bit"; 577 vc5_change 1 ro "Unmasked change on vcontrol_status bit"; 578 vc4_change 1 ro "Unmasked change on vcontrol_status bit"; 579 vc3_change 1 ro "Unmasked change on vcontrol_status bit"; 580 vc2_change 1 ro "Unmasked change on vcontrol_status bit"; 581 vc1_change 1 ro "Unmasked change on vcontrol_status bit"; 582 vc0_change 1 ro "Unmasked change on vcontrol_status bit"; 583 }; 584 585 register utmi_vcontrol_latch_i_1 addr(base, 0x134) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. Set by unmasked changes on the corresponding vcontrol_status bits to generate the ULPI ALT interrupt. Cleared upon read, and when low-power mode, serial mode or carkit mode are entered. Lowest VCS_CTRL_WIDTH (HDL generic) bits are implemented, others are always-0, read-only. (UTMI standard is 4-bit.)" { 586 vc7_change 1 ro "Unmasked change on vcontrol_status bit"; 587 vc6_change 1 ro "Unmasked change on vcontrol_status bit"; 588 vc5_change 1 ro "Unmasked change on vcontrol_status bit"; 589 vc4_change 1 ro "Unmasked change on vcontrol_status bit"; 590 vc3_change 1 ro "Unmasked change on vcontrol_status bit"; 591 vc2_change 1 ro "Unmasked change on vcontrol_status bit"; 592 vc1_change 1 ro "Unmasked change on vcontrol_status bit"; 593 vc0_change 1 ro "Unmasked change on vcontrol_status bit"; 594 }; 595 596 register utmi_vstatus_i_0 rw addr(base, 0x35) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): information written into this register goes directly to the UTMI controller, and can contain any user-defined data. Read/write address. Lowest VCS_STAT_WIDTH (HDL generic) bits are implemented, others are always-0, read-only. (UTMI standard is 8-bit.)" type(uint8); 597 598 register utmi_vstatus_i_1 rw addr(base, 0x135) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): information written into this register goes directly to the UTMI controller, and can contain any user-defined data. Read/write address. Lowest VCS_STAT_WIDTH (HDL generic) bits are implemented, others are always-0, read-only. (UTMI standard is 8-bit.)" type(uint8); 599 600 register utmi_vstatus_set_i_0 rw addr(base, 0x36) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): information written into this register goes directly to the UTMI controller, and can contain any user-defined data. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." type(uint8); 601 602 register utmi_vstatus_set_i_1 rw addr(base, 0x136) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): information written into this register goes directly to the UTMI controller, and can contain any user-defined data. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." type(uint8); 603 604 register utmi_vstatus_clr_i_0 rw addr(base, 0x37) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): information written into this register goes directly to the UTMI controller, and can contain any user-defined data. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See field description at the read/write address of the same register." type(uint8); 605 606 register utmi_vstatus_clr_i_1 rw addr(base, 0x137) "Part of nonstandard UTMI-to-ULPI mailbox system, implemented if HDL generic VCS_MAILBOX bit is 1. UTMI-standard Vstatus vector byte is sent by the PHY (emulated here by the TLL) to the UTMI controller (other side of TLL): information written into this register goes directly to the UTMI controller, and can contain any user-defined data. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See field description at the read/write address of the same register." type(uint8); 607 608 register usb_int_latch_noclr_i_0 addr(base, 0x38) "Set by unmasked changes on the corresponding status bits to generate the ULPI interrupt. Debug, nonstandard address to the standard register: Register is not cleared on read. See field description at the 'clear-on-read' address of the same register." { 609 _ 3 mbz; 610 idgnd_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on IdGnd."; 611 sessend_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on SessEnd."; 612 sessvalid_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on SessValid. SessValid is the same as UTMI+ AValid."; 613 vbusvalid_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on VbusValid."; 614 hostdisconnect_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on Hostdisconnect. Applicable only in host mode."; 615 }; 616 617 register usb_int_latch_noclr_i_1 addr(base, 0x138) "Set by unmasked changes on the corresponding status bits to generate the ULPI interrupt. Debug, nonstandard address to the standard register: Register is not cleared on read. See field description at the 'clear-on-read' address of the same register." { 618 _ 3 mbz; 619 idgnd_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on IdGnd."; 620 sessend_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on SessEnd."; 621 sessvalid_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on SessValid. SessValid is the same as UTMI+ AValid."; 622 vbusvalid_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on VbusValid."; 623 hostdisconnect_latch 1 ro "Set to 1 by the PHY when an unmasked event occurs on Hostdisconnect. Applicable only in host mode."; 624 }; 625 626 constants p2p_en_status width(1) "" { 627 P2P_EN_0 = 0 "PHY-to-PHY wakeup enabled"; 628 P2P_EN_1 = 1 "PHY-to-PHY wakeup enabled"; 629 }; 630 631 register vendor_int_en_i_0 addr(base, 0x3B) "Vendor-specific interrupt enables (mask) for miscellaneous ULPI alt_int events. Read/write address." { 632 _ 7 mbz; 633 p2p_en 1 rw type(p2p_en_status) "Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm."; 634 }; 635 636 register vendor_int_en_i_1 addr(base, 0x13B) "Vendor-specific interrupt enables (mask) for miscellaneous ULPI alt_int events. Read/write address." { 637 _ 7 mbz; 638 p2p_en 1 rw type(p2p_en_status) "Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm."; 639 }; 640 641 register vendor_int_en_set_i_0 addr(base, 0x3C) "Vendor-specific interrupt enable bit (mask) for miscellaneous ULPI alt_int events. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." { 642 _ 7 mbz; 643 p2p_en 1 rw type(suspendm_status1) "Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm."; 644 }; 645 646 register vendor_int_en_set_i_1 addr(base, 0x13C) "Vendor-specific interrupt enable bit (mask) for miscellaneous ULPI alt_int events. Read/set address (write 1 to a bit to set it to 1, writing 0 has no effect on bit value). See field description at the read/write address of the same register." { 647 _ 7 mbz; 648 p2p_en 1 rw type(suspendm_status1) "Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm."; 649 }; 650 651 register vendor_int_en_clr_i_0 addr(base, 0x3D) "Vendor-specific interrupt enables (mask) for miscellaneous ULPI alt_int events. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 652 _ 7 mbz; 653 p2p_en 1 rw type(suspendm_status2) "Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm."; 654 }; 655 656 register vendor_int_en_clr_i_1 addr(base, 0x13D) "Vendor-specific interrupt enables (mask) for miscellaneous ULPI alt_int events. Read/clear address (write 1 to a bit to clear it to 0, writing 0 has no effect on bit value). See fields description at the read/write address of the same register." { 657 _ 7 mbz; 658 p2p_en 1 rw type(suspendm_status2) "Enable PHY-to-PHY ULPI wakeup upon inactive UTMI suspendm."; 659 }; 660 661 constants utmi_suspendm_status width(1) "" { 662 UTMI_SUSPENDM_1_r = 1 "UTMI interface is active (not suspended)."; 663 UTMI_SUSPENDM_0_r = 0 "UTMI interface is suspended."; 664 }; 665 666 register vendor_int_status_i_0 addr(base, 0x3E) "Vendor-specific interrupt sources for miscellaneous ULPI alt_int events" { 667 _ 7 mbz; 668 utmi_suspendm 1 ro type(utmi_suspendm_status) "UTMI suspendm status (active-low), source of TLL PHY-to-PHY wake-up interrupt."; 669 }; 670 671 register vendor_int_status_i_1 addr(base, 0x13E) "Vendor-specific interrupt sources for miscellaneous ULPI alt_int events" { 672 _ 7 mbz; 673 utmi_suspendm 1 ro type(utmi_suspendm_status) "UTMI suspendm status (active-low), source of TLL PHY-to-PHY wake-up interrupt."; 674 }; 675 676 constants p2p_latch_status width(1) "" { 677 P2P_LATCH_1_r = 1 "PHY-to-PHY wake-up event was latched, ALT interrupt active."; 678 P2P_LATCH_0_r = 0 "No PHY-to-PHY wake-up event was latched."; 679 }; 680 681 register vendor_int_latch_i_0 addr(base, 0x3F) "Vendor-specific interrupt latches for miscellaneous ULPI alt_int events. Cleared upon read, and when low-power mode, serial mode or carkit mode are entered." { 682 _ 7 mbz; 683 p2p_latch 1 ro type(p2p_latch_status) "PHY-to-PHY ULPI wake-up event latch. Set when ULPI is in low-power mode (suspendm = 0) and UTMI is active (suspendm = 1)."; 684 }; 685 686 register vendor_int_latch_i_1 addr(base, 0x13F) "Vendor-specific interrupt latches for miscellaneous ULPI alt_int events. Cleared upon read, and when low-power mode, serial mode or carkit mode are entered." { 687 _ 7 mbz; 688 p2p_latch 1 ro type(p2p_latch_status) "PHY-to-PHY ULPI wake-up event latch. Set when ULPI is in low-power mode (suspendm = 0) and UTMI is active (suspendm = 1)."; 689 }; 690};