1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_system_mailbox_l4_cfginterconnect.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_system_mailbox_l4_cfginterconnect msbfirst ( addr base ) "" { 29 30 31 register mailbox_revision ro addr(base, 0x0) "This register contains the IP revision code" type(uint32); 32 33 constants sidlemode_status width(2) "" { 34 SIDLEMODE_0 = 0 "Force-idle. An idle request is acknowledged unconditionally"; 35 SIDLEMODE_1 = 1 "No-idle. An idle request is never acknowledged"; 36 SIDLEMODE_2 = 2 "Smart-idle. Acknowledgement to an idle request is given based on the internal activity of the module based on the internal activity of the module"; 37 SIDLEMODE_3 = 3 "reserved do not use"; 38 }; 39 40 constants softreset_status width(1) "" { 41 SOFTRESET_0_r = 0 "Soft/Hard reset done"; 42 SOFTRESET_0_w = 0 "No action"; 43 SOFTRESET_1_r = 1 "Reset is ongoing"; 44 SOFTRESET_1_w = 1 "Start the soft reset sequence"; 45 }; 46 47 register mailbox_sysconfig addr(base, 0x10) "This register controls the various parameters of the communication interface" { 48 _ 28 mbz; 49 sidlemode 2 rw type(sidlemode_status) "Idle Mode"; 50 _ 1 mbz; 51 softreset 1 rw type(softreset_status) "Softreset"; 52 }; 53 54 register mailbox_message_m_0 rw addr(base, 0x40) "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." type(uint32); 55 56 register mailbox_message_m_1 rw addr(base, 0x44) "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." type(uint32); 57 58 register mailbox_message_m_2 rw addr(base, 0x48) "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." type(uint32); 59 60 register mailbox_message_m_3 rw addr(base, 0x4C) "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." type(uint32); 61 62 register mailbox_message_m_4 rw addr(base, 0x50) "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." type(uint32); 63 64 register mailbox_message_m_5 rw addr(base, 0x54) "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." type(uint32); 65 66 register mailbox_message_m_6 rw addr(base, 0x58) "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." type(uint32); 67 68 register mailbox_message_m_7 rw addr(base, 0x5C) "The message register stores the next to be read message of the mailbox. Reads remove the message from the FIFO queue." type(uint32); 69 70 constants fifofullmbm_status width(1) "" { 71 FIFOFULLMBM_0_r = 0 "Mailbox FIFO is not full"; 72 FIFOFULLMBM_1_r = 1 "Mailbox FIFO is full"; 73 }; 74 75 register mailbox_fifostatus_m_0 addr(base, 0x80) "The FIFO status register has the status related to the mailbox internal FIFO" { 76 _ 31 mbz; 77 fifofullmbm 1 ro type(fifofullmbm_status) "Full flag for Mailbox"; 78 }; 79 80 register mailbox_fifostatus_m_1 addr(base, 0x84) "The FIFO status register has the status related to the mailbox internal FIFO" { 81 _ 31 mbz; 82 fifofullmbm 1 ro type(fifofullmbm_status) "Full flag for Mailbox"; 83 }; 84 85 register mailbox_fifostatus_m_2 addr(base, 0x88) "The FIFO status register has the status related to the mailbox internal FIFO" { 86 _ 31 mbz; 87 fifofullmbm 1 ro type(fifofullmbm_status) "Full flag for Mailbox"; 88 }; 89 90 register mailbox_fifostatus_m_3 addr(base, 0x8C) "The FIFO status register has the status related to the mailbox internal FIFO" { 91 _ 31 mbz; 92 fifofullmbm 1 ro type(fifofullmbm_status) "Full flag for Mailbox"; 93 }; 94 95 register mailbox_fifostatus_m_4 addr(base, 0x90) "The FIFO status register has the status related to the mailbox internal FIFO" { 96 _ 31 mbz; 97 fifofullmbm 1 ro type(fifofullmbm_status) "Full flag for Mailbox"; 98 }; 99 100 register mailbox_fifostatus_m_5 addr(base, 0x94) "The FIFO status register has the status related to the mailbox internal FIFO" { 101 _ 31 mbz; 102 fifofullmbm 1 ro type(fifofullmbm_status) "Full flag for Mailbox"; 103 }; 104 105 register mailbox_fifostatus_m_6 addr(base, 0x98) "The FIFO status register has the status related to the mailbox internal FIFO" { 106 _ 31 mbz; 107 fifofullmbm 1 ro type(fifofullmbm_status) "Full flag for Mailbox"; 108 }; 109 110 register mailbox_fifostatus_m_7 addr(base, 0x9C) "The FIFO status register has the status related to the mailbox internal FIFO" { 111 _ 31 mbz; 112 fifofullmbm 1 ro type(fifofullmbm_status) "Full flag for Mailbox"; 113 }; 114 115 register mailbox_msgstatus_m_0 addr(base, 0xC0) "The message status register has the status of the messages in the mailbox." { 116 _ 29 mbz; 117 nbofmsgmbm 3 ro "Number of unread messages in MailboxNote: Limited to four messages per mailbox."; 118 }; 119 120 register mailbox_msgstatus_m_1 addr(base, 0xC4) "The message status register has the status of the messages in the mailbox." { 121 _ 29 mbz; 122 nbofmsgmbm 3 ro "Number of unread messages in MailboxNote: Limited to four messages per mailbox."; 123 }; 124 125 register mailbox_msgstatus_m_2 addr(base, 0xC8) "The message status register has the status of the messages in the mailbox." { 126 _ 29 mbz; 127 nbofmsgmbm 3 ro "Number of unread messages in MailboxNote: Limited to four messages per mailbox."; 128 }; 129 130 register mailbox_msgstatus_m_3 addr(base, 0xCC) "The message status register has the status of the messages in the mailbox." { 131 _ 29 mbz; 132 nbofmsgmbm 3 ro "Number of unread messages in MailboxNote: Limited to four messages per mailbox."; 133 }; 134 135 register mailbox_msgstatus_m_4 addr(base, 0xD0) "The message status register has the status of the messages in the mailbox." { 136 _ 29 mbz; 137 nbofmsgmbm 3 ro "Number of unread messages in MailboxNote: Limited to four messages per mailbox."; 138 }; 139 140 register mailbox_msgstatus_m_5 addr(base, 0xD4) "The message status register has the status of the messages in the mailbox." { 141 _ 29 mbz; 142 nbofmsgmbm 3 ro "Number of unread messages in MailboxNote: Limited to four messages per mailbox."; 143 }; 144 145 register mailbox_msgstatus_m_6 addr(base, 0xD8) "The message status register has the status of the messages in the mailbox." { 146 _ 29 mbz; 147 nbofmsgmbm 3 ro "Number of unread messages in MailboxNote: Limited to four messages per mailbox."; 148 }; 149 150 register mailbox_msgstatus_m_7 addr(base, 0xDC) "The message status register has the status of the messages in the mailbox." { 151 _ 29 mbz; 152 nbofmsgmbm 3 ro "Number of unread messages in MailboxNote: Limited to four messages per mailbox."; 153 }; 154 155 constants notfullstatusenuumb7_status width(1) "" { 156 NOTFULLSTATUSENUUMB7_0_r = 0 "No event pending (message queue full)"; 157 NOTFULLSTATUSENUUMB7_0_w = 0 "No action"; 158 NOTFULLSTATUSENUUMB7_1_r = 1 "Event pending (message queue not full)"; 159 NOTFULLSTATUSENUUMB7_1_w = 1 "Set the event (for debug)"; 160 }; 161 162 constants newmsgstatusuumb7_status width(1) "" { 163 NEWMSGSTATUSUUMB7_0_r = 0 "No event (message) pending"; 164 NEWMSGSTATUSUUMB7_0_w = 0 "No action"; 165 NEWMSGSTATUSUUMB7_1_r = 1 "Event (message) pending"; 166 NEWMSGSTATUSUUMB7_1_w = 1 "Set the event (for debug)"; 167 }; 168 169 register mailbox_irqstatus_raw_u_0 addr(base, 0x100) "The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." { 170 _ 16 mbz; 171 notfullstatusenuumb7 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 7"; 172 newmsgstatusuumb7 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 7"; 173 notfullstatusuumb6 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 6"; 174 newmsgstatusuumb6 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 6"; 175 notfullstatusuumb5 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 5"; 176 newmsgstatusuumb5 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 5"; 177 notfullstatusuumb4 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 4"; 178 newmsgstatusuumb4 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 4"; 179 notfullstatusuumb3 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 3"; 180 newmsgstatusuumb3 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 3"; 181 notfullstatusuumb2 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 2"; 182 newmsgstatusuumb2 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 2"; 183 notfullstatusuumb1 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 1"; 184 newmsgstatusuumb1 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 1"; 185 notfullstatusuumb0 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 0"; 186 newmsgstatusuumb0 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 0"; 187 }; 188 189 register mailbox_irqstatus_raw_u_1 addr(base, 0x110) "The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." { 190 _ 16 mbz; 191 notfullstatusenuumb7 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 7"; 192 newmsgstatusuumb7 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 7"; 193 notfullstatusuumb6 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 6"; 194 newmsgstatusuumb6 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 6"; 195 notfullstatusuumb5 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 5"; 196 newmsgstatusuumb5 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 5"; 197 notfullstatusuumb4 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 4"; 198 newmsgstatusuumb4 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 4"; 199 notfullstatusuumb3 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 3"; 200 newmsgstatusuumb3 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 3"; 201 notfullstatusuumb2 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 2"; 202 newmsgstatusuumb2 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 2"; 203 notfullstatusuumb1 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 1"; 204 newmsgstatusuumb1 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 1"; 205 notfullstatusuumb0 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 0"; 206 newmsgstatusuumb0 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 0"; 207 }; 208 209 register mailbox_irqstatus_raw_u_2 addr(base, 0x120) "The interrupt status register has the raw status for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit sets this bit. This register is mainly used for debug purpose." { 210 _ 16 mbz; 211 notfullstatusenuumb7 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 7"; 212 newmsgstatusuumb7 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 7"; 213 notfullstatusuumb6 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 6"; 214 newmsgstatusuumb6 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 6"; 215 notfullstatusuumb5 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 5"; 216 newmsgstatusuumb5 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 5"; 217 notfullstatusuumb4 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 4"; 218 newmsgstatusuumb4 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 4"; 219 notfullstatusuumb3 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 3"; 220 newmsgstatusuumb3 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 3"; 221 notfullstatusuumb2 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 2"; 222 newmsgstatusuumb2 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 2"; 223 notfullstatusuumb1 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 1"; 224 newmsgstatusuumb1 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 1"; 225 notfullstatusuumb0 1 rw type(notfullstatusenuumb7_status) "NotFull Status bit for User u, Mailbox 0"; 226 newmsgstatusuumb0 1 rw type(newmsgstatusuumb7_status) "NewMessage Status bit for User u, Mailbox 0"; 227 }; 228 229 constants notfullstatusenuumb7_status1 width(1) "" { 230 NOTFULLSTATUSENUUMB7_0_r_3 = 0 "No event pending (message queue full)"; 231 NOTFULLSTATUSENUUMB7_0_w_3 = 0 "No action"; 232 NOTFULLSTATUSENUUMB7_1_r_3 = 1 "Event pending (message queue not full)"; 233 NOTFULLSTATUSENUUMB7_1_w_3 = 1 "Clear pending event, if any"; 234 }; 235 236 constants newmsgstatusenuumb7_status width(1) "" { 237 NEWMSGSTATUSENUUMB7_0_r = 0 "No event (message) pending"; 238 NEWMSGSTATUSENUUMB7_0_w = 0 "No action"; 239 NEWMSGSTATUSENUUMB7_1_r = 1 "Event (message) pending"; 240 NEWMSGSTATUSENUUMB7_1_w = 1 "Clear pending event, if any"; 241 }; 242 243 register mailbox_irqstatus_clr_u_0 addr(base, 0x104) "The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" { 244 _ 16 mbz; 245 notfullstatusenuumb7 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 7"; 246 newmsgstatusenuumb7 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 7"; 247 notfullstatusenuumb6 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 6"; 248 newmsgstatusenuumb6 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 6"; 249 notfullstatusenuumb5 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 5"; 250 newmsgstatusenuumb5 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 5"; 251 notfullstatusenuumb4 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 4"; 252 newmsgstatusenuumb4 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 4"; 253 notfullstatusenuumb3 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 3"; 254 newmsgstatusenuumb3 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 3"; 255 notfullstatusenuumb2 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 2"; 256 newmsgstatusenuumb2 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 2"; 257 notfullstatusenuumb1 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 1"; 258 newmsgstatusenuumb1 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 1"; 259 notfullstatusenuumb0 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 0"; 260 newmsgstatusenuumb0 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 0"; 261 }; 262 263 register mailbox_irqstatus_clr_u_1 addr(base, 0x114) "The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" { 264 _ 16 mbz; 265 notfullstatusenuumb7 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 7"; 266 newmsgstatusenuumb7 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 7"; 267 notfullstatusenuumb6 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 6"; 268 newmsgstatusenuumb6 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 6"; 269 notfullstatusenuumb5 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 5"; 270 newmsgstatusenuumb5 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 5"; 271 notfullstatusenuumb4 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 4"; 272 newmsgstatusenuumb4 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 4"; 273 notfullstatusenuumb3 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 3"; 274 newmsgstatusenuumb3 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 3"; 275 notfullstatusenuumb2 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 2"; 276 newmsgstatusenuumb2 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 2"; 277 notfullstatusenuumb1 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 1"; 278 newmsgstatusenuumb1 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 1"; 279 notfullstatusenuumb0 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 0"; 280 newmsgstatusenuumb0 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 0"; 281 }; 282 283 register mailbox_irqstatus_clr_u_2 addr(base, 0x124) "The interrupt status register has the status combined with irq-enable for each event that may be responsible for the generation of an interrupt to the corresponding user - write 1 to a given bit resets this bit" { 284 _ 16 mbz; 285 notfullstatusenuumb7 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 7"; 286 newmsgstatusenuumb7 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 7"; 287 notfullstatusenuumb6 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 6"; 288 newmsgstatusenuumb6 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 6"; 289 notfullstatusenuumb5 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 5"; 290 newmsgstatusenuumb5 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 5"; 291 notfullstatusenuumb4 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 4"; 292 newmsgstatusenuumb4 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 4"; 293 notfullstatusenuumb3 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 3"; 294 newmsgstatusenuumb3 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 3"; 295 notfullstatusenuumb2 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 2"; 296 newmsgstatusenuumb2 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 2"; 297 notfullstatusenuumb1 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 1"; 298 newmsgstatusenuumb1 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 1"; 299 notfullstatusenuumb0 1 rw type(notfullstatusenuumb7_status1) "NotFull Status bit for User u, Mailbox 0"; 300 newmsgstatusenuumb0 1 rw type(newmsgstatusenuumb7_status) "NewMessage Status bit for User u, Mailbox 0"; 301 }; 302 303 constants notfullenableuumb7_status width(1) "" { 304 NOTFULLENABLEUUMB7_0_r = 0 "Interupt disabled"; 305 NOTFULLENABLEUUMB7_0_w = 0 "No action"; 306 NOTFULLENABLEUUMB7_1_r = 1 "Interrupt enabled"; 307 NOTFULLENABLEUUMB7_1_w = 1 "Enable interrupt"; 308 }; 309 310 register mailbox_irqenable_set_u_0 addr(base, 0x108) "The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." { 311 _ 16 mbz; 312 notfullenableuumb7 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 7"; 313 newmsgenableuumb7 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 7"; 314 notfullenableuumb6 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 6"; 315 newmsgenableuumb6 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 6"; 316 notfullenableuumb5 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 5"; 317 newmsgenableuumb5 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 5"; 318 notfullenableuumb4 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 4"; 319 newmsgenableuumb4 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 4"; 320 notfullenableuumb3 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 3"; 321 newmsgenableuumb3 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 3"; 322 notfullenableuumb2 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 2"; 323 newmsgenableuumb2 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 2"; 324 notfullenableuumb1 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 1"; 325 newmsgenableuumb1 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 1"; 326 notfullenableuumb0 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 0"; 327 newmsgenableuumb0 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 0"; 328 }; 329 330 register mailbox_irqenable_set_u_1 addr(base, 0x118) "The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." { 331 _ 16 mbz; 332 notfullenableuumb7 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 7"; 333 newmsgenableuumb7 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 7"; 334 notfullenableuumb6 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 6"; 335 newmsgenableuumb6 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 6"; 336 notfullenableuumb5 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 5"; 337 newmsgenableuumb5 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 5"; 338 notfullenableuumb4 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 4"; 339 newmsgenableuumb4 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 4"; 340 notfullenableuumb3 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 3"; 341 newmsgenableuumb3 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 3"; 342 notfullenableuumb2 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 2"; 343 newmsgenableuumb2 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 2"; 344 notfullenableuumb1 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 1"; 345 newmsgenableuumb1 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 1"; 346 notfullenableuumb0 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 0"; 347 newmsgenableuumb0 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 0"; 348 }; 349 350 register mailbox_irqenable_set_u_2 addr(base, 0x128) "The interrupt enable register enables to unmask the module internal source of interrupt to the corresponding user. This register is write 1 to set." { 351 _ 16 mbz; 352 notfullenableuumb7 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 7"; 353 newmsgenableuumb7 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 7"; 354 notfullenableuumb6 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 6"; 355 newmsgenableuumb6 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 6"; 356 notfullenableuumb5 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 5"; 357 newmsgenableuumb5 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 5"; 358 notfullenableuumb4 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 4"; 359 newmsgenableuumb4 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 4"; 360 notfullenableuumb3 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 3"; 361 newmsgenableuumb3 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 3"; 362 notfullenableuumb2 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 2"; 363 newmsgenableuumb2 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 2"; 364 notfullenableuumb1 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 1"; 365 newmsgenableuumb1 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 1"; 366 notfullenableuumb0 1 rw type(notfullenableuumb7_status) "NotFull Enable bit for User u, Mailbox 0"; 367 newmsgenableuumb0 1 rw type(notfullenableuumb7_status) "NewMessage Enable bit for User u, Mailbox 0"; 368 }; 369 370 constants notfullenableuumb7_status1 width(1) "" { 371 NOTFULLENABLEUUMB7_0_r_3 = 0 "Interupt disabled"; 372 NOTFULLENABLEUUMB7_0_w_3 = 0 "No action"; 373 NOTFULLENABLEUUMB7_1_r_3 = 1 "Interrupt enabled"; 374 NOTFULLENABLEUUMB7_1_w_3 = 1 "Disable interrupt"; 375 }; 376 377 register mailbox_irqenable_clr_u_0 addr(base, 0x10C) "The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." { 378 _ 16 mbz; 379 notfullenableuumb7 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 7"; 380 newmsgenableuumb7 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 7"; 381 notfullenableuumb6 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 6"; 382 newmsgenableuumb6 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 6"; 383 notfullenableuumb5 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 5"; 384 newmsgenableuumb5 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 5"; 385 notfullenableuumb4 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 4"; 386 newmsgenableuumb4 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 4"; 387 notfullenableuumb3 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 3"; 388 newmsgenableuumb3 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 3"; 389 notfullenableuumb2 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 2"; 390 newmsgenableuumb2 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 2"; 391 notfullenableuumb1 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 1"; 392 newmsgenableuumb1 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 1"; 393 notfullenableuumb0 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 0"; 394 newmsgenableuumb0 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 0"; 395 }; 396 397 register mailbox_irqenable_clr_u_1 addr(base, 0x11C) "The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." { 398 _ 16 mbz; 399 notfullenableuumb7 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 7"; 400 newmsgenableuumb7 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 7"; 401 notfullenableuumb6 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 6"; 402 newmsgenableuumb6 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 6"; 403 notfullenableuumb5 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 5"; 404 newmsgenableuumb5 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 5"; 405 notfullenableuumb4 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 4"; 406 newmsgenableuumb4 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 4"; 407 notfullenableuumb3 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 3"; 408 newmsgenableuumb3 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 3"; 409 notfullenableuumb2 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 2"; 410 newmsgenableuumb2 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 2"; 411 notfullenableuumb1 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 1"; 412 newmsgenableuumb1 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 1"; 413 notfullenableuumb0 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 0"; 414 newmsgenableuumb0 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 0"; 415 }; 416 417 register mailbox_irqenable_clr_u_2 addr(base, 0x12C) "The interrupt enable register enables to mask the module internal source of interrupt to the corresponding user. This register is write 1 to clear." { 418 _ 16 mbz; 419 notfullenableuumb7 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 7"; 420 newmsgenableuumb7 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 7"; 421 notfullenableuumb6 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 6"; 422 newmsgenableuumb6 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 6"; 423 notfullenableuumb5 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 5"; 424 newmsgenableuumb5 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 5"; 425 notfullenableuumb4 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 4"; 426 newmsgenableuumb4 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 4"; 427 notfullenableuumb3 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 3"; 428 newmsgenableuumb3 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 3"; 429 notfullenableuumb2 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 2"; 430 newmsgenableuumb2 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 2"; 431 notfullenableuumb1 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 1"; 432 newmsgenableuumb1 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 1"; 433 notfullenableuumb0 1 rw type(notfullenableuumb7_status1) "NotFull Enable bit for User u, Mailbox 0"; 434 newmsgenableuumb0 1 rw type(notfullenableuumb7_status1) "NewMessage Enable bit for User u, Mailbox 0"; 435 }; 436};