1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_sgx_prm.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_sgx_prm msbfirst ( addr base ) "" { 29 30 31 constants sgx_mem_onstate_status width(2) "" { 32 SGX_MEM_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON."; 33 }; 34 35 constants lowpowerstatechange_status width(1) "" { 36 LOWPOWERSTATECHANGE_0 = 0 "Do not request a low power state change."; 37 LOWPOWERSTATECHANGE_1 = 1 "Request a low power state change. This bit is automatically cleared when the power state is effectively changed or when power state is ON."; 38 }; 39 40 constants powerstate_status width(2) "" { 41 POWERSTATE_0 = 0 "OFF state"; 42 POWERSTATE_1 = 1 "Reserved"; 43 POWERSTATE_2 = 2 "INACTIVE state"; 44 POWERSTATE_3 = 3 "ON State"; 45 }; 46 47 register pm_sgx_pwrstctrl addr(base, 0x0) "This register controls the SGX power state to reach upon a domain sleep transition" { 48 _ 14 mbz; 49 sgx_mem_onstate 2 ro type(sgx_mem_onstate_status) "SGX_MEM memory bank state when domain is ON."; 50 _ 11 mbz; 51 lowpowerstatechange 1 rw type(lowpowerstatechange_status) "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."; 52 _ 2 mbz; 53 powerstate 2 rw type(powerstate_status) "Power state control"; 54 }; 55 56 constants lastpowerstateentered_status width(2) "" { 57 LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously OFF"; 58 LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously in RETENTION"; 59 LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously ON-INACTIVE"; 60 LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously ON-ACTIVE"; 61 }; 62 63 constants intransition_status width(1) "" { 64 INTRANSITION_0_r = 0 "No ongoing transition on power domain"; 65 INTRANSITION_1_r = 1 "Power domain transition is in progress."; 66 }; 67 68 constants sgx_mem_statest_status width(2) "" { 69 SGX_MEM_STATEST_0_r = 0 "Memory is OFF"; 70 SGX_MEM_STATEST_1_r = 1 "Reserved"; 71 SGX_MEM_STATEST_2_r = 2 "Reserved"; 72 SGX_MEM_STATEST_3_r = 3 "Memory is ON"; 73 }; 74 75 constants logicstatest_status width(1) "" { 76 LOGICSTATEST_0_r = 0 "Logic in domain is OFF"; 77 LOGICSTATEST_1_r = 1 "Logic in domain is ON"; 78 }; 79 80 constants powerstatest_status width(2) "" { 81 POWERSTATEST_0_r = 0 "Power domain is OFF"; 82 POWERSTATEST_1_r = 1 "Power domain is in RETENTION"; 83 POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE"; 84 POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE"; 85 }; 86 87 register pm_sgx_pwrstst addr(base, 0x4) "This register provides a status on the current SGX power domain state. [warm reset insensitive]" { 88 _ 6 mbz; 89 lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only."; 90 _ 3 mbz; 91 intransition 1 ro type(intransition_status) "Domain transition status"; 92 _ 14 mbz; 93 sgx_mem_statest 2 ro type(sgx_mem_statest_status) "SGX_MEM memory bank state status"; 94 _ 1 mbz; 95 logicstatest 1 ro type(logicstatest_status) "Logic state status"; 96 powerstatest 2 ro type(powerstatest_status) "Current power state status"; 97 }; 98 99 constants lostmem_sgx_mem_status width(1) "" { 100 LOSTMEM_SGX_MEM_0 = 0 "Context has been maintained"; 101 LOSTMEM_SGX_MEM_1 = 1 "Context has been lost"; 102 }; 103 104 register rm_sgx_sgx_context addr(base, 0x24) "This register contains dedicated SGX context statuses. [warm reset insensitive]" { 105 _ 23 mbz; 106 lostmem_sgx_mem 1 rw1c type(lostmem_sgx_mem_status) "Specify if memory-based context in SGX_MEM memory bank has been lost due to a previous power transition or other reset source."; 107 _ 7 mbz; 108 lostcontext_dff 1 rw1c type(lostmem_sgx_mem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of SGX_RST signal)"; 109 }; 110};