1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_ocp2scp.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_ocp2scp msbfirst ( addr base ) "" { 29 30 31 register ocp2scp_revision ro addr(base, 0x0) "IP revision identifier" type(uint32); 32 33 constants idlemode_status width(2) "" { 34 IDLEMODE_0 = 0 "Force-idle mode. An idle request is acknowledged unconditionally."; 35 IDLEMODE_1 = 1 "No-idle mode. An idle request is never acknowledged."; 36 IDLEMODE_2 = 2 "Smart-idle mode. The acknowledgment to an idle request is given based on the internal activity."; 37 IDLEMODE_3 = 3 "Reserved"; 38 }; 39 40 constants softreset_status width(1) "" { 41 SOFTRESET_0 = 0 "Normal mode"; 42 SOFTRESET_1 = 1 "The module is reset."; 43 }; 44 45 constants autoidle_status width(1) "" { 46 AUTOIDLE_0 = 0 "Internal interface OCP clock is free-running."; 47 AUTOIDLE_1 = 1 "Automatic internal OCP clock gating, based on the OCP interface activity"; 48 }; 49 50 register ocp2scp_sysconfig addr(base, 0x10) "System configuration register" { 51 _ 27 mbz; 52 idlemode 2 rw type(idlemode_status) "Module power management control"; 53 _ 1 mbz; 54 softreset 1 rw type(softreset_status) "Software reset. Set this bit to 1 to trigger a module reset. During reads, it always returns 0."; 55 autoidle 1 rw type(autoidle_status) "OCP clock-gating control"; 56 }; 57 58 constants resetdone_status width(1) "" { 59 RESETDONE_1 = 1 "Reset is complete."; 60 }; 61 62 register ocp2scp_sysstatus addr(base, 0x14) "System status register" { 63 _ 31 mbz; 64 resetdone 1 ro type(resetdone_status) "0: Internal reset is on-going."; 65 }; 66 67 register ocp2scp_timing addr(base, 0x18) "Timing configuration register" { 68 _ 22 mbz; 69 divisionratio 3 rw "Division ratio of the SCP clock in relation to the OCP input clock. When the value 0x0 is programmed, and the transaction to be made is a valid transaction on the SCP interface, the value of DIVISIONRATIO is set to 0x7 by hardware to avoid a block on the OCP interface.CAUTION:To ensure correct operation, DIVISIONRATIO must not be modified. See also the SYNC2 description. ."; 70 sync1 3 rw "Number of SCP clock cycles defining SYNC1 delay"; 71 sync2 4 ro "Number of SCP clock cycles defining the SYNC2 delay. When the value 0x0 is programmed, and the transaction to be made is a valid transaction on the SCP interface, SYNC2 is set to the minimum allowed value 0x1 to avoid a block on the OCP interface.CAUTION:To ensure correct operation, the value of SYNC2 must be set to 0x6 or more. RW 0x1 ."; 72 }; 73};