1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_mpu_prm.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_mpu_prm msbfirst ( addr base ) "" { 29 30 31 constants mpu_ram_onstate_status width(2) "" { 32 MPU_RAM_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON."; 33 }; 34 35 constants mpu_ram_retstate_status width(1) "" { 36 MPU_RAM_RETSTATE_1_r = 1 "Memory bank is retained when domain is in RETENTION state."; 37 }; 38 39 constants mpu_l2_retstate_status width(1) "" { 40 MPU_L2_RETSTATE_0 = 0 "Memory bank is off when the domain is in the RETENTION state."; 41 MPU_L2_RETSTATE_1 = 1 "Memory bank is retained when domain is in RETENTION state."; 42 }; 43 44 constants lowpowerstatechange_status width(1) "" { 45 LOWPOWERSTATECHANGE_0 = 0 "Do not request a low power state change."; 46 LOWPOWERSTATECHANGE_1 = 1 "Request a low power state change. This bit is automatically cleared when the power state is effectively changed or when power state is ON."; 47 }; 48 49 constants powerstate_status width(2) "" { 50 POWERSTATE_0 = 0 "Reserved"; 51 POWERSTATE_1 = 1 "RETENTION state"; 52 POWERSTATE_2 = 2 "INACTIVE state"; 53 POWERSTATE_3 = 3 "ON State"; 54 }; 55 56 register pm_mpu_pwrstctrl addr(base, 0x0) "This register controls the MPU domain power state to reach upon a domain sleep transition" { 57 _ 10 mbz; 58 mpu_ram_onstate 2 ro type(mpu_ram_onstate_status) "MPU_RAM memory state when domain is ON."; 59 mpu_l2_onstate 2 ro type(mpu_ram_onstate_status) "MPU_L2 memory state when domain is ON."; 60 _ 7 mbz; 61 mpu_ram_retstate 1 ro type(mpu_ram_retstate_status) "MPU_RAM memory state when domain is RETENTION."; 62 mpu_l2_retstate 1 rw type(mpu_l2_retstate_status) "MPU_L2 memory state when domain is RETENTION."; 63 _ 4 mbz; 64 lowpowerstatechange 1 rw type(lowpowerstatechange_status) "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."; 65 _ 1 mbz; 66 logicretstate 1 rw type(mpu_l2_retstate_status) "Logic state when power domain is RETENTION"; 67 powerstate 2 rw type(powerstate_status) "Power state control."; 68 }; 69 70 constants lastpowerstateentered_status width(2) "" { 71 LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously ON-ACTIVE"; 72 LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously ON-INACTIVE"; 73 LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously in RETENTION"; 74 LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously OFF"; 75 }; 76 77 constants intransition_status width(1) "" { 78 INTRANSITION_0_r = 0 "No ongoing transition on power domain"; 79 INTRANSITION_1_r = 1 "Power domain transition is in progress."; 80 }; 81 82 constants mpu_ram_statest_status width(2) "" { 83 MPU_RAM_STATEST_0_r = 0 "Memory is OFF"; 84 MPU_RAM_STATEST_1_r = 1 "Memory is RETENTION"; 85 MPU_RAM_STATEST_2_r = 2 "Reserved"; 86 MPU_RAM_STATEST_3_r = 3 "Memory is ON"; 87 }; 88 89 constants logicstatest_status width(1) "" { 90 LOGICSTATEST_0_r = 0 "Logic in domain is OFF"; 91 LOGICSTATEST_1_r = 1 "Logic in domain is ON"; 92 }; 93 94 constants powerstatest_status width(2) "" { 95 POWERSTATEST_0_r = 0 "Power domain is OFF"; 96 POWERSTATEST_1_r = 1 "Power domain is in RETENTION"; 97 POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE"; 98 POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE"; 99 }; 100 101 register pm_mpu_pwrstst addr(base, 0x4) "This register provides a status on the MPU domain current power state. [warm reset insensitive]" { 102 _ 6 mbz; 103 lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only."; 104 _ 3 mbz; 105 intransition 1 ro type(intransition_status) "Domain transition status"; 106 _ 10 mbz; 107 mpu_ram_statest 2 ro type(mpu_ram_statest_status) "MPU_RAM memory state status"; 108 mpu_l2_statest 2 ro type(mpu_ram_statest_status) "MPU_L2 memory state status"; 109 _ 3 mbz; 110 logicstatest 1 ro type(logicstatest_status) "Logic state status"; 111 powerstatest 2 ro type(powerstatest_status) "Current power state status"; 112 }; 113 114 constants emulation_rst_status width(1) "" { 115 EMULATION_RST_0 = 0 "No emulation reset"; 116 EMULATION_RST_1 = 1 "The domain has been reset upon emulation reset"; 117 }; 118 119 register rm_mpu_rstst addr(base, 0x14) "This register logs the different reset sources of the MPU domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" { 120 _ 31 mbz; 121 emulation_rst 1 rw1c type(emulation_rst_status) "MPU domain has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module"; 122 }; 123 124 constants lostmem_mpu_ram_status width(1) "" { 125 LOSTMEM_MPU_RAM_0 = 0 "Context has been maintained"; 126 LOSTMEM_MPU_RAM_1 = 1 "Context has been lost"; 127 }; 128 129 register rm_mpu_mpu_context addr(base, 0x24) "This register contains dedicated MPU context statuses. [warm reset insensitive]" { 130 _ 21 mbz; 131 lostmem_mpu_ram 1 rw1c type(lostmem_mpu_ram_status) "Specify if memory-based context in MPU_RAM memory bank has been lost due to a previous power transition or other reset source (not affected by a global warm reset)."; 132 lostmem_mpu_l2 1 rw1c type(lostmem_mpu_ram_status) "Specify if memory-based context in MPU_L2 memory bank has been lost due to a previous power transition or other reset source."; 133 _ 7 mbz; 134 lostcontext_rff 1 rw1c type(lostmem_mpu_ram_status) "Specify if RFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of MPU_MA_PWRON_RET_RST signal)"; 135 lostcontext_dff 1 rw1c type(lostmem_mpu_ram_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of MPU_RST signal)"; 136 }; 137};