1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_mmchs3.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_mmchs3 msbfirst ( addr base ) "" { 29 30 31 register mmchs_hl_rev ro addr(base, 0x0) "IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" type(uint32); 32 33 constants retmode_status width(1) "" { 34 RETMODE_0 = 0 "Retention mode disabled"; 35 RETMODE_1 = 1 "Retention mode enabled"; 36 }; 37 38 constants mem_size_status width(4) "" { 39 MEM_SIZE_1_r = 1 "Memory of 512 bytes, max block length is 512 bytes"; 40 MEM_SIZE_2_r = 2 "Memory of 1024 bytes, max block length is 1024 bytes"; 41 MEM_SIZE_4_r = 4 "Memory of 2048 bytes, max block length is 2048 bytes"; 42 MEM_SIZE_8_r = 8 "Memory of 4096 bytes, max block length is 2048 bytes"; 43 }; 44 45 constants merge_mem_status width(1) "" { 46 MERGE_MEM_0_r = 0 "2 memories instantiated, one per data transfer direction."; 47 MERGE_MEM_1_r = 1 "A single memory is used with multiplexed addresses, data and clocks."; 48 }; 49 50 constants madma_en_status width(1) "" { 51 MADMA_EN_0_r = 0 "No Master DMA (ADMA) management supported"; 52 MADMA_EN_1_r = 1 "Controller supports ADMA"; 53 }; 54 55 register mmchs_hl_hwinfo addr(base, 0x4) "Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." { 56 _ 25 mbz; 57 retmode 1 ro type(retmode_status) "Retention mode generic parameter This bit field indicates whether the retention mode is supported using the pin PIRFFRET."; 58 mem_size 4 ro type(mem_size_status) "Memory size for FIFO buffer:"; 59 merge_mem 1 ro type(merge_mem_status) "Memory merged for FIFO buffer: This register defines the configuration of FIFO buffer architecture. If the bit is set STA and DFT shall support clock multiplexing and balancing."; 60 madma_en 1 ro type(madma_en_status) "Master DMA enabled generic parameter: This register defines the configuration of the controller to know if it supports the master DMA management called ADMA."; 61 }; 62 63 constants standbymode_status width(2) "" { 64 STANDBYMODE_0 = 0 "Force-standby mode: local initiator is unconditionally placed in standby state.Backup mode, for debug only."; 65 STANDBYMODE_1 = 1 "No-standby mode: local initiator is unconditionally placed out of standby state.Backup mode, for debug only."; 66 STANDBYMODE_2 = 2 "Smart-standby mode: local initiator standby status depends on local conditions, that is, the module's functional requirement from the initiator.IP module shall not generate (initiator-related) wakeup events."; 67 STANDBYMODE_3 = 3 "Smart-Standby wakeup-capable mode: local initiator standby status depends on local conditions, that is, the module's functional requirement from the initiator. IP module may generate (master-related) wakeup events when in standby state.Mode is only relevant if the appropriate IP module 'mwakeup' output is implemented."; 68 }; 69 70 constants idlemode_status width(2) "" { 71 IDLEMODE_0 = 0 "Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, that is, regardless of the IP module's internal requirements.Backup mode, for debug only."; 72 IDLEMODE_1 = 1 "No-idle mode: local target never enters idle state.Backup mode, for debug only."; 73 IDLEMODE_2 = 2 "Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements.IP module shall not generate (IRQ- or DMA-request-related) wakeup events."; 74 IDLEMODE_3 = 3 "Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements.IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state.Mode is only relevant if the appropriate IP module 'swakeup' output(s) is (are) implemented."; 75 }; 76 77 constants freeemu_status width(1) "" { 78 FREEEMU_0 = 0 "IP module is sensitive to emulation suspend"; 79 FREEEMU_1 = 1 "IP module is not sensitive to emulation suspend"; 80 }; 81 82 constants softreset_status width(1) "" { 83 SOFTRESET_0_w = 0 "No action"; 84 SOFTRESET_0_r = 0 "Reset done, no pending action"; 85 SOFTRESET_1_r = 1 "Reset (software or other) ongoing"; 86 SOFTRESET_1_w = 1 "Initiate software reset"; 87 }; 88 89 register mmchs_hl_sysconfig addr(base, 0x10) "Clock management configuration" { 90 _ 26 mbz; 91 standbymode 2 rw type(standbymode_status) "Configuration of the local initiator state management mode. By definition, initiator may generate read/write transaction as long as it is out of STANDBY state."; 92 idlemode 2 rw type(idlemode_status) "Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state."; 93 freeemu 1 rw type(freeemu_status) "Sensitivity to emulation (debug) suspend input signal. Functionality NOT implemented in MMCHS."; 94 softreset 1 rw type(softreset_status) "Software reset. (Optional)"; 95 }; 96 97 constants standbymode_status1 width(2) "" { 98 STANDBYMODE_0_1 = 0 "Force-standby. Mstandby is forced unconditionnaly."; 99 STANDBYMODE_1_1 = 1 "No-standby. Mstandby is never asserted."; 100 STANDBYMODE_2_1 = 2 "Smart-standby mode: local initiator standby status depends on local conditions, that is, the module's functional requirement from the initiator.IP module shall not generate (initiator-related) wakeup events."; 101 STANDBYMODE_3_1 = 3 "Smart-Standby wakeup-capable mode: local initiator standby status depends on local conditions, that is, the module's functional requirement from the initiator. IP module may generate (master-related) wakeup events when in standby state.Mode is only relevant if the appropriate IP module 'mwakeup' output is implemented."; 102 }; 103 104 constants clockactivity_status width(2) "" { 105 CLOCKACTIVITY_0 = 0 "Interface and Functional clock may be switched off."; 106 CLOCKACTIVITY_1 = 1 "Interface clock is maintained. Functional clock may be switched-off."; 107 CLOCKACTIVITY_2 = 2 "Functional clock is maintained. Interface clock may be switched-off."; 108 CLOCKACTIVITY_3 = 3 "Interface and Functional clocks are maintained."; 109 }; 110 111 constants sidlemode_status width(2) "" { 112 SIDLEMODE_0 = 0 "If an idle request is detected, the MMCHS acknowledges it unconditionally and goes in Inactive mode. Interrupt and DMA requests are unconditionally de-asserted."; 113 SIDLEMODE_1 = 1 "If an idle request is detected, the request is ignored and the module keeps on behaving normally."; 114 SIDLEMODE_2 = 2 "Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements.IP module shall not generate (IRQ- or DMA-request-related) wakeup events."; 115 SIDLEMODE_3 = 3 "Smart-idle wakeup-capable mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements.IP module may generate (IRQ- or DMA-request-related) wakeup events when in idle state.Mode is only relevant if the appropriate IP module 'swakeup' output(s) is (are) implemented."; 116 }; 117 118 constants enawakeup_status width(1) "" { 119 ENAWAKEUP_0 = 0 "Wakeup capability is disabled"; 120 ENAWAKEUP_1 = 1 "Wakeup capability is enabled"; 121 }; 122 123 constants softreset_status1 width(1) "" { 124 SOFTRESET_0_r_1 = 0 "Normal mode"; 125 SOFTRESET_0_w_1 = 0 "No effect."; 126 SOFTRESET_1_w_1 = 1 "Trigger a module reset."; 127 SOFTRESET_1_r_1 = 1 "The module is reset."; 128 }; 129 130 constants autoidle_status width(1) "" { 131 AUTOIDLE_0 = 0 "Clocks are free-running"; 132 AUTOIDLE_1 = 1 "Automatic clock gating strategy is applied, based on the Interconnect and MMC interface activity"; 133 }; 134 135 register mmchs_sysconfig addr(base, 0x110) "System Configuration Register This register allows controlling various parameters of the Interconnect interface." { 136 _ 18 mbz; 137 standbymode 2 rw type(standbymode_status1) "Master interface power Management, standby/wait control. The bit field is only useful when generic parameter MMCHS_HL_HWINFO[0] MADMA_EN (Master ADMA enable) is set as active, otherwise it is a read only register read a 0."; 138 _ 2 mbz; 139 clockactivity 2 rw type(clockactivity_status) "Clocks activity during wake up mode period. Bit8: Interface clock Bit9: Functional clock"; 140 _ 1 mbz; 141 _ 1 mbz; 142 _ 1 mbz; 143 sidlemode 2 rw type(sidlemode_status) "Power management"; 144 enawakeup 1 rw type(enawakeup_status) "Wakeup feature control"; 145 softreset 1 rw type(softreset_status1) "Software reset. The bit is automatically reset by the hardware. During reset, it always returns 0."; 146 autoidle 1 rw type(autoidle_status) "Internal Clock gating strategy"; 147 }; 148 149 constants resetdone_status width(1) "" { 150 RESETDONE_0_r = 0 "Internal module reset is on-going"; 151 RESETDONE_1_r = 1 "Reset completed."; 152 }; 153 154 register mmchs_sysstatus addr(base, 0x114) "System Status Register This register provides status information about the module excluding the interrupt status information" { 155 _ 31 mbz; 156 resetdone 1 ro type(resetdone_status) "Internal Reset Monitoring Note: the debounce clock , the system clock (Interface) and the functional clock shall be provided to the MMC/SD/SDIO host controller to allow the internal reset monitoring."; 157 }; 158 159 register mmchs_csre rw addr(base, 0x124) "Card status response error This register enables the host controller to detect card status errors of response type R1, R1b for all cards and of R5, R5b and R6 response for cards types SD or SDIO. When a bit [i] is set to 1, if the corresponding bit at the same position in the response [i] is set to 1, the host controller indicates a card error ([CERR]) interrupt status to avoid the host driver reading the response register (). Note: No automatic card error detection for autoCMD12 is implemented; the host system has to check autoCMD12 response register () for possible card errors." type(uint32); 160 161 constants sdcd_status width(1) "" { 162 SDCD_0_r = 0 "The card detect pin is driven low."; 163 SDCD_1_r = 1 "The card detect pin is driven high."; 164 }; 165 166 constants sdwp_status width(1) "" { 167 SDWP_0_r = 0 "The write protect pin SDWP is driven low."; 168 SDWP_1_r = 1 "The write protect pin SDWP is driven high."; 169 }; 170 171 constants wakd_status width(1) "" { 172 WAKD_0_w = 0 "The pin SWAKEUP is driven low."; 173 WAKD_0_r = 0 "No action. Returns 0."; 174 WAKD_1_w = 1 "The pin SWAKEUP is driven high."; 175 WAKD_1_r = 1 "No action. Returns 1."; 176 }; 177 178 constants ssb_status width(1) "" { 179 SSB_0_w = 0 "Clear this SSB bit field. Writing 0 does not clear already set status bits;"; 180 SSB_0_r = 0 "No action. Returns 0."; 181 SSB_1_r = 1 "No action. Returns 1."; 182 SSB_1_w = 1 "Force to 1 all status bits of the interrupt status register () only if the corresponding bit field in the Interrupt signal enable register () is set."; 183 }; 184 185 constants d7d_status width(1) "" { 186 D7D_0_r = 0 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT7 line (low). If [3] DDIR = 0 (output mode direction), returns 0"; 187 D7D_0_w = 0 "If[3] DDIR = 0 (output mode direction), the DAT7 line is driven low. If [3] DDIR = 1 (input mode direction), no effect."; 188 D7D_1_r = 1 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT7 line (high) If [3] DDIR = 0 (output mode direction), returns 1"; 189 D7D_1_w = 1 "If[3] DDIR = 0 (output mode direction), the DAT7 line is driven high. If [3] DDIR = 1 (input mode direction), no effect."; 190 }; 191 192 constants d6d_status width(1) "" { 193 D6D_0_r = 0 "If SYSTEST[DDIR] = 1 (input mode direction), returns the value on the DAT6 line (low). If [3] DDIR = 0 (output mode direction), returns 0"; 194 D6D_0_w = 0 "If[3] DDIR = 0 (output mode direction), the DAT6 line is driven low. If [3] DDIR = 1 (input mode direction), no effect."; 195 D6D_1_r = 1 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT6 line (high) If [3] DDIR = 0 (output mode direction), returns 1"; 196 D6D_1_w = 1 "If[3] DDIR = 0 (output mode direction), the DAT6 line is driven high. If [3] DDIR = 1 (input mode direction), no effect."; 197 }; 198 199 constants d5d_status width(1) "" { 200 D5D_0_r = 0 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT5 line (low). If [3] DDIR = 0 (output mode direction), returns 0"; 201 D5D_0_w = 0 "If[3] DDIR = 0 (output mode direction), the DAT5 line is driven low. If [3] DDIR = 1 (input mode direction), no effect."; 202 D5D_1_r = 1 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT5 line (high) If [3] DDIR = 0 (output mode direction), returns 1"; 203 D5D_1_w = 1 "If[3] DDIR = 0 (output mode direction), the DAT5 line is driven high. If [3] DDIR = 1 (input mode direction), no effect."; 204 }; 205 206 constants d4d_status width(1) "" { 207 D4D_0_w = 0 "If[3] DDIR = 0 (output mode direction), the DAT4 line is driven low. If [3] DDIR = 1 (input mode direction), no effect."; 208 D4D_0_r = 0 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT4 line (low). If [3] DDIR = 0 (output mode direction), returns 0"; 209 D4D_1_w = 1 "If[3] DDIR = 0 (output mode direction), the DAT4 line is driven high. If [3] DDIR = 1 (input mode direction), no effect."; 210 D4D_1_r = 1 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT4 line (high) If [3] DDIR = 0 (output mode direction), returns 1"; 211 }; 212 213 constants d3d_status width(1) "" { 214 D3D_0_w = 0 "If[3] DDIR = 0 (output mode direction), the DAT3 line is driven low. If [3] DDIR = 1 (input mode direction), no effect."; 215 D3D_0_r = 0 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT3 line (low). If [3] DDIR = 0 (output mode direction), returns 0"; 216 D3D_1_r = 1 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT3 line (high) If [3] DDIR = 0 (output mode direction), returns 1"; 217 D3D_1_w = 1 "If[3] DDIR = 0 (output mode direction), the DAT3 line is driven high. If [3] DDIR = 1 (input mode direction), no effect."; 218 }; 219 220 constants d2d_status width(1) "" { 221 D2D_0_w = 0 "If[3] DDIR = 0 (output mode direction), the DAT2 line is driven low. If [3] DDIR = 1 (input mode direction), no effect."; 222 D2D_0_r = 0 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT2 line (low). If [3] DDIR = 0 (output mode direction), returns 0"; 223 D2D_1_w = 1 "If[3] DDIR = 0 (output mode direction), the DAT2 line is driven high. If [3] DDIR = 1 (input mode direction), no effect."; 224 D2D_1_r = 1 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT2 line (high) If [3] DDIR = 0 (output mode direction), returns 1"; 225 }; 226 227 constants d1d_status width(1) "" { 228 D1D_0_r = 0 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT1 line (low). If [3] DDIR = 0 (output mode direction), returns 0"; 229 D1D_0_w = 0 "If[3] DDIR = 0 (output mode direction), the DAT1 line is driven low. If [3] DDIR = 1 (input mode direction), no effect."; 230 D1D_1_r = 1 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT1 line (high) If [3] DDIR = 0 (output mode direction), returns 1"; 231 D1D_1_w = 1 "If[3] DDIR = 0 (output mode direction), the DAT1 line is driven high. If [3] DDIR = 1 (input mode direction), no effect."; 232 }; 233 234 constants d0d_status width(1) "" { 235 D0D_0_w = 0 "If[3] DDIR = 0 (output mode direction), the DAT0 line is driven low. If [3] DDIR = 1 (input mode direction), no effect."; 236 D0D_0_r = 0 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT0 line (low). If [3] DDIR = 0 (output mode direction), returns 0"; 237 D0D_1_w = 1 "If[3] DDIR = 0 (output mode direction), the DAT0 line is driven high. If [3] DDIR = 1 (input mode direction), no effect."; 238 D0D_1_r = 1 "If[3] DDIR = 1 (input mode direction), returns the value on the DAT0 line (high) If [3] DDIR = 0 (output mode direction), returns 1"; 239 }; 240 241 constants ddir_status width(1) "" { 242 DDIR_0_w = 0 "The DAT lines are outputs (host to card)"; 243 DDIR_0_r = 0 "No action. Returns 0."; 244 DDIR_1_r = 1 "No action. Returns 1."; 245 DDIR_1_w = 1 "The DAT lines are inputs (card to host)"; 246 }; 247 248 constants cdat_status width(1) "" { 249 CDAT_0_w = 0 "If[1] CDIR = 0 (output mode direction), the CMD line is driven low. If [1] CDIR = 1 (input mode direction), no effect."; 250 CDAT_0_r = 0 "If[1] CDIR = 1 (input mode direction), returns the value on the CMD line (low). If [1] CDIR = 0 (output mode direction), returns 0"; 251 CDAT_1_w = 1 "If[1] CDIR = 0 (output mode direction), the CMD line is driven high. If [1] CDIR = 1 (input mode direction), no effect."; 252 CDAT_1_r = 1 "If[1] CDIR = 1 (input mode direction), returns the value on the CMD line (high) If [1] CDIR = 0 (output mode direction), returns 1"; 253 }; 254 255 constants cdir_status width(1) "" { 256 CDIR_0_r = 0 "No action. Returns 0."; 257 CDIR_0_w = 0 "The CMD line is an output (host to card)"; 258 CDIR_1_r = 1 "No action. Returns 1."; 259 CDIR_1_w = 1 "The CMD line is an input (card to host)"; 260 }; 261 262 constants mckd_status width(1) "" { 263 MCKD_0_r = 0 "No action. Returns 0."; 264 MCKD_0_w = 0 "The output clock is driven low."; 265 MCKD_1_w = 1 "The output clock is driven high."; 266 MCKD_1_r = 1 "No action. Returns 1."; 267 }; 268 269 register mmchs_systest addr(base, 0x128) "System Test register This register is used to control the signals that connect to I/O pins when the module is configured in system test (SYSTEST) mode for boundary connectivity verification. Note: In SYSTEST mode, a write into register will not start a transfer. The buffer behaves as a stack accessible only by the local host (push and pop operations). In this mode, the Transfer Block Size ([11:0] BLEN) and the Blocks count for current transfer ([31:16] NBLK) are needed to generate a Buffer write ready interrupt ([4] BWR) or a Buffer read ready interrupt ([5] BRR) and DMA requests if enabled." { 270 _ 15 mbz; 271 obi 1 rw type(standbymode_status) "Out-Of-Band Interrupt (OBI) data value"; 272 sdcd 1 ro type(sdcd_status) "Card detect input signal (SDCD) data value"; 273 sdwp 1 ro type(sdwp_status) "Write protect input signal (SDWP) data value"; 274 wakd 1 rw type(wakd_status) "Wake request output signal data value"; 275 ssb 1 rw type(ssb_status) "Set status bit This bit must be cleared prior attempting to clear a status bit of the interrupt status register (MMCHS_STAT)."; 276 d7d 1 rw type(d7d_status) "DAT7 input/output signal data value"; 277 d6d 1 rw type(d6d_status) "DAT6 input/output signal data value"; 278 d5d 1 rw type(d5d_status) "DAT5 input/output signal data value"; 279 d4d 1 rw type(d4d_status) "DAT4 input/output signal data value"; 280 d3d 1 rw type(d3d_status) "DAT3 input/output signal data value"; 281 d2d 1 rw type(d2d_status) "DAT2 input/output signal data value"; 282 d1d 1 rw type(d1d_status) "DAT1 input/output signal data value"; 283 d0d 1 rw type(d0d_status) "DAT0 input/output signal data value"; 284 ddir 1 rw type(ddir_status) "Control of the DAT[7:0] pins direction."; 285 cdat 1 rw type(cdat_status) "CMD input/output signal data value"; 286 cdir 1 rw type(cdir_status) "Control of the CMD pin direction."; 287 mckd 1 rw type(mckd_status) "MMC clock output signal data value"; 288 }; 289 290 constants sdma_lne_status width(1) "" { 291 SDMA_LNE_0 = 0 "Slave DMA edge sensitive, Early DMA de-assertion"; 292 SDMA_LNE_1 = 1 "Slave DMA level sensitive, Late DMA de-assertion"; 293 }; 294 295 constants dma_mns_status width(1) "" { 296 DMA_MNS_0 = 0 "The controller is slave on data transfers with system."; 297 DMA_MNS_1 = 1 "The controller is master on data exchange with system, controller must be configured as using DMA."; 298 }; 299 300 constants ddr_status width(1) "" { 301 DDR_0 = 0 "Standard mode : data are transmitted on a single edge depending on[2] HSPE."; 302 DDR_1 = 1 "Data Bytes and CRC are transmitted on both edge."; 303 }; 304 305 constants boot_cf0_status width(1) "" { 306 BOOT_CF0_0_w = 0 "CMD line is released when it was previously forced to 0 by a boot sequence."; 307 BOOT_CF0_0_r = 0 "CMD line not forced"; 308 BOOT_CF0_1_r = 1 "CMD line forced to 0 is enabled"; 309 BOOT_CF0_1_w = 1 "CMD line forced to 0 is enabled and will be active after writing into"; 310 }; 311 312 constants boot_ack_status width(1) "" { 313 BOOT_ACK_0 = 0 "No acknowledge to be received"; 314 BOOT_ACK_1 = 1 "A boot status will be received on DAT0 line after issuing a command."; 315 }; 316 317 constants clkextfree_status width(1) "" { 318 CLKEXTFREE_0 = 0 "External card clock is cut off outside active transaction period."; 319 CLKEXTFREE_1 = 1 "External card clock is maintain even out of active transaction period only if[2] CEN is set."; 320 }; 321 322 constants paden_status width(1) "" { 323 PADEN_0 = 0 "ADPIDLE module pin is not forced, it is automatically generated by the MMC fsms."; 324 PADEN_1 = 1 "ADPIDLE module pin is forced to active state."; 325 }; 326 327 constants obie_status width(1) "" { 328 OBIE_0 = 0 "Out-of-Band interrupt detection disabled"; 329 OBIE_1 = 1 "Out-of-Band interrupt detection enabled"; 330 }; 331 332 constants obip_status width(1) "" { 333 OBIP_0 = 0 "active high level"; 334 OBIP_1 = 1 "active low level"; 335 }; 336 337 constants ceata_status width(1) "" { 338 CEATA_0 = 0 "Standard MMC/SD/SDIO mode."; 339 CEATA_1 = 1 "CE-ATA mode next commands are considered as CE-ATA commands."; 340 }; 341 342 constants ctpl_status width(1) "" { 343 CTPL_0 = 0 "Disable all the input buffers outside of a transaction."; 344 CTPL_1 = 1 "Disable all the input buffers except the buffer of DAT[1] outside of a transaction."; 345 }; 346 347 constants dval_status width(2) "" { 348 DVAL_0 = 0 "33 us debounce period"; 349 DVAL_1 = 1 "231 us debounce period"; 350 DVAL_2 = 2 "1 ms debounce period"; 351 DVAL_3 = 3 "8,4 ms debounce period"; 352 }; 353 354 constants mit_status width(1) "" { 355 MIT_0 = 0 "Command timeout enabled"; 356 MIT_1 = 1 "Command timeout disabled"; 357 }; 358 359 constants dw8_status width(1) "" { 360 DW8_0 = 0 "1-bit or 4-bit Data width (DAT[0] used, MMC, SD cards)"; 361 DW8_1 = 1 "8-bit Data width (DAT[7:0] used, MMC cards)"; 362 }; 363 364 constants mode_status width(1) "" { 365 MODE_0 = 0 "Functional mode. Transfers to the MMC/SD/SDIO cards follow the card protocol. MMC clock is enabled. MMC/SD transfers are operated under the control of the CMD register."; 366 MODE_1 = 1 "SYSTEST mode The signal pins are configured as general-purpose input/output and the 1024-byte buffer is configured as a stack memory accessible only by the local host or system DMA. The pins retain their default type (input, output or in-out). SYSTEST mode is operated under the control of the SYSTEST register."; 367 }; 368 369 constants str_status width(1) "" { 370 STR_0 = 0 "Block oriented data transfer"; 371 STR_1 = 1 "Stream oriented data transfer"; 372 }; 373 374 constants od_status width(1) "" { 375 OD_0 = 0 "No Open Drain"; 376 OD_1 = 1 "Open Drain or Broadcast host response"; 377 }; 378 379 register mmchs_con addr(base, 0x12C) "Configuration register This register is used: - to select the functional mode or the SYSTEST mode for any card. - to send an initialization sequence to any card. - to enable the detection on DAT[1] of a card interrupt for SDIO cards only. and also to configure : - specific data and command transfers for MMC cards only. - the parameters related to the card detect and write protect input signals." { 380 _ 10 mbz; 381 sdma_lne 1 rw type(sdma_lne_status) "Slave DMA Level/Edge Request: The waveform of the DMA request can be configured either edge sensitive with early de-assertion on first access to MMCHS_DATA register or late de-assertion, request remains active until last allowed data written into MMCHS_DATA."; 382 dma_mns 1 rw type(dma_mns_status) "DMA Master or Slave selection: When this bit is set and the controller is configured to use the DMA, Interconnect master interface is used to get datas from system using ADMA2 procedure (direct access to the memory).This option is only available if generic parameter MMCHS_HL_HWINFO[0] MADMA_EN is asserted to 1."; 383 ddr 1 rw type(ddr_status) "Dual Data Rate mode: When this register is set, the controller uses both clock edge to emit or receive data. Odd bytes are transmitted on falling edges and even bytes are transmitted on rise edges. It only applies on Data bytes and CRC, Start, end bits and CRC status are kept full cycle. This bit field is only meaningful and active for even clock divider ratio of MMCHS_SYSCTL[15:6] CLKD, it is insensitive to MMCHS_HCTL[2] HSPE setting."; 384 boot_cf0 1 rw type(boot_cf0_status) "Boot status supported: This register is set when the CMD line need to be forced to 0 for a boot sequence. CMD line is driven to 0 after writing in MMCHS_CMD. The line is released when this bit field is de-asserted and abort data transfer in case of a pending transaction."; 385 boot_ack 1 rw type(boot_ack_status) "Book acknowledge received: When this bit is set the controller should receive a boot status on DAT0 line after next command issued. If no status is received a data timeout will be generated."; 386 clkextfree 1 rw type(clkextfree_status) "External clock free running: This register is used to maintain card clock out of transfer transaction to enable slave module for example to generate a synchronous interrupt on DAT[1]. The Clock will be maintain only if MMCHS_SYSCTL[2] CEN is set."; 387 paden 1 rw type(paden_status) "Control Power for MMC Lines: This register is only useful when MMC PADs contain power saving mechanism to minimize its leakage power. It works as a GPIO that directly control the ACTIVE pin of PADs. Excepted for DAT[1], the signal is also combine outside the module with the dedicated power control MMCHS_CON[11] CTPL bit."; 388 obie 1 rw type(obie_status) "Out-of-Band Interrupt Enable MMC cards only: This bit enables the detection of Out-of-Band Interrupt on MMCOBI input pin. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration."; 389 obip 1 rw type(obip_status) "Out-of-Band Interrupt Polarity MMC cards only: This bit selects the active level of the out-of-band interrupt coming from MMC cards. The usage of the Out-of-Band signal (OBI) is optional and depends on the system integration."; 390 ceata 1 rw type(ceata_status) "CE-ATA control mode MMC cards compliant with CE-ATA:By default, this bit is set to 0. It is use to indicate that next commands are considered as specific CE-ATA commands that potentially use 'command completion' features."; 391 ctpl 1 rw type(ctpl_status) "Control Power for DAT[1] line MMC and SD cards: By default, this bit is set to 0 and the host controller automatically disables all the input buffers outside of a transaction to minimize the leakage current. SDIO cards: When this bit is set to 1, the host controller automatically disables all the input buffers except the buffer of DAT[1] outside of a transaction in order to detect asynchronous card interrupt on DAT[1] line and minimize the leakage current of the buffers."; 392 dval 2 rw type(dval_status) "Debounce filter value All cards This register is used to define a debounce period to filter the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type of the connector housing that accommodates the card."; 393 wpp 1 rw type(obip_status) "Write protect polarity For SD and SDIO cards only This bit selects the active level of the write protect input signal (SDWP). The usage of the write protect input signal (SDWP) is optional and depends on the system integration and the type of the connector housing that accommodates the card."; 394 cdp 1 rw type(obip_status) "Card detect polarity All cards This bit selects the active level of the card detect input signal (SDCD). The usage of the card detect input signal (SDCD) is optional and depends on the system integration and the type of the connector housing that accommodates the card."; 395 mit 1 rw type(mit_status) "MMC interrupt command Only for MMC cards. This bit must be set to 1, when the next write access to the command register (MMCHS_CMD) is for writing a MMC interrupt command (CMD40) requiring the command timeout detection to be disabled for the command response."; 396 dw8 1 rw type(dw8_status) "8-bit mode MMC select For SD/SDIO cards, this bit must be set to 0. For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliancy with MMC standard specification 4.x (see section 3.6)."; 397 mode 1 rw type(mode_status) "Mode select All cards These bits select between Functional mode and SYSTEST mode."; 398 str 1 rw type(str_status) "Stream command Only for MMC cards. This bit must be set to 1 only for the stream data transfers (read or write) of the adtc commands. Stream read is a class 1 command (CMD11: READ_DAT_UNTIL_STOP). Stream write is a class 3 command (CMD20: WRITE_DAT_UNTIL_STOP)."; 399 hr 1 rw type(standbymode_status) "Broadcast host response Only for MMC cards. This register is used to force the host to generate a 48-bit response for bc command type. It can be used to terminate the interrupt mode by generating a CMD40 response by the core (see section 4.3, 'Interrupt Mode', in the MMC [1] specification). In order to have the host response to be generated in open drain mode, the register MMCHS_CON[0] OD must be set to 1. When MMCHS_CON[12] CEATA is set to 1 and MMCHS_ARG set to 0x00000000 when writing 0x00000000 into MMCHS_CMD register, the host controller performs a 'command completion signal disable' token that is, CMD line held to 0 during 47 cycles followed by a 1."; 400 init 1 rw type(standbymode_status) "Send initialization stream All cards. When this bit is set to 1, and the card is idle, an initialization sequence is sent to the card. An initialization sequence consists of setting the CMD line to 1 during 80 clock cycles. The initialisation sequence is mandatory - but it is not required to do it through this bit - this bit makes it easier. Clock divider (MMCHS_SYSCTL[15:6] CLKD) should be set to ensure that 80 clock periods are greater than 1ms. (see section 9.3, 'Power-Up', in the MMC card specification [1], or section 6.4 in the SD card specification [2]). Note: in this mode, there is no command sent to the card and no response is expected"; 401 od 1 rw type(od_status) "Card open drain mode. Only for MMC cards. This bit must be set to 1 for MMC card commands 1, 2, 3 and 40, and if the MMC card bus is operating in open-drain mode during the response phase to the command sent. Typically, during card identification mode when the card is either in idle, ready or ident state. It is also necessary to set this bit to 1, for a broadcast host response (see Broadcast host response register MMCHS_CON[2] HR)"; 402 }; 403 404 constants pwrcnt_status width(16) "" { 405 PWRCNT_0 = 0 "No additional delay added"; 406 PWRCNT_1 = 1 "TCF delay (card clock period)"; 407 PWRCNT_2 = 2 "TCF x 2 delay (card clock period)"; 408 PWRCNT_65534 = 65534 "TCF x 65534 delay (card clock period)"; 409 PWRCNT_65535 = 65535 "TCF x 65535 delay (card clock period)"; 410 }; 411 412 register mmchs_pwcnt addr(base, 0x130) "Power counter register This register is used to program a mmc counter to delay command transfers after activating the PAD power, this value depends on PAD characteristics and voltage." { 413 _ 16 mbz; 414 pwrcnt 16 rw type(pwrcnt_status) "Power counter register. This register is used to introduce a delay between the PAD ACTIVE pin assertion and the command issued."; 415 }; 416 417 constants nblk_status width(16) "" { 418 NBLK_0 = 0 "Stop count"; 419 NBLK_1 = 1 "1 block"; 420 NBLK_2 = 2 "2 blocks"; 421 NBLK_65535 = 65535 "65535 blocks"; 422 }; 423 424 constants blen_status width(12) "" { 425 BLEN_0 = 0 "No data transfer"; 426 BLEN_1 = 1 "1 byte block length"; 427 BLEN_2 = 2 "2 bytes block length"; 428 BLEN_3 = 3 "3 bytes block length"; 429 BLEN_511 = 511 "511 bytes block length"; 430 BLEN_512 = 512 "512 bytes block length"; 431 BLEN_1024 = 1024 "1024 bytes block length"; 432 }; 433 434 register mmchs_blk addr(base, 0x204) "Transfer Length Configuration register [11:0] BLEN is the block size register. [31:16] NBLK is the block count register. This register shall be used for any card." { 435 nblk 16 rw type(nblk_status) "Blocks count for current transfer This register is enabled when Block count Enable (MMCHS_CMD[1] BCE) is set to 1 and is valid only for multiple block transfers. Setting the block count to 0 results no data blocks being transferred. Note: The host controller decrements the block count after each block transfer and stops when the count reaches zero. This register can be accessed only if no transaction is executing (i.e, after a transaction has stopped). Read operations during transfers may return an invalid value and write operation will be ignored. In suspend context, the number of blocks yet to be transferred can be determined by reading this register. When restoring transfer context prior to issuing a Resume command, The local host shall restore the previously saved block count."; 436 _ 4 mbz; 437 blen 12 rw type(blen_status) "Transfer Block Size. This register specifies the block size for block data transfers. Read operations during transfers may return an invalid value, and write operations are ignored. When a CMD12 command is issued to stop the transfer, a read of the BLEN field after transfer completion (MMCHS_STAT[1] TC set to 1) will not return the true byte number of data length while the stop occurs but the value written in this register before transfer is launched."; 438 }; 439 440 register mmchs_arg rw addr(base, 0x208) "Command argument Register This register contains command argument specified as bit 39-8 of Command-Format These registers must be initialized prior to sending the command itself to the card (write action into the register register). Only exception is for a command index specifying stuff bits in arguments, making a write unnecessary." type(uint32); 441 442 constants indx_status width(6) "" { 443 INDX_0 = 0 "CMD0 or ACMD0"; 444 INDX_1 = 1 "CMD1 or ACMD1"; 445 INDX_2 = 2 "CMD2 or ACMD2"; 446 INDX_3 = 3 "CMD3 or ACMD3"; 447 INDX_4 = 4 "CMD4 or ACMD4"; 448 INDX_5 = 5 "CMD5 or ACMD5"; 449 INDX_6 = 6 "CMD6 or ACMD6"; 450 INDX_7 = 7 "CMD7 or ACMD7"; 451 INDX_8 = 8 "CMD8 or ACMD8"; 452 INDX_9 = 9 "CMD9 or ACMD9"; 453 INDX_10 = 10 "CMD10 or ACMD10"; 454 INDX_11 = 11 "CMD11 or ACMD11"; 455 INDX_12 = 12 "CMD12 or ACMD12"; 456 INDX_13 = 13 "CMD13 or ACMD13"; 457 INDX_14 = 14 "CMD14 or ACMD14"; 458 INDX_15 = 15 "CMD15 or ACMD15"; 459 INDX_16 = 16 "CMD16 or ACMD16"; 460 INDX_17 = 17 "CMD17 or ACMD17"; 461 INDX_18 = 18 "CMD18 or ACMD18"; 462 INDX_19 = 19 "CMD19 or ACMD19"; 463 INDX_20 = 20 "CMD20 or ACMD20"; 464 INDX_21 = 21 "CMD21 or ACMD21"; 465 INDX_22 = 22 "CMD22 or ACMD22"; 466 INDX_23 = 23 "CMD23 or ACMD23"; 467 INDX_24 = 24 "CMD24 or ACMD24"; 468 INDX_25 = 25 "CMD25 or ACMD25"; 469 INDX_26 = 26 "CMD26 or ACMD26"; 470 INDX_27 = 27 "CMD27 or ACMD27"; 471 INDX_28 = 28 "CMD28 or ACMD28"; 472 INDX_29 = 29 "CMD29 or ACMD29"; 473 INDX_30 = 30 "CMD30 or ACMD30"; 474 INDX_31 = 31 "CMD31 or ACMD31"; 475 INDX_32 = 32 "CMD32 or ACMD32"; 476 INDX_33 = 33 "CMD33 or ACMD33"; 477 INDX_34 = 34 "CMD34 or ACMD34"; 478 INDX_35 = 35 "CMD35 or ACMD35"; 479 INDX_36 = 36 "CMD36 or ACMD36"; 480 INDX_37 = 37 "CMD37 or ACMD37"; 481 INDX_38 = 38 "CMD38 or ACMD38"; 482 INDX_39 = 39 "CMD39 or ACMD39"; 483 INDX_40 = 40 "CMD40 or ACMD40"; 484 INDX_41 = 41 "CMD41 or ACMD41"; 485 INDX_42 = 42 "CMD42 or ACMD42"; 486 INDX_43 = 43 "CMD43 or ACMD43"; 487 INDX_44 = 44 "CMD44 or ACMD44"; 488 INDX_45 = 45 "CMD45 or ACMD45"; 489 INDX_46 = 46 "CMD46 or ACMD46"; 490 INDX_47 = 47 "CMD47 or ACMD47"; 491 INDX_48 = 48 "CMD48 or ACMD48"; 492 INDX_49 = 49 "CMD49 or ACMD49"; 493 INDX_50 = 50 "CMD50 or ACMD50"; 494 INDX_51 = 51 "CMD51 or ACMD51"; 495 INDX_52 = 52 "CMD52 or ACMD52"; 496 INDX_53 = 53 "CMD53 or ACMD53"; 497 INDX_54 = 54 "CMD54 or ACMD54"; 498 INDX_55 = 55 "CMD55 or ACMD55"; 499 INDX_56 = 56 "CMD56 or ACMD56"; 500 INDX_57 = 57 "CMD57 or ACMD57"; 501 INDX_58 = 58 "CMD58 or ACMD58"; 502 INDX_59 = 59 "CMD59 or ACMD59"; 503 INDX_60 = 60 "CMD60 or ACMD60"; 504 INDX_61 = 61 "CMD61 or ACMD61"; 505 INDX_62 = 62 "CMD62 or ACMD62"; 506 INDX_63 = 63 "CMD63 or ACMD63"; 507 }; 508 509 constants cmd_type_status width(2) "" { 510 CMD_TYPE_0 = 0 "Others Commands"; 511 CMD_TYPE_1 = 1 "CMD52 for writing 'Bus Suspend' in CCCR"; 512 CMD_TYPE_2 = 2 "CMD52 for writing 'Function Select' in CCCR"; 513 CMD_TYPE_3 = 3 "Abort command CMD12, CMD52 for writing ' I/O Abort' in CCCR"; 514 }; 515 516 constants dp_status width(1) "" { 517 DP_0 = 0 "Command with no data transfer"; 518 DP_1 = 1 "Command with data transfer"; 519 }; 520 521 constants cice_status width(1) "" { 522 CICE_0 = 0 "Index check disable"; 523 CICE_1 = 1 "Index check enable"; 524 }; 525 526 constants ccce_status width(1) "" { 527 CCCE_0 = 0 "CRC7 check disable"; 528 CCCE_1 = 1 "CRC7 check enable"; 529 }; 530 531 constants rsp_type_status width(2) "" { 532 RSP_TYPE_0 = 0 "No response"; 533 RSP_TYPE_1 = 1 "Response Length 136 bits"; 534 RSP_TYPE_2 = 2 "Response Length 48 bits"; 535 RSP_TYPE_3 = 3 "Response Length 48 bits with busy after response"; 536 }; 537 538 constants msbs_status width(1) "" { 539 MSBS_0 = 0 "Single block. If this bit is 0, it is not necessary to set the register [31:16] NBLK."; 540 MSBS_1 = 1 "Multi block. When Block Count is disabled ([1] BCE is set to 0) in Multiple block transfers ([5] MSBS is set to 1), the module can perform infinite transfer."; 541 }; 542 543 constants ddir_status1 width(1) "" { 544 DDIR_0 = 0 "Data Write (host to card)"; 545 DDIR_1 = 1 "Data Read (card to host)"; 546 }; 547 548 constants acen_status width(1) "" { 549 ACEN_0 = 0 "Auto CMD12 disable"; 550 ACEN_1 = 1 "Auto CMD12 enable or CCS detection enabled."; 551 }; 552 553 constants de_status width(1) "" { 554 DE_0 = 0 "DMA mode disable"; 555 DE_1 = 1 "DMA mode enable"; 556 }; 557 558 register mmchs_cmd addr(base, 0x20C) "Command and transfer mode register [31:16] = the command register [15:0] = the transfer mode. This register configures the data and command transfers. A write into the most significant byte send the command. A write into [15:0] registers during data transfer has no effect. This register shall be used for any card. Note: In SYSTEST mode, a write into register will not start a transfer." { 559 _ 2 mbz; 560 indx 6 rw type(indx_status) "Command index Binary encoded value from 0 to 63 specifying the command number send to card"; 561 cmd_type 2 rw type(cmd_type_status) "Command type This register specifies three types of special command: Suspend, Resume and Abort. These bits shall be set to 00b for all other commands."; 562 dp 1 rw type(dp_status) "Data present select This register indicates that data is present and DAT line shall be used. It must be set to 0 in the following conditions: - command using only CMD line - command with no data transfer but using busy signal on DAT[0] - Resume command"; 563 cice 1 rw type(cice_status) "Command Index check enable This bit must be set to 1 to enable index check on command response to compare the index field in the response against the index of the command. If the index is not the same in the response as in the command, it is reported as a command index error (MMCHS_STAT[19] CIE set to1) Note: The register CICE cannot be configured for an Auto CMD12, then index check is automatically checked when this command is issued."; 564 ccce 1 rw type(ccce_status) "Command CRC check enable This bit must be set to 1 to enable CRC7 check on command response to protect the response against transmission errors on the bus. If an error is detected, it is reported as a command CRC error (MMCHS_STAT[17] CCRC set to 1). Note: The register CCCE cannot be configured for an Auto CMD12, and then CRC check is automatically checked when this command is issued."; 565 _ 1 mbz; 566 rsp_type 2 rw type(rsp_type_status) "Response type This bits defines the response type of the command"; 567 _ 10 mbz; 568 msbs 1 rw type(msbs_status) "Multi/Single block select This bit must be set to 1 for data transfer in case of multi block command. For any others command this bit shall be set to 0."; 569 ddir 1 rw type(ddir_status1) "Data transfer Direction Select This bit defines either data transfer will be a read or a write."; 570 _ 1 mbz; 571 acen 1 rw type(acen_status) "Auto CMD12 Enable SDIO does not support this feature. When this bit is set to 1, the host controller issues a CMD12 automatically after the transfer completion of the last block. The Host Driver shall not set this bit to issue commands that do not require CMD12 to stop data transfer. In particular, safe commands do not require CMD12."; 572 bce 1 rw type(standbymode_status) "Block Count Enable Multiple block transfers only. This bit is used to enable the block count register (MMCHS_BLK[31:16] NBLK). When Block Count is disabled (MMCHS_CMD[1] BCE is set to 0) in Multiple block transfers (MMCHS_CMD[5] MSBS is set to 1), the module can perform infinite transfer."; 573 de 1 rw type(de_status) "DMA Enable This bit is used to enable DMA mode for host data access."; 574 }; 575 576 register mmchs_rsp10 addr(base, 0x210) "Command response[31:0] Register This 32-bit register holds bits positions [31:0] of command response type R1/R1b/R2/R3/R4/R5/R5b/R6" { 577 rsp1 16 ro "Command Response [31:16]"; 578 rsp0 16 ro "Command Response [15:0]"; 579 }; 580 581 register mmchs_rsp32 addr(base, 0x214) "Command response[63:32] Register This 32-bit register holds bits positions [63:32] of command response type R2" { 582 rsp3 16 ro "Command Response [63:48]"; 583 rsp2 16 ro "Command Response [47:32]"; 584 }; 585 586 register mmchs_rsp54 addr(base, 0x218) "Command response[95:64] Register This 32-bit register holds bits positions [95:64] of command response type R2" { 587 rsp5 16 ro "Command Response [95:80]"; 588 rsp4 16 ro "Command Response [79:64]"; 589 }; 590 591 register mmchs_rsp76 addr(base, 0x21C) "Command response[127:96] Register This 32-bit register holds bits positions [127:96] of command response type R2" { 592 rsp7 16 ro "Command Response [127:112]"; 593 rsp6 16 ro "Command Response [111:96]"; 594 }; 595 596 register mmchs_data rw addr(base, 0x220) "Data Register This register is the 32-bit entry point of the buffer for read or write data transfers. The buffer size is 32bits x256(1024 bytes). Bytes within a word are stored and read in little endian format. This buffer can be used as two 512 byte buffers to transfer data efficiently without reducing the throughput. Sequential and contiguous access is necessary to increment the pointer correctly. Random or skipped access is not allowed. In little endian, if the local host accesses this register byte-wise or 16bit-wise, the least significant byte (bits [7:0]) must always be written/read first. The update of the buffer address is done on the most significant byte write for full 32-bit DATA register or on the most significant byte of the last word of block transfer. Example 1: Byte or 16-bit access Mbyteen[3:0]=>0001 (1-byte) = Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1100 (2-bytes) OK Mbyteen[3:0]=>0001 (1-byte) = Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=0100 (1-byte) OK Mbyteen[3:0]=>0001 (1-byte) = Mbyteen[3:0]=0010 (1-byte) => Mbyteen[3:0]=1000 (1-byte) Bad" type(uint32); 597 598 constants clev_status width(1) "" { 599 CLEV_0_r = 0 "The CMD line level is 0."; 600 CLEV_1_r = 1 "The CMD line level is 1."; 601 }; 602 603 constants wp_status width(1) "" { 604 WP_0_r = 0 "If[8] WPP is set to 0 (default), the card is write protected, otherwise the card is not protected."; 605 WP_1_r = 1 "If[8] WPP is set to 0 (default), the card is not write protected, otherwise the card is protected."; 606 }; 607 608 constants cdpl_status width(1) "" { 609 CDPL_0_r = 0 "The value of the card detect input pin (SDCD) is 1"; 610 CDPL_1_r = 1 "The value of the card detect input pin (SDCD) is 0"; 611 }; 612 613 constants css_status width(1) "" { 614 CSS_0_r = 0 "Reset or Debouncing"; 615 CSS_1_r = 1 "No card or card inserted"; 616 }; 617 618 constants cins_status width(1) "" { 619 CINS_0_r = 0 "If[7] CDP is set to 0 (default), no card is detected. The card may have been removed from the card slot. If [7] CDP is set to 1, the card has been inserted."; 620 CINS_1_r = 1 "If[7] CDP is set to 0 (default), the card has been inserted from the card slot. If [7] CDP is set to 1, no card is detected. The card may have been removed from the card slot."; 621 }; 622 623 constants bre_status width(1) "" { 624 BRE_0_r = 0 "Read BLEN bytes disable"; 625 BRE_1_r = 1 "Read BLEN bytes enable. Readable data exists in the buffer."; 626 }; 627 628 constants bwe_status width(1) "" { 629 BWE_0_r = 0 "There is no room left in the buffer to write BLEN bytes of data."; 630 BWE_1_r = 1 "There is enough space in the buffer to write BLEN bytes of data."; 631 }; 632 633 constants rta_status width(1) "" { 634 RTA_0_r = 0 "No valid data on the DAT lines."; 635 RTA_1_r = 1 "read data transfer on going."; 636 }; 637 638 constants wta_status width(1) "" { 639 WTA_0_r = 0 "No valid data on the DAT lines."; 640 WTA_1_r = 1 "Write data transfer on going."; 641 }; 642 643 constants dla_status width(1) "" { 644 DLA_0_r = 0 "DAT Line inactive"; 645 DLA_1_r = 1 "DAT Line active"; 646 }; 647 648 constants dati_status width(1) "" { 649 DATI_0_r = 0 "Issuing of command using the DAT lines is allowed"; 650 DATI_1_r = 1 "Issuing of command using DAT lines is not allowed"; 651 }; 652 653 register mmchs_pstate addr(base, 0x224) "Present state register The Host can get status of the Host Controller from this 32-bit read only register." { 654 _ 7 mbz; 655 clev 1 ro type(clev_status) "CMD line signal level This status is used to check the CMD line level to recover from errors, and for debugging. The value of this register after reset depends on the CMD line level at that time."; 656 dlev 4 ro "DAT[3:0] line signal level DAT[3] => bit 23 DAT[2] => bit 22 DAT[1] => bit 21 DAT[0] => bit 20 This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. The value of these registers after reset depends on the DAT lines level at that time."; 657 wp 1 ro type(wp_status) "Write protect switch pin level For SDIO cards only. This bit reflects the write protect input pin (SDWP) level. The value of this register after reset depends on the protect input pin (SDWP) level at that time."; 658 cdpl 1 ro type(cdpl_status) "Card detect pin level This bit reflects the inverse value of the card detect input pin (SDCD), debouncing is not performed on this bit and bit is valid only when Card State Stable (MMCHS_PSTATE[17] CSS) is set to 1. Use of this bit is limited to testing since it must be debounced y software. The value of this register after reset depends on the card detect input pin (SDCD) level at that time."; 659 css 1 ro type(css_status) "Card State Stable This bit is used for testing. It is set to 1 only when Card Detect Pin Level is stable (MMCHS_PSTATE[18] CDPL). Debouncing is performed on the card detect input pin (SDCD) to detect card stability. This bit is not affected by a software reset."; 660 cins 1 ro type(cins_status) "Card inserted This bit is the debounced value of the card detect input pin (SDCD). An inactive to active transition of the card detect input pin (SDCD) will generate a card insertion interrupt (MMCHS_STAT[6] CINS). A active to inactive transition of the card detect input pin (SDCD) will generate a card removal interrupt (MMCHS_STAT[7] CREM). This bit is not affected by a software reset."; 661 _ 4 mbz; 662 bre 1 ro type(bre_status) "Buffer read enable This bit is used for non-DMA read transfers. It indicates that a complete block specified by MMCHS_BLK[11:0] BLEN has been written in the buffer and is ready to be read. It is set to 0 when the entire block is read from the buffer. It is set to 1 when a block data is ready in the buffer and generates the Buffer read ready status of interrupt (MMCHS_STAT[5] BRR)."; 663 bwe 1 ro type(bwe_status) "Buffer Write enable This status is used for non-DMA write transfers. It indicates if space is available for write data."; 664 rta 1 ro type(rta_status) "Read transfer active This status is used for detecting completion of a read transfer. It is set to 1 after the end bit of read command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block gap request. This bit is set to 0 when all data have been read by the local host after last block or after a stop at block gap request."; 665 wta 1 ro type(wta_status) "Write transfer active This status indicates a write transfer active. It is set to 1 after the end bit of write command or by activating a continue request (MMCHS_HCTL[17] CR) following a stop at block gap request. This bit is set to 0 when CRC status has been received after last block or after a stop at block gap request."; 666 _ 5 mbz; 667 dla 1 ro type(dla_status) "DAT line active This status bit indicates whether one of the DAT line is in use. In the case of read transactions (card to host): This bit is set to 1 after the end bit of read command or by activating continue request MMCHS_HCTL[17] CR. This bit is set to 0 when the host controller received the end bit of the last data block or at the beginning of the read wait mode. In the case of write transactions (host to card): This bit is set to 1 after the end bit of write command or by activating continue request MMCHS_HCTL[17] CR. This bit is set to 0 on the end of busy event for the last block; host controller must wait 8 clock cycles with line not busy to really consider not 'busy state' or after the busy block as a result of a stop at gap request."; 668 dati 1 ro type(dati_status) "Command inhibit(DAT) This status bit is generated if either DAT line is active (MMCHS_PSTATE[2] DLA) or Read transfer is active (MMCHS_PSTATE[9] RTA) or when a command with busy is issued. This bit prevents the local host to issue a command. A change of this bit from 1 to 0 generates a transfer complete interrupt (MMCHS_STAT[1] TC)."; 669 cmdi 1 ro type(boot_cf0_status) "Command inhibit(CMD) This status bit indicates that the CMD line is in use. This bit is set to 0 when the most significant byte is written into the command register. This bit is not set when Auto CMD12 is transmitted. This bit is set to 0 in either the following cases: - After the end bit of the command response, excepted if there is a command conflict error (MMCHS_STAT[17] CCRC or MMCHS_STAT[18] CEB set to 1) or a Auto CMD12 is not executed (MMCHS_AC12[0] ACNE). - After the end bit of the command without response (MMCHS_CMD[17:16] RSP_TYPE set to '00') In case of a command data error is detected (MMCHS_STAT[16] CTO set to 1), this register is not automatically cleared."; 670 }; 671 672 constants rem_status width(1) "" { 673 REM_0 = 0 "Disable wakeup on card removal"; 674 REM_1 = 1 "Enable wakeup on card removal"; 675 }; 676 677 constants ins_status width(1) "" { 678 INS_0 = 0 "Disable wakeup on card insertion"; 679 INS_1 = 1 "Enable wakeup on card insertion"; 680 }; 681 682 constants iwe_status width(1) "" { 683 IWE_0 = 0 "Disable wakeup on card interrupt"; 684 IWE_1 = 1 "Enable wakeup on card interrupt"; 685 }; 686 687 constants rwc_status width(1) "" { 688 RWC_0 = 0 "Disable Read Wait Control. Suspend/Resume cannot be supported."; 689 RWC_1 = 1 "Enable Read Wait Control"; 690 }; 691 692 constants cr_status width(1) "" { 693 CR_0 = 0 "No affect"; 694 CR_1 = 1 "transfer restart"; 695 }; 696 697 constants sbgr_status width(1) "" { 698 SBGR_0 = 0 "Transfer mode"; 699 SBGR_1 = 1 "Stop at block gap"; 700 }; 701 702 constants sdvs_status width(3) "" { 703 SDVS_5 = 5 "1.8V (Typical)"; 704 SDVS_6 = 6 "3.0V (Typical)"; 705 SDVS_7 = 7 "3.3V (Typical)"; 706 }; 707 708 constants sdbp_status width(1) "" { 709 SDBP_0 = 0 "Power off"; 710 SDBP_1 = 1 "Power on"; 711 }; 712 713 constants cdss_status width(1) "" { 714 CDSS_0 = 0 "SDCD# is selected (for normal use)"; 715 CDSS_1 = 1 "The Card Detect Test Level is selected (for test purpose)"; 716 }; 717 718 constants cdtl_status width(1) "" { 719 CDTL_0 = 0 "No Card"; 720 CDTL_1 = 1 "Card Inserted"; 721 }; 722 723 constants dmas_status width(2) "" { 724 DMAS_0 = 0 "Reserved"; 725 DMAS_1 = 1 "Reserved"; 726 DMAS_2 = 2 "32-bit Address ADMA2 is selected"; 727 DMAS_3 = 3 "Reserved"; 728 }; 729 730 constants hspe_status width(1) "" { 731 HSPE_0 = 0 "Normal speed mode"; 732 HSPE_1 = 1 "High speed mode"; 733 }; 734 735 constants dtw_status width(1) "" { 736 DTW_0 = 0 "1-bit Data width (DAT[0] used)"; 737 DTW_1 = 1 "4-bit Data width (DAT[3:0] used)"; 738 }; 739 740 register mmchs_hctl addr(base, 0x228) "Control register This register defines the host controls to set power, wakeup and transfer parameters. [31:24] = Wakeup control [23:16] = Block gap control [15:8] = Power control [7:0] = Host control" { 741 _ 4 mbz; 742 obwe 1 rw type(standbymode_status) "Wakeup event enable for 'Out-of-Band' Interrupt. This bit enables wakeup events for 'Out-of-Band' assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP). The write to this register is ignored when MMCHS_CON[14] OBIE is not set."; 743 rem 1 rw type(rem_status) "Wakeup event enable on SD card removal This bit enables wakeup events for card removal assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP)."; 744 ins 1 rw type(ins_status) "Wakeup event enable on SD card insertion This bit enables wakeup events for card insertion assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP)."; 745 iwe 1 rw type(iwe_status) "Wakeup event enable on SD card interrupt This bit enables wakeup events for card interrupt assertion. Wakeup is generated if the wakeup feature is enabled (MMCHS_SYSCONFIG[2] ENAWAKEUP)."; 746 _ 4 mbz; 747 ibg 1 rw type(standbymode_status) "Interrupt block at gap This bit is valid only in 4-bit mode of SDIO card to enable interrupt detection in the interrupt cycle at block gap for a multiple block transfer. For MMC cards and for SD card this bit should be set to 0."; 748 rwc 1 rw type(rwc_status) "Read wait control The read wait function is optional only for SDIO cards. If the card supports read wait, this bit must be enabled, then requesting a stop at block gap (MMCHS_HCTL[16] SBGR) generates a read wait period after the current end of block. Be careful, if read wait is not supported it may cause a conflict on DAT line."; 749 cr 1 rw type(cr_status) "Continue request This bit is used to restart a transaction that was stopped by requesting a stop at block gap (MMCHS_HCTL[16] SBGR). Set this bit to 1 restarts the transfer. The bit is automatically set to 0 by the host controller when transfer has restarted i.e DAT line is active (MMCHS_PSTATE[2] DLA) or transferring data (MMCHS_PSTATE[8] WTA). The Stop at block gap request must be disabled (MMCHS_HCTL[16] SBGR = 0) before setting this bit."; 750 sbgr 1 rw type(sbgr_status) "Stop at block gap request This bit is used to stop executing a transaction at the next block gap. The transfer can restart with a continue request (MMCHS_HCTL[17] CR) or during a suspend/resume sequence. In case of read transfer, the card must support read wait control. In case of write transfer, the host driver shall set this bit after all block data written. Until the transfer completion (MMCHS_STAT[1] TC set to 1), the host driver shall leave this bit set to 1. If this bit is set, the local host shall not write to the data register (MMCHS_DATA)."; 751 _ 4 mbz; 752 sdvs 3 rw type(sdvs_status) "SD bus voltage select All cards. The host driver should set to these bits to select the voltage level for the card according to the voltage supported by the system (MMCHS_CAPA[26:24]) before starting a transfer."; 753 sdbp 1 rw type(sdbp_status) "SD bus power Before setting this bit, the host driver shall select the SD bus voltage (MMCHS_HCTL[11:9] SDVS). If the host controller detects the No card state, this bit is automatically set to 0. If the module is power off, a write in the command register (MMCHS_CMD) will not start the transfer. A write to this bit has no effect if the selected SD bus voltage is not supported according to capability register (MMCHS_CAPA[26:24])."; 754 cdss 1 rw type(cdss_status) "Card Detect Signal Selection This bit selects source for the card detection.When the source for the card detection is switched, the interrupt should be disabled during the switching period by clearing the Interrupt Status/Signal Enable register in order to mask unexpected interrupt being caused by the glitch. The Interrupt Status/Signal Enable should be disabled during over the period of debouncing."; 755 cdtl 1 rw type(cdtl_status) "Card Detect Test Level: This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates card inserted or not."; 756 _ 1 mbz; 757 dmas 2 rw type(dmas_status) "DMA Select Mode: One of supported DMA modes can be selected. The host driver shall check support of DMA modes by referring the Capabilities register. Use of selected DMA is determined by DMA Enable of the Transfer Mode register. This register is only meaningful when MMCHS_HL_HWINFO[0] MADMA_EN is set to 1. When MMCHS_HL_HWINFO[0] MADMA_EN is set to 0 the bit field is read only and returned value is 0."; 758 hspe 1 rw type(hspe_status) "High Speed Enable: Before setting this bit, the Host Driver shall check the High Speed Support in the Capabilities register. If this bit is set to 0 (default), the Host Controller outputs CMD line and DAT lines at the falling edge of the SD Clock. If this bit is set to 1, the Host Controller outputs CMD line and DAT lines at the rising edge of the SD Clock.This bit shall not be set when dual data rate mode is activated in MMCHS_CON[19] DDR."; 759 dtw 1 rw type(dtw_status) "Data transfer width For MMC card, this bit must be set following a valid SWITCH command (CMD6) with the correct value and extend CSD index written in the argument. Prior to this command, the MMC card configuration register (CSD and EXT_CSD) must be verified for compliance with MMC standard specification 4.x (see section 3.6). This register has no effect when the MMC 8-bit mode is selected (register MMCHS_CON[5] DW8 set to1 ), For SD/SDIO cards, this bit must be set following a valid SET_BUS_WIDTH command (ACMD6) with the value written in bit 1 of the argument. Prior to this command, the SD card configuration register (SCR) must be verified for the supported bus width by the SD card."; 760 led 1 ro "Reserved bit. LED control feature is not supported This bit is initialized to zero, and writes to it are ignored."; 761 }; 762 763 constants srd_status width(1) "" { 764 SRD_0 = 0 "Reset completed"; 765 SRD_1 = 1 "Software reset for DAT line"; 766 }; 767 768 constants src_status width(1) "" { 769 SRC_0 = 0 "Reset completed"; 770 SRC_1 = 1 "Software reset for CMD line"; 771 }; 772 773 constants sra_status width(1) "" { 774 SRA_0 = 0 "Reset completed"; 775 SRA_1 = 1 "Software reset for all the design"; 776 }; 777 778 constants dto_status width(4) "" { 779 DTO_0 = 0 "TCF x 213"; 780 DTO_1 = 1 "TCF x 214"; 781 DTO_14 = 14 "TCF x 227"; 782 DTO_15 = 15 "Reserved"; 783 }; 784 785 constants clkd_status width(10) "" { 786 CLKD_0 = 0 "MMCi_FCLK bypass"; 787 CLKD_1 = 1 "MMCi_FCLK bypass"; 788 CLKD_2 = 2 "MMCi_FCLK / 2"; 789 CLKD_3 = 3 "MMCi_FCLK / 3"; 790 CLKD_1023 = 1023 "MMCi_FCLK / 1023"; 791 }; 792 793 constants cen_status width(1) "" { 794 CEN_0 = 0 "The clock is not provided to the card . Clock frequency can be changed ."; 795 CEN_1 = 1 "The clock is provided to the card and can be automatically gated when[0] AUTOIDLE is set to 1 (default value) . The host driver shall wait to set this bit to 1 until the Internal clock is stable ([1] ICS)."; 796 }; 797 798 constants ics_status width(1) "" { 799 ICS_0_r = 0 "The internal clock is not stable."; 800 ICS_1_r = 1 "The internal clock is stable after enabling the clock ([1] ICE) or after changing the clock ratio ([15:6] CLKD)."; 801 }; 802 803 constants ice_status width(1) "" { 804 ICE_0 = 0 "The internal clock is stopped (very low power state)."; 805 ICE_1 = 1 "The internal clock oscillates and can be automatically gated when[0] AUTOIDLE is set to 1 (default value) ."; 806 }; 807 808 register mmchs_sysctl addr(base, 0x22C) "SD system control register This register defines the system controls to set software resets, clock frequency management and data timeout. [31:24] = Software resets [23:16] = Timeout control [15:0] = Clock control" { 809 _ 5 mbz; 810 srd 1 rw type(srd_status) "Software reset for DAT line. This bit is set to 1 for reset and released to 0 when completed. For more information about SRD bit manipulation, see , . DAT finite state machine in both clock domain are also reset. The following registers are cleared by MMCHS_SYSCTL[26] SRD: - MMCHS_DATA - MMCHS_PSTATE[11] BRE, MMCHS_PSTATE[10] BWE, MMCHS_PSTATE[9] RTA, MMCHS_PSTATE[8] WTA, MMCHS_PSTATE[2] DLA, MMCHS_PSTATE[1] DATI - MMCHS_HCTL: SBGR and CR - MMCHS_STAT: MMCHS_STAT[5] BRR, MMCHS_STAT[4] BWR, MMCHS_STAT[2] BGE and MMCHS_STAT[1] TC Interconnect and MMC buffer data management is reinitialized."; 811 src 1 rw type(src_status) "Software reset for CMD line For more information about SRC bit manipulation, see , . This bit is set to 1 for reset and released to 0 when completed. CMD finite state-machine in both clock domain are also reset. The following registers are cleared by MMCHS_SYSCTL[25] SRC: - MMCHS_PSTATE[0] CMDI - MMCHS_STAT[0] CC Interconnect and MMC command status management is reinitialized."; 812 sra 1 rw type(sra_status) "Software reset for all This bit is set to 1 for reset, and released to 0 when completed. This reset affects the entire host controller except for the card detection circuit and capabilities registers."; 813 _ 4 mbz; 814 dto 4 rw type(dto_status) "Data timeout counter value and busy timeout. This value determines the interval by which DAT lines timeouts are detected. The host driver needs to set this bit field based on - the maximum read access time (NAC) (Refer to the SD Specification Part1 Physical Layer), - the data read access time values (TAAC and NSAC) in the card specific data register (CSD) of the card, - the timeout clock base frequency (MMCHS_CAPA[5:0] TCF). If the card does not respond within the specified number of cycles, a data timeout error occurs (MMCHS_STAT[20] DTO). The MMCHS_SYSCTL[19:16] DTO register is also used to check busy duration, to generate busy timeout for commands with busy response or for busy programming during a write command. Timeout on CRC status is generated if no CRC token is present after a block write."; 815 clkd 10 rw type(clkd_status) "Clock frequency select These bits define the ratio between MMCi_FCLK and the output clock frequency on the CLK pin of either the memory card (MMC, SD or SDIO)."; 816 _ 3 mbz; 817 cen 1 rw type(cen_status) "Clock enable This bit controls if the clock is provided to the card or not."; 818 ics 1 ro type(ics_status) "Internal clock stable (status) This bit indicates either the internal clock is stable or not."; 819 ice 1 rw type(ice_status) "Internal clock enable This register controls the internal clock activity. In very low power state, the internal clock is stopped. Note: The activity of the debounce clock (used for wakeup events) and the interface clock (used for reads and writes to the module register map) are not affected by this register."; 820 }; 821 822 constants bada_status width(1) "" { 823 BADA_0_w = 0 "Status bit unchanged"; 824 BADA_0_r = 0 "No Interrupt."; 825 BADA_1_r = 1 "Bad Access"; 826 BADA_1_w = 1 "Status is cleared"; 827 }; 828 829 constants cerr_status width(1) "" { 830 CERR_0_w = 0 "Status bit unchanged"; 831 CERR_0_r = 0 "No Error"; 832 CERR_1_w = 1 "Status is cleared"; 833 CERR_1_r = 1 "Card error"; 834 }; 835 836 constants admae_status width(1) "" { 837 ADMAE_0_w = 0 "Status bit unchanged"; 838 ADMAE_0_r = 0 "No Interrupt."; 839 ADMAE_1_w = 1 "Status is cleared"; 840 ADMAE_1_r = 1 "ADMA error"; 841 }; 842 843 constants ace_status width(1) "" { 844 ACE_0_w = 0 "Status bit unchanged"; 845 ACE_0_r = 0 "No Error."; 846 ACE_1_r = 1 "AutoCMD12 error"; 847 ACE_1_w = 1 "Status is cleared"; 848 }; 849 850 constants deb_status width(1) "" { 851 DEB_0_r = 0 "No Error"; 852 DEB_0_w = 0 "Status bit unchanged"; 853 DEB_1_w = 1 "Status is cleared"; 854 DEB_1_r = 1 "Data end bit error"; 855 }; 856 857 constants dcrc_status width(1) "" { 858 DCRC_0_r = 0 "No Error."; 859 DCRC_0_w = 0 "Status bit unchanged"; 860 DCRC_1_r = 1 "Data CRC error"; 861 DCRC_1_w = 1 "Status is cleared"; 862 }; 863 864 constants dto_status1 width(1) "" { 865 DTO_0_r = 0 "No error."; 866 DTO_0_w = 0 "Status bit unchanged"; 867 DTO_1_w = 1 "Status is cleared"; 868 DTO_1_r = 1 "Time out"; 869 }; 870 871 constants cie_status width(1) "" { 872 CIE_0_r = 0 "No error."; 873 CIE_0_w = 0 "Status bit unchanged"; 874 CIE_1_r = 1 "Command index error"; 875 CIE_1_w = 1 "Status is cleared"; 876 }; 877 878 constants ceb_status width(1) "" { 879 CEB_0_w = 0 "Status bit unchanged"; 880 CEB_0_r = 0 "No error."; 881 CEB_1_r = 1 "Command end bit error"; 882 CEB_1_w = 1 "Status is cleared"; 883 }; 884 885 constants ccrc_status width(1) "" { 886 CCRC_0_r = 0 "No Error."; 887 CCRC_0_w = 0 "Status bit unchanged"; 888 CCRC_1_w = 1 "Status is cleared"; 889 CCRC_1_r = 1 "Command CRC error"; 890 }; 891 892 constants cto_status width(1) "" { 893 CTO_0_w = 0 "Status bit unchanged"; 894 CTO_0_r = 0 "No error"; 895 CTO_1_r = 1 "Time Out"; 896 CTO_1_w = 1 "Status is cleared"; 897 }; 898 899 constants erri_status width(1) "" { 900 ERRI_0_r = 0 "No Interrupt."; 901 ERRI_1_r = 1 "Error interrupt event(s) occurred"; 902 }; 903 904 constants bsr_status width(1) "" { 905 BSR_0_w = 0 "Status bit unchanged"; 906 BSR_0_r = 0 "No Interrupt."; 907 BSR_1_w = 1 "Status is cleared"; 908 BSR_1_r = 1 "Boot status received interrupt."; 909 }; 910 911 constants obi_status width(1) "" { 912 OBI_0_r_1 = 0 "No Out-Of-Band interrupt."; 913 OBI_0_w = 0 "Status bit unchanged"; 914 OBI_1_r_1 = 1 "Interrupt Out-Of-Band occurs"; 915 OBI_1_w = 1 "Status is cleared"; 916 }; 917 918 constants cirq_status width(1) "" { 919 CIRQ_0_r = 0 "No card interrupt"; 920 CIRQ_1_r = 1 "Generate card interrupt"; 921 }; 922 923 constants crem_status width(1) "" { 924 CREM_0_w = 0 "Status bit unchanged"; 925 CREM_0_r = 0 "Card state stable or Debouncing"; 926 CREM_1_r = 1 "Card removed"; 927 CREM_1_w = 1 "Status is cleared"; 928 }; 929 930 constants cins_status1 width(1) "" { 931 CINS_0_r_1 = 0 "Card state stable or debouncing"; 932 CINS_0_w = 0 "Status bit unchanged"; 933 CINS_1_w = 1 "Status is cleared"; 934 CINS_1_r_1 = 1 "Card inserted"; 935 }; 936 937 constants brr_status width(1) "" { 938 BRR_0_r = 0 "Not Ready to read buffer"; 939 BRR_0_w = 0 "Status bit unchanged"; 940 BRR_1_r = 1 "Ready to read buffer"; 941 BRR_1_w = 1 "Status is cleared"; 942 }; 943 944 constants bwr_status width(1) "" { 945 BWR_0_w = 0 "Status bit unchanged"; 946 BWR_0_r = 0 "Not Ready to write buffer"; 947 BWR_1_r = 1 "Ready to write buffer"; 948 BWR_1_w = 1 "Status is cleared"; 949 }; 950 951 constants dma_status width(1) "" { 952 DMA_0_r = 0 "Dma interrupt detected"; 953 DMA_0_w = 0 "Status bit unchanged"; 954 DMA_1_w = 1 "Status is cleared"; 955 DMA_1_r = 1 "No dma interrupt"; 956 }; 957 958 constants bge_status width(1) "" { 959 BGE_0_r = 0 "No block gap event"; 960 BGE_0_w = 0 "Status bit unchanged"; 961 BGE_1_w = 1 "Status is cleared"; 962 BGE_1_r = 1 "Transaction stopped at block gap"; 963 }; 964 965 constants tc_status width(1) "" { 966 TC_0_w = 0 "Status bit unchanged"; 967 TC_0_r = 0 "No transfer complete"; 968 TC_1_w = 1 "Status is cleared"; 969 TC_1_r = 1 "Data transfer complete"; 970 }; 971 972 constants cc_status width(1) "" { 973 CC_0_w = 0 "Status bit unchanged"; 974 CC_0_r = 0 "No Command complete"; 975 CC_1_w = 1 "Status is cleared"; 976 CC_1_r = 1 "Command complete"; 977 }; 978 979 register mmchs_stat addr(base, 0x230) "Interrupt status register The interrupt status regroups all the status of the module internal events that can generate an interrupt. [31:16] = Error Interrupt Status [15:0] = Normal Interrupt Status" { 980 _ 2 mbz; 981 bada 1 rw type(bada_status) "Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register (MMCHS_DATA) while buffer reads are not allowed (MMCHS_PSTATE[11] BRE = 0) -This bit is set during a write access to the data register (MMCHS_DATA) while buffer writes are not allowed (MMCHS_PSTATE[10] BWE = 0)"; 982 cerr 1 rw type(cerr_status) "Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E(error) in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error MMCHS_CSRE in set. There is no card error detection for autoCMD12 command. The host driver shall read MMCHS_RSP76 register to detect error bits in the command response."; 983 _ 2 mbz; 984 admae 1 rw type(admae_status) "ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller generates this interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state. The Host Driver may find that Valid bit is not set at the error descriptor."; 985 ace 1 rw type(ace_status) "Auto CMD12 error This bit is set automatically when one of the bits in Auto CMD12 Error status register has changed from 0 to 1."; 986 cle 1 ro "Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored."; 987 deb 1 rw type(deb_status) "Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode."; 988 dcrc 1 rw type(dcrc_status) "Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position '010' token during a block write command."; 989 dto 1 rw type(dto_status1) "Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout"; 990 cie 1 rw type(cie_status) "Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCHS_CMD[20] CICE register."; 991 ceb 1 rw type(ceb_status) "Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response."; 992 ccrc 1 rw type(ccrc_status) "Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCHS_CMD[19] CCCE register."; 993 cto 1 rw type(cto_status) "Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles."; 994 erri 1 ro type(erri_status) "Error Interrupt If any of the bits in the Error Interrupt Status register (MMCHS_STAT[24:15]) are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored."; 995 _ 4 mbz; 996 bsr 1 rw type(bsr_status) "Boot status received interrupt This bit is set automatically when MMCHS_CON[18] BOOT_CF0 is set 0x0 or 0x1 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card."; 997 obi 1 rw type(obi_status) "Out-Of-Band interrupt This bit is set automatically when MMCHS_CON[14] OBIE is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCHS_CON[13] OBIP. This interrupt is only useful for MMC card. The Out-of-Band interrupt signal is a system specific feature for future use, this signal is not required for existing specification implementation."; 998 cirq 1 ro type(cirq_status) "Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous (can be a source of asynchronous wakeup). In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drives CMD line to zero during one cycle after data transmission end.All modes above are fully exclusive. The controller interrupt must be clear by setting MMCHS_IE[8] CIRQ_ENABLE to 0, then the host driver must start the interrupt service with card (clearing card interrupt status) to remove card interrupt source. Otherwise the Controller interrupt will be reasserted as soon as MMCHS_IE[8] CIRQ_ENABLE is set to 1. Writes to this bit are ignored."; 999 crem 1 rw type(crem_status) "Card removal This bit is set automatically when MMCHS_PSTATE[16] CINS changes from 1 to 0. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS)."; 1000 cins 1 rw type(cins_status1) "Card insertion This bit is set automatically when MMCHS_PSTATE[16] changes from 0 to 1. A clear of this bit doesn't affect Card inserted present state (MMCHS_PSTATE[16] CINS)."; 1001 brr 1 rw type(brr_status) "Buffer read ready This bit is set automatically during a read operation to the card (see class 2 - block oriented read commands) when one block specified by MMCHS_BLK[11:0] BLEN is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by reading it. Note: If the DMA receive-mode is enabled, this bit is never set; instead a DMA receive request to the main DMA controller of the system is generated."; 1002 bwr 1 rw type(bwr_status) "Buffer write ready This bit is set automatically during a write operation to the card (see class 4 - block oriented write command) when the host can write a complete block as specified by MMCHS_BLK[11:0] BLEN. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer. Note: If the DMA transmit mode is enabled, this bit is never set; instead, a DMA transmit request to the main DMA controller of the system is generated."; 1003 dma 1 rw type(dma_status) "DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion."; 1004 bge 1 rw type(bge_status) "Block gap event When a stop at block gap is requested (MMCHS_HCTL[16] SBGR), this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap is requested on the last block. In read mode, a 1-to-0 transition of the DAT Line active status (MMCHS_PSTATE[2] DLA) between data blocks generates a Block gap event interrupt."; 1005 tc 1 rw type(tc_status) "Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request (MMCHS_HCTL[16] SBGR). In Read mode: This bit is automatically set on completion of a read transfer (MMCHS_PSTATE[9] RTA). In write mode: This bit is set automatically on completion of the DAT line use (MMCHS_PSTATE[2] DLA)."; 1006 cc 1 rw type(cc_status) "Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit (MMCHS_PSTATE[0] CMDI) If the command is a type for which no response is expected, then the command complete interrupt is generated at the end of the command. A command timeout error (MMCHS_STAT[16] CTO) has higher priority than command complete (MMCHS_STAT[0] CC). If a response is expected but none is received, then a command timeout error is detected and signaled instead of the command complete interrupt."; 1007 }; 1008 1009 constants bada_enable_status width(1) "" { 1010 BADA_ENABLE_0 = 0 "Masked"; 1011 BADA_ENABLE_1 = 1 "Enabled"; 1012 }; 1013 1014 constants dto_enable_status width(1) "" { 1015 DTO_ENABLE_0 = 0 "The data timeout detection is deactivated. The host controller provides the clock to the card until the card sends the data or the transfer is aborted."; 1016 DTO_ENABLE_1 = 1 "The data timeout detection is enabled."; 1017 }; 1018 1019 register mmchs_ie addr(base, 0x234) "Interrupt SD enable register This register allows to enable/disable the module to set status bits, on an event-by-event basis. [31:16] = Error Interrupt Status Enable [15:0] = Normal Interrupt Status Enable" { 1020 _ 2 mbz; 1021 bada_enable 1 rw type(bada_enable_status) "Bad access to data space Interrupt Enable"; 1022 cerr_enable 1 rw type(bada_enable_status) "Card error interrupt Enable"; 1023 _ 2 mbz; 1024 admae_enable 1 rw type(bada_enable_status) "ADMA error Interrupt Enable"; 1025 ace_enable 1 rw type(bada_enable_status) "Auto CMD12 error Interrupt Enable"; 1026 cle 1 ro "Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored."; 1027 deb_enable 1 rw type(bada_enable_status) "Data end bit error Interrupt Enable"; 1028 dcrc_enable 1 rw type(bada_enable_status) "Data CRC error Interrupt Enable"; 1029 dto_enable 1 rw type(dto_enable_status) "Data timeout error Interrupt Enable"; 1030 cie_enable 1 rw type(bada_enable_status) "Command index error Interrupt Enable"; 1031 ceb_enable 1 rw type(bada_enable_status) "Command end bit error Interrupt Enable"; 1032 ccrc_enable 1 rw type(bada_enable_status) "Command CRC error Interrupt Enable"; 1033 cto_enable 1 rw type(bada_enable_status) "Command timeout error Interrupt Enable"; 1034 null 1 ro "Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored"; 1035 _ 4 mbz; 1036 bsr_enable 1 rw type(bada_enable_status) "Boot status interrupt Enable A write to this register when MMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored."; 1037 obi_enable 1 rw type(bada_enable_status) "Out-of-Band interrupt Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored."; 1038 cirq_enable 1 rw type(bada_enable_status) "Card interrupt Enable A clear of this bit also clears the corresponding status bit. During 1-bit mode, if the interrupt routine doesn't remove the source of a card interrupt in the SDIO card, the status bit is reasserted when this bit is set to 1."; 1039 crem_enable 1 rw type(bada_enable_status) "Card removal Interrupt Enable"; 1040 cins_enable 1 rw type(bada_enable_status) "Card insertion Interrupt Enable"; 1041 brr_enable 1 rw type(bada_enable_status) "Buffer Read Ready Interrupt Enable"; 1042 bwr_enable 1 rw type(bada_enable_status) "Buffer Write Ready Interrupt Enable"; 1043 dma_enable 1 rw type(bada_enable_status) "DMA interrupt Enable"; 1044 bge_enable 1 rw type(bada_enable_status) "Block Gap Event Interrupt Enable"; 1045 tc_enable 1 rw type(bada_enable_status) "Transfer completed Interrupt Enable"; 1046 cc_enable 1 rw type(bada_enable_status) "Command completed Interrupt Enable"; 1047 }; 1048 1049 register mmchs_ise addr(base, 0x238) "Interrupt signal enable register This register allows to enable/disable the module internal sources of status, on an event-by-event basis. [31:16] = Error Interrupt Signal Enable [15:0] = Normal Interrupt Signal Enable" { 1050 _ 2 mbz; 1051 bada_sigen 1 rw type(bada_enable_status) "Bad access to data space signal status Enable"; 1052 cerr_sigen 1 rw type(bada_enable_status) "Card error interrupt signal status Enable"; 1053 _ 2 mbz; 1054 admae_sigen 1 rw type(bada_enable_status) "ADMA error signal status Enable"; 1055 ace_sigen 1 rw type(bada_enable_status) "Auto CMD12 error signal status Enable"; 1056 cle 1 ro "Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored."; 1057 deb_sigen 1 rw type(bada_enable_status) "Data end bit error signal status Enable"; 1058 dcrc_sigen 1 rw type(bada_enable_status) "Data CRC error signal status Enable"; 1059 dto_sigen 1 rw type(bada_enable_status) "Data timeout error signal status Enable"; 1060 cie_sigen 1 rw type(bada_enable_status) "Command index error signal status Enable"; 1061 ceb_sigen 1 rw type(bada_enable_status) "Command end bit error signal status Enable"; 1062 ccrc_sigen 1 rw type(bada_enable_status) "Command CRC error signal status Enable"; 1063 cto_sigen 1 rw type(bada_enable_status) "Command timeout error signal status Enable"; 1064 null 1 ro "Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored"; 1065 _ 4 mbz; 1066 bsr_sigen 1 rw type(bada_enable_status) "Boot status signal status EnableA write to this register whenMMCHS_CON[17] BOOT_ACK is set to 0x0 is ignored."; 1067 obi_sigen 1 rw type(bada_enable_status) "Out-Of-Band Interrupt signal status Enable A write to this register when MMCHS_CON[14] OBIE is set to 0 is ignored."; 1068 cirq_sigen 1 rw type(bada_enable_status) "Card interrupt signal status Enable"; 1069 crem_sigen 1 rw type(bada_enable_status) "Card removal signal status Enable"; 1070 cins_sigen 1 rw type(bada_enable_status) "Card insertion signal status Enable"; 1071 brr_sigen 1 rw type(bada_enable_status) "Buffer Read Ready signal status Enable"; 1072 bwr_sigen 1 rw type(bada_enable_status) "Buffer Write Ready signal status Enable"; 1073 dma_sigen 1 rw type(bada_enable_status) "DMA interrupt Signal status enable"; 1074 bge_sigen 1 rw type(bada_enable_status) "Black Gap Event signal status Enable"; 1075 tc_sigen 1 rw type(bada_enable_status) "Transfer completed signal status Enable"; 1076 cc_sigen 1 rw type(bada_enable_status) "Command completed signal status Enable"; 1077 }; 1078 1079 constants cni_status width(1) "" { 1080 CNI_0_r = 0 "Not error"; 1081 CNI_1_r = 1 "Command not issued"; 1082 }; 1083 1084 constants acie_status width(1) "" { 1085 ACIE_0_r = 0 "No error"; 1086 ACIE_1_r = 1 "Auto CMD12 Index Error"; 1087 }; 1088 1089 constants aceb_status width(1) "" { 1090 ACEB_0_r = 0 "No error"; 1091 ACEB_1_r = 1 "AutoCMD12 End bit Error"; 1092 }; 1093 1094 constants acce_status width(1) "" { 1095 ACCE_0_r = 0 "No error"; 1096 ACCE_1_r = 1 "Auto CMD12 CRC Error"; 1097 }; 1098 1099 constants acto_status width(1) "" { 1100 ACTO_0_r = 0 "No error"; 1101 ACTO_1_r = 1 "Auto CMD12 Time Out"; 1102 }; 1103 1104 constants acne_status width(1) "" { 1105 ACNE_0_r = 0 "Auto CMD12 Executed"; 1106 ACNE_1_r = 1 "Auto CMD12 Not Executed"; 1107 }; 1108 1109 register mmchs_ac12 addr(base, 0x23C) "Auto CMD12 Error Status Register The host driver may determine which of the errors cases related to Auto CMD12 has occurred by checking this register when an Auto CMD12 Error interrupt occurs. This register is valid only when Auto CMD12 is enabled ([2] ACEN) and Auto CMD12Error ([24] ACE) is set to 1. Note: These bits are automatically reset when starting a new adtc command with data." { 1110 _ 24 mbz; 1111 cni 1 ro type(cni_status) "Command not issue by Auto CMD12 error If this bit is set to 1, it means that pending command is not executed due to Auto CMD12 error : ACEB, ACCE, ACTO or ACNE."; 1112 _ 2 mbz; 1113 acie 1 ro type(acie_status) "Auto CMD12 index error This bit is a set to 1 when response index differs from corresponding command auto CMD12 index previously emitted. This bit depends on the command index check enable (MMCHS_CMD[20] CICE)."; 1114 aceb 1 ro type(aceb_status) "Auto CMD12 end bit error This bit is set to 1 when detecting a 0 at the end bit position of auto CMD12 command response."; 1115 acce 1 ro type(acce_status) "Auto CMD12 CRC error This bit is automatically set to 1 when a CRC7 error is detected in the auto CMD12 command response depending on the enable in MMCHS_CMD[19] CCCE register."; 1116 acto 1 ro type(acto_status) "Auto CMD12 timeout error This bit is set to 1 if no response is received within 64 clock cycles from the end bit of the auto CMD12 command."; 1117 acne 1 ro type(acne_status) "Auto CMD12 not executed This bit is set to 1 if multiple block data transfer command has started and if an error occurs in command before Auto CMD12 starts."; 1118 }; 1119 1120 constants bit64_status width(1) "" { 1121 BIT64_0_r = 0 "32-bit system bus address"; 1122 BIT64_1_r = 1 "64-bit system bus address"; 1123 }; 1124 1125 constants vs18_status width(1) "" { 1126 VS18_0_w = 0 "1.8 V not supported"; 1127 VS18_0_r = 0 "1.8 V not supported"; 1128 VS18_1_r = 1 "1.8 V supported"; 1129 VS18_1_w = 1 "1.8 V supported"; 1130 }; 1131 1132 constants vs30_status width(1) "" { 1133 VS30_0_r = 0 "3.0 V not supported"; 1134 VS30_0_w = 0 "3.0 V not supported"; 1135 VS30_1_w = 1 "3.0 V supported"; 1136 VS30_1_r = 1 "3.0 V supported"; 1137 }; 1138 1139 constants vs33_status width(1) "" { 1140 VS33_0_r = 0 "3.3 V not supported"; 1141 VS33_0_w = 0 "3.3 V not supported"; 1142 VS33_1_w = 1 "3.3 V supported"; 1143 VS33_1_r = 1 "3.3 V supported"; 1144 }; 1145 1146 constants ds_status width(1) "" { 1147 DS_0_r = 0 "DMA not supported"; 1148 DS_1_r = 1 "DMA supported"; 1149 }; 1150 1151 constants hss_status width(1) "" { 1152 HSS_0_r = 0 "High speed not supported"; 1153 HSS_1_r = 1 "High speed supported"; 1154 }; 1155 1156 constants ad2s_status width(1) "" { 1157 AD2S_0_r = 0 "ADMA2 not supported"; 1158 AD2S_1_r = 1 "ADMA2 supported"; 1159 }; 1160 1161 constants mbl_status width(2) "" { 1162 MBL_0_r = 0 "512 bytes"; 1163 MBL_1_r = 1 "1024 bytes"; 1164 MBL_2_r = 2 "2048 bytes"; 1165 }; 1166 1167 constants tcu_status width(1) "" { 1168 TCU_0_r = 0 "kHz"; 1169 TCU_1_r = 1 "MHz"; 1170 }; 1171 1172 register mmchs_capa addr(base, 0x240) "Capabilities register This register lists the capabilities of the MMC/SD/SDIO host controller." { 1173 _ 3 mbz; 1174 bit64 1 ro type(bit64_status) "64-bit system bus support: Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus."; 1175 _ 1 mbz; 1176 vs18 1 rw type(vs18_status) "Voltage support 1.8 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)"; 1177 vs30 1 rw type(vs30_status) "Voltage support 3.0 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)"; 1178 vs33 1 rw type(vs33_status) "Voltage support 3.3 V Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)"; 1179 srs 1 ro type(standbymode_status) "Suspend/Resume support (SDIO cards only) This bit indicates whether the host controller supports suspend/resume functionality."; 1180 ds 1 ro type(ds_status) "DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly."; 1181 hss 1 ro type(hss_status) "High-speed support This bit indicates that the host controller supports high-speed operations and can supply an up-to maximum card frequency."; 1182 _ 1 mbz; 1183 ad2s 1 ro type(ad2s_status) "ADMA2 support: This bit indicates whether the host controller is capable of using ADMA2. It depends on setting of generic parameter MMCHS_HL_HWINFO[0] MADMA_EN"; 1184 _ 1 mbz; 1185 mbl 2 ro type(mbl_status) "Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048 bytes. The host controller supports 512- byte and 1024-byte block transfers."; 1186 _ 2 mbz; 1187 bcf 6 ro type(merge_mem_status) "Base clock frequency for clock provided to the card."; 1188 tcu 1 ro type(tcu_status) "Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error (MMCHS_STAT[20] DTO)."; 1189 _ 1 mbz; 1190 tcf 6 ro type(merge_mem_status) "Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error (MMCHS_STAT[20] DTO)."; 1191 }; 1192 1193 register mmchs_cur_capa addr(base, 0x248) "Maximum current capabilities Register This register indicates the maximum current capability for each voltage. The value is meaningful if the voltage support is set in the capabilities register (). Initialization of this register (via a write access to this register) depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset (via RESETN signal)" { 1194 _ 8 mbz; 1195 cur_1v8 8 rw type(merge_mem_status) "Maximum current for 1.8V"; 1196 cur_3v0 8 rw type(merge_mem_status) "Maximum current for 3.0V"; 1197 cur_3v3 8 rw type(merge_mem_status) "Maximum current for 3.3V"; 1198 }; 1199 1200 constants fe_bada_status width(1) "" { 1201 FE_BADA_0_w = 0 "No effect, No Interrupt."; 1202 FE_BADA_1_w = 1 "Interrupt Forced"; 1203 }; 1204 1205 register mmchs_fe addr(base, 0x250) "Force Event Register for Error Interrupt status The force Event Register is not a physically implemented register. Rather, it is an address at which the Error Interrupt Status register can be written. The effect of a write to this address will be reflected in the Error Interrupt Status Register, if corresponding bit of the Error Interrupt Status Enable Register is set." { 1206 _ 2 mbz; 1207 fe_bada 1 wo type(fe_bada_status) "Force Event Bad access to data space"; 1208 fe_cerr 1 wo type(fe_bada_status) "Force Event Card error"; 1209 _ 2 mbz; 1210 fe_admae 1 wo type(fe_bada_status) "Force Event ADMA Error:"; 1211 fe_ace 1 wo type(fe_bada_status) "Force Event Auto CMD12 error"; 1212 fe_cle 1 rsvd "Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored."; 1213 fe_deb 1 wo type(fe_bada_status) "Force Event Data End Bit error"; 1214 fe_dcrc 1 wo type(fe_bada_status) "Force Event Data CRC Error"; 1215 fe_dto 1 wo type(fe_bada_status) "Force Event Data timeout error"; 1216 fe_cie 1 wo type(fe_bada_status) "Force Event Command index error"; 1217 fe_ceb 1 wo type(fe_bada_status) "Force Event Command end bit error"; 1218 fe_ccrc 1 wo type(fe_bada_status) "Force Event Command CRC Error"; 1219 fe_cto 1 wo type(admae_status) "Command Timeout ErrorThis bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. . For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles. ."; 1220 _ 8 mbz; 1221 fe_cni 1 wo type(fe_bada_status) "Force Event Command not issue by Auto CMD12 error"; 1222 _ 2 mbz; 1223 fe_acie 1 wo type(fe_bada_status) "Force Event Auto CMD12 index error"; 1224 fe_aceb 1 wo type(fe_bada_status) "Force Event Auto CMD12 end bit error"; 1225 fe_acce 1 wo type(fe_bada_status) "Force Event Auto CMD12 CRC error"; 1226 fe_acto 1 wo type(fe_bada_status) "Force Event Auto CMD12 timeout error"; 1227 fe_acne 1 wo type(fe_bada_status) "Force Event Auto CMD12 not executed"; 1228 }; 1229 1230 constants srev_status width(8) "" { 1231 SREV_0_r = 0 "SD Host Specification Version 1.0"; 1232 SREV_1_r = 1 "SD Host Specification Version 2.0"; 1233 }; 1234 1235 register mmchs_rev addr(base, 0x2FC) "Versions Register This register contains the hard coded RTL vendor revision number, the version number of SD specification compliancy and a slot status bit. [31:16] = Host controller version [15:0] = Slot Interrupt Status" { 1236 vrev 8 ro "Vendor Version Number: IP revision [7:4] Major revision [3:0] Minor revision Examples: 0x10 for 1.0 0x21 for 2.1"; 1237 srev 8 ro type(srev_status) "Specification Version Number This status indicates the Standard SD Host Controller Specification Version. The upper and lower 4-bits indicate the version."; 1238 _ 15 mbz; 1239 sis 1 ro "Slot Interrupt Status This status bit indicates the inverted state of interrupt signal for the module. By a power on reset or by setting a software reset for all (MMCHS_SYSCTL[24] SRA), the interrupt signal shall be de-asserted and this status shall read 0."; 1240 }; 1241};