1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_mcspi3.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_mcspi3 msbfirst ( addr base ) "" { 29 30 31 register mcspi_hl_rev ro addr(base, 0x0) "IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" type(uint32); 32 33 constants ffnbyte_status width(5) "" { 34 FFNBYTE_1_r = 1 "FIFO 16 bytes depth"; 35 FFNBYTE_2_r = 2 "FIFO 32 bytes depth"; 36 FFNBYTE_4_r = 4 "FIFO 64 bytes depth"; 37 FFNBYTE_8_r = 8 "FIFO 128 bytes depth"; 38 FFNBYTE_16_r = 16 "FIFO 256 bytes depth"; 39 }; 40 41 constants usefifo_status width(1) "" { 42 USEFIFO_0_r = 0 "FIFO not implemented in design"; 43 USEFIFO_1_r = 1 "FIFO and its management implemented in design with depth defined by FFNBYTE generic"; 44 }; 45 46 register mcspi_hl_hwinfo addr(base, 0x4) "Information about the IP module's hardware configuration, that is, typically the module's HDL generics (if any). Actual field format and encoding is up to the module's designer to decide." { 47 rsvd 25 ro "Reserved These bits are initialized to 0, and writes to them are ignored."; 48 retmode 1 ro "Retention Mode generic parameter. This bit field indicates whether the retention mode is supported using the pin PIRFFRET. 0x0: Retention mode disabled 0x1: Retention mode enabled"; 49 ffnbyte 5 ro type(ffnbyte_status) "FIFO number of byte generic parameter This register defines the value of FFNBYTE generic parameter, only MSB bits from 8 down to 4 are taken into account."; 50 usefifo 1 ro type(usefifo_status) "Use of a FIFO enable: This bit indicates if a FIFO is integrated within controller design with its management."; 51 }; 52 53 constants idlemode_status width(2) "" { 54 IDLEMODE_0 = 0 "Force-idle mode: local target's IDLE state follows (acknowledges) the system's idle requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only."; 55 IDLEMODE_1 = 1 "No-idle mode: local target never enters IDLE state. Backup mode, for debug only."; 56 IDLEMODE_2 = 2 "Smart-idle mode: local target's IDLE state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events."; 57 IDLEMODE_3 = 3 "Smart-idle wake-up-capable mode: local target's IDLE state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module may generate (IRQ- or DMA-request-related) wake-up events when in IDLE state. Mode is relevant only if the appropriate IP module 'swake-up' output(s) is (are) implemented."; 58 }; 59 60 constants freeemu_status width(1) "" { 61 FREEEMU_0 = 0 "IP module is sensitive to emulation suspend."; 62 FREEEMU_1 = 1 "IP module is not sensitive to emulation suspend."; 63 }; 64 65 constants softreset_status width(1) "" { 66 SOFTRESET_0_w = 0 "No action"; 67 SOFTRESET_0_r = 0 "Reset done, no pending action"; 68 SOFTRESET_1_r = 1 "Reset (software or other) ongoing"; 69 SOFTRESET_1_w = 1 "Initiate software reset"; 70 }; 71 72 register mcspi_hl_sysconfig addr(base, 0x10) "Clock management configuration" { 73 rsvd 28 ro ""; 74 idlemode 2 rw type(idlemode_status) "Configuration of the local target state management mode. By definition, target can handle read/write transaction as long as it is out of IDLE state."; 75 freeemu 1 rw type(freeemu_status) "Sensitivity to emulation (debug) suspend input signal."; 76 softreset 1 rw type(softreset_status) "Software reset. (Optional)"; 77 }; 78 79 register mcspi_revision ro addr(base, 0x100) "This register contains the revision number." type(uint32); 80 81 constants clockactivity_status width(2) "" { 82 CLOCKACTIVITY_0 = 0 "OCP and functional clocks may be switched off."; 83 CLOCKACTIVITY_1 = 1 "OCP clock is maintained. Functional clock may be switched off."; 84 CLOCKACTIVITY_2 = 2 "Functional clock is maintained. OCP clock may be switched off."; 85 CLOCKACTIVITY_3 = 3 "OCP and functional clocks are maintained."; 86 }; 87 88 constants sidlemode_status width(2) "" { 89 SIDLEMODE_0 = 0 "If an idle request is detected, the McSPI acknowledges it unconditionally and goes in inactive mode. Interrupt, DMA requests and wake-up lines are unconditionally deasserted and the module wake-up capability is deactivated even if the[EnaWakeUp] bit is set."; 90 SIDLEMODE_1 = 1 "If an idle request is detected, the request is ignored and the module does not switch to wake-up mode, and keeps on behaving normally."; 91 SIDLEMODE_2 = 2 "If an idle request is detected, the module will switch to wake-up mode based on its internal activity, and the wake-up capability can be used if the bit[EnaWakeUp] is set."; 92 SIDLEMODE_3 = 3 "Reserved - do not use."; 93 }; 94 95 constants enawakeup_status width(1) "" { 96 ENAWAKEUP_0 = 0 "Wake-up capability is disabled."; 97 ENAWAKEUP_1 = 1 "Wake-up capability is enabled."; 98 }; 99 100 constants softreset_status1 width(1) "" { 101 SOFTRESET_0 = 0 "(write) Normal mode"; 102 SOFTRESET_1 = 1 "(write) Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware."; 103 }; 104 105 constants autoidle_status width(1) "" { 106 AUTOIDLE_0 = 0 "OCP clock is free-running."; 107 AUTOIDLE_1 = 1 "Automatic OCP clock gating strategy is applied, based on the OCP interface activity."; 108 }; 109 110 register mcspi_sysconfig addr(base, 0x110) "This register allows controlling various parameters of the OCP interface." { 111 _ 22 mbz; 112 clockactivity 2 rw type(clockactivity_status) "Clocks activity during wake-up mode period"; 113 _ 3 mbz; 114 sidlemode 2 rw type(sidlemode_status) "Power management"; 115 enawakeup 1 rw type(enawakeup_status) "Wake-up feature control"; 116 softreset 1 rw type(softreset_status1) "Software reset. During reads it always returns 0."; 117 autoidle 1 rw type(autoidle_status) "Internal OCP clock-gating strategy"; 118 }; 119 120 constants resetdone_status width(1) "" { 121 RESETDONE_0_r = 0 "Internal module reset is ongoing"; 122 RESETDONE_1_r = 1 "Reset completed"; 123 }; 124 125 register mcspi_sysstatus addr(base, 0x114) "This register provides status information about the module excluding the interrupt status information." { 126 _ 31 mbz; 127 resetdone 1 ro type(resetdone_status) "Internal reset monitoring"; 128 }; 129 130 constants eow_status width(1) "" { 131 EOW_0_w = 0 "w:Event status bit unchanged"; 132 EOW_0_r = 0 "r: Event false"; 133 EOW_1_r = 1 "r: Event is pending"; 134 EOW_1_w = 1 "w:Event status bit is reset"; 135 }; 136 137 register mcspi_irqstatus addr(base, 0x118) "The interrupt status regroups all the status of the module internal events that can generate an interrupt." { 138 _ 14 mbz; 139 eow 1 rw1c type(eow_status) "End of word count event when a channel is enabled using the FIFO buffer and the channel had sent the number of SPI word defined byMCSPI_XFERLEVEL[WCNT]."; 140 wks 1 rw1c type(eow_status) "Wake-up event in slave mode when an active control signal is detected on the SPIEN line programmed in the field MCSPI_CH0CONF[SPIENSLV]"; 141 _ 1 mbz; 142 rx3_full 1 rw1c type(eow_status) "Receiver register is full or almost full. Only when Channel 3 is enabled"; 143 tx3_underflow 1 rw1c type(eow_status) "Transmitter register underflow. Only when Channel 3 is enabled. The transmitter register is empty (not updated by host or DMA with new data) before its time slot assignment. Exception: No TX_underflow event when no data has been loaded into the transmitter register since channel has been enabled."; 144 tx3_empty 1 rw1c type(eow_status) "Transmitter register is empty or almost empty. Note: Enabling the channel automatically rises this event."; 145 _ 1 mbz; 146 rx2_full 1 rw1c type(eow_status) "Receiver register full or almost full. Channel 2"; 147 tx2_underflow 1 rw1c type(eow_status) "Transmitter register underflow. Channel 2"; 148 tx2_empty 1 rw1c type(eow_status) "Transmitter register empty or almost empty. Channel 2"; 149 _ 1 mbz; 150 rx1_full 1 rw1c type(eow_status) "Receiver register full or almost full. Channel 1"; 151 tx1_underflow 1 rw1c type(eow_status) "Transmitter register underflow. Channel 1"; 152 tx1_empty 1 rw1c type(eow_status) "Transmitter register empty or almost empty. Channel 1"; 153 rx0_overflow 1 rw1c type(eow_status) "Receiver register overflow (slave mode only). Channel 0"; 154 rx0_full 1 rw1c type(eow_status) "Receiver register full or almost full. Channel 0"; 155 tx0_underflow 1 rw1c type(eow_status) "Transmitter register underflow. Channel 0"; 156 tx0_empty 1 rw1c type(eow_status) "Transmitter register empty or almost empty. Channel 0"; 157 }; 158 159 constants eow_enable_status width(1) "" { 160 EOW_ENABLE_0 = 0 "Interrupt disabled"; 161 EOW_ENABLE_1 = 1 "Interrupt enabled"; 162 }; 163 164 register mcspi_irqenable addr(base, 0x11C) "This register allows enabling/disabling of the module internal sources of interrupt, on an event-by-event basis." { 165 _ 14 mbz; 166 eow_enable 1 rw type(eow_enable_status) "End of Word count Interrupt Enable."; 167 wke 1 rw type(eow_enable_status) "Wake-up event interrupt enable in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit"; 168 _ 1 mbz; 169 rx3_full_enable 1 rw type(eow_enable_status) "Receiver register Full Interrupt Enable. Channel 3"; 170 tx3_underflow_enable 1 rw type(eow_enable_status) "Transmitter register Underflow Interrupt Enable. Channel 3"; 171 tx3_empty_enable 1 rw type(eow_enable_status) "Transmitter register Empty Interrupt Enable. Channel 3"; 172 _ 1 mbz; 173 rx2_full_enable 1 rw type(eow_enable_status) "Receiver register Full Interrupt Enable. Channel 2"; 174 tx2_underflow_enable 1 rw type(eow_enable_status) "Transmitter register Underflow Interrupt Enable. Channel 2"; 175 tx2_empty_enable 1 rw type(eow_enable_status) "Transmitter register Empty Interrupt Enable. Channel 2"; 176 _ 1 mbz; 177 rx1_full_enable 1 rw type(eow_enable_status) "Receiver register Full Interrupt Enable. Channel 1"; 178 tx1_underflow_enable 1 rw type(eow_enable_status) "Transmitter register Underflow Interrupt Enable. Channel 1"; 179 tx1_empty_enable 1 rw type(eow_enable_status) "Transmitter register Empty Interrupt Enable. Channel 1"; 180 rx0_overflow_enable 1 rw type(eow_enable_status) "Receiver register Overflow Interrupt Enable. Channel 0"; 181 rx0_full_enable 1 rw type(eow_enable_status) "Receiver register Full Interrupt Enable. Channel 0"; 182 tx0_underflow_enable 1 rw type(eow_enable_status) "Transmitter register Underflow Interrupt Enable. Channel 0"; 183 tx0_empty_enable 1 rw type(eow_enable_status) "Transmitter register Empty Interrupt Enable. Channel 0"; 184 }; 185 186 constants wken_status width(1) "" { 187 WKEN_0 = 0 "The event is not allowed to wake-up the system, even if the global control bit MCSPI_SYSCONF[EnaWakeUp] is set."; 188 WKEN_1 = 1 "The event is allowed to wake-up the system if the global control bit MCSPI_SYSCONF[EnaWakeUp] is set."; 189 }; 190 191 register mcspi_wakeupenable addr(base, 0x120) "The wake-up enable register allows enabling and disabling of the module internal sources of wakeup on event-by-event basis." { 192 _ 31 mbz; 193 wken 1 rw type(wken_status) "Wake-up functionality in slave mode when an active control signal is detected on the SPIEN line programmed in the MCSPI_CH0CONF[SPIENSLV] bit"; 194 }; 195 196 constants spiendir_status width(1) "" { 197 SPIENDIR_0 = 0 "Output (as in master mode)"; 198 SPIENDIR_1 = 1 "Input (as in slave mode)"; 199 }; 200 201 constants spidatdir1_status width(1) "" { 202 SPIDATDIR1_0 = 0 "Output"; 203 SPIDATDIR1_1 = 1 "Input"; 204 }; 205 206 constants wakd_status width(1) "" { 207 WAKD_0 = 0 "The pin is driven low."; 208 WAKD_1 = 1 "The pin is driven high."; 209 }; 210 211 register mcspi_syst addr(base, 0x124) "This register is used to check the correctness of the system interconnect either internally to peripheral bus, or externally to device I/O pads, when the module is configured in system test (SYSTEST) mode." { 212 _ 20 mbz; 213 ssb 1 rw type(wken_status) "Set status bit"; 214 spiendir 1 rw type(spiendir_status) "Set the direction of the SPIEN[3:0] lines and SPICLK line."; 215 spidatdir1 1 rw type(spidatdir1_status) "Set the direction of the SPIDAT[1]."; 216 spidatdir0 1 rw type(spidatdir1_status) "Set the direction of the SPIDAT[0]."; 217 wakd 1 rw type(wakd_status) "SWAKEUP output (signal data value of internal signal to system). The signal is driven high or low according to the value written into this register bit."; 218 spiclk 1 rw "SPICLK line (signal data value) If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the CLKSPI line (high or low), and a write into this bit has no effect. If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the CLKSPI line is driven high or low according to the value written into this register."; 219 spidat_1 1 rw "SPIDAT[1] line (signal data value) If MCSPI_SYST[SPIDATDIR1] = 0 (output mode direction), the SPIDAT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR1] = 1 (input mode direction), this bit returns the value on the SPIDAT[1] line (high or low), and a write into this bit has no effect."; 220 spidat_0 1 rw "SPIDAT[0] line (signal data value) If MCSPI_SYST[SPIDATDIR0] = 0 (output mode direction), the SPIDAT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIDATDIR0] = 1 (input mode direction), this bit returns the value on the SPIDAT[0] line (high or low), and a write into this bit has no effect."; 221 spien_3 1 rw "SPIEN[3] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[3] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[3] line (high or low), and a write into this bit has no effect."; 222 spien_2 1 rw "SPIEN[2] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[2] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[2] line (high or low), and a write into this bit has no effect."; 223 spien_1 1 rw "SPIEN[1] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[1] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[1] line (high or low), and a write into this bit has no effect."; 224 spien_0 1 rw "SPIEN[0] line (signal data value) If MCSPI_SYST[SPIENDIR] = 0 (output mode direction), the SPIENT[0] line is driven high or low according to the value written into this register. If MCSPI_SYST[SPIENDIR] = 1 (input mode direction), this bit returns the value on the SPIEN[0] line (high or low), and a write into this bit has no effect."; 225 }; 226 227 constants fdaa_status width(1) "" { 228 FDAA_0 = 0 "FIFO data managed by MCSPI_TX(i) and MCSPI_RX(i) registers."; 229 FDAA_1 = 1 "FIFO data managed by MCSPI_DAFTX and MCSPI_DAFRX registers."; 230 }; 231 232 constants moa_status width(1) "" { 233 MOA_0 = 0 "Multiple word access disabled"; 234 MOA_1 = 1 "Multiple word access enabled with FIFO"; 235 }; 236 237 constants initdly_status width(3) "" { 238 INITDLY_0 = 0 "No delay for first spi transfer."; 239 INITDLY_1 = 1 "The controller wait 4 SPI bus clock"; 240 INITDLY_2 = 2 "The controller wait 8 SPI bus clock"; 241 INITDLY_3 = 3 "The controller wait 16 SPI bus clock"; 242 INITDLY_4 = 4 "The controller wait 32 SPI bus clock"; 243 }; 244 245 constants system_test_status width(1) "" { 246 SYSTEM_TEST_0 = 0 "Functional mode"; 247 SYSTEM_TEST_1 = 1 "System test mode (SYSTEST)"; 248 }; 249 250 constants ms_status width(1) "" { 251 MS_0 = 0 "Master - The module generates the SPICLK and SPIEN[3:0]."; 252 MS_1 = 1 "Slave - The module receives the SPICLK and SPIEN[3:0]."; 253 }; 254 255 constants pin34_status width(1) "" { 256 PIN34_0 = 0 "SPIEN is used as a chip-select."; 257 PIN34_1 = 1 "SPIEN is not used. In this mode all related options to chip-select have no meaning."; 258 }; 259 260 constants single_status width(1) "" { 261 SINGLE_0 = 0 "More than one channel will be used in master mode."; 262 SINGLE_1 = 1 "Only one channel will be used in master mode. This bit must be set in Force SPIEN mode."; 263 }; 264 265 register mcspi_modulctrl addr(base, 0x128) "This register is dedicated to the configuration of the serial port interface." { 266 _ 23 mbz; 267 fdaa 1 rw type(fdaa_status) "FIFO DMA address 256-bit aligned This register is used when a FIFO is managed by the module and DMA connected to the controller provides only 256-bit aligned address. If this bit is set the enabled channel which uses the FIFO has its data managed through MCSPI_DAFTX and MCSPI_DAFRX registers instead of MCSPI_TX(i) and MCSPI_RX(i) registers."; 268 moa 1 rw type(moa_status) "Multiple word OCP access: This register can only be used when a channel is enabled using a FIFO. It allows the system to perform multiple SPI word access for a single 32-bit OCP word access. This is possible for WL < 16."; 269 initdly 3 rw type(initdly_status) "Initial SPI delay for first transfer: This register is an option only available in SINGLE master mode. The controller waits for a delay to transmit the first SPI word after channel enabled and corresponding TX register filled. This delay is based on SPI output frequency clock. No clock output provided to the boundary and chip select is not active in 4-pin mode within this period."; 270 system_test 1 rw type(system_test_status) "Enables the system test mode"; 271 ms 1 rw type(ms_status) "Master/slave"; 272 pin34 1 rw type(pin34_status) "Pin mode selection: This register is used to configure the SPI pin mode, in master or slave mode. If asserted the controller only use SIMO, SOMI, and SPICLK clock pin for SPI transfers."; 273 single 1 rw type(single_status) "Single channel/Multi Channel (master mode only)"; 274 }; 275 276 constants clkg_status width(1) "" { 277 CLKG_0 = 0 "Clock granularity of power of 2"; 278 CLKG_1 = 1 "One clock cycle granularity"; 279 }; 280 281 constants ffer_status width(1) "" { 282 FFER_0 = 0 "The buffer is not used to receive data."; 283 FFER_1 = 1 "The buffer is used to receive data."; 284 }; 285 286 constants ffew_status width(1) "" { 287 FFEW_0 = 0 "The buffer is not used to transmit data."; 288 FFEW_1 = 1 "The buffer is used to transmit data."; 289 }; 290 291 constants tcs0_status width(2) "" { 292 TCS0_0 = 0 "0.5 clock cycle"; 293 TCS0_1 = 1 "1.5 clock cycles"; 294 TCS0_2 = 2 "2.5 clock cycles"; 295 TCS0_3 = 3 "3.5 clock cycles"; 296 }; 297 298 constants sbpol_status width(1) "" { 299 SBPOL_0 = 0 "Start-bit polarity is held to 0 during SPI transfer."; 300 SBPOL_1 = 1 "Start-bit polarity is held to 1 during SPI transfer."; 301 }; 302 303 constants sbe_status width(1) "" { 304 SBE_0 = 0 "Default SPI transfer length as specified by WL bit field"; 305 SBE_1 = 1 "Start bit D/CX added before SPI transfer polarity is defined by MCSPI_CH0CONF[SBPOL]"; 306 }; 307 308 constants spienslv_status width(2) "" { 309 SPIENSLV_0 = 0 "Detection enabled only on SPIEN[0]"; 310 SPIENSLV_1 = 1 "Detection enabled only on SPIEN[1]"; 311 SPIENSLV_2 = 2 "Detection enabled only on SPIEN[2]"; 312 SPIENSLV_3 = 3 "Detection enabled only on SPIEN[3]"; 313 }; 314 315 constants force_status width(1) "" { 316 FORCE_0 = 0 "Writing 0 into this bit drives low the SPIEN line when MCSPI_CHCONF(i)[EPOL]=0, and drives it high when MCSPI_CHCONF(i)[EPOL]=1."; 317 FORCE_1 = 1 "Writing 1 into this bit drives high the SPIEN line when MCSPI_CHCONF(i)[EPOL]=0, and drives it low when MCSPI_CHCONF(i)[EPOL]=1."; 318 }; 319 320 constants is_status width(1) "" { 321 IS_0 = 0 "Data line 0 (SPIDAT[0]) selected for reception"; 322 IS_1 = 1 "Data line 1 (SPIDAT[1]) selected for reception"; 323 }; 324 325 constants dpe1_status width(1) "" { 326 DPE1_0 = 0 "Data line 1 (SPIDAT[1]) selected for transmission"; 327 DPE1_1 = 1 "No transmission on Data Line1 (SPIDAT[1])"; 328 }; 329 330 constants dpe0_status width(1) "" { 331 DPE0_0 = 0 "Data Line0 (SPIDAT[0]) selected for transmission"; 332 DPE0_1 = 1 "No transmission on data line 0 (SPIDAT[0])"; 333 }; 334 335 constants dmar_status width(1) "" { 336 DMAR_0 = 0 "DMA read request disabled"; 337 DMAR_1 = 1 "DMA read request enabled"; 338 }; 339 340 constants dmaw_status width(1) "" { 341 DMAW_0 = 0 "DMA write request disabled"; 342 DMAW_1 = 1 "DMA write request enabled"; 343 }; 344 345 constants trm_status width(2) "" { 346 TRM_0 = 0 "Transmit-and-receive mode"; 347 TRM_1 = 1 "Receive-only mode"; 348 TRM_2 = 2 "Transmit-only mode"; 349 TRM_3 = 3 "Reserved"; 350 }; 351 352 constants wl_status width(5) "" { 353 WL_0 = 0 "Reserved"; 354 WL_1 = 1 "Reserved"; 355 WL_2 = 2 "Reserved"; 356 WL_3 = 3 "The SPI word is 4 bits long"; 357 WL_4 = 4 "The SPI word is 5 bits long"; 358 WL_5 = 5 "The SPI word is 6 bits long"; 359 WL_6 = 6 "The SPI word is 7 bits long"; 360 WL_7 = 7 "The SPI word is 8 bits long"; 361 WL_8 = 8 "The SPI word is 9 bits long"; 362 WL_9 = 9 "The SPI word is 10 bits long"; 363 WL_10 = 10 "The SPI word is 11 bits long"; 364 WL_11 = 11 "The SPI word is 12 bits long"; 365 WL_12 = 12 "The SPI word is 13 bits long"; 366 WL_13 = 13 "The SPI word is 14 bits long"; 367 WL_14 = 14 "The SPI word is 15 bits long"; 368 WL_15 = 15 "The SPI word is 16 bits long"; 369 WL_16 = 16 "The SPI word is 17 bits long"; 370 WL_17 = 17 "The SPI word is 18 bits long"; 371 WL_18 = 18 "The SPI word is 19 bits long"; 372 WL_19 = 19 "The SPI word is 20 bits long"; 373 WL_20 = 20 "The SPI word is 21 bits long"; 374 WL_21 = 21 "The SPI word is 22 bits long"; 375 WL_22 = 22 "The SPI word is 23 bits long"; 376 WL_23 = 23 "The SPI word is 24 bits long"; 377 WL_24 = 24 "The SPI word is 25 bits long"; 378 WL_25 = 25 "The SPI word is 26 bits long"; 379 WL_26 = 26 "The SPI word is 27 bits long"; 380 WL_27 = 27 "The SPI word is 28 bits long"; 381 WL_28 = 28 "The SPI word is 29 bits long"; 382 WL_29 = 29 "The SPI word is 30 bits long"; 383 WL_30 = 30 "The SPI word is 31 bits long"; 384 WL_31 = 31 "The SPI word is 32 bits long"; 385 }; 386 387 constants epol_status width(1) "" { 388 EPOL_0 = 0 "SPIEN is held high during the ACTIVE state."; 389 EPOL_1 = 1 "SPIEN is held low during the ACTIVE state."; 390 }; 391 392 constants clkd_status width(4) "" { 393 CLKD_0 = 0 "1"; 394 CLKD_1 = 1 "2"; 395 CLKD_2 = 2 "4"; 396 CLKD_3 = 3 "8"; 397 CLKD_4 = 4 "16"; 398 CLKD_5 = 5 "32"; 399 CLKD_6 = 6 "64"; 400 CLKD_7 = 7 "128"; 401 CLKD_8 = 8 "256"; 402 CLKD_9 = 9 "512"; 403 CLKD_10 = 10 "1024"; 404 CLKD_11 = 11 "2048"; 405 CLKD_12 = 12 "4096"; 406 CLKD_13 = 13 "8192"; 407 CLKD_14 = 14 "16384"; 408 CLKD_15 = 15 "32768"; 409 }; 410 411 constants pol_status width(1) "" { 412 POL_0 = 0 "SPICLK is held high during the ACTIVE state"; 413 POL_1 = 1 "SPICLK is held low during the ACTIVE state"; 414 }; 415 416 constants pha_status width(1) "" { 417 PHA_0 = 0 "Data are latched on odd-numbered edges of SPICLK."; 418 PHA_1 = 1 "Data are latched on even-numbered edges of SPICLK."; 419 }; 420 421 register mcspi_chxconf addr(base, 0x12C) "This register is dedicated to the configuration of the channel 0" { 422 _ 2 mbz; 423 clkg 1 rw type(clkg_status) "Clock divider granularity This register defines the granularity of channel clock divider: power of 2 or one clock cycle granularity. When this bit is set the register MCSPI_CHCTRL[EXTCLK] must be configured to reach a maximum of 4096 clock divider ratio. Then the clock divider ratio is a concatenation of MCSPI_CHCONF[CLKD] and MCSPI_CHCTRL[EXTCLK] values"; 424 ffer 1 rw type(ffer_status) "FIFO enabled for receive: Only one channel can have this bit field set."; 425 ffew 1 rw type(ffew_status) "FIFO enabled for transmit: Only one channel can have this bit field set."; 426 tcs0 2 rw type(tcs0_status) "Chip-select time control This 2-bit field defines the number of interface clock cycles between CS toggling and first or last edge of SPI clock."; 427 sbpol 1 rw type(sbpol_status) "Start-bit polarity"; 428 sbe 1 rw type(sbe_status) "Start-bit enable for SPI transfer"; 429 spienslv 2 rw type(spienslv_status) "Channel 0 only and slave mode only: SPI slave select signal detection. Reserved bits for other cases."; 430 force 1 rw type(force_status) "Manual SPIEN assertion to keep SPIEN active between SPI words (single channel master mode only)."; 431 turbo 1 rw type(sbpol_status) "Turbo mode"; 432 is 1 rw type(is_status) "Input Select"; 433 dpe1 1 rw type(dpe1_status) "Transmission enable for data line 1 (SPIDATAGZEN[1])"; 434 dpe0 1 rw type(dpe0_status) "Transmission Enable for data line 0 (SPIDATAGZEN[0])"; 435 dmar 1 rw type(dmar_status) "DMA read request The DMA read request line is asserted when the channel is enabled and a new data is available in the receive register of the channel. The DMA read request line is deasserted on read completion of the receive register of the channel."; 436 dmaw 1 rw type(dmaw_status) "DMA write request. The DMA write request line is asserted when The channel is enabled and the transmitter register of the channel is empty. The DMA write request line is deasserted on load completion of the transmitter register of the channel."; 437 trm 2 rw type(trm_status) "Transmit/receive modes"; 438 wl 5 rw type(wl_status) "SPI word length"; 439 epol 1 rw type(epol_status) "SPIEN polarity"; 440 clkd 4 rw type(clkd_status) "Frequency divider for SPICLK (only when the module is a Master SPI device). A programmable clock divider divides the SPI reference clock (CLKSPIREF) with a 4-bit value, and results in a new clock SPICLK available to shift-in and shift-out data. By default the clock divider ratio has a power of 2 granularity when MCSPI_CHCONF[CLKG] is cleared. Otherwise this register is the 4-LSB bit of a 12-bit register concatenated with clock divider extension MCSPI_CHCTRL[EXTCLK] register. The value description below defines the clock ratio when MCSPI_CHCONF[CLKG] is set to 0."; 441 pol 1 rw type(pol_status) "SPICLK polarity"; 442 pha 1 rw type(pha_status) "SPICLK phase"; 443 }; 444 445 constants rxfff_status width(1) "" { 446 RXFFF_0_r = 0 "FIFO receive buffer is not full"; 447 RXFFF_1_r = 1 "FIFO receive buffer is full"; 448 }; 449 450 constants rxffe_status width(1) "" { 451 RXFFE_0_r = 0 "FIFO receive buffer is not empty"; 452 RXFFE_1_r = 1 "FIFO receive buffer is empty"; 453 }; 454 455 constants txfff_status width(1) "" { 456 TXFFF_0_r = 0 "FIFO transmit buffer is not full"; 457 TXFFF_1_r = 1 "FIFO transmit buffer is full"; 458 }; 459 460 constants txffe_status width(1) "" { 461 TXFFE_0_r = 0 "FIFO transmit buffer is not empty"; 462 TXFFE_1_r = 1 "FIFO transmit buffer is empty"; 463 }; 464 465 constants eot_status width(1) "" { 466 EOT_0_r = 0 "This flag is automatically cleared when the shift register is loaded with the data from the transmitter register (beginning of transfer)."; 467 EOT_1_r = 1 "This flag is automatically set to one at the end of an SPI transfer."; 468 }; 469 470 constants txs_status width(1) "" { 471 TXS_0_r = 0 "Register is full."; 472 TXS_1_r = 1 "Register is empty."; 473 }; 474 475 constants rxs_status width(1) "" { 476 RXS_0_r = 0 "Register is empty."; 477 RXS_1_r = 1 "Register is full."; 478 }; 479 480 register mcspi_chxstat addr(base, 0x130) "This register provides status information about transmitter and receiver registers of channel 0." { 481 _ 25 mbz; 482 rxfff 1 ro type(rxfff_status) "Channel 'i' FIFO receive buffer full status"; 483 rxffe 1 ro type(rxffe_status) "Channel 'i' FIFO receive buffer empty status"; 484 txfff 1 ro type(txfff_status) "Channel 'i' FIFO transmit buffer full status"; 485 txffe 1 ro type(txffe_status) "Channel 'i' FIFO transmit buffer empty status"; 486 eot 1 ro type(eot_status) "Channel 'i' end of transfer status. The definitions of beginning and end of transfer vary with master versus slave and the transfer format (transmit/receive modes, turbo mode). See dedicated chapters for details."; 487 txs 1 ro type(txs_status) "Channel 'i' transmitter register status"; 488 rxs 1 ro type(rxs_status) "Channel 'i' receiver register status"; 489 }; 490 491 constants extclk_status width(8) "" { 492 EXTCLK_0 = 0 "Clock ratio is CLKD + 1."; 493 EXTCLK_1 = 1 "Clock ratio is CLKD + 1 + 16."; 494 EXTCLK_255 = 255 "Clock ratio is CLKD + 1 + 4080."; 495 }; 496 497 constants en_status width(1) "" { 498 EN_0 = 0 "Channel 'i' is not active."; 499 EN_1 = 1 "Channel 'i' is active."; 500 }; 501 502 register mcspi_chxctrl addr(base, 0x134) "This register is dedicated to enable channel 0." { 503 _ 16 mbz; 504 extclk 8 rw type(extclk_status) "Clock ratio extension: This register is used to concatenate with MCSPI_CHCONF[CLKD] register for clock ratio only when granularity is one clock cycle (MCSPI_CHCONF[CLKG] set to 1). Then the maximum value reached is 4096 clock divider ratio."; 505 _ 7 mbz; 506 en 1 rw type(en_status) "Channel enable"; 507 }; 508 509 register mcspi_txx rw addr(base, 0x138) "This register contains a single SPI word to transmit on the serial link, what ever SPI word length is." type(uint32); 510 511 register mcspi_rxx ro addr(base, 0x13C) "This register contains a single SPI word received through the serial link, what ever SPI word length is." type(uint32); 512 513 constants wcnt_status width(16) "" { 514 WCNT_0 = 0 "Counter not used"; 515 WCNT_1 = 1 "One word"; 516 WCNT_65534 = 65534 "65534 SPI word"; 517 WCNT_65535 = 65535 "65535 SPI word"; 518 }; 519 520 constants afl_status width(8) "" { 521 AFL_0 = 0 "1 byte"; 522 AFL_1 = 1 "2 bytes"; 523 AFL_254 = 254 "255bytes"; 524 AFL_255 = 255 "256bytes"; 525 }; 526 527 constants ael_status width(8) "" { 528 AEL_0 = 0 "1 byte"; 529 AEL_1 = 1 "2 bytes"; 530 AEL_254 = 254 "255 bytes"; 531 AEL_255 = 255 "256bytes"; 532 }; 533 534 register mcspi_xferlevel addr(base, 0x17C) "This register provides transfer levels needed while using FIFO buffer during transfer." { 535 wcnt 16 rw type(wcnt_status) "SPI word counter. This register holds the programmable value of number of SPI word to be transferred on channel which is using the FIFO buffer. When transfer had started, a read back in this register returns the current SPI word transfer index."; 536 afl 8 rw type(afl_status) "Buffer almost full This register holds the programmable almost full level value used to determine almost full buffer condition. If the user wants an interrupt or a DMA read request to be issued during a receive operation when the data buffer holds at least n bytes, then the buffer MCSPI_MODULCTRL[AFL] must be set with n-1.The size of this register is defined by the generic parameter FFNBYTE."; 537 ael 8 rw type(ael_status) "Buffer almost empty. This register holds the programmable almost empty level value used to determine almost empty buffer condition. If the user wants an interrupt or a DMA write request to be issued during a transmit operation when the data buffer is able to receive n bytes, then the bufferMCSPI_MODULCTRL[AEL] must be set with - 1."; 538 }; 539};