1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_l3_ram_firewall.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_l3_ram_firewall msbfirst ( addr base ) "" { 29 30 31 register error_log_k addr(base, 0x0) "Error log register for port k" { 32 _ 8 mbz; 33 blk_burst_violation 1 rw "Read 0x1: 2D burst not allowed or exceeding allowed size Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 34 _ 1 mbz; 35 region_start_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 36 region_end_errlog 5 rw "Read: Wrong access hit this region number Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 37 reqinfo_errlog 12 rw "Read: Error in reqinfo vector mapped as follows: [11: 8] ConnID [3:0] [7] MCMD [0] [6:4] Reserved [3] MReqDebug [2] Reserved [1] MReqSupervisor [0] MReqType Write to clear ERROR_LOG_k and LOGICAL_ADDR_ERRLOG_k registers"; 38 }; 39 40 register logical_addr_errlog_k ro addr(base, 0x4) "Logical Physical Address Error log register for port k" type(uint32); 41 42 register regupdate_control addr(base, 0x40) "Register update control register" { 43 _ 30 mbz; 44 fw_load_req 1 ro "Hadrdware set/Software clear"; 45 busy_req 1 rw "Busy request"; 46 }; 47 48 register start_region_i_1 addr(base, 0x90) "Start physical address of region i" { 49 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 50 _ 12 mbz; 51 }; 52 53 register start_region_i_2 addr(base, 0xA0) "Start physical address of region i" { 54 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 55 _ 12 mbz; 56 }; 57 58 register start_region_i_3 addr(base, 0xB0) "Start physical address of region i" { 59 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 60 _ 12 mbz; 61 }; 62 63 register start_region_i_4 addr(base, 0xC0) "Start physical address of region i" { 64 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 65 _ 12 mbz; 66 }; 67 68 register start_region_i_5 addr(base, 0xD0) "Start physical address of region i" { 69 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 70 _ 12 mbz; 71 }; 72 73 register start_region_i_6 addr(base, 0xE0) "Start physical address of region i" { 74 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 75 _ 12 mbz; 76 }; 77 78 register start_region_i_7 addr(base, 0xF0) "Start physical address of region i" { 79 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 80 _ 12 mbz; 81 }; 82 83 register start_region_i_8 addr(base, 0x100) "Start physical address of region i" { 84 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 85 _ 12 mbz; 86 }; 87 88 register start_region_i_9 addr(base, 0x110) "Start physical address of region i" { 89 start_region 20 rw "Physical target start address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 90 _ 12 mbz; 91 }; 92 93 register end_region_i_1 addr(base, 0x94) "End physical address of region i" { 94 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 95 _ 9 mbz; 96 region_enable_port2 1 rw "Enable this region for port 2."; 97 region_enable_port1 1 rw "Enable this region for port 1."; 98 region_enable_port0 1 rw "Enable this region for port 0."; 99 }; 100 101 register end_region_i_2 addr(base, 0xA4) "End physical address of region i" { 102 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 103 _ 9 mbz; 104 region_enable_port2 1 rw "Enable this region for port 2."; 105 region_enable_port1 1 rw "Enable this region for port 1."; 106 region_enable_port0 1 rw "Enable this region for port 0."; 107 }; 108 109 register end_region_i_3 addr(base, 0xB4) "End physical address of region i" { 110 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 111 _ 9 mbz; 112 region_enable_port2 1 rw "Enable this region for port 2."; 113 region_enable_port1 1 rw "Enable this region for port 1."; 114 region_enable_port0 1 rw "Enable this region for port 0."; 115 }; 116 117 register end_region_i_4 addr(base, 0xC4) "End physical address of region i" { 118 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 119 _ 9 mbz; 120 region_enable_port2 1 rw "Enable this region for port 2."; 121 region_enable_port1 1 rw "Enable this region for port 1."; 122 region_enable_port0 1 rw "Enable this region for port 0."; 123 }; 124 125 register end_region_i_5 addr(base, 0xD4) "End physical address of region i" { 126 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 127 _ 9 mbz; 128 region_enable_port2 1 rw "Enable this region for port 2."; 129 region_enable_port1 1 rw "Enable this region for port 1."; 130 region_enable_port0 1 rw "Enable this region for port 0."; 131 }; 132 133 register end_region_i_6 addr(base, 0xE4) "End physical address of region i" { 134 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 135 _ 9 mbz; 136 region_enable_port2 1 rw "Enable this region for port 2."; 137 region_enable_port1 1 rw "Enable this region for port 1."; 138 region_enable_port0 1 rw "Enable this region for port 0."; 139 }; 140 141 register end_region_i_7 addr(base, 0xF4) "End physical address of region i" { 142 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 143 _ 9 mbz; 144 region_enable_port2 1 rw "Enable this region for port 2."; 145 region_enable_port1 1 rw "Enable this region for port 1."; 146 region_enable_port0 1 rw "Enable this region for port 0."; 147 }; 148 149 register end_region_i_8 addr(base, 0x104) "End physical address of region i" { 150 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 151 _ 9 mbz; 152 region_enable_port2 1 rw "Enable this region for port 2."; 153 region_enable_port1 1 rw "Enable this region for port 1."; 154 region_enable_port0 1 rw "Enable this region for port 0."; 155 }; 156 157 register end_region_i_9 addr(base, 0x114) "End physical address of region i" { 158 end_region 20 rw "Physical target end address of firewall region i. The size of this bit field depends on target addressable space, the maximum is [31:12]. See."; 159 _ 9 mbz; 160 region_enable_port2 1 rw "Enable this region for port 2."; 161 region_enable_port1 1 rw "Enable this region for port 1."; 162 region_enable_port0 1 rw "Enable this region for port 0."; 163 }; 164 165 register mrm_permission_region_low_j_0 addr(base, 0x88) "Region j Permission Low" { 166 _ 1 rsvd; 167 _ 1 rsvd; 168 _ 1 rsvd; 169 _ 1 rsvd; 170 _ 1 rsvd; 171 _ 1 rsvd; 172 _ 1 rsvd; 173 _ 1 rsvd; 174 _ 1 rsvd; 175 _ 1 rsvd; 176 _ 1 rsvd; 177 _ 1 rsvd; 178 _ 1 rsvd; 179 _ 1 rsvd; 180 _ 1 rsvd; 181 _ 1 rsvd; 182 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 183 pub_usr_debug 1 rw "Public User Debug Allowed"; 184 _ 1 rsvd; 185 _ 1 rsvd; 186 pub_prv_write 1 rw "Public Privilege Write Allowed"; 187 pub_prv_read 1 rw "Public Privilege Read Allowed"; 188 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 189 pub_usr_write 1 rw "Public User Write Access Allowed"; 190 pub_usr_read 1 rw "Public User Read Access Allowed"; 191 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 192 _ 1 rsvd; 193 _ 1 rsvd; 194 _ 1 rsvd; 195 _ 1 rsvd; 196 _ 1 rsvd; 197 _ 1 rsvd; 198 }; 199 200 register mrm_permission_region_low_j_1 addr(base, 0x98) "Region j Permission Low" { 201 _ 1 rsvd; 202 _ 1 rsvd; 203 _ 1 rsvd; 204 _ 1 rsvd; 205 _ 1 rsvd; 206 _ 1 rsvd; 207 _ 1 rsvd; 208 _ 1 rsvd; 209 _ 1 rsvd; 210 _ 1 rsvd; 211 _ 1 rsvd; 212 _ 1 rsvd; 213 _ 1 rsvd; 214 _ 1 rsvd; 215 _ 1 rsvd; 216 _ 1 rsvd; 217 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 218 pub_usr_debug 1 rw "Public User Debug Allowed"; 219 _ 1 rsvd; 220 _ 1 rsvd; 221 pub_prv_write 1 rw "Public Privilege Write Allowed"; 222 pub_prv_read 1 rw "Public Privilege Read Allowed"; 223 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 224 pub_usr_write 1 rw "Public User Write Access Allowed"; 225 pub_usr_read 1 rw "Public User Read Access Allowed"; 226 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 227 _ 1 rsvd; 228 _ 1 rsvd; 229 _ 1 rsvd; 230 _ 1 rsvd; 231 _ 1 rsvd; 232 _ 1 rsvd; 233 }; 234 235 register mrm_permission_region_low_j_2 addr(base, 0xA8) "Region j Permission Low" { 236 _ 1 rsvd; 237 _ 1 rsvd; 238 _ 1 rsvd; 239 _ 1 rsvd; 240 _ 1 rsvd; 241 _ 1 rsvd; 242 _ 1 rsvd; 243 _ 1 rsvd; 244 _ 1 rsvd; 245 _ 1 rsvd; 246 _ 1 rsvd; 247 _ 1 rsvd; 248 _ 1 rsvd; 249 _ 1 rsvd; 250 _ 1 rsvd; 251 _ 1 rsvd; 252 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 253 pub_usr_debug 1 rw "Public User Debug Allowed"; 254 _ 1 rsvd; 255 _ 1 rsvd; 256 pub_prv_write 1 rw "Public Privilege Write Allowed"; 257 pub_prv_read 1 rw "Public Privilege Read Allowed"; 258 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 259 pub_usr_write 1 rw "Public User Write Access Allowed"; 260 pub_usr_read 1 rw "Public User Read Access Allowed"; 261 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 262 _ 1 rsvd; 263 _ 1 rsvd; 264 _ 1 rsvd; 265 _ 1 rsvd; 266 _ 1 rsvd; 267 _ 1 rsvd; 268 }; 269 270 register mrm_permission_region_low_j_3 addr(base, 0xB8) "Region j Permission Low" { 271 _ 1 rsvd; 272 _ 1 rsvd; 273 _ 1 rsvd; 274 _ 1 rsvd; 275 _ 1 rsvd; 276 _ 1 rsvd; 277 _ 1 rsvd; 278 _ 1 rsvd; 279 _ 1 rsvd; 280 _ 1 rsvd; 281 _ 1 rsvd; 282 _ 1 rsvd; 283 _ 1 rsvd; 284 _ 1 rsvd; 285 _ 1 rsvd; 286 _ 1 rsvd; 287 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 288 pub_usr_debug 1 rw "Public User Debug Allowed"; 289 _ 1 rsvd; 290 _ 1 rsvd; 291 pub_prv_write 1 rw "Public Privilege Write Allowed"; 292 pub_prv_read 1 rw "Public Privilege Read Allowed"; 293 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 294 pub_usr_write 1 rw "Public User Write Access Allowed"; 295 pub_usr_read 1 rw "Public User Read Access Allowed"; 296 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 297 _ 1 rsvd; 298 _ 1 rsvd; 299 _ 1 rsvd; 300 _ 1 rsvd; 301 _ 1 rsvd; 302 _ 1 rsvd; 303 }; 304 305 register mrm_permission_region_low_j_4 addr(base, 0xC8) "Region j Permission Low" { 306 _ 1 rsvd; 307 _ 1 rsvd; 308 _ 1 rsvd; 309 _ 1 rsvd; 310 _ 1 rsvd; 311 _ 1 rsvd; 312 _ 1 rsvd; 313 _ 1 rsvd; 314 _ 1 rsvd; 315 _ 1 rsvd; 316 _ 1 rsvd; 317 _ 1 rsvd; 318 _ 1 rsvd; 319 _ 1 rsvd; 320 _ 1 rsvd; 321 _ 1 rsvd; 322 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 323 pub_usr_debug 1 rw "Public User Debug Allowed"; 324 _ 1 rsvd; 325 _ 1 rsvd; 326 pub_prv_write 1 rw "Public Privilege Write Allowed"; 327 pub_prv_read 1 rw "Public Privilege Read Allowed"; 328 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 329 pub_usr_write 1 rw "Public User Write Access Allowed"; 330 pub_usr_read 1 rw "Public User Read Access Allowed"; 331 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 332 _ 1 rsvd; 333 _ 1 rsvd; 334 _ 1 rsvd; 335 _ 1 rsvd; 336 _ 1 rsvd; 337 _ 1 rsvd; 338 }; 339 340 register mrm_permission_region_low_j_5 addr(base, 0xD8) "Region j Permission Low" { 341 _ 1 rsvd; 342 _ 1 rsvd; 343 _ 1 rsvd; 344 _ 1 rsvd; 345 _ 1 rsvd; 346 _ 1 rsvd; 347 _ 1 rsvd; 348 _ 1 rsvd; 349 _ 1 rsvd; 350 _ 1 rsvd; 351 _ 1 rsvd; 352 _ 1 rsvd; 353 _ 1 rsvd; 354 _ 1 rsvd; 355 _ 1 rsvd; 356 _ 1 rsvd; 357 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 358 pub_usr_debug 1 rw "Public User Debug Allowed"; 359 _ 1 rsvd; 360 _ 1 rsvd; 361 pub_prv_write 1 rw "Public Privilege Write Allowed"; 362 pub_prv_read 1 rw "Public Privilege Read Allowed"; 363 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 364 pub_usr_write 1 rw "Public User Write Access Allowed"; 365 pub_usr_read 1 rw "Public User Read Access Allowed"; 366 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 367 _ 1 rsvd; 368 _ 1 rsvd; 369 _ 1 rsvd; 370 _ 1 rsvd; 371 _ 1 rsvd; 372 _ 1 rsvd; 373 }; 374 375 register mrm_permission_region_low_j_6 addr(base, 0xE8) "Region j Permission Low" { 376 _ 1 rsvd; 377 _ 1 rsvd; 378 _ 1 rsvd; 379 _ 1 rsvd; 380 _ 1 rsvd; 381 _ 1 rsvd; 382 _ 1 rsvd; 383 _ 1 rsvd; 384 _ 1 rsvd; 385 _ 1 rsvd; 386 _ 1 rsvd; 387 _ 1 rsvd; 388 _ 1 rsvd; 389 _ 1 rsvd; 390 _ 1 rsvd; 391 _ 1 rsvd; 392 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 393 pub_usr_debug 1 rw "Public User Debug Allowed"; 394 _ 1 rsvd; 395 _ 1 rsvd; 396 pub_prv_write 1 rw "Public Privilege Write Allowed"; 397 pub_prv_read 1 rw "Public Privilege Read Allowed"; 398 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 399 pub_usr_write 1 rw "Public User Write Access Allowed"; 400 pub_usr_read 1 rw "Public User Read Access Allowed"; 401 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 402 _ 1 rsvd; 403 _ 1 rsvd; 404 _ 1 rsvd; 405 _ 1 rsvd; 406 _ 1 rsvd; 407 _ 1 rsvd; 408 }; 409 410 register mrm_permission_region_low_j_7 addr(base, 0xF8) "Region j Permission Low" { 411 _ 1 rsvd; 412 _ 1 rsvd; 413 _ 1 rsvd; 414 _ 1 rsvd; 415 _ 1 rsvd; 416 _ 1 rsvd; 417 _ 1 rsvd; 418 _ 1 rsvd; 419 _ 1 rsvd; 420 _ 1 rsvd; 421 _ 1 rsvd; 422 _ 1 rsvd; 423 _ 1 rsvd; 424 _ 1 rsvd; 425 _ 1 rsvd; 426 _ 1 rsvd; 427 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 428 pub_usr_debug 1 rw "Public User Debug Allowed"; 429 _ 1 rsvd; 430 _ 1 rsvd; 431 pub_prv_write 1 rw "Public Privilege Write Allowed"; 432 pub_prv_read 1 rw "Public Privilege Read Allowed"; 433 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 434 pub_usr_write 1 rw "Public User Write Access Allowed"; 435 pub_usr_read 1 rw "Public User Read Access Allowed"; 436 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 437 _ 1 rsvd; 438 _ 1 rsvd; 439 _ 1 rsvd; 440 _ 1 rsvd; 441 _ 1 rsvd; 442 _ 1 rsvd; 443 }; 444 445 register mrm_permission_region_low_j_8 addr(base, 0x108) "Region j Permission Low" { 446 _ 1 rsvd; 447 _ 1 rsvd; 448 _ 1 rsvd; 449 _ 1 rsvd; 450 _ 1 rsvd; 451 _ 1 rsvd; 452 _ 1 rsvd; 453 _ 1 rsvd; 454 _ 1 rsvd; 455 _ 1 rsvd; 456 _ 1 rsvd; 457 _ 1 rsvd; 458 _ 1 rsvd; 459 _ 1 rsvd; 460 _ 1 rsvd; 461 _ 1 rsvd; 462 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 463 pub_usr_debug 1 rw "Public User Debug Allowed"; 464 _ 1 rsvd; 465 _ 1 rsvd; 466 pub_prv_write 1 rw "Public Privilege Write Allowed"; 467 pub_prv_read 1 rw "Public Privilege Read Allowed"; 468 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 469 pub_usr_write 1 rw "Public User Write Access Allowed"; 470 pub_usr_read 1 rw "Public User Read Access Allowed"; 471 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 472 _ 1 rsvd; 473 _ 1 rsvd; 474 _ 1 rsvd; 475 _ 1 rsvd; 476 _ 1 rsvd; 477 _ 1 rsvd; 478 }; 479 480 register mrm_permission_region_low_j_9 addr(base, 0x118) "Region j Permission Low" { 481 _ 1 rsvd; 482 _ 1 rsvd; 483 _ 1 rsvd; 484 _ 1 rsvd; 485 _ 1 rsvd; 486 _ 1 rsvd; 487 _ 1 rsvd; 488 _ 1 rsvd; 489 _ 1 rsvd; 490 _ 1 rsvd; 491 _ 1 rsvd; 492 _ 1 rsvd; 493 _ 1 rsvd; 494 _ 1 rsvd; 495 _ 1 rsvd; 496 _ 1 rsvd; 497 pub_prv_debug 1 rw "Public Privilege Debug Allowed"; 498 pub_usr_debug 1 rw "Public User Debug Allowed"; 499 _ 1 rsvd; 500 _ 1 rsvd; 501 pub_prv_write 1 rw "Public Privilege Write Allowed"; 502 pub_prv_read 1 rw "Public Privilege Read Allowed"; 503 pub_prv_exe 1 rw "Public Privilege Exe Allowed"; 504 pub_usr_write 1 rw "Public User Write Access Allowed"; 505 pub_usr_read 1 rw "Public User Read Access Allowed"; 506 pub_usr_exe 1 rw "Public User Exe Access Allowed"; 507 _ 1 rsvd; 508 _ 1 rsvd; 509 _ 1 rsvd; 510 _ 1 rsvd; 511 _ 1 rsvd; 512 _ 1 rsvd; 513 }; 514 515 register mrm_permission_region_high_j_0 addr(base, 0x8C) "Region j Permission High" { 516 _ 6 rsvd; 517 w12 1 rw "Master NIU ConnID = 12 write permission"; 518 r12 1 rw "Master NIU ConnID = 12 read permission"; 519 _ 1 rsvd; 520 _ 1 rsvd; 521 w10 1 rw "Master NIU ConnID = 10 write permission"; 522 r10 1 rw "Master NIU ConnID = 10 read permission"; 523 w9 1 rw "Master NIU ConnID = 9 write permission"; 524 r9 1 rw "Master NIU ConnID = 9 read permission"; 525 w8 1 rw "Master NIU ConnID = 8 write permission"; 526 r8 1 rw "Master NIU ConnID = 8 read permission"; 527 w7 1 rw "Master NIU ConnID = 7 write permission"; 528 r7 1 rw "Master NIU ConnID = 7 read permission"; 529 w6 1 rw "Master NIU ConnID = 6 write permission"; 530 r6 1 rw "Master NIU ConnID = 6 read permission"; 531 w5 1 rw "Master NIU ConnID = 5 write permission"; 532 r5 1 rw "Master NIU ConnID = 5 read permission"; 533 w4 1 rw "Master NIU ConnID = 4 write permission"; 534 r4 1 rw "Master NIU ConnID = 4 read permission"; 535 w3 1 rw "Master NIU ConnID = 3 write permission"; 536 r3 1 rw "Master NIU ConnID = 3 read permission"; 537 w2 1 rw "Master NIU ConnID = 2 write permission"; 538 r2 1 rw "Master NIU ConnID = 2 read permission"; 539 w1 1 rw "Master NIU ConnID = 1 write permission"; 540 r1 1 rw "Master NIU ConnID = 1 read permission"; 541 w0 1 rw "Master NIU ConnID = 0 write permission"; 542 r0 1 rw "Master NIU ConnID = 0 read permission"; 543 }; 544 545 register mrm_permission_region_high_j_1 addr(base, 0x9C) "Region j Permission High" { 546 _ 6 rsvd; 547 w12 1 rw "Master NIU ConnID = 12 write permission"; 548 r12 1 rw "Master NIU ConnID = 12 read permission"; 549 _ 1 rsvd; 550 _ 1 rsvd; 551 w10 1 rw "Master NIU ConnID = 10 write permission"; 552 r10 1 rw "Master NIU ConnID = 10 read permission"; 553 w9 1 rw "Master NIU ConnID = 9 write permission"; 554 r9 1 rw "Master NIU ConnID = 9 read permission"; 555 w8 1 rw "Master NIU ConnID = 8 write permission"; 556 r8 1 rw "Master NIU ConnID = 8 read permission"; 557 w7 1 rw "Master NIU ConnID = 7 write permission"; 558 r7 1 rw "Master NIU ConnID = 7 read permission"; 559 w6 1 rw "Master NIU ConnID = 6 write permission"; 560 r6 1 rw "Master NIU ConnID = 6 read permission"; 561 w5 1 rw "Master NIU ConnID = 5 write permission"; 562 r5 1 rw "Master NIU ConnID = 5 read permission"; 563 w4 1 rw "Master NIU ConnID = 4 write permission"; 564 r4 1 rw "Master NIU ConnID = 4 read permission"; 565 w3 1 rw "Master NIU ConnID = 3 write permission"; 566 r3 1 rw "Master NIU ConnID = 3 read permission"; 567 w2 1 rw "Master NIU ConnID = 2 write permission"; 568 r2 1 rw "Master NIU ConnID = 2 read permission"; 569 w1 1 rw "Master NIU ConnID = 1 write permission"; 570 r1 1 rw "Master NIU ConnID = 1 read permission"; 571 w0 1 rw "Master NIU ConnID = 0 write permission"; 572 r0 1 rw "Master NIU ConnID = 0 read permission"; 573 }; 574 575 register mrm_permission_region_high_j_2 addr(base, 0xAC) "Region j Permission High" { 576 _ 6 rsvd; 577 w12 1 rw "Master NIU ConnID = 12 write permission"; 578 r12 1 rw "Master NIU ConnID = 12 read permission"; 579 _ 1 rsvd; 580 _ 1 rsvd; 581 w10 1 rw "Master NIU ConnID = 10 write permission"; 582 r10 1 rw "Master NIU ConnID = 10 read permission"; 583 w9 1 rw "Master NIU ConnID = 9 write permission"; 584 r9 1 rw "Master NIU ConnID = 9 read permission"; 585 w8 1 rw "Master NIU ConnID = 8 write permission"; 586 r8 1 rw "Master NIU ConnID = 8 read permission"; 587 w7 1 rw "Master NIU ConnID = 7 write permission"; 588 r7 1 rw "Master NIU ConnID = 7 read permission"; 589 w6 1 rw "Master NIU ConnID = 6 write permission"; 590 r6 1 rw "Master NIU ConnID = 6 read permission"; 591 w5 1 rw "Master NIU ConnID = 5 write permission"; 592 r5 1 rw "Master NIU ConnID = 5 read permission"; 593 w4 1 rw "Master NIU ConnID = 4 write permission"; 594 r4 1 rw "Master NIU ConnID = 4 read permission"; 595 w3 1 rw "Master NIU ConnID = 3 write permission"; 596 r3 1 rw "Master NIU ConnID = 3 read permission"; 597 w2 1 rw "Master NIU ConnID = 2 write permission"; 598 r2 1 rw "Master NIU ConnID = 2 read permission"; 599 w1 1 rw "Master NIU ConnID = 1 write permission"; 600 r1 1 rw "Master NIU ConnID = 1 read permission"; 601 w0 1 rw "Master NIU ConnID = 0 write permission"; 602 r0 1 rw "Master NIU ConnID = 0 read permission"; 603 }; 604 605 register mrm_permission_region_high_j_3 addr(base, 0xBC) "Region j Permission High" { 606 _ 6 rsvd; 607 w12 1 rw "Master NIU ConnID = 12 write permission"; 608 r12 1 rw "Master NIU ConnID = 12 read permission"; 609 _ 1 rsvd; 610 _ 1 rsvd; 611 w10 1 rw "Master NIU ConnID = 10 write permission"; 612 r10 1 rw "Master NIU ConnID = 10 read permission"; 613 w9 1 rw "Master NIU ConnID = 9 write permission"; 614 r9 1 rw "Master NIU ConnID = 9 read permission"; 615 w8 1 rw "Master NIU ConnID = 8 write permission"; 616 r8 1 rw "Master NIU ConnID = 8 read permission"; 617 w7 1 rw "Master NIU ConnID = 7 write permission"; 618 r7 1 rw "Master NIU ConnID = 7 read permission"; 619 w6 1 rw "Master NIU ConnID = 6 write permission"; 620 r6 1 rw "Master NIU ConnID = 6 read permission"; 621 w5 1 rw "Master NIU ConnID = 5 write permission"; 622 r5 1 rw "Master NIU ConnID = 5 read permission"; 623 w4 1 rw "Master NIU ConnID = 4 write permission"; 624 r4 1 rw "Master NIU ConnID = 4 read permission"; 625 w3 1 rw "Master NIU ConnID = 3 write permission"; 626 r3 1 rw "Master NIU ConnID = 3 read permission"; 627 w2 1 rw "Master NIU ConnID = 2 write permission"; 628 r2 1 rw "Master NIU ConnID = 2 read permission"; 629 w1 1 rw "Master NIU ConnID = 1 write permission"; 630 r1 1 rw "Master NIU ConnID = 1 read permission"; 631 w0 1 rw "Master NIU ConnID = 0 write permission"; 632 r0 1 rw "Master NIU ConnID = 0 read permission"; 633 }; 634 635 register mrm_permission_region_high_j_4 addr(base, 0xCC) "Region j Permission High" { 636 _ 6 rsvd; 637 w12 1 rw "Master NIU ConnID = 12 write permission"; 638 r12 1 rw "Master NIU ConnID = 12 read permission"; 639 _ 1 rsvd; 640 _ 1 rsvd; 641 w10 1 rw "Master NIU ConnID = 10 write permission"; 642 r10 1 rw "Master NIU ConnID = 10 read permission"; 643 w9 1 rw "Master NIU ConnID = 9 write permission"; 644 r9 1 rw "Master NIU ConnID = 9 read permission"; 645 w8 1 rw "Master NIU ConnID = 8 write permission"; 646 r8 1 rw "Master NIU ConnID = 8 read permission"; 647 w7 1 rw "Master NIU ConnID = 7 write permission"; 648 r7 1 rw "Master NIU ConnID = 7 read permission"; 649 w6 1 rw "Master NIU ConnID = 6 write permission"; 650 r6 1 rw "Master NIU ConnID = 6 read permission"; 651 w5 1 rw "Master NIU ConnID = 5 write permission"; 652 r5 1 rw "Master NIU ConnID = 5 read permission"; 653 w4 1 rw "Master NIU ConnID = 4 write permission"; 654 r4 1 rw "Master NIU ConnID = 4 read permission"; 655 w3 1 rw "Master NIU ConnID = 3 write permission"; 656 r3 1 rw "Master NIU ConnID = 3 read permission"; 657 w2 1 rw "Master NIU ConnID = 2 write permission"; 658 r2 1 rw "Master NIU ConnID = 2 read permission"; 659 w1 1 rw "Master NIU ConnID = 1 write permission"; 660 r1 1 rw "Master NIU ConnID = 1 read permission"; 661 w0 1 rw "Master NIU ConnID = 0 write permission"; 662 r0 1 rw "Master NIU ConnID = 0 read permission"; 663 }; 664 665 register mrm_permission_region_high_j_5 addr(base, 0xDC) "Region j Permission High" { 666 _ 6 rsvd; 667 w12 1 rw "Master NIU ConnID = 12 write permission"; 668 r12 1 rw "Master NIU ConnID = 12 read permission"; 669 _ 1 rsvd; 670 _ 1 rsvd; 671 w10 1 rw "Master NIU ConnID = 10 write permission"; 672 r10 1 rw "Master NIU ConnID = 10 read permission"; 673 w9 1 rw "Master NIU ConnID = 9 write permission"; 674 r9 1 rw "Master NIU ConnID = 9 read permission"; 675 w8 1 rw "Master NIU ConnID = 8 write permission"; 676 r8 1 rw "Master NIU ConnID = 8 read permission"; 677 w7 1 rw "Master NIU ConnID = 7 write permission"; 678 r7 1 rw "Master NIU ConnID = 7 read permission"; 679 w6 1 rw "Master NIU ConnID = 6 write permission"; 680 r6 1 rw "Master NIU ConnID = 6 read permission"; 681 w5 1 rw "Master NIU ConnID = 5 write permission"; 682 r5 1 rw "Master NIU ConnID = 5 read permission"; 683 w4 1 rw "Master NIU ConnID = 4 write permission"; 684 r4 1 rw "Master NIU ConnID = 4 read permission"; 685 w3 1 rw "Master NIU ConnID = 3 write permission"; 686 r3 1 rw "Master NIU ConnID = 3 read permission"; 687 w2 1 rw "Master NIU ConnID = 2 write permission"; 688 r2 1 rw "Master NIU ConnID = 2 read permission"; 689 w1 1 rw "Master NIU ConnID = 1 write permission"; 690 r1 1 rw "Master NIU ConnID = 1 read permission"; 691 w0 1 rw "Master NIU ConnID = 0 write permission"; 692 r0 1 rw "Master NIU ConnID = 0 read permission"; 693 }; 694 695 register mrm_permission_region_high_j_6 addr(base, 0xEC) "Region j Permission High" { 696 _ 6 rsvd; 697 w12 1 rw "Master NIU ConnID = 12 write permission"; 698 r12 1 rw "Master NIU ConnID = 12 read permission"; 699 _ 1 rsvd; 700 _ 1 rsvd; 701 w10 1 rw "Master NIU ConnID = 10 write permission"; 702 r10 1 rw "Master NIU ConnID = 10 read permission"; 703 w9 1 rw "Master NIU ConnID = 9 write permission"; 704 r9 1 rw "Master NIU ConnID = 9 read permission"; 705 w8 1 rw "Master NIU ConnID = 8 write permission"; 706 r8 1 rw "Master NIU ConnID = 8 read permission"; 707 w7 1 rw "Master NIU ConnID = 7 write permission"; 708 r7 1 rw "Master NIU ConnID = 7 read permission"; 709 w6 1 rw "Master NIU ConnID = 6 write permission"; 710 r6 1 rw "Master NIU ConnID = 6 read permission"; 711 w5 1 rw "Master NIU ConnID = 5 write permission"; 712 r5 1 rw "Master NIU ConnID = 5 read permission"; 713 w4 1 rw "Master NIU ConnID = 4 write permission"; 714 r4 1 rw "Master NIU ConnID = 4 read permission"; 715 w3 1 rw "Master NIU ConnID = 3 write permission"; 716 r3 1 rw "Master NIU ConnID = 3 read permission"; 717 w2 1 rw "Master NIU ConnID = 2 write permission"; 718 r2 1 rw "Master NIU ConnID = 2 read permission"; 719 w1 1 rw "Master NIU ConnID = 1 write permission"; 720 r1 1 rw "Master NIU ConnID = 1 read permission"; 721 w0 1 rw "Master NIU ConnID = 0 write permission"; 722 r0 1 rw "Master NIU ConnID = 0 read permission"; 723 }; 724 725 register mrm_permission_region_high_j_7 addr(base, 0xFC) "Region j Permission High" { 726 _ 6 rsvd; 727 w12 1 rw "Master NIU ConnID = 12 write permission"; 728 r12 1 rw "Master NIU ConnID = 12 read permission"; 729 _ 1 rsvd; 730 _ 1 rsvd; 731 w10 1 rw "Master NIU ConnID = 10 write permission"; 732 r10 1 rw "Master NIU ConnID = 10 read permission"; 733 w9 1 rw "Master NIU ConnID = 9 write permission"; 734 r9 1 rw "Master NIU ConnID = 9 read permission"; 735 w8 1 rw "Master NIU ConnID = 8 write permission"; 736 r8 1 rw "Master NIU ConnID = 8 read permission"; 737 w7 1 rw "Master NIU ConnID = 7 write permission"; 738 r7 1 rw "Master NIU ConnID = 7 read permission"; 739 w6 1 rw "Master NIU ConnID = 6 write permission"; 740 r6 1 rw "Master NIU ConnID = 6 read permission"; 741 w5 1 rw "Master NIU ConnID = 5 write permission"; 742 r5 1 rw "Master NIU ConnID = 5 read permission"; 743 w4 1 rw "Master NIU ConnID = 4 write permission"; 744 r4 1 rw "Master NIU ConnID = 4 read permission"; 745 w3 1 rw "Master NIU ConnID = 3 write permission"; 746 r3 1 rw "Master NIU ConnID = 3 read permission"; 747 w2 1 rw "Master NIU ConnID = 2 write permission"; 748 r2 1 rw "Master NIU ConnID = 2 read permission"; 749 w1 1 rw "Master NIU ConnID = 1 write permission"; 750 r1 1 rw "Master NIU ConnID = 1 read permission"; 751 w0 1 rw "Master NIU ConnID = 0 write permission"; 752 r0 1 rw "Master NIU ConnID = 0 read permission"; 753 }; 754 755 register mrm_permission_region_high_j_8 addr(base, 0x10C) "Region j Permission High" { 756 _ 6 rsvd; 757 w12 1 rw "Master NIU ConnID = 12 write permission"; 758 r12 1 rw "Master NIU ConnID = 12 read permission"; 759 _ 1 rsvd; 760 _ 1 rsvd; 761 w10 1 rw "Master NIU ConnID = 10 write permission"; 762 r10 1 rw "Master NIU ConnID = 10 read permission"; 763 w9 1 rw "Master NIU ConnID = 9 write permission"; 764 r9 1 rw "Master NIU ConnID = 9 read permission"; 765 w8 1 rw "Master NIU ConnID = 8 write permission"; 766 r8 1 rw "Master NIU ConnID = 8 read permission"; 767 w7 1 rw "Master NIU ConnID = 7 write permission"; 768 r7 1 rw "Master NIU ConnID = 7 read permission"; 769 w6 1 rw "Master NIU ConnID = 6 write permission"; 770 r6 1 rw "Master NIU ConnID = 6 read permission"; 771 w5 1 rw "Master NIU ConnID = 5 write permission"; 772 r5 1 rw "Master NIU ConnID = 5 read permission"; 773 w4 1 rw "Master NIU ConnID = 4 write permission"; 774 r4 1 rw "Master NIU ConnID = 4 read permission"; 775 w3 1 rw "Master NIU ConnID = 3 write permission"; 776 r3 1 rw "Master NIU ConnID = 3 read permission"; 777 w2 1 rw "Master NIU ConnID = 2 write permission"; 778 r2 1 rw "Master NIU ConnID = 2 read permission"; 779 w1 1 rw "Master NIU ConnID = 1 write permission"; 780 r1 1 rw "Master NIU ConnID = 1 read permission"; 781 w0 1 rw "Master NIU ConnID = 0 write permission"; 782 r0 1 rw "Master NIU ConnID = 0 read permission"; 783 }; 784 785 register mrm_permission_region_high_j_9 addr(base, 0x11C) "Region j Permission High" { 786 _ 6 rsvd; 787 w12 1 rw "Master NIU ConnID = 12 write permission"; 788 r12 1 rw "Master NIU ConnID = 12 read permission"; 789 _ 1 rsvd; 790 _ 1 rsvd; 791 w10 1 rw "Master NIU ConnID = 10 write permission"; 792 r10 1 rw "Master NIU ConnID = 10 read permission"; 793 w9 1 rw "Master NIU ConnID = 9 write permission"; 794 r9 1 rw "Master NIU ConnID = 9 read permission"; 795 w8 1 rw "Master NIU ConnID = 8 write permission"; 796 r8 1 rw "Master NIU ConnID = 8 read permission"; 797 w7 1 rw "Master NIU ConnID = 7 write permission"; 798 r7 1 rw "Master NIU ConnID = 7 read permission"; 799 w6 1 rw "Master NIU ConnID = 6 write permission"; 800 r6 1 rw "Master NIU ConnID = 6 read permission"; 801 w5 1 rw "Master NIU ConnID = 5 write permission"; 802 r5 1 rw "Master NIU ConnID = 5 read permission"; 803 w4 1 rw "Master NIU ConnID = 4 write permission"; 804 r4 1 rw "Master NIU ConnID = 4 read permission"; 805 w3 1 rw "Master NIU ConnID = 3 write permission"; 806 r3 1 rw "Master NIU ConnID = 3 read permission"; 807 w2 1 rw "Master NIU ConnID = 2 write permission"; 808 r2 1 rw "Master NIU ConnID = 2 read permission"; 809 w1 1 rw "Master NIU ConnID = 1 write permission"; 810 r1 1 rw "Master NIU ConnID = 1 read permission"; 811 w0 1 rw "Master NIU ConnID = 0 write permission"; 812 r0 1 rw "Master NIU ConnID = 0 read permission"; 813 }; 814};