1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_ivahd_prm.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_ivahd_prm msbfirst ( addr base ) "" { 29 30 31 constants tcm2_mem_onstate_status width(2) "" { 32 TCM2_MEM_ONSTATE_3_r = 3 "Memory bank is on when the domain is ON."; 33 }; 34 35 constants tcm2_mem_retstate_status width(1) "" { 36 TCM2_MEM_RETSTATE_0 = 0 "Memory bank is off when the domain is in the RETENTION state."; 37 TCM2_MEM_RETSTATE_1 = 1 "Memory bank is retained when domain is in RETENTION state."; 38 }; 39 40 constants lowpowerstatechange_status width(1) "" { 41 LOWPOWERSTATECHANGE_0 = 0 "Do not request a low power state change."; 42 LOWPOWERSTATECHANGE_1 = 1 "Request a low power state change. This bit is automatically cleared when the power state is effectively changed or when power state is ON."; 43 }; 44 45 constants powerstate_status width(2) "" { 46 POWERSTATE_0 = 0 "OFF state"; 47 POWERSTATE_1 = 1 "RETENTION state"; 48 POWERSTATE_2 = 2 "INACTIVE state"; 49 POWERSTATE_3 = 3 "ON State"; 50 }; 51 52 register pm_ivahd_pwrstctrl addr(base, 0x0) "This register controls the IVAHD power state to reach upon a domain sleep transition" { 53 _ 8 mbz; 54 tcm2_mem_onstate 2 ro type(tcm2_mem_onstate_status) "TCM2 memory state when domain is ON."; 55 tcm1_mem_onstate 2 ro type(tcm2_mem_onstate_status) "TCM1 memory state when domain is ON."; 56 sl2_mem_onstate 2 ro type(tcm2_mem_onstate_status) "SL2 memory state when domain is ON."; 57 hwa_mem_onstate 2 ro type(tcm2_mem_onstate_status) "HWA memory state when domain is ON."; 58 _ 4 mbz; 59 tcm2_mem_retstate 1 rw type(tcm2_mem_retstate_status) "TCM2 memory state when domain is RETENTION."; 60 tcm1_mem_retstate 1 rw type(tcm2_mem_retstate_status) "TCM1 memory state when domain is RETENTION."; 61 sl2_mem_retstate 1 rw type(tcm2_mem_retstate_status) "SL2 memory state when domain is RETENTION."; 62 hwa_mem_retstate 1 ro type(tcm2_mem_retstate_status) "HWA memory state when domain is RETENTION."; 63 _ 3 mbz; 64 lowpowerstatechange 1 rw type(lowpowerstatechange_status) "Power state change request when domain has already performed a sleep transition. Allows going into deeper low power state without waking up the power domain."; 65 _ 1 mbz; 66 logicretstate 1 ro type(tcm2_mem_retstate_status) "Logic state when power domain is RETENTION"; 67 powerstate 2 rw type(powerstate_status) "Power state control"; 68 }; 69 70 constants lastpowerstateentered_status width(2) "" { 71 LASTPOWERSTATEENTERED_3_r = 3 "Power domain was previously ON-ACTIVE"; 72 LASTPOWERSTATEENTERED_2_r = 2 "Power domain was previously ON-INACTIVE"; 73 LASTPOWERSTATEENTERED_1_r = 1 "Power domain was previously in RETENTION"; 74 LASTPOWERSTATEENTERED_0_r = 0 "Power domain was previously OFF"; 75 }; 76 77 constants intransition_status width(1) "" { 78 INTRANSITION_0_r = 0 "No ongoing transition on power domain"; 79 INTRANSITION_1_r = 1 "Power domain transition is in progress."; 80 }; 81 82 constants tcm2_mem_statest_status width(2) "" { 83 TCM2_MEM_STATEST_0_r = 0 "Memory is OFF"; 84 TCM2_MEM_STATEST_1_r = 1 "Memory is RETENTION"; 85 TCM2_MEM_STATEST_2_r = 2 "Reserved"; 86 TCM2_MEM_STATEST_3_r = 3 "Memory is ON"; 87 }; 88 89 constants logicstatest_status width(1) "" { 90 LOGICSTATEST_0_r = 0 "Logic in domain is OFF"; 91 LOGICSTATEST_1_r = 1 "Logic in domain is ON"; 92 }; 93 94 constants powerstatest_status width(2) "" { 95 POWERSTATEST_0_r = 0 "Power domain is OFF"; 96 POWERSTATEST_1_r = 1 "Power domain is in RETENTION"; 97 POWERSTATEST_2_r = 2 "Power domain is ON-INACTIVE"; 98 POWERSTATEST_3_r = 3 "Power domain is ON-ACTIVE"; 99 }; 100 101 register pm_ivahd_pwrstst addr(base, 0x4) "This register provides a status on the current IVAHD power domain state. [warm reset insensitive]" { 102 _ 6 mbz; 103 lastpowerstateentered 2 rw type(lastpowerstateentered_status) "Last low power state entered. Set to 0x3 upon write of the same only. This register is intended for debug purpose only."; 104 _ 3 mbz; 105 intransition 1 ro type(intransition_status) "Domain transition status"; 106 _ 8 mbz; 107 tcm2_mem_statest 2 ro type(tcm2_mem_statest_status) "TCM2 memory state status"; 108 tcm1_mem_statest 2 ro type(tcm2_mem_statest_status) "TCM1 memory state status"; 109 sl2_mem_statest 2 ro type(tcm2_mem_statest_status) "SL2 memory state status"; 110 hwa_mem_statest 2 ro type(tcm2_mem_statest_status) "HWA memory state status"; 111 _ 1 mbz; 112 logicstatest 1 ro type(logicstatest_status) "Logic state status"; 113 powerstatest 2 ro type(powerstatest_status) "Current power state status"; 114 }; 115 116 constants rst3_status width(1) "" { 117 RST3_0 = 0 "Reset is cleared for the IVAHD logic and SL2"; 118 RST3_1 = 1 "Reset is asserted for IVAHD logic and SL2"; 119 }; 120 121 constants rst2_status width(1) "" { 122 RST2_0 = 0 "Reset is cleared for IVAHD Sequencer CPU2"; 123 RST2_1 = 1 "Reset is asserted for IVAHD Sequencer CPU2"; 124 }; 125 126 constants rst1_status width(1) "" { 127 RST1_0 = 0 "Reset is cleared for the IVAHD Sequencer CPU1"; 128 RST1_1 = 1 "Reset is asserted for the IVAHD sequencer CPU1"; 129 }; 130 131 register rm_ivahd_rstctrl addr(base, 0x10) "This register controls the release of the IVAHD sub-system resets." { 132 _ 29 mbz; 133 rst3 1 rw type(rst3_status) "IVAHD logic and SL2 reset control"; 134 rst2 1 rw type(rst2_status) "IVAHD Sequencer2 reset control"; 135 rst1 1 rw type(rst1_status) "IVAHD sequencer1 reset control"; 136 }; 137 138 constants icecrusher_seq2_rst2st_status width(1) "" { 139 ICECRUSHER_SEQ2_RST2ST_0 = 0 "No icecrusher reset"; 140 ICECRUSHER_SEQ2_RST2ST_1 = 1 "Sequencer2 has been reset upon icecrusher reset"; 141 }; 142 143 constants emulation_seq2_rst2st_status width(1) "" { 144 EMULATION_SEQ2_RST2ST_0 = 0 "No emulation reset"; 145 EMULATION_SEQ2_RST2ST_1 = 1 "Sequencer2 has been reset upon emulation reset"; 146 }; 147 148 constants rst3st_status width(1) "" { 149 RST3ST_0 = 0 "No software reset occured"; 150 RST3ST_1 = 1 "IVAHD logic and SL2 has been reset upon software reset"; 151 }; 152 153 constants rst2st_status width(1) "" { 154 RST2ST_0 = 0 "No software reset occured"; 155 RST2ST_1 = 1 "Sequencer2 has been reset upon software reset"; 156 }; 157 158 register rm_ivahd_rstst addr(base, 0x14) "This register logs the different reset sources of the IVAHD domain. Each bit is set upon release of the domain reset signal. Must be cleared by software. [warm reset insensitive]" { 159 _ 25 mbz; 160 icecrusher_seq2_rst2st 1 rw1c type(icecrusher_seq2_rst2st_status) "Sequencer2 CPU has been reset due to IVAHD ICECRUSHER2 reset event"; 161 icecrusher_seq1_rst1st 1 rw1c type(icecrusher_seq2_rst2st_status) "Sequencer1 CPU has been reset due to IVAHD ICECRUSHER1 reset event"; 162 emulation_seq2_rst2st 1 rw1c type(emulation_seq2_rst2st_status) ""; 163 emulation_seq1_rst1st 1 rw1c type(emulation_seq2_rst2st_status) "Sequencer1 CPU has been reset due to emulation reset source e.g. assert reset command initiated by the icepick module"; 164 rst3st 1 rw1c type(rst3st_status) "IVAHD logic and SL2 software reset"; 165 rst2st 1 rw1c type(rst2st_status) "IVAHD Sequencer2 CPU software reset"; 166 rst1st 1 rw1c type(rst2st_status) "IVAHD Sequencer1 CPU software reset"; 167 }; 168 169 constants lostmem_hwa_mem_status width(1) "" { 170 LOSTMEM_HWA_MEM_0 = 0 "Context has been maintained"; 171 LOSTMEM_HWA_MEM_1 = 1 "Context has been lost"; 172 }; 173 174 register rm_ivahd_ivahd_context addr(base, 0x24) "This register contains dedicated IVAHD context statuses. [warm reset insensitive]" { 175 _ 21 mbz; 176 lostmem_hwa_mem 1 rw1c type(lostmem_hwa_mem_status) "Specify if memory-based context in HWA_MEM memory bank has been lost due to a previous power transition or other reset source."; 177 lostmem_tcm2_mem 1 rw1c type(lostmem_hwa_mem_status) "Specify if memory-based context in TCM2_MEM memory bank has been lost due to a previous power transition or other reset source."; 178 lostmem_tcm1_mem 1 rw1c type(lostmem_hwa_mem_status) "Specify if memory-based context in TCM1_MEM memory bank has been lost due to a previous power transition or other reset source."; 179 _ 7 mbz; 180 lostcontext_dff 1 rw1c type(lostmem_hwa_mem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of IVAHD_RST signal)"; 181 }; 182 183 register rm_ivahd_sl2_context addr(base, 0x2C) "This register contains dedicated SL2 context statuses. [warm reset insensitive]" { 184 _ 23 mbz; 185 lostmem_sl2_mem 1 rw1c type(lostmem_hwa_mem_status) "Specify if memory-based context in SL2_MEM memory bank has been lost due to a previous power transition or other reset source."; 186 _ 7 mbz; 187 lostcontext_dff 1 rw1c type(lostmem_hwa_mem_status) "Specify if DFF-based context has been lost due to a previous power transition or other reset source. (set upon assertion of IVAHD_RST signal)"; 188 }; 189};