1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_iss_resizer.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_iss_resizer msbfirst ( addr base ) "" { 29 30 31 register rsz_revision ro addr(base, 0x0) "IP Revision Identifier (X.Y.R) Used by software to track features, bugs, and compatibility" type(uint32); 32 33 constants rszb_clk_en_status width(1) "" { 34 RSZB_CLK_EN_0 = 0 "off"; 35 RSZB_CLK_EN_1 = 1 "on"; 36 }; 37 38 constants autogating_status width(1) "" { 39 AUTOGATING_0 = 0 "Clocks are free running"; 40 AUTOGATING_1 = 1 "Automatic clock gating strategy."; 41 }; 42 43 register rsz_sysconfig addr(base, 0x4) "SYSTEM CONFIGURATION REGISTER This register is not shadowed. There is no standalone software reset for the resizer module." { 44 _ 22 mbz; 45 rszb_clk_en 1 rw type(rszb_clk_en_status) "Resizer B clock enable This bit enable to enable / disable the RESIZER B clock. Note that it is a second level clock enable. This bit has effect only if RSZ_GCK_SDR is set to 1."; 46 rsza_clk_en 1 rw type(rszb_clk_en_status) "Resizer A clock enable This bit enable to enable / disable the RESIZER A clock. Note that it is a second level clock enable. This bit has effect only if RSZ_GCK_SDR is set to 1."; 47 _ 7 mbz; 48 autogating 1 rw type(autogating_status) "Internal Clock Gating Strategy Enables or disables auto clock gating."; 49 }; 50 51 register rsz_in_fifo_ctrl addr(base, 0xC) "INPUT DATA BUFFER CONTROL REGISTER This register is not shadowed" { 52 _ 3 mbz; 53 thrld_low 13 rw "WhenRSZ_IN_FIFO_CTRL.THRLD_HIGH = RSZ_IN_FIFO_CTRL.THRLD_LOW, the rsz_stall_input is not asserted. The only purpose of the RSZ_IN_FIFO_CTRL.THRLD_LOW register is to prevent rsz_stall_input signal assertion."; 54 _ 3 mbz; 55 thrld_high 13 rw "High threshold value. The rsz_stall_input signal is asserted if 2 lines of circular buffer are full and the third line has more pixels than RSZ_IN_FIFO_CTRL.THRLD_HIGH. The rsz_stall_input signal stays high as long as one full line is not free for receiving further data. THRLD_HIGH is in terms of line size and can at max be programmed equal to the input line size (RSZ_SRC_HSZ)."; 56 }; 57 58 register rsz_gnc addr(base, 0x10) "GENERIC PARAMETER REGISTER" { 59 _ 3 mbz; 60 rszb_mem_line_size 13 ro "Resizer #B memory line size (pixels). The output image cannot exceed this size."; 61 _ 3 mbz; 62 rsza_mem_line_size 13 ro "Resizer #A memory line size (pixels). The output image cannot exceed this size."; 63 }; 64 65 register rsz_fracdiv addr(base, 0x14) "Fractional clock divider settings" { 66 _ 16 mbz; 67 rsz_fracdiv 16 rw "Fractional clock divider value. The fractional clock divider gates the read requests made to the input data buffer such that the input data buffer is read at an average frequency equal to FFCLK instead of FCLK. The value of FFCLK depends upon the upscaling ratios as well as the input pixel clock: see the functional spec. We have FFCLK = FCLK / FRACDIV MHz and RSZ_FRACDIV = 65536 / FRACDIV. When RSZ_ FRACDIV = 65536, we have: FFCLK = FCLK."; 68 }; 69 70 constants en_status width(1) "" { 71 EN_0 = 0 "Disable"; 72 EN_1 = 1 "Enable"; 73 }; 74 75 register rsz_src_en addr(base, 0x20) "RESIZER ENABLE REGISTER This register is not shadowed" { 76 _ 31 mbz; 77 en 1 rw type(en_status) "Resizer module enable The start flag of the RESIZER module. When EN is set to 1, the RESIZER module starts the processing from the next rising edge of the VD pulse. If the processing mode of the RESIZER module is set to 'one shot', the EN bit is cleared to 0 after the end of the processing. One has to pay attention that when this bit is enabled and"; 78 }; 79 80 constants ost_status width(1) "" { 81 OST_0 = 0 "Free running"; 82 OST_1 = 1 "One shot"; 83 }; 84 85 register rsz_src_mode addr(base, 0x24) "This register is not shadowed" { 86 _ 30 mbz; 87 wrt 1 rw type(en_status) "Video port WEN signal selection This bit selects whether the WEN signal which is present on the IPIPE and IPIPEIF video port is used or not to select the input data. If WRT is 0, the RESIZER module ignores the WEN signal and processes all image frame while RESIZER is enabled. If WRT is 1, the RESIZER module only processes the lines that arrived while the WEN is high. HD is used to sample the WEN signal."; 88 ost 1 rw type(ost_status) "The processing mode selection of the RESIZER module. Value 0 indicates the mode of free run, value 1 indicates the mode of one shot."; 89 }; 90 91 constants bypass_status width(1) "" { 92 BYPASS_0 = 0 "Pass through off = normal output mode, the input data buffer is used."; 93 BYPASS_1 = 1 "Pass through on = normal output mode, the input data buffer is bypassed."; 94 }; 95 96 constants sel_status width(1) "" { 97 SEL_0 = 0 "IPIPE"; 98 SEL_1 = 1 "IPIPEIF"; 99 }; 100 101 register rsz_src_fmt0 addr(base, 0x28) "This register is not shadowed" { 102 _ 30 mbz; 103 bypass 1 rw type(bypass_status) "Pass Through This bit enables or disables the RESIZER module pass through mode. The pass through mode can transfer images which are 8K pixel wide. When it is enabled, the input data buffer and the resizer engines are bypassed."; 104 sel 1 rw type(sel_status) "Input selection This bit selects which of the two video port is selected to push data through the RESIZER module."; 105 }; 106 107 constants col_status width(1) "" { 108 COL_0 = 0 "Y data is input"; 109 COL_1 = 1 "Chroma data is input"; 110 }; 111 112 constants in420_status width(1) "" { 113 IN420_0 = 0 "YUV4:2:2 is input"; 114 IN420_1 = 1 "YUV4:2:0 is input"; 115 }; 116 117 constants raw_status width(1) "" { 118 RAW_0 = 0 "Flipping preserves YCbCr format"; 119 RAW_1 = 1 "Flipping preserves RAW format"; 120 }; 121 122 register rsz_src_fmt1 addr(base, 0x2C) "" { 123 _ 29 mbz; 124 col 1 rw type(col_status) "Y/C selection This bit is valid only if the input data is YUV4:2:0 (IN420 = 1). It enables to specify where the data which is input to the RESIZER module is luma or chroma data."; 125 in420 1 rw type(in420_status) "Chroma Format Selection This bit sets the chroma undersampling when YUV data is input to the RESIZER module."; 126 raw 1 rw type(raw_status) "Pass-through mode input data format selection This bit affects the horizontal reversal (flipping) process."; 127 }; 128 129 register rsz_src_vps addr(base, 0x30) "VERTICAL POSITION REGISTER This register is not shadowed" { 130 _ 16 mbz; 131 vps 16 rw "Vertical Start Position Sets the vertical position of the global frame from the rising edge of the VD. The RSZ module will start the image processing from the VPS'th line. This value can be odd or even whatever the input data format."; 132 }; 133 134 register rsz_src_vsz addr(base, 0x34) "VERTICAL SIZER REGISTER" { 135 _ 19 mbz; 136 vsz 13 rw "Vertical Processing Size Sets the vertical size of the processing area. The RSZ module will process (VSZ+1) lines. This value can be odd or even whatever the input data format."; 137 }; 138 139 register rsz_src_hps addr(base, 0x38) "HORIZONTAL POSITION REGISTER This register is not shadowed" { 140 _ 16 mbz; 141 hps 16 rw "Horizontal Start Position The RSZ_SRC_HPS register has two functions: The first function is to compensate for possible delay between the HD pulse and the first valid data. It is possible for this delay to be different than 0 when the RESIZER module gets its input data from the VP connected to the IPIPEIF module (the offset value can be odd or even). When data are coming from the IPIPE module, it is not required to resynchronize HD and the first valid data. The second function is to crop the data in the horizontal direction. When used for cropping, only RSZ_SRC_HPS must be even or null."; 142 }; 143 144 register rsz_src_hsz addr(base, 0x3C) "HORIZONTAL SIZE REGISTER The HSZ value is given by HSZ concatenated with HSZ_LSB" { 145 _ 19 mbz; 146 hsz 13 rw "Horizontal size Sets the horizontal size of the processing area. The RSZ module processes (HSZ+1) pixels. (HSZ+1) must be even for YUV4:2:2 and RAW data. The valid available values for HSZ are 1~xxxx."; 147 }; 148 149 register rsz_dma_rza addr(base, 0x40) "RESIZER A - MEMORY REQUEST MINIMUM INTERVAL REGISTER" { 150 _ 16 mbz; 151 rza 16 rw "Sets the minimum interval btw two consecutive memory request for resizer #A. Specified in number of interface clock cycles. Values of 0, 1, and 2 are used as a condition to keep the bandwidth limiter off. When this function is enabled, this value must be greater than 10 cycles."; 152 }; 153 154 register rsz_dma_rzb addr(base, 0x44) "RESIZER B - MEMORY REQUEST MINIMUM INTERVAL REGISTER" { 155 _ 16 mbz; 156 rzb 16 rw "Sets the minimum interval btw two consecutive memory request for resizer #B. Specified in number of interface clock cycles. Values of 0, 1, and 2 are used as a condition to keep the bandwidth limiter off. When this function is enabled, this value must be greater than 10 cycles."; 157 }; 158 159 constants status_status width(1) "" { 160 STATUS_1_r = 1 "Active"; 161 STATUS_0_r = 0 "Not active"; 162 }; 163 164 register rsz_dma_sta addr(base, 0x48) "RESIZER STATUS REGISTER" { 165 _ 31 mbz; 166 status 1 ro type(status_status) "Resizer process status This bit is set in the time window from rsz_int_reg to rsz_int_dma."; 167 }; 168 169 constants mmr_status width(1) "" { 170 MMR_0 = 0 "Off"; 171 MMR_1 = 1 "On"; 172 }; 173 174 register rsz_gck_mmr addr(base, 0x4C) "MMR CLOCK CONTROL REGISTER This register is not shadowed" { 175 _ 31 mbz; 176 mmr 1 rw type(mmr_status) "The on/off selection of the MMR interface clock which is used for MMR register access."; 177 }; 178 179 constants core_status width(1) "" { 180 CORE_0 = 0 "Resizer core clock disabled. Resizer in bypass mode if .BYPASS = 0 Resizer in pass-through if .BYPASS = 1"; 181 CORE_1 = 1 "Resizer core clock enabled. Resizer in rescaling mode if .BYPASS = 0 Resizer in pass-through if .BYPASS = 1"; 182 }; 183 184 register rsz_gck_sdr addr(base, 0x54) "CORE CLOCK CONTROL REGISTER This register is not shadowed" { 185 _ 31 mbz; 186 core 1 rw type(core_status) "RSZ Core Clock Enable. This bit enables or disables the resizer core functional clock. When this bit is off, the resizer core (interpolator) is automatically bypassed (resizer-bypass mode of pass-through mode is selected depending on RSZ_SRC_FMT0 value). In resizer-bypass mode or pass-through mode, no up-scaling or downscaling process is operated."; 187 }; 188 189 register rsz_irq_rza addr(base, 0x58) "RESIZER A - CIRCULAR BUFFER INTERRUPT INTERVAL REGISTER" { 190 _ 19 mbz; 191 rza 13 rw "Resizer A circular buffer interval Sets the circular buffer interval for Resizer A. The interrupt is triggered every time (RZA+1) lines are written to the circular buffer (Y buffer). The range goes from 1 to 8192 lines. Usually, the circular buffer vertical size should be a multiple of RZA."; 192 }; 193 194 register rsz_irq_rzb addr(base, 0x5C) "RESIZER B - CIRCULAR BUFFER INTERRUPT INTERVAL REGISTER" { 195 _ 19 mbz; 196 rzb 13 rw "Resizer B circular buffer interval Sets the circular buffer interval for Resizer B. The interrupt is triggered every time (RZB+1) lines are written to the circular buffer (Y buffer). The range goes from 1 to 8192 lines. Usually, the circular buffer vertical size should be a multiple of RZB."; 197 }; 198 199 register rsz_yuv_y_min addr(base, 0x60) "LUMINANCE SATURATION REGISTER" { 200 _ 24 mbz; 201 min 8 rw "The minimum value of Luminance (8bits unsigned). If the value of the Luminance is smaller than VAL, it will be clipped to VAL. This bit field must be set to its default values when the resizer is set in pass-though mode."; 202 }; 203 204 register rsz_yuv_y_max addr(base, 0x64) "LUMINANCE SATURATION REGISTER" { 205 _ 24 mbz; 206 max 8 rw "The maximum value of Luminance (8bits unsigned). If the value of the Luminance is larger than VAL, it will be clipped to VAL. This bit field must be set to its default values when the resizer is set in pass-through mode."; 207 }; 208 209 register rsz_yuv_c_min addr(base, 0x68) "CHROMINANCE SATURATION REGISTER" { 210 _ 24 mbz; 211 min 8 rw "The minimum value of Chrominance (8bits unsigned). If the value of the Chrominance is smaller than VAL, it will be clipped to VAL. This bit field must be set to its default values when the resizer is set in pass-though mode."; 212 }; 213 214 register rsz_yuv_c_max addr(base, 0x6C) "CHROMINANCE SATURATION REGISTER" { 215 _ 24 mbz; 216 max 8 rw "The maximum value of Chrominance (8bits unsigned). If the value of the Chrominance is larger than VAL, it will be clipped to VAL. This bit field must be set to its default values when the resizer is set in pass-through mode."; 217 }; 218 219 constants pos_status width(1) "" { 220 POS_0 = 0 "Same position with Luminance: cosited"; 221 POS_1 = 1 "The middle of the luminance: centered"; 222 }; 223 224 register rsz_yuv_phs addr(base, 0x70) "The phase position of the output of the Chrominance" { 225 _ 31 mbz; 226 pos 1 rw type(pos_status) "The phase position of the output of the chrominance. The RESIZER module does not change the relative position of the chroma samples vs. the luma samples between the input and output and the chroma position at the output of the IPIPE module and at the output of the RESIZER module must be identical. In other words, we must have RSZ_YUV_PHS.POS = IPIPE_YUV_PHS.POS."; 227 }; 228 229 constants crv_status width(1) "" { 230 CRV_0 = 0 "Chroma sampling point is not changed"; 231 CRV_1 = 1 "Chroma sampling point is changed from odd-numbered pixels to even-number pixels. The pixel at the left end is removed and the pixel at the right end is duplicated."; 232 }; 233 234 register rsz_seq addr(base, 0x74) "" { 235 _ 27 mbz; 236 crv 1 rw type(crv_status) "Chroma sampling point change"; 237 vrvb 1 rw type(bypass_status) "Resizer B - Vertical reversal of output image"; 238 hrvb 1 rw type(bypass_status) "Resizer B -Horizontal reversal of output image"; 239 vrva 1 rw type(bypass_status) "Resizer A - Vertical reversal of output image"; 240 hrva 1 rw type(bypass_status) "Resizer A - Horizontal reversal of output image"; 241 }; 242 243 register rza_en addr(base, 0x78) "RESIZER A - ENABLE REGISTER" { 244 _ 31 mbz; 245 en 1 rw type(en_status) "Enable resizer #A This bit is latched on video port VD input. The reason is that the resizer must only starts the processing on a clean frame boundary. In one-shot mode, this bit is negated on VD."; 246 }; 247 248 constants mode_status width(1) "" { 249 MODE_0 = 0 "Free run"; 250 MODE_1 = 1 "One shot"; 251 }; 252 253 register rza_mode addr(base, 0x7C) "RESIZER #A MODE REGISTER" { 254 _ 31 mbz; 255 mode 1 rw type(mode_status) "Select 'Free Run mode' or 'One Shot Mode'"; 256 }; 257 258 constants cen_status width(1) "" { 259 CEN_0 = 0 "C output disable"; 260 CEN_1 = 1 "C output enable and 422to420 conversion enabled"; 261 }; 262 263 constants yen_status width(1) "" { 264 YEN_0 = 0 "Y output disable"; 265 YEN_1 = 1 "Y output enable and 422to420 conversion enabled"; 266 }; 267 268 register rza_420 addr(base, 0x80) "YEN/CEN: 0/0: in = YUV4:2:2 input, out = YUV4:2:2 output 0/1: in = YUV4:2:2 input, out = Chrominance of YUV4:2:0 output 1/0: in = YUV4:2:2 input, out = Luminance of YUV4:2:0 output 1/1: in = YUV4:2:2 input, out = YUV4:2:0 output" { 269 _ 30 mbz; 270 cen 1 rw type(cen_status) "Output Enable for Chrominance This bit is valid in 422 input mode. When CEN=0 and YEN=0, output is 422"; 271 yen 1 rw type(yen_status) "Output Enable for Luminance. This bit is valid in 422 input mode. When CEN=0 and YEN=0, output is 422"; 272 }; 273 274 register rza_i_vps addr(base, 0x84) "RESIZER A - INPUT VERTICAL START REGISTER The height of the image after the second-level crop must be 2 or larger." { 275 _ 19 mbz; 276 vps 13 rw "Input Vertical Position Sets the vertical start position of the input image within the global frame. It enables to crop data into the global frame. After SRC_VPS, the Vps'th line is processed as the first line in each image. After the second-level crop, the height of the image area must be two lines or larger, that is, a one-line image is not allowed. (RSZ_SRC_VSZ - RZA_I_VPS > 0)."; 277 }; 278 279 register rza_i_hps addr(base, 0x88) "RESIZER A - INPUT HORIZONTAL START REGISTER" { 280 _ 19 mbz; 281 hps 13 rw "Input Horizontal Position Sets the horizontal position of the first pixel for each line within the global frame. After SRC_HPS, the pixel at the VAL'th position is processed as the first pixel. This value must be even."; 282 }; 283 284 register rza_o_vsz addr(base, 0x8C) "RESIZER A - OUTPUT VERTICAL SIZER REGISTER" { 285 _ 19 mbz; 286 vsz 13 rw "The target output size of the resized image. The number of output lines is (VSZ+1). Set 479, when 480 lines of output is required."; 287 }; 288 289 register rza_o_hsz addr(base, 0x90) "RESIZER A - OUTPUT HORIZONTAL SIZE REGISTER" { 290 _ 19 mbz; 291 hsz 12 rw "The horizontal size of output image. The number of pixel in each line is (HSZ+1). Set 479, when 480 pixels are required. This value must be lower than the max memory line size supported by the resizer engine, except in RAW pass through mode. Note that the LSB of the 13-bit HSZ value is fixed to 1 such that the horizontal size is always even."; 292 hsz_lsb 1 ro "The least significant bit of HSZ is forced to 1."; 293 }; 294 295 register rza_v_phs_y addr(base, 0x94) "RESIZER A - INITIAL LUMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV4:2:2 data are output, the phase values for luma and chroma should typically be equal, that is, RZX_V_PHS_Y= RZX_V_PHS_C. The following constraints apply when setting the initial vertical phases ABS(RZX_V_PHS_Y - RZX_V_PHS_C) RZX_V_DIF. This constraint means that at most the distance between the initial phases for luminance and chrominance is not expected to exceed the distance between two luma pixels. Note that the absolute value is used, hence, the initial luma phase can be greater than the initial chroma phase or the other way around. As a reminder, the distance between two output pixels for luma is given by RZX_V_DIF." { 296 _ 18 mbz; 297 y 14 rw "The initial value for the luma phase in vertical resizing process. This value is in U14Q8 fractional format."; 298 }; 299 300 register rza_v_phs_c addr(base, 0x98) "RESIZER A - INITIAL CHROMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV4:2:2 data are output, the phase values for luma and chroma should typically be equal, that is, RZX_V_PHS_Y= RZX_V_PHS_C. The following constraints apply when setting the initial vertical phases ABS(RZX_V_PHS_Y - RZX_V_PHS_C) RZX_V_DIF. This constraint means that at most the distance between the initial phases for luminance and chrominance is not expected to exceed the distance between two luma pixels. Note that the absolute value is used, hence, the initial luma phase can be greater than the initial chroma phase or the other way around. As a reminder, the distance between two output pixels for luma is given by RZX_V_DIF." { 301 _ 18 mbz; 302 c 14 rw "The initial value for the chroma phase in vertical resizing process. This value is in U14Q8 fractional format."; 303 }; 304 305 register rza_v_dif addr(base, 0x9C) "RESIZER A - VERTICAL RESIZER REGISTER" { 306 _ 18 mbz; 307 v 14 rw "The parameter for vertical resize. The actual resizing ratio is 256/RZA_V_DIF. In normal mode: 16 <= RZA_V_DIF <= 4096. In down-scale mode: 256 <= RZA_V_DIF <= 4096."; 308 }; 309 310 constants c_status width(1) "" { 311 C_0 = 0 "4-tap cubic convolution (default)"; 312 C_1 = 1 "2-tap linear interpolation"; 313 }; 314 315 register rza_v_typ addr(base, 0xA0) "RESIZER A - INTERPOLATION METHOD FOR VERTICAL RESIZING" { 316 _ 30 mbz; 317 c 1 rw type(c_status) "Selection of resizing method for chrominance: vertical"; 318 y 1 rw type(c_status) "Selection of resizing method for luminance: vertical"; 319 }; 320 321 register rza_v_lpf addr(base, 0xA4) "RESIZER A - VERTICAL LPF INTENSITY REGISTER" { 322 _ 20 mbz; 323 c 6 rw "The intensity parameter for chroma vertical low pass filtering."; 324 y 6 rw "The intensity parameter for luma vertical low pass filtering."; 325 }; 326 327 register rza_h_phs addr(base, 0xA8) "RESIZER A - INITIAL PHASE OF HORIZONTAL RESIZING PROCESS" { 328 _ 18 mbz; 329 phs 14 rw "Initial value for the phase in horizontal resizing process, that is, the sampling position is shifted. This value is in U14Q8 fractional format. Example: If RZX_H_PHS = 128, the first output pixel is sampled at the center of the first two valid input pixels. If RZX_I_HPS=100 and RZX_H_PHS=128, the first output pixel is resampled at the center of the 100-th and the 101-st input pixels."; 330 }; 331 332 register rza_h_phs_adj addr(base, 0xAC) "RESIZER A - LUMINANCE HORIZONTAL PHASE ADJUSTMENT The register enables to adjust the horizontal phase for the luma component when averaging is enabled (the horizontal averaging disrupts the relative sampling point between luminance and chrominance when YUV4:2:2 cosited data is input), that is, the relative phase between luma and chroma is different before and after the horizontal averager." { 333 _ 23 mbz; 334 adj 9 rw "Horizontal phase adjustment value. This value is in U9Q8 fractional format. This value is expected to be equal to zero if the averager is disabled or if input chroma is centered."; 335 }; 336 337 register rza_h_dif addr(base, 0xB0) "RESIZER A - HORIZONTAL RESIZER REGISTER" { 338 _ 18 mbz; 339 h 14 rw "The parameter for horizontal resizing process. The actual resizing ratio is 256/VAL. In normal mode 16 <= RSZ_RZA_H_DIF<=4096 In down-scale mode 256<=RSZ_RZA_H_DIF<=4096"; 340 }; 341 342 register rza_h_typ addr(base, 0xB4) "Resize-A" { 343 _ 30 mbz; 344 c 1 rw type(c_status) "Selection of resizing method for chrominance: horizontal"; 345 y 1 rw type(c_status) "Selection of resizing method for luminance: horizontal"; 346 }; 347 348 register rza_h_lpf addr(base, 0xB8) "RESIZER A - HORIZONTAL LPF INTENSITY REGISTER" { 349 _ 20 mbz; 350 c 6 rw "Horizontal LPF Intensity for Chrominance"; 351 y 6 rw "Selection of resizing method for Luminance in horizontal direction"; 352 }; 353 354 constants dwn_en_status width(1) "" { 355 DWN_EN_0 = 0 "Off. Normal operation: upscale and downscale are allowed."; 356 DWN_EN_1 = 1 "On. Downscale mode."; 357 }; 358 359 register rza_dwn_en addr(base, 0xBC) "RESIZER #A - DOWNSCALE ENABLE REGISTER" { 360 _ 31 mbz; 361 dwn_en 1 rw type(dwn_en_status) "Resizer downscale enable"; 362 }; 363 364 register rza_dwn_av addr(base, 0xC0) "Resize-A" { 365 _ 26 mbz; 366 v 3 rw "Vertical averaging size : 1/2 The range goes from 1/2 to 1/256 in power of two. 0:_DIV2 1/2 down scale 1:_DIV4 1/4 down scale 2:_DIV8 1/8 down scale 3:_DIV16 1/16 down scale 4:_DIV32 1/32 down scale 5:_DIV64 1/64 down scale 6:_DIV128 1/128 down scale 7:_DIV256 1/256 down scale"; 367 h 3 rw "Horizontal averaging size : 1/2 The range goes from 1/2 to 1/256 in power of two. 0:_DIV2 1/2 down scale 1:_DIV4 1/4 down scale 2:_DIV8 1/8 down scale 3:_DIV16 1/16 down scale 4:_DIV32 1/32 down scale 5:_DIV64 1/64 down scale 6:_DIV128 1/128 down scale 7:_DIV256 1/256 down scale"; 368 }; 369 370 constants rgb_en_status width(1) "" { 371 RGB_EN_0 = 0 "Off (YCbCr output)"; 372 RGB_EN_1 = 1 "On (RGB output)"; 373 }; 374 375 register rza_rgb_en addr(base, 0xC4) "RESIZER #A - RGB OUTPUT ENABLE" { 376 _ 31 mbz; 377 rgb_en 1 rw type(rgb_en_status) "Enable of RGB output In pass through mode, this register must be 0. This bit can only be set to 1 when YUV4:2:2 data are output. YUV4:2:2 data output is selected when SRC_FMT1.IN420 = 0 and RZA_420.YEN = RZA_420.CEN = 0"; 378 }; 379 380 constants msk1_status width(1) "" { 381 MSK1_0 = 0 "output the last 2 pixels"; 382 MSK1_1 = 1 "mask the last 2 pixels (Resizer do not output them.)"; 383 }; 384 385 constants msk0_status width(1) "" { 386 MSK0_0 = 0 "output the first 2 pixels"; 387 MSK0_1 = 1 "mask the first 2 pixels (Resizer do not output them.)"; 388 }; 389 390 constants typ_status width(1) "" { 391 TYP_0 = 0 "32-bit output: alpha + R + G + B (8 bit each) This mode comes with performance degradation. The maximum input frequency in this mode is 160 MHz. This due to the fact that the output is 4 bytes / pixel."; 392 TYP_1 = 1 "16-bit output: R(5 bit) + G (6 bit) + B (5 bit)"; 393 }; 394 395 register rza_rgb_typ addr(base, 0xC8) "RESIZER A - RGB OUTPUT CONTROL REGISTER" { 396 _ 29 mbz; 397 msk1 1 rw type(msk1_status) "Enables masking of the last 2 pixels This bit is used to mask the 2 last pixels at the image boundary which are affected by the YUV4:2:2 to YUV4:4:4 conversion."; 398 msk0 1 rw type(msk0_status) "Enables masking of the first 2 pixels This bit is used to mask the 2 first pixels at the image boundary which are affected by the YUV4:2:2 to YUV4:4:4 conversion."; 399 typ 1 rw type(typ_status) "16bit/32bit output selection"; 400 }; 401 402 register rza_rgb_bld addr(base, 0xCC) "RESIZER A - RGB BLEND REGISTER" { 403 _ 24 mbz; 404 bld 8 rw "The alpha value used in 32-bit RGBA output mode"; 405 }; 406 407 register rza_sdr_y_bad_h addr(base, 0xD0) "RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER (HIGH) This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to this address YUV4:2:0: Y data is written to this address RGB5:6:5: 16-bit RGB data is written to this address RGBA: 32-bit RGBA data is written to this address" { 408 _ 16 mbz; 409 y_bad_h 16 rw "Memory Base Address Sets the 16 upper bits of the 32-bit base address of the circular buffer in memory."; 410 }; 411 412 register rza_sdr_y_bad_l addr(base, 0xD4) "RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER (LOW) This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to this address YUV4:2:0: Y data is written to this address RGB5:6:5: 16-bit RGB data is written to this address RGBA: 32-bit RGBA data is written to this address" { 413 _ 16 mbz; 414 y_bad_l 16 rw "Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory. It is a byte address. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on. RAW, RGB5:6:5 and YUV4:2:2 formats (output data on 16 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on. RGBA format (output data on 32 bits): The three least significant bits must be set to '000' when horizontal reversal mode is off. The three least significant bits must be set to '111' when horizontal reversal mode is on."; 415 }; 416 417 register rza_sdr_y_sad_h addr(base, 0xD8) "RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER (HIGH) This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to this address YUV4:2:0: Y data is written to this address RGB5:6:5: 16-bit RGB data is written to this address RGBA: 32-bit RGBA data is written to this address" { 418 _ 16 mbz; 419 y_sad_h 16 rw "Memory Start Address Sets the 16 upper bits of the 32-bit start address in memory."; 420 }; 421 422 register rza_sdr_y_sad_l addr(base, 0xDC) "RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER (LOW) This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to this address YUV4:2:0: Y data is written to this address RGB5:6:5: 16-bit RGB data is written to this address RGBA: 32-bit RGBA data is written to this address" { 423 _ 16 mbz; 424 y_sad_l 16 rw "Memory Start Address Sets 16 lower bits of the 32-bit start address in memory. It is a byte address. For every frame, the first line of data will be written to this address. We have: SAD = BAD + (PTR_S x OFT) and PTR_S < PTR_E If the first line must be written at the beginning of the circular buffer memory then SAD = BAD and PTR_S = 0. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on. RAW, RGB5:6:5 and YUV4:2:2 formats (output data on 16 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on. RGBA format (output data on 32 bits): The three least significant bits must be set to '000' when horizontal reversal mode is off. The three least significant bits must be set to '111' when horizontal reversal mode is on."; 425 }; 426 427 register rza_sdr_y_oft addr(base, 0xE0) "RESIZER A - OUTPUT MEMORY OFFSET REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0 or RGBA." { 428 _ 15 mbz; 429 y_oft 17 rw "Memory Line Offset Sets the size of each line in the circular buffer. It is expressed in bytes and unsigned. Note that OFT does not necessary corresponds to the size of a line in a frame, it can be much bigger. The line offset must be a multiple of 128 bytes (bits [6:0] of RZX_SDR_Y_OFT and RZX_SDR_C_OFT must be set to 0). Example: line 0 address = SAD line 1 address = SAD + 1 x OFT line 2 address = SAD + 2 x OFT"; 430 }; 431 432 register rza_sdr_y_ptr_s addr(base, 0xE4) "RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0 or RGBA." { 433 _ 19 mbz; 434 y_ptr_s 13 rw "Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space. This value is expressed in number of lines. The hardware uses it to set up the initial value of the circular buffer. It must be set up such as PTR_S = (SAD - BAD) / OFT. This value must be set to 0 when RSZ_RZA_SDR_Y_BAD = RSZ_RZA_SDR_Y_SAD."; 435 }; 436 437 register rza_sdr_y_ptr_e addr(base, 0xE8) "RESIZER A - OUTPUT MEMORY END ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0 or RGBA." { 438 _ 19 mbz; 439 y_ptr_e 13 rw "End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space. This value is expressed in number of lines. When the number of output lines exceeds this value, the address restarts from the first address in the output memory space (BAD)."; 440 }; 441 442 register rza_sdr_c_bad_h addr(base, 0xEC) "RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." { 443 _ 16 mbz; 444 c_bad_h 16 rw "Memory Base Address Sets the 16 higher bits of the 32-bit base address of the circular buffer in memory."; 445 }; 446 447 register rza_sdr_c_bad_l addr(base, 0xF0) "RESIZER A - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." { 448 _ 16 mbz; 449 c_bad_l 16 rw "Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory. It is a byte address. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on."; 450 }; 451 452 register rza_sdr_c_sad_h addr(base, 0xF4) "RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." { 453 _ 16 mbz; 454 c_sad_h 16 rw "Memory Base Address Sets the 16 higher bits of the 32-bit start address in memory."; 455 }; 456 457 register rza_sdr_c_sad_l addr(base, 0xF8) "RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." { 458 _ 16 mbz; 459 c_sad_l 16 rw "Memory Base Address Sets the 16 lower bits of the 32-bit start address in memory. It is a byte address. For every frame, the first line of data will be written to this address. We have: SAD = BAD + (PTR_S x OFT) and PTR_S < PTR_E If the first line must be written at the beginning of the circular buffer memory then SAD = BAD and PTR_S = 0. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on."; 460 }; 461 462 register rza_sdr_c_oft addr(base, 0xFC) "RESIZER A - OUTPUT MEMORY OFFSET REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" { 463 _ 15 mbz; 464 c_oft 17 rw "Memory Line Offset Sets the size of each line in the circular buffer. It is expressed in bytes and unsigned. Note that OFT does not necessary corresponds to the size of a line in a frame, it can be much bigger. The line offset must be a multiple of 128 bytes (bits [6:0] of RZX_SDR_Y_OFT and RZX_SDR_C_OFT must be set to 0). Example: line 0 address = SAD line 1 address = SAD + 1 x OFT line 2 address = SAD + 2 x OFT"; 465 }; 466 467 register rza_sdr_c_ptr_s addr(base, 0x100) "RESIZER A - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" { 468 _ 19 mbz; 469 c_ptr_s 13 rw "Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space. This value is expressed in number of lines. The hardware uses it to set up the initial value of the circular buffer. It must be set up such as PTR_S = (SAD - BAD) / OFT. This value must be set to 0 when RSZ_RZA_SDR_C_BAD = RSZ_RZA_SDR_C_SAD."; 470 }; 471 472 register rza_sdr_c_ptr_e addr(base, 0x104) "RESIZER A - OUTPUT MEMORY END ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" { 473 _ 19 mbz; 474 c_ptr_e 13 rw "End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space. This value is expressed in number of lines. When the number of output lines exceeds this value, the address restarts from the first address in the output memory space (BAD)."; 475 }; 476 477 register rzb_en addr(base, 0x108) "RESIZER B - ENABLE REGISTER" { 478 _ 31 mbz; 479 en 1 rw type(en_status) "Enable resizer #A This bit is latched on the video port VD input signal. The reason is that the resizer must only starts the processing on a clean frame boundary. In one-shot mode, this bit is negated on VD."; 480 }; 481 482 register rzb_mode addr(base, 0x10C) "RESIZER B MODE REGISTER" { 483 _ 31 mbz; 484 mode 1 rw type(mode_status) "Select 'Free Run mode' or 'One Shot Mode'"; 485 }; 486 487 register rzb_420 addr(base, 0x110) "YEN/CEN: 0/0: in = YUV4:2:2 input, out = YUV4:2:2 output 0/1: in = YUV4:2:2 input, out = Chrominance of YUV4:2:0 output 1/0: in = YUV4:2:2 input, out = Luminance of YUV4:2:0 output 1/1: in = YUV4:2:2 input, out = YUV4:2:0 output" { 488 _ 30 mbz; 489 cen 1 rw type(cen_status) "Output Enable for Chrominance This bit is valid in 422 input mode. When CEN=0 and YEN=0, output is 422"; 490 yen 1 rw type(yen_status) "Output Enable for Luminance. This bit is valid in 422 input mode. When CEN=0 and YEN=0, output is 422"; 491 }; 492 493 register rzb_i_vps addr(base, 0x114) "RESIZER B - INPUT VERTICAL START REGISTER The height of the image after the second-level crop must be 2 or larger." { 494 _ 19 mbz; 495 vps 13 rw "Input Vertical Position Sets the vertical start position of the input image within the global frame. It enables to crop data into the global frame. After SRC_VPS, the Vps'th line is processed as the first line in each image. After the second-level crop, the height of the image area must be two lines or larger, that is, a one-line image is not allowed. (RSZ_SRC_VSZ - RZB_I_VPS > 0)."; 496 }; 497 498 register rzb_i_hps addr(base, 0x118) "RESIZER B - INPUT HORIZONTAL START REGISTER" { 499 _ 19 mbz; 500 hps 13 rw "Input Horizontal Position Sets the horizontal position of the first pixel for each line within the global frame. After SRC_HPS, the pixel at the VAL'th position is processed as the first pixel. This value must be even."; 501 }; 502 503 register rzb_o_vsz addr(base, 0x11C) "RESIZER B - OUTPUT VERTICAL SIZER REGISTER" { 504 _ 19 mbz; 505 vsz 13 rw "The target output size of the resized image. The number of output lines is (VSZ+1). Set 479, when 480 lines of output is required."; 506 }; 507 508 register rzb_o_hsz addr(base, 0x120) "RESIZER B - OUTPUT HORIZONTAL SIZE REGISTER" { 509 _ 19 mbz; 510 hsz 12 rw "The horizontal size of output image. The number of pixel in each line is (HSZ+1). Set 479, when 480 pixels are required. This value must be lower than the max memory line size supported by the resizer engine, except in RAW pass through mode. Note that the LSB of the 13-bit HSZ value is fixed to 1 such that the horizontal size is always even."; 511 hsz_lsb 1 ro "The least significant bit of HSZ is forced to 1."; 512 }; 513 514 register rzb_v_phs_y addr(base, 0x124) "RESIZER B - INITIAL LUMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV4:2:2 data are output, the phase values for luma and chroma should typically be equal, that is, RZX_V_PHS_Y= RZX_V_PHS_C. The following constraints apply when setting the initial vertical phases ABS(RZX_V_PHS_Y - RZX_V_PHS_C) RZX_V_DIF. This constraint means that at most the distance between the initial phases for luminance and chrominance is not expected to exceed the distance between two luma pixels. Note that the absolute value is used, hence, the initial luma phase can be greater than the initial chroma phase or the other way around. As a reminder, the distance between two output pixels for luma is given by RZX_V_DIF." { 515 _ 18 mbz; 516 y 14 rw "The initial value for the luma phase in vertical resizing process. This value is in U14Q8 fractional format."; 517 }; 518 519 register rzb_v_phs_c addr(base, 0x128) "RESIZER B - INITIAL CHROMINANCE PHASE OF VERTICAL RESIZING PROCESS When YUV4:2:2 data are output, the phase values for luma and chroma should typically be equal, that is, RZX_V_PHS_Y= RZX_V_PHS_C. The following constraints apply when setting the initial vertical phases ABS(RZX_V_PHS_Y - RZX_V_PHS_C) RZX_V_DIF. This constraint means that at most the distance between the initial phases for luminance and chrominance is not expected to exceed the distance between two luma pixels. Note that the absolute value is used, hence, the initial luma phase can be greater than the initial chroma phase or the other way around. As a reminder, the distance between two output pixels for luma is given by RZX_V_DIF." { 520 _ 18 mbz; 521 c 14 rw "The initial value for the chroma phase in vertical resizing process. This value is in U14Q8 fractional format."; 522 }; 523 524 register rzb_v_dif addr(base, 0x12C) "RESIZER B - VERTICAL RESIZER REGISTERR" { 525 _ 18 mbz; 526 v 14 rw "The parameter for vertical resize. The actual resizing ratio is 256/RZB_V_DIF. In normal mode: 16 <= RZB_V_DIF <= 4096. In down-scale mode: 256 <= RZB_V_DIF <= 4096."; 527 }; 528 529 register rzb_v_typ addr(base, 0x130) "RESIZER B - INTERPOLATION METHOD FOR VERTICAL RESIZING" { 530 _ 30 mbz; 531 c 1 rw type(c_status) "Selection of resizing method for chrominance: vertical"; 532 y 1 rw type(c_status) "Selection of resizing method for luminance: vertical"; 533 }; 534 535 register rzb_v_lpf addr(base, 0x134) "RESIZER B - VERTICAL LPF INTENSITY REGISTER" { 536 _ 20 mbz; 537 c 6 rw "The intensity parameter for chroma vertical low pass filtering."; 538 y 6 rw "The intensity parameter for luma vertical low pass filtering."; 539 }; 540 541 register rzb_h_phs addr(base, 0x138) "RESIZER B - INITIAL PHASE OF HORIZONTAL RESIZING PROCESS" { 542 _ 18 mbz; 543 phs 14 rw "Initial value for the phase in horizontal resizing process, that is, the sampling position is shifted. This value is in U14Q8 fractional format. Example: If RZX_H_PHS = 128, the first output pixel is sampled at the center of the first two valid input pixels. If RZX_I_HPS=100 and RZX_H_PHS=128, the first output pixel is resampled at the center of the 100-th and the 101-st input pixels."; 544 }; 545 546 register rzb_h_phs_adj addr(base, 0x13C) "RESIZER B - LUMINANCE HORIZONTAL PHASE ADJUSTMENT The register enables to adjust the horizontal phase for the luma component when averaging is enabled (the horizontal averaging disrupts the relative sampling point between luminance and chrominance when YUV4:2:2 cosited data is input), that is, the relative phase between luma and chroma is different before and after the horizontal averager." { 547 _ 23 mbz; 548 adj 9 rw "Horizontal phase adjustment value. This value is in U9Q8 fractional format. This value is expected to be equal to zero if the averager is disabled or if input chroma is centered."; 549 }; 550 551 register rzb_h_dif addr(base, 0x140) "RESIZER B - HORIZONTAL RESIZER REGISTER" { 552 _ 18 mbz; 553 h 14 rw "The parameter for horizontal resizing process. The actual resizing ratio is 256/VAL. In normal mode 16 <= RSZ_RZA_H_DIF<=4096 In down-scale mode 256<=RSZ_RZA_H_DIF<=4096"; 554 }; 555 556 register rzb_h_typ addr(base, 0x144) "RESIZER B" { 557 _ 30 mbz; 558 c 1 rw type(c_status) "Selection of resizing method for chrominance: horizontal"; 559 y 1 rw type(c_status) "Selection of resizing method for luminance: horizontal"; 560 }; 561 562 register rzb_h_lpf addr(base, 0x148) "RESIZER B - HORIZONTAL LPF INTENSITY REGISTER" { 563 _ 20 mbz; 564 c 6 rw "Horizontal LPF Intensity for Chrominance"; 565 y 6 rw "Selection of resizing method for Luminance in horizontal direction"; 566 }; 567 568 register rzb_dwn_en addr(base, 0x14C) "RESIZER B - DOWNSCALE ENABLE REGISTER" { 569 _ 31 mbz; 570 dwn_en 1 rw type(dwn_en_status) "Resizer downscale enable"; 571 }; 572 573 register rzb_dwn_av addr(base, 0x150) "RESIZER B" { 574 _ 26 mbz; 575 v 3 rw "Vertical averaging size : 1/2 The range goes from 1/2 to 1/256 in power of two. 0:_DIV2 1/2 down scale 1:_DIV4 1/4 down scale 2:_DIV8 1/8 down scale 3:_DIV16 1/16 down scale 4:_DIV32 1/32 down scale 5:_DIV64 1/64 down scale 6:_DIV128 1/128 down scale 7:_DIV256 1/256 down scale"; 576 h 3 rw "Horizontal averaging size : 1/2 The range goes from 1/2 to 1/256 in power of two. 0:_DIV2 1/2 down scale 1:_DIV4 1/4 down scale 2:_DIV8 1/8 down scale 3:_DIV16 1/16 down scale 4:_DIV32 1/32 down scale 5:_DIV64 1/64 down scale 6:_DIV128 1/128 down scale 7:_DIV256 1/256 down scale"; 577 }; 578 579 register rzb_rgb_en addr(base, 0x154) "RESIZER B - RGB OUTPUT ENABLE" { 580 _ 31 mbz; 581 rgb_en 1 rw type(rgb_en_status) "Enable of RGB output In pass through mode, this register must be 0. This bit can only be set to 1 when YUV4:2:2 data are output. YUV4:2:2 data output is selected when SRC_FMT1.IN420 = 0 and RZB_420.YEN = RZB_420.CEN = 0"; 582 }; 583 584 register rzb_rgb_typ addr(base, 0x158) "RESIZER B - RGB OUTPUT CONTROL REGISTER" { 585 _ 29 mbz; 586 msk1 1 rw type(msk1_status) "Enables masking of the last 2 pixels This bit is used to mask the 2 last pixels at the image boundary which are affected by the YUV4:2:2 to YUV4:4:4 conversion."; 587 msk0 1 rw type(msk0_status) "Enables masking of the first 2 pixels This bit is used to mask the 2 first pixels at the image boundary which are affected by the YUV4:2:2 to YUV4:4:4 conversion."; 588 typ 1 rw type(typ_status) "16bit/32bit output selection"; 589 }; 590 591 register rzb_rgb_bld addr(base, 0x15C) "RESIZER B - RGB BLEND REGISTER" { 592 _ 24 mbz; 593 bld 8 rw "The alpha value used in 32-bit RGBA output mode"; 594 }; 595 596 register rzb_sdr_y_bad_h addr(base, 0x160) "RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to this address YUV4:2:0: Y data is written to this address RGB5:6:5: 16-bit RGB data is written to this address RGBA: 32-bit RGBA data is written to this address" { 597 _ 16 mbz; 598 y_bad_h 16 rw "Memory Base Address Sets 16 upper bits of the 32-bit base address of the circular buffer in memory."; 599 }; 600 601 register rzb_sdr_y_bad_l addr(base, 0x164) "RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to this address YUV4:2:0: Y data is written to this address RGB5:6:5: 16-bit RGB data is written to this address RGBA: 32-bit RGBA data is written to this address" { 602 _ 16 mbz; 603 y_bad_l 16 rw "Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory. It is a byte address. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on. RAW, RGB5:6:5 and YUV4:2:2 formats (output data on 16 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on. RGBA format (output data on 32 bits): The three least significant bits must be set to '000' when horizontal reversal mode is off. The three least significant bits must be set to '111' when horizontal reversal mode is on."; 604 }; 605 606 register rzb_sdr_y_sad_h addr(base, 0x168) "RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to this address YUV4:2:0: Y data is written to this address RGB5:6:5: 16-bit RGB data is written to this address RGBA: 32-bit RGBA data is written to this address" { 607 _ 16 mbz; 608 y_sad_h 16 rw "Memory Start Address Sets 16 upper bits of the 32-bit start address in memory."; 609 }; 610 611 register rzb_sdr_y_sad_l addr(base, 0x16C) "RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0, RGB5:6:5, RGBA. RAW: RAW data is written to this address YUV4:2:2: YUV data is written to this address YUV4:2:0: Y data is written to this address RGB5:6:5: 16-bit RGB data is written to this address RGBA: 32-bit RGBA data is written to this address" { 612 _ 16 mbz; 613 y_sad_l 16 rw "Memory Start Address Sets the 16 lower bits of the 32-bit start address in memory. It is a byte address. For every frame, the first line of data will be written to this address. We have: SAD = BAD + (PTR_S x OFT) and PTR_S < PTR_E If the first line must be written at the beginning of the circular buffer memory then SAD = BAD and PTR_S = 0. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on. RAW, RGB5:6:5 and YUV4:2:2 formats (output data on 16 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on. RGBA format (output data on 32 bits): The three least significant bits must be set to '000' when horizontal reversal mode is off. The three least significant bits must be set to '111' when horizontal reversal mode is on."; 614 }; 615 616 register rzb_sdr_y_oft addr(base, 0x170) "RESIZER B - OUTPUT MEMORY OFFSET REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0 or RGBA." { 617 _ 15 mbz; 618 y_oft 17 rw "Memory Line Offset Sets the size of each line in the circular buffer. It is expressed in bytes and unsigned. Note that OFT does not necessary corresponds to the size of a line in a frame, it can be much bigger. The line offset must be a multiple of 128 bytes (bits [6:0] of RZX_SDR_Y_OFT and RZX_SDR_C_OFT must be set to 0). Example: line 0 address = SAD line 1 address = SAD + 1 x OFT line 2 address = SAD + 2 x OFT"; 619 }; 620 621 register rzb_sdr_y_ptr_s addr(base, 0x174) "RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4;2:2, YUV4:2:0 or RGBA." { 622 _ 19 mbz; 623 y_ptr_s 13 rw "Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space. This value is expressed in number of lines. The hardware uses it to set up the initial value of the circular buffer. It must be set up such as PTR_S = (SAD - BAD) / OFT. This value must be set to 0 when RSZ_RZA_SDR_Y_BAD = RSZ_RZA_SDR_Y_SAD."; 624 }; 625 626 register rzb_sdr_y_ptr_e addr(base, 0x178) "RESIZER B - OUTPUT MEMORY END ADDRESS REGISTER This register is used if the output data format is one of the following: RAW, YUV4:2:2, YUV4:2:0 or RGBA." { 627 _ 19 mbz; 628 y_ptr_e 13 rw "End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space. This value is expressed in number of lines. When the number of output lines exceeds this value, the address restarts from the first address in the output memory space (BAD)."; 629 }; 630 631 register rzb_sdr_c_bad_h addr(base, 0x17C) "RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." { 632 _ 16 mbz; 633 c_bad_h 16 rw "Memory Base Address Sets the 16 upper bits of the 32-bit base address of the circular buffer in memory."; 634 }; 635 636 register rzb_sdr_c_bad_l addr(base, 0x180) "RESIZER B - OUTPUT MEMORY BASE ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." { 637 _ 16 mbz; 638 c_bad_l 16 rw "Memory Base Address Sets the 16 lower bits of the 32-bit base address of the circular buffer in memory. It is a byte address. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on."; 639 }; 640 641 register rzb_sdr_c_sad_h addr(base, 0x184) "RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." { 642 _ 16 mbz; 643 c_sad_h 16 rw "Memory Base Address Sets the 16 upper bits of the 32-bit start address in memory."; 644 }; 645 646 register rzb_sdr_c_sad_l addr(base, 0x188) "RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0. U and V data are written into this buffer." { 647 _ 16 mbz; 648 c_sad_l 16 rw "Memory Base Address Sets the 16 lower bits of the 32-bit start address in memory. It is a byte address. For every frame, the first line of data will be written to this address (C_SAD_H/C_SAD_L). We have: SAD = BAD + (PTR_S x OFT) and PTR_S < PTR_E If the first line must be written at the beginning of the circular buffer memory then SAD = BAD and PTR_S = 0. YUV4:2:0 format (output data on 8 bits): The two least significant bits must be set to 00 when horizontal reversal mode is off. The two least significant bits must be set to 11 when horizontal reversal mode is on."; 649 }; 650 651 register rzb_sdr_c_oft addr(base, 0x18C) "RESIZER B - OUTPUT MEMORY OFFSET REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" { 652 _ 15 mbz; 653 c_oft 17 rw "Memory Line Offset Sets the size of each line in the circular buffer. It is expressed in bytes and unsigned. Note that OFT does not necessary corresponds to the size of a line in a frame, it can be much bigger. The line offset must be a multiple of 128 bytes (bits [6:0] of RZX_SDR_Y_OFT and RZX_SDR_C_OFT must be set to 0). Example: line 0 address = SAD line 1 address = SAD + 1 x OFT line 2 address = SAD + 2 x OFT"; 654 }; 655 656 register rzb_sdr_c_ptr_s addr(base, 0x190) "RESIZER B - OUTPUT MEMORY START ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" { 657 _ 19 mbz; 658 c_ptr_s 13 rw "Start Line of Memory Pointer Sets the vertical position of the first output line in the output memory space. This value is expressed in number of lines. The hardware uses it to set up the initial value of the circular buffer. It must be set up such as PTR_S = (SAD - BAD) / OFT. This value must be set to 0 when RSZ_RZA_SDR_C_BAD = RSZ_RZA_SDR_C_SAD."; 659 }; 660 661 register rzb_sdr_c_ptr_e addr(base, 0x194) "RESIZER B - OUTPUT MEMORY END ADDRESS REGISTER FOR CHROMA DATA (YUV4:2:0) This register is used if the output data format is YUV4:2:0" { 662 _ 19 mbz; 663 c_ptr_e 13 rw "End Line of Memory Pointer Sets the maximum number of lines to be stored in the output memory space. This value is expressed in number of lines. When the number of output lines exceeds this value, the address restarts from the first address in the output memory space (BAD)."; 664 }; 665};