1/*
2 * Copyright (c) 2013 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstrasse 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_intrconn_socket_cm1.dev
12 *
13 * DESCRIPTION: 
14 *
15 * NOTE: This file has been automatically generated based on the
16 * XML files extracted from the TI RDT v1.0.0.4p Tool.
17 * Download from here: http://www.ti.com/product/omap4460
18 * This means that the file might not be optimal in terms of naming
19 * conventions for constants and registers (duplicated
20 * namespaces in register and device name etc.).
21 * Also, because of the underlying structure from the original XML
22 * it's possible that some constants appear multiple times (if they
23 * have slightly different descriptions for example).
24 *
25 * You want to clean that up before using the files for the first time!
26 */
27 
28device omap44xx_intrconn_socket_cm1 msbfirst ( addr base ) "" {
29    
30    
31    register revision_cm1 ro addr(base, 0x0) "This register contains the IP revision code for the CM1 part of the PRCM" type(uint32);
32
33    constants idlest_status width(2) "" {
34        IDLEST_0_r = 0 "Module is fully functional";
35        IDLEST_1_r = 1 "Module is performing transition: wakeup, or sleep, or sleep abortion";
36        IDLEST_2_r = 2 "Module is in Idle";
37        IDLEST_3_r = 3 "Module is disabled";
38    };
39
40    constants modulemode_status width(2) "" {
41        MODULEMODE_0 = 0 "Module is disabled by software. INTRCONN configuration port is not accessible.";
42        MODULEMODE_1 = 1 "Module is managed automatically by hardware along with CM1 and EMU domain. INTRCONN configuration port is accessible only when EMU domain is on.";
43        MODULEMODE_2_r = 2 "Reserved";
44        MODULEMODE_3_r = 3 "Reserved";
45    };
46    
47    register cm_cm1_profiling_clkctrl addr(base, 0x40) "This register manages the CM1_PROFILING clock. [warm reset insensitive]" {
48        _ 14 mbz;
49        idlest 2 ro type(idlest_status) "Module idle status";
50        _ 14 mbz;
51        modulemode 2 rw type(modulemode_status) "Control the way mandatory clocks are managed.";
52    };
53    
54    register cm1_debug_cfg addr(base, 0xF0) "This register is used to configure the CM1's 32-bit debug output. There is one 7-bit source select field for selecting from a shared set of 8-bit internal signal blocks per byte. [warm reset insensitive]" {
55        _ 1 mbz;
56        sel3 7 rw "Internal signal block select for debug word byte-3";
57        _ 1 mbz;
58        sel2 7 rw "Internal signal block select for debug word byte-2";
59        _ 1 mbz;
60        sel1 7 rw "Internal signal block select for debug word byte-1";
61        _ 1 mbz;
62        sel0 7 rw "Internal signal block select for debug word byte-0";
63    };
64};